Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a first element in a substrate. The semiconductor structure includes a gap fill layer. A first portion of the gap fill layer covers the first element. The first portion of the gap fill layer has a tapered sidewall. A first portion of the substrate separates the first portion of the gap fill layer from the first element.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures and methods for manufacturing them. Background Technology

[0002] Semiconductor components are used in a variety of electronic devices (e.g., mobile phones, laptops, desktop computers, tablets, watches, gaming systems, and various other industrial, commercial, and consumer electronics). A semiconductor component typically consists of a semiconductor portion and wiring formed within the semiconductor portion. Summary of the Invention

[0003] According to some embodiments of this disclosure, a semiconductor structure is provided, comprising: a first element and a gap filling layer. The first element is located in a substrate. A first portion of the gap filling layer covers the first element. The first portion of the gap filling layer has tapered sidewalls. A first portion of the substrate separates the first portion of the gap filling layer from the first element.

[0004] According to some embodiments of this disclosure, a semiconductor structure is provided, comprising: a first element and a gap filling layer. The first element is located in a substrate. A first portion of the gap filling layer covers the first element. A second portion of the gap filling layer is laterally offset from the first element. A first portion of the substrate separates the second portion of the gap filling layer from the first element.

[0005] According to some embodiments of this disclosure, a method for manufacturing a semiconductor structure is provided, comprising: forming a first groove in a substrate, wherein the first groove covers a first element in the substrate; forming a first trench in the substrate, wherein the first trench is between the first element and a second element in the substrate; and forming a gap-filling layer in the first groove and the first trench, such that a first portion of the gap-filling layer covers the first element, and a second portion of the gap-filling layer is between the first element and the second element. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings, based on the following detailed description. It should be understood that, in accordance with standard industry practice, the features are not drawn to scale. In fact, for clarity, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figures 1 to 15 Cross-sectional views of a semiconductor structure at various stages of the manufacturing process are illustrated according to some embodiments;

[0008] Figure 16 A cross-sectional view of a semiconductor structure according to a partial embodiment is shown;

[0009] Figure 17 A cross-sectional view of a semiconductor structure according to a partial embodiment is shown;

[0010] Figure 18 A cross-sectional view of a semiconductor structure according to a partial embodiment is shown.

[0011] [Symbol Explanation]

[0012] 100: Semiconductor Structure

[0013] 102: Substrate

[0014] 102a: Partial

[0015] 102b: Partial

[0016] 104: Components

[0017] 106: Structure

[0018] 108: Second dielectric layer

[0019] 110: Low resistance structure

[0020] 112: First dielectric layer

[0021] 202: First side view

[0022] 204: Second side view

[0023] 206: Thickness

[0024] 208: Direction

[0025] 302: Masking layer

[0026] 402: Patterned mask layer

[0027] 502: Groove

[0028] 602: Distance

[0029] 604: Distance

[0030] 606: Distance

[0031] 608: First conical sidewall

[0032] 610: Second conical sidewall

[0033] 702: Optical Resistor

[0034] 802: Photoresist

[0035] 902: Trench

[0036] 1002: Distance

[0037] 1004: First sidewall

[0038] 1006: Second sidewall

[0039] 1102: Buffer layer

[0040] 1102a: Partial

[0041] 1102b: Partial

[0042] 1202: Gap Filler Layer

[0043] 1202a: Part 1

[0044] 1202b: Part Two

[0045] 1204: Third conical sidewall

[0046] 1206: Fourth conical sidewall

[0047] 1208: Third sidewall

[0048] 1210: Fourth lateral wall

[0049] 1302: Third dielectric layer

[0050] 1402: Grid structure

[0051] 1502: Passivation layer

[0052] 1600: Semiconductor Structure

[0053] 1602: Gap

[0054] 1702: Radiation

[0055] 1800: Semiconductor Structure

[0056] 1802: Connection Structure

[0057] 1804: First Interconnect Layer

[0058] 1806: First Connector Layer

[0059] 1808: Second Connecting Layer

[0060] 1810: Second Interconnect Layer

[0061] 1812: Second substrate

[0062] 1813: Conductor

[0063] 1814: Source / Drain Region

[0064] 1816: First conductive structure

[0065] 1818: Second conductive structure

[0066] 1820: Conductor

[0067] 1822: Polycrystalline silicon structure

[0068] 1824: Doped well region

[0069] 1826: Shallow trench isolation area Detailed Implementation

[0070] The following provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or words may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0071] Furthermore, spatially relative terms (e.g., "below," "below," "under," "above," "above," etc.) are used here to simply describe the relationship between an element or feature as shown in the figure and another element or feature. In use or operation, these spatially relative terms cover different orientations of the device, in addition to the orientations shown in the figure. Moreover, these devices are rotatable (rotating 90 degrees or other angles), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0072] Some embodiments of this disclosure relate to a semiconductor structure. According to some embodiments, the semiconductor structure includes a first element (e.g., a first photodiode) in a substrate (e.g., a semiconductor wafer). The semiconductor structure includes a gap-filling layer. A first portion of the gap-filling layer covers the first element. In some embodiments, the first portion of the gap-filling layer has tapered sidewalls. Compared to a gap-filling layer without tapered sidewalls, the first portion of the gap-filling layer covering the first element has higher radiation absorption, thereby directing more radiation to the first element. In some embodiments, the first portion of the gap-filling layer is a high absorption (HA) structure. Compared to the first portion of the gap-filling layer with tapered sidewalls, a gap-filling layer without tapered sidewalls is not a high absorption structure and scatters or reflects more radiation away from the first element.

[0073] In some embodiments, a second portion of the gap-fill layer is laterally offset from the first and second elements in the substrate, thereby situated between the first and second elements. The second portion of the gap-fill layer corresponds to a deep trench isolation (DTI) feature. In some embodiments, the semiconductor structure is typically formed in the back side of the substrate, such that the second portion of the gap-fill layer corresponds to a backside deep trench isolation (BDTI) feature. In some embodiments, the second element includes a second photodiode. The second portion of the gap-fill layer suppresses (e.g., through the tapered first portion of the gap-fill layer) radiation propagation toward the first element to the second element, thereby suppressing crosstalk between the first and second elements or enhancing the modulation transfer function (MTF) (where a higher MTF provides higher resolution).

[0074] In some embodiments, at least one of the first element, second element, or other elements in the substrate comprises a material with relatively high absorption for near-infrared (NIR) wavelengths. At least one of the first element, second element, or other elements in the substrate comprises at least one of germanium or other suitable materials. Compared to a semiconductor structure with a tapered first portion without a gap-filling layer, a laterally offset second portion of the gap-filling layer, or at least one of a highly absorbing first element, a semiconductor structure with at least one of a tapered first portion, a gap-filling layer laterally offset from the first element in the substrate, or a first element comprising a highly absorbing material has a higher quantum efficiency (QE), which can improve the quantum efficiency to approximately 94% (e.g., for near-infrared wavelengths). In some embodiments, the semiconductor structure is a sensor (e.g., an image sensor, a proximity sensor, or at least one of different types of sensors). Due to the improved quantum efficiency, this semiconductor structure operates more efficiently than other sensors (e.g., requiring less power, being more efficient in low light conditions, providing higher resolution, etc.).

[0075] Figures 1 to 15This is a cross-sectional view of a semiconductor structure 100 according to a partial embodiment. In some embodiments, sensors are implemented through the semiconductor structure 100. The semiconductor structure (semiconductor arrangement) 100 may also be referred to as a semiconductor architecture or semiconductor configuration. Sensors include image sensors, proximity sensors, time-of-flight (ToF) sensors, indirect time-of-flight (iToF) sensors, backside illumination (BSI) sensors, complementary metal-oxide-semiconductor (CMOS) image sensors, backside-illuminated CMOS image sensors, or other types of sensors. Other structures and configurations of the semiconductor structure 100 and sensors are within the scope of this disclosure.

[0076] Figure 1 A semiconductor structure 100 according to a partial embodiment is illustrated. The semiconductor structure 100 includes at least one of a first dielectric layer 112, a second dielectric layer 108, or a substrate 102. The first dielectric layer 112 includes at least one of a low-k dielectric material or other suitable material. As used herein, the term "low-k dielectric material" refers to a material with a dielectric constant k less than about 3.9. Some low-k dielectric materials have a dielectric constant less than about 3.5, while some low-k dielectric materials have a dielectric constant less than about 2.5.

[0077] According to some embodiments, one or more low-resistance structures 110 are disposed in the first dielectric layer 112. The one or more low-resistance structures 110 comprise a conductive material (e.g., at least one of a metallic material or other suitable material). In some embodiments, the one or more low-resistance structures 110 provide interconnections (e.g., wiring) between at least one of various doping features, circuits, inputs / outputs, etc., of the semiconductor structure 100. Other structures and configurations of the first dielectric layer 112 and the one or more low-resistance structures 110 are also within the scope of this disclosure.

[0078] According to some embodiments, a second dielectric layer 108 is formed over a first dielectric layer 112. In some embodiments, the second dielectric layer 108 is in direct contact with the top surface of the first dielectric layer 112. The second dielectric layer 108 comprises at least one of oxide or other suitable materials. In some embodiments, the second dielectric layer 108 comprises undoped silicate glass (USG) oxide. Other structures and configurations of the second dielectric layer 108 are also within the scope of this disclosure. In some embodiments, one or more structures 106 are disposed in the second dielectric layer 108. The one or more structures 106 comprise polysilicon or other suitable materials. Other structures and configurations of the second dielectric layer 108 and the one or more structures 106 are also within the scope of this disclosure.

[0079] According to some embodiments, a substrate 102 is formed above a second dielectric layer 108. In some embodiments, the substrate 102 is in direct contact with the top surface of the second dielectric layer 108. The substrate 102 includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a grain formed from a wafer. The substrate 102 includes silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium gallium phosphide (InGaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or other suitable materials. According to some embodiments, the substrate 102 includes monocrystalline silicon and has <100> Crystalline silicon with crystal orientation <110> Crystalline silicon or other suitable materials with crystal orientation. In some embodiments, substrate 102 includes at least one doped region. Other structures and configurations of substrate 102 are also within the scope of this disclosure.

[0080] According to some embodiments, substrate 102 includes element 104. Element 104 is formed within substrate 102 (e.g., through doped substrate 102). Other processes and techniques for forming element 104 are also within the scope of this disclosure. In some embodiments, element 104 includes a photodiode. Other structures and configurations of element 104 are also within the scope of this disclosure. Element 104 includes at least one of a pinned layer photodiode, phototransistor, photogate, reset transistor, source follower transistor, transfer transistor, or a different type of element. In some embodiments, elements 104 are different from each other to have at least one of different junction depths, thicknesses, widths, material compositions, etc. In some embodiments, elements 104 are identical to each other to have the same junction depth, thickness, width, material composition, etc. Although three elements 104 are illustrated, any number of elements 104 are contemplated.In some embodiments, at least some elements 104 include at least one of the source or drain of one or more transistors (wherein, one or more transistors are, for example, at least one of the following: field-effect transistor (FET), metal-oxide-semiconductor field-effect transistor (MOSFET), metal-insulator-semiconductor field-effect transistor (MISFET), metal-semiconductor field-effect transistor (MESFET), insulated-gate field-effect transistor (IGFET), insulated-gate bipolar transistor (IGBT), high-electron mobility transistor (HEMT), heterostructure field-effect transistor (HFET), modulation-doped field-effect transistor (MODFET), or other types of transistors). According to some embodiments, at least some elements 104 are connected to at least one of the source or drain of one or more transistors (wherein, the one or more transistors are, for example, at least one of field-effect transistors, metal-oxide-semiconductor field-effect transistors, metal-semiconductor field-effect transistors, insulated-gate field-effect transistors, insulated-gate bipolar transistors, high electron mobility transistors, heterostructure field-effect transistors, modulation-doped field-effect transistors, or other types of transistors). In some embodiments, one or more structures 106 are used to facilitate the supply of voltage to the elements 104 or to drive at least one of the elements 104. Other structures and configurations of the elements 104 and one or more structures 106 are also within the scope of this disclosure.

[0081] According to some embodiments, at least some elements 104 comprise materials having an energy bandgap of less than 1.6 electron volts. Other materials and energy bandgap of element 104 are also within the scope of this disclosure. In some embodiments, at least some elements 104 comprise materials having an energy bandgap smaller than that of silicon. Other materials and energy bandgap of element 104 are also within the scope of this disclosure. At least some elements 104 comprise at least one of germanium, indium arsenide (InAs), indium antimonide (InSb), gallium antimonide (GaSb), gallium arsenide (GaAs), indium phosphide (InP), or other suitable materials. In some embodiments, at least some of elements 104 comprise materials with relatively high absorption for near-infrared wavelengths (e.g., radiation having wavelengths between approximately 700 nm and approximately 2500 nm). Other materials of element 104, as well as other radiation wavelengths for which the materials of element 104 have relatively high absorption, are also within the scope of this disclosure.

[0082] Figure 2 The illustration depicts a reduced substrate 102 thickness according to a partial embodiment. For example, the thickness of substrate 102 is reduced by removing a portion of substrate 102 through at least one of chemical mechanical planarization (CMP), etching, or other suitable techniques. According to a partial embodiment, after removing a portion of substrate 102, the thickness 206 of substrate 102 is between approximately 25,000 angstroms and approximately 60,000 angstroms. Other values ​​for thickness 206 are also within the scope of this disclosure. Other processes and techniques for forming a substrate 102 having a thickness 206 are also within the scope of this disclosure.

[0083] Substrate 102 has a first side surface 202 and a second side surface 204. In some embodiments, substrate 102 is inverted such that the first side surface 202 corresponds to the back surface of substrate 102, and the second side surface 204 corresponds to the front surface of substrate 102. Other structures and configurations of substrate 102 are also within the scope of this disclosure. In some embodiments, element 104 is used to sense radiation (e.g., incident light) incident on substrate 102 from the first side surface 202. One or more elements 104 detect radiation entering substrate 102 through the first side surface 202. In some embodiments, the radiation travels along direction 208 to enter substrate 102 and is detected by element 104. Other structures and configurations of substrate 102 and element 104 are also within the scope of this disclosure.

[0084] Figure 3A masking layer 302 formed over a substrate 102 is illustrated according to a partial embodiment. In some embodiments, the masking layer 302 is in direct contact with the top surface of the substrate 102. In some embodiments, the masking layer 302 is a hard masking layer. The masking layer 302 includes at least one of oxides, nitrides, metals, or other suitable materials. The masking layer 302 is formed through at least one of the following techniques: physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), reduced pressure chemical vapor deposition (RPCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin-on coating, growth, or other suitable techniques.

[0085] Figure 4A patterned mask layer 402 formed over a substrate 102 is illustrated according to a partial embodiment. The mask layer 302 is patterned to form the patterned mask layer 402. According to a partial embodiment, a photoresist (not shown) is used to pattern the mask layer 302 to form the patterned mask layer 402. The photoresist is formed on the mask layer 302. The photoresist is formed by at least one of physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable techniques. The photoresist includes a photosensitive material, wherein the properties of the photoresist (e.g., solubility) are affected by light. The photoresist is a negative photoresist or a positive photoresist. For negative photoresist, when illuminated by a light source, the areas of the negative photoresist become insoluble, such that during the subsequent development stage, applying solvent to the negative photoresist removes the unilluminated areas. Therefore, the pattern formed in the negative photoresist is a negative image of the pattern defined by the opaque areas of the template (e.g., a mask) between the light source and the negative photoresist. In positive photoresist, the illuminated areas of the positive photoresist become soluble and are removed by the solvent applied during development. Therefore, the pattern formed in the positive photoresist is a positive image of the opaque areas of the template (e.g., a mask) between the light source and the positive photoresist. One or more etchants are selective, such that they remove or etch away one or more layers exposed or not covered by the photoresist at a rate faster than the rate at which they remove or etch away the photoresist. Therefore, openings in the photoresist allow one or more etchants to form corresponding openings in one or more layers beneath the photoresist, thereby transferring the pattern in the photoresist to one or more layers beneath the photoresist. After pattern transfer, the photoresist is stripped or washed away (e.g., using at least one of hydrogen fluoride (HF), diluted hydrogen fluoride, chlorine compounds (e.g., hydrogen chloride (HCl2)), hydrogen sulfide (H2S), or other suitable materials). Other processes and techniques for forming the patterned mask layer 402 are also within the scope of this disclosure.

[0086] The etching process used to remove portions of the masking layer 302 to expose portions of the substrate 102 and form a patterned masking layer 402 is at least one of a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process, or other suitable etching processes. The etching process uses at least one of hydrogen fluoride (HF), diluted hydrogen fluoride, a chlorine compound (e.g., hydrogen chloride (HCl2)), hydrogen sulfide (H2S), or other suitable materials. In some embodiments, the etching process for removing portions of the masking layer 302 and forming the patterned masking layer 402 also removes at least a portion of the substrate 102 (e.g., the portion of the substrate 102 located below the opening in the patterned masking layer 402). Other processes and techniques for removing portions of the masking layer 302 and forming the patterned masking layer 402 are also within the scope of this disclosure.

[0087] Figure 5 The illustration depicts the formation of a recess 502 in a substrate 102 using a patterned mask layer 402 according to a partial embodiment. In a partial embodiment, an etching process is performed to form the recess 502, wherein openings in the patterned mask layer 402 allow one or more etchants applied during the etching process to remove portions of the substrate 102, while the patterned mask layer 402 protects or shields portions of the substrate 102 covered by the patterned mask layer 402. The etching process is at least one of a dry etching process, a wet etching process, anisotropic etching process, isotropic etching process, or other suitable etching process. The etching process uses at least one of hydrogen fluoride (HF), diluted hydrogen fluoride, a chlorine compound (e.g., hydrogen chloride (HCl2)), hydrogen sulfide (H2S), or other suitable materials.

[0088] In some embodiments, the groove 502 includes one or more grooves on the element 104. Although three grooves 502 above the element 104 are illustrated, any number of grooves 502 are within the scope of this disclosure. In some embodiments, assuming the groove 502 is defined in the top surface of the substrate 102, a portion of the substrate 102 separates the groove 502 from the element 104. Other processes and techniques for forming the groove 502 are also within the scope of this disclosure.

[0089] Figure 6The removal of a patterned mask layer 402 according to a partial embodiment is illustrated. The patterned mask layer 402 is removed after the groove 502 is formed. In some embodiments, the patterned mask layer 402 is removed by at least one of chemical mechanical planarization or etching. The etching process is at least one of dry etching, wet etching, anisotropic etching, isotropic etching, or other suitable etching processes. The etching process uses at least one of hydrogen fluoride (HF), diluted hydrogen fluoride, chlorine compounds (e.g., hydrogen chloride (HCl2)), hydrogen sulfide (H2S), or other suitable materials. Other processes and techniques for removing the patterned mask layer 402 are also within the scope of this disclosure.

[0090] A portion of the substrate 102 has at least one of a first conical sidewall 608 or a second conical sidewall 610 defining a recess 502. In some embodiments, the recess 502 has a first conical sidewall 608 and a second conical sidewall 610. At least the first conical sidewall 608 has a first slope (e.g., a negative slope), or the second conical sidewall 610 has a second slope (e.g., a positive slope). In some embodiments, the second slope is opposite in polarity to the first slope. In some embodiments, the recess 502 has a triangular shape. In some embodiments, the cross-sectional area of ​​the recess 502 decreases along direction 208. The width of the uppermost portion of the recess 502 is greater than the width of the lowermost portion of the recess 502. Other structures and configurations of the recess 502 are also within the scope of this disclosure.

[0091] In some embodiments, an etching process is performed to form the groove 502, such that the substrate 102 has tapered sidewalls defining the groove 502 (e.g., a first tapered sidewall 608 and a second tapered sidewall 610). One or more etchants are designed or selected for performing the etching process to form tapered sidewalls in the substrate 102 defining the groove 502. According to some embodiments, the substrate 102 has a specific crystal orientation (e.g., having...). <100> Crystal orientation or <110> At least one of the crystal orientations of crystalline silicon enables the etching process to form a tapered sidewall defining the recess 502 in the substrate 102. Other processes and techniques for forming the sidewall defining the recess 502 are also within the scope of this disclosure.

[0092] In some embodiments, the distance 602 between the lowermost portion of the groove 502 and at least one of the uppermost portion of the groove 502 or the top surface of the substrate 102 is between approximately 500 angstroms and approximately 10,000 angstroms. Other values ​​for distance 602 are also within the scope of this disclosure. Distance 602 corresponds to the depth of the groove 502. In some embodiments, the distance 604 between the top surface of the substrate 102 and the top surface of the element 104 is between approximately 5,500 angstroms and approximately 30,000 angstroms. Other values ​​for distance 604 are also within the scope of this disclosure. In some embodiments, the distance 606 between the lowermost portion of the groove 502 and the top surface of the element 104 is between approximately 5,000 angstroms and approximately 20,000 angstroms. Other values ​​for distance 606 are also within the scope of this disclosure.

[0093] Figure 7 The illustration depicts a photoresist 702 formed above a substrate 102 according to a partial embodiment. In some embodiments, the photoresist 702 is in direct contact with the top surface of the substrate 102. In some embodiments, the photoresist 702 is in a recess 502 in the substrate 102. The photoresist 702 is formed by at least one of physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable techniques. The photoresist 702 comprises a photosensitive material, wherein the properties of the photoresist 702 (e.g., solubility) are affected by light. The photoresist 702 can be a negative photoresist or a positive photoresist.

[0094] Figure 8 A patterned photoresist 802 formed of photoresist 702 is illustrated according to a partial embodiment. The patterned photoresist 802 has openings that expose portions of the substrate 102. In some embodiments, the openings in the patterned photoresist 802 are between elements 104 such that these openings do not overlap with or laterally offset from the elements 104. In some embodiments, the openings in the patterned photoresist 802 are between two adjacent elements 104 such that the openings are above the portion of the substrate 102 between the first element 104 and the second element 104. According to a partial embodiment, the openings in the patterned photoresist 802 are above portions of the elements 104.

[0095] Figure 9The illustration depicts the formation of trenches 902 in a substrate 102 using patterned photoresist 802 according to a partial embodiment. In a partial embodiment, an etching process is performed to form the trenches 902, wherein openings in the patterned photoresist 802 allow one or more etchants applied during the etching process to remove a portion of the substrate 102, while the patterned photoresist 802 protects or shields a portion of the substrate 102 covered by the patterned photoresist 802. The etching process is at least one of dry etching, wet etching, anisotropic etching, isotropic etching, or other suitable etching processes. The etching process uses at least one of hydrogen fluoride (HF), diluted hydrogen fluoride, chlorine compounds (e.g., hydrogen chloride (HCl2)), hydrogen sulfide (H2S), or other suitable materials. Other processes and techniques for forming the trenches 902 are also within the scope of this disclosure.

[0096] In some embodiments, trenches 902 are located between elements 104 such that trenches 902 are laterally offset from elements 104. Trench 902 is located between two adjacent elements 104. In some embodiments, each trench 902 is located between two adjacent elements 104. Trench 902 is laterally offset from elements 104, and a portion of substrate 102 separates the trench 902 from the element 104. In some embodiments, trench 902 is located between two adjacent elements 104, a first portion of substrate 102 separates the trench 902 from a first element of the two adjacent elements 104, and a second portion of substrate 102 separates the trench 902 from a second element of the two adjacent elements 104. Other structures and configurations of trench 902 are also within the scope of this disclosure.

[0097] Figure 10 The removal of patterned photoresist 802 according to a partial embodiment is illustrated. The patterned photoresist 802 is removed after the trench 902 is formed. In some embodiments, the patterned photoresist 802 is removed by at least one of chemical mechanical planarization, etching, or other suitable techniques. The etching process is at least one of dry etching, wet etching, anisotropic etching, isotropic etching, or other suitable etching processes. The etching process uses at least one of hydrogen fluoride (HF), diluted hydrogen fluoride, chlorine compounds (e.g., hydrogen chloride (HCl2)), hydrogen sulfide (H2S), or other suitable materials. Other processes and techniques for removing patterned photoresist 802 are also within the scope of this disclosure.

[0098] According to some embodiments, a portion of the substrate 102 has a first sidewall 1004 and a second sidewall 1006 defining a trench 902. According to some embodiments, at least one of the first sidewall 1004 or the second sidewall 1006 is a tapered sidewall. At least the first sidewall 1004 has a first slope (e.g., a negative slope), or the second sidewall 1006 has a second slope (e.g., a positive slope). In some embodiments, the second slope is opposite in polarity to the first slope. In some embodiments, the cross-sectional area of ​​the trench 902 decreases along direction 208. The width of the uppermost portion of the trench 902 is greater than the width of the lowermost portion of the trench 902. Other structures and configurations of the trench 902 are also within the scope of this disclosure.

[0099] In some embodiments, an etching process is performed to form trench 902 such that substrate 102 has tapered sidewalls (e.g., first sidewall 1004 and second sidewall 1006) defining trench 902. One or more etchants are designed or selected for use in the etching process to form tapered sidewalls defining trench 902 in substrate 102. According to some embodiments, substrate 102 having a specific crystal orientation (e.g., having...) <100> Crystal orientation or <110> The presence of at least one crystalline silicon in the crystal orientation enables the etching process to form tapered sidewalls defining the trench 902 in the substrate 102. Other processes and techniques for forming the sidewalls defining the trench 902 are also within the scope of this disclosure.

[0100] According to some embodiments, the sidewalls defining the trench 902 (e.g., first sidewall 1004 and second sidewall 1006) extend vertically (e.g., in a direction parallel to the direction 208 in which radiation propagates into the substrate 102 and is detected by the element 104). Other structures and configurations of the trench 902 are also within the scope of this disclosure.

[0101] In some embodiments, the distance 1002 between the lowest portion of the trench 902 and at least one of the highest portion of the trench 902 or the top surface of the substrate 102 is at least half the thickness 206 of the substrate 102. Other values ​​for the distance 1002 are also within the scope of this disclosure. The distance 1002 corresponds to the depth of the trench 902.

[0102] The lowest portion of trench 902 is lower than the highest portion of element 104. According to some embodiments, the lowest portion of trench 902 is higher than the lowest portion of element 104. According to some embodiments, the lowest portion of trench 902 is lower than the lowest portion of element 104. According to some embodiments, the lowest portion of trench 902 is flush with the lowest portion of element 104. Other structures and configurations of trench 902 and element 104 are also within the scope of this disclosure.

[0103] Figure 11A buffer layer 1102 formed over a substrate 102 according to a partial embodiment is illustrated. In a partial embodiment, the buffer layer 1102 is in direct contact with the top surface of the substrate 102 and sidewalls defined in the substrate 102 (e.g., sidewalls defining recess 502 and sidewalls defining trench 902). The buffer layer 1102 includes at least one dielectric material, a high dielectric constant dielectric material, an oxide (e.g., a high dielectric constant oxide), an antireflective coating, silicon dioxide (SiO2), hafnium oxynitride (HfSiON), or hafnium silicate (HfSiO2). x ), Hafnium alumina (HfAlO) x The buffer layer 1102 is formed using at least one of the following techniques: physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable techniques. In some embodiments, the buffer layer 1102 is formed in the recesses 502 and trenches 902 and above the top surface of the substrate 102.

[0104] According to some embodiments, buffer layer 1102 comprises a single layer. This single layer is used to provide improved adhesion to the subsequently formed gap-filling layer. According to some embodiments, buffer layer 1102 comprises multiple layers. The outer layers of the multiple layers are used to provide improved adhesion to the gap-filling layer.

[0105] Figure 12 A gap-filling layer 1202 formed over at least one of a substrate 102 or a buffer layer 1102, according to a partial embodiment, is illustrated. According to a partial embodiment, the gap-filling layer 1202 is in direct contact with the top surface of the substrate 102 and sidewalls defined in the substrate 102 (e.g., sidewalls defining recess 502 and sidewalls defining trench 902). In the case where the semiconductor structure 100 includes a buffer layer 1102 over the substrate 102, the gap-filling layer 1202 is in direct contact with at least one of the top surface of the buffer layer 1102 or the sidewalls of the buffer layer 1102. The gap-filling layer 1202 includes a metallic material, a dielectric material, a high-dielectric-constant dielectric material, silicon dioxide (SiO2), hafnium oxynitride (HfSiON), or hafnium silicate (HfSiO2). x ), Hafnium alumina (HfAlO) xThe gap-filling layer 1202 is formed using at least one of the following: hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), or other suitable materials. The gap-filling layer 1202 is formed using at least one of the following techniques: physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable techniques. The gap-filling layer 1202 is formed in at least one of the following: in the groove 502, in the trench 902, or on the top surface of the substrate 102. In some embodiments, the gap-filling layer 1202 covers the top surface of the substrate 102 and sidewalls defined in the substrate 102 (e.g., the sidewalls defining the groove 502 and the sidewalls defining the trench 902). In the case where the semiconductor structure 100 includes a buffer layer 1102 over the substrate 102, the buffer layer 1102 separates the gap filling layer 1202 from the substrate 102. Other structures and configurations of the gap filling layer 1202 are also within the scope of this disclosure.

[0106] A first portion 1202a of the gap filling layer 1202 is located in the recess 502. The first portion 1202a of the gap filling layer 1202 has a third tapered sidewall 1204, to which the first tapered sidewall 608 of the substrate 102 is aligned. In cases where the semiconductor structure 100 includes a buffer layer 1102 on the substrate 102, a portion of the buffer layer 1102 separates the third tapered sidewall 1204 of the first portion 1202a of the gap filling layer 1202 from the first tapered sidewall 608 of the substrate 102. In some embodiments, the first portion 1202a of the gap filling layer 1202 has a fourth tapered sidewall 1206, to which the second tapered sidewall 610 of the substrate 102 is aligned. In the case where the semiconductor structure 100 includes a buffer layer 1102 on the substrate 102, a portion of the buffer layer 1102 separates the fourth tapered sidewall 1206 of the first portion 1202a of the gap-filling layer 1202 from the second tapered sidewall 610 of the substrate 102. The first portion 1202a of the gap-filling layer 1202 covers the element 104. In some embodiments, at least one of the portion 1102a of the buffer layer 1102 or the portion 102a of the substrate 102 separates the first portion 1202a of the gap-filling layer 1202 from the element 104. Other structures and configurations of the gap-filling layer 1202 and the substrate 102 are also within the scope of this disclosure.

[0107] In some embodiments, a first portion 1202a of the gap-filling layer 1202 in the recess 502 defined in the substrate 102 is a high-absorption structure (e.g., at least one of the third conical sidewall 1204 of the first portion 1202a of the gap-filling layer 1202, the first conical sidewall 608 of the substrate 102, the fourth conical sidewall 1206 of the first portion 1202a of the gap-filling layer 1202, or the second conical sidewall 610 of the substrate 102 is at least partially a high-absorption structure). Compared to a lower substrate with a gap-filling layer that does not have a portion having one or more conical sidewalls and one or more corresponding conical sidewalls, the high-absorption structure can direct more radiation to the element 104 located below the first portion 1202a of the gap-filling layer 1202. One or more additional portions of the gap-filling layer in the recess 502 of the substrate 102 are high-absorption structures with a similar configuration covering the element 104. Other structures and configurations of high-absorption structures are also within the scope of this disclosure.

[0108] A second portion 1202b of the gap filler layer 1202 is located in the trench 902. The second portion 1202b of the gap filler layer 1202 has a third sidewall 1208, to which the first sidewall 1004 of the substrate 102 is aligned. According to some embodiments, the third sidewall 1208 of the second portion 1202b of the gap filler layer 1202 and the first sidewall 1004 of the substrate 102 are tapered. According to some embodiments, the third sidewall 1208 of the second portion 1202b of the gap filler layer 1202 and the first sidewall 1004 of the substrate 102 extend vertically. In the case where the semiconductor structure 100 includes a buffer layer 1102 located above the substrate 102, a portion of the buffer layer 1102 separates the third sidewall 1208 of the second portion 1202b of the gap filler layer 1202 from the first sidewall 1004 of the substrate 102. The second portion 1202b of the gap filling layer 1202 has a fourth sidewall 1210, to which the second sidewall 1006 of the substrate 102 is aligned. According to some embodiments, the fourth sidewall 1210 of the second portion 1202b of the gap filling layer 1202 and the second sidewall 1006 of the substrate 102 are tapered. According to some embodiments, the fourth sidewall 1210 of the second portion 1202b of the gap filling layer 1202 and the second sidewall 1006 of the substrate 102 extend vertically. In the case where the semiconductor structure 100 includes a buffer layer 1102 over the substrate 102, a portion of the buffer layer 1102 separates the fourth sidewall 1210 of the second portion 1202b of the gap filling layer 1202 from the second sidewall 1006 of the substrate 102. Other structures and configurations of the second portion 1202b of the gap filling layer 1202 are also within the scope of this disclosure.

[0109] In some embodiments, a second portion 1202b of the gap filler layer 1202 is laterally offset from element 104, and at least one of a portion 1102b of the buffer layer 1102 or a portion 102b of the substrate 102 separates the second portion 1202b of the gap filler layer 1202 from element 104. The second portion 1202b of the gap filler layer 1202 is located between two adjacent elements 104. In some embodiments, a first portion of the substrate 102 separates the second portion 1202b of the gap filler layer 1202 from the first portions of two adjacent elements 104, and a second portion of the substrate 102 separates the second portion 1202b of the gap filler layer 1202 from the second portions of two adjacent elements 104. Other structures and configurations of the second portion 1202b of the gap filler layer 1202 are also within the scope of this disclosure.

[0110] In some embodiments, the second portion 1202b of the gap-filling layer 1202 in the trench 902 defined in the substrate 102 is a deep trench isolation structure in the substrate 102. The deep trench isolation structure is a back-side deep trench isolation structure or a different type of deep trench isolation structure. In some embodiments, the deep trench isolation structure is laterally offset from the element 104, and a portion of the substrate 102 separates the deep trench isolation structure from the element 104. In some embodiments, the deep trench isolation structure is between two adjacent elements 104; that is, a first portion of the substrate 102 separates the deep trench isolation structure from the first elements of the two adjacent elements 104, and a second portion of the substrate 102 separates the deep trench isolation structure from the second elements of the two adjacent elements 104. Other structures and configurations of the deep trench isolation structure are also within the scope of this disclosure.

[0111] In some embodiments, a deep trench isolation structure is formed by forming a gap-filling layer 1202 in the trench 902. The deep trench isolation structure corresponds to the material in the trench 902 (e.g., at least one of a portion of the buffer layer 1102 or a portion of the gap-filling layer 1202). The deep trench isolation structure corresponds to the material filling the trench 902 (e.g., at least one of a portion of the buffer layer 1102 or a portion of the gap-filling layer 1202). The deep trench isolation structure is positioned between two adjacent elements 104 such that the deep trench isolation structure is laterally offset relative to a first element of the two adjacent elements 104 and laterally offset relative to a second element of the two adjacent elements 104. In some embodiments, the deep trench isolation structures are respectively disposed between two adjacent elements 104. Other structures and configurations of the deep trench isolation structure are also within the scope of this disclosure.

[0112] Figure 13A third dielectric layer 1302 formed over a gap-filling layer 1202 is illustrated according to a partial embodiment. In some embodiments, the third dielectric layer 1302 is in direct contact with the top surface of the gap-filling layer 1202. The third dielectric layer 1302 comprises at least one of oxides or other suitable materials. In some embodiments, the third dielectric layer 1302 comprises a material that is substantially optically transparent to the wavelength of radiation to be received by element 104 (e.g., near-infrared wavelengths). Other materials of the third dielectric layer 1302, as well as other radiation wavelengths that are substantially optically transparent to the material of the third dielectric layer 1302, are also within the scope of this disclosure. The third dielectric layer 1302 is formed by at least one of physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable techniques.

[0113] Figure 14 A gate structure 1402 formed above a third dielectric layer 1302 is illustrated according to a partial embodiment. In a partial embodiment, the gate structure 1402 is in direct contact with the top surface of the third dielectric layer 1302. The gate structure 1402 is positioned between elements 104 such that at least one of the gate structures 1402 does not cover or is laterally offset from an element 104. The gate structure 1402 is disposed between two adjacent elements 104 such that the gate structure 1402 covers a portion of the substrate 102 between the first element 104 and the second element 104. In a partial embodiment, at least some of the gate structures 1402 have at least one tapered sidewall. The gate structure 1402 comprises at least one of a dielectric material, an oxide, a metallic material, or other suitable material. In a partial embodiment, the gate structure 1402 is formed by forming one or more gate structure layers on the third dielectric layer 1302 and patterning one or more gate structure layers. One or more gate structure layers are formed using at least one of the following techniques: physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth, or other suitable techniques. One or more gate structure layers are patterned to form a gate structure 1402 using at least one of the following techniques: photoresist, hard mask layer, etching process, or other suitable techniques. In some embodiments, two adjacent gate structures 1402 provide an optical path through which radiation is guided by the two adjacent gate structures 1402 to an element 104 between the two adjacent gate structures 1402. Other structures and configurations of the gate structure 1402 are also within the scope of this disclosure.

[0114] Figure 15A passivation layer 1502 is illustrated, formed over at least one of a gate structure 1402 or a third dielectric layer 1302, according to a partial embodiment. In some embodiments, the passivation layer 1502 is in direct contact with at least one of the top surface of the third dielectric layer 1302, the sidewall of the gate structure 1402, or the top surface of the gate structure 1402. In some embodiments, a portion of the passivation layer 1502 covers the gate structure 1402. The passivation layer 1502 comprises an oxide or other suitable material. In some embodiments, the passivation layer 1502 comprises a material that is substantially optically transparent to the wavelength of radiation to be received by element 104 (e.g., near-infrared wavelengths). Other materials of the passivation layer 1502, as well as other radiation wavelengths that are substantially optically transparent to the material of the passivation layer 1502, are also within the scope of this disclosure. The passivation layer 1502 may be formed by at least one of physical vapor deposition, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, spin coating, growth or other suitable techniques.

[0115] Figure 16 A cross-sectional view of a semiconductor structure 1600 according to a partial embodiment is illustrated. The semiconductor structure 1600 includes at least some elements, structures, layers, features, etc., of the semiconductor structure 100. In some embodiments, the semiconductor structure 1600 includes one or more gaps 1602 (e.g., gaps containing air) between elements 104. The gaps 1602 are defined in at least a portion of a gap-filling layer 1202 of a trench 902 or deep trench isolation structure. In some embodiments, the gaps 1602 are between two sidewalls of a portion of the gap-filling layer 1202. The gaps 1602 are between a third sidewall 1208 and a fourth sidewall 1210 of a portion of the gap-filling layer. Other structures and configurations of the one or more gaps 1602 are also within the scope of this disclosure.

[0116] Figure 17 A cross-sectional view of a semiconductor structure 100 according to a partial embodiment is shown. Figure 17Radiation 1702 projected toward semiconductor structure 100 according to a partial embodiment is illustrated. At least some of the radiation 1702 passes through at least one of passivation layer 1502, third dielectric layer 1302, gap fill layer 1202, or portion of substrate 102, and at least some of the radiation 1702 is sensed, detected, or converted into electrons by element 104. A high-absorption structure (e.g., a portion of gap fill layer 1202 located in a recess 502 above element 104) can increase the amount of radiation 1702 (at least one of which is sensed, detected, or converted by element 104) compared to other sensors that do not have a high-absorption structure. In some embodiments, the increase in radiation is due to the high-absorption structure providing an improved optical path for directing radiation to element 104. In some embodiments, the improved optical path is achieved by having at least one of the high-absorption structures have a triangular shape or tapered sidewalls aligned with tapered sidewalls defined in substrate 102. In some embodiments, at least one of the high-absorption structures has a triangular shape or a tapered sidewall aligned with a tapered sidewall defined in the substrate 102, which reduces the amount of radiation projected toward the element 104 that is reflected or deflected away from the element 104 by the substrate 102. In some embodiments, radiation 1702 includes near-infrared radiation (e.g., radiation having wavelengths between about 700 nanometers and about 2500 nanometers). In some embodiments, radiation 1702 includes radiation with a wavelength of about 940 nanometers. Other radiation wavelengths that are sensed, detected, or converted by at least one of the elements 104 are also within the scope of this disclosure.

[0117] In some embodiments, the deep trench isolation structure (e.g., the gap fill layer 1202 in a portion of the trench 902 between elements 104) at least prevents or reduces crosstalk between elements 104. The deep trench isolation structure at least prevents or reduces radiation propagating from the first element 104 to the second element 104, or simply prevents or mitigates radiation away from the first element 104 when there is no second element adjacent to the first element 104. Radiation leaving the first element 104 is reflected back to the first element 104 by the deep trench isolation structure. In some embodiments, because the radiation is guided back to the first element 104, more radiation is detected or detected by the first element 104.

[0118] In some embodiments, a sensor having at least one of a high-absorption structure or a deep trench isolation structure may increase at least one of the sensor's modulation transfer function or spatial frequency response compared to other sensors that do not have at least one of a high-absorption structure or a deep trench isolation structure. The increase in at least one of the modulation transfer function or spatial frequency response is at least in part due to radiation being directed, pointed, reflected, etc., toward an element such as a photodiode. In some embodiments, a sensor having at least one of a high-absorption structure or a deep trench isolation structure may improve resolution compared to other sensors that do not have at least one of a high-absorption structure or a deep trench isolation structure. The improvement in resolution is at least in part attributed to radiation being directed, pointed, reflected, etc., toward an element such as a photodiode. In some embodiments, a sensor having at least one of a high-absorption structure or a deep trench isolation structure provides improved quantum efficiency (e.g., an increase in quantum efficiency of about 14%) for a sensor implemented via semiconductor structure 100 compared to other sensors that do not have at least one of a high-absorption structure or a deep trench isolation structure. Other increases in quantum efficiency are also within the scope of this disclosure. Therefore, at least one of the high-absorption structures or deep trench isolation structures provides an increase in radiation (e.g., near-infrared light radiation that is sensed, detected, converted into electrons, etc.). Other types of radiation with other wavelengths are also within the scope of this disclosure.

[0119] In some embodiments, the sensor is used to determine the distance between the sensor and surrounding objects. A sensor having at least one of a high-absorption structure or a deep trench isolation structure can determine the distance between the sensor and surrounding objects more accurately than other sensors that do not have at least one of a high-absorption structure or a deep trench isolation structure.

[0120] In some embodiments, the sensor is used to generate an image. Compared to other sensors that do not have at least one of a high absorption structure or a deep trench isolation structure, a sensor having at least one of a high absorption structure or a deep trench isolation structure can generate at least one of more accurate images or generate images with higher resolution.

[0121] In some embodiments, the sensor is used to generate a depth map indicating the distance between the sensor and surrounding objects. Compared to other sensors that do not have at least one of a high-absorption structure or a deep trench isolation structure, a sensor having at least one of a high-absorption structure or a deep trench isolation structure can generate a more accurate depth map or at least one of a depth map with higher resolution.

[0122] In some embodiments, this sensor is used by a vehicle for navigation based on the distance between the sensor and surrounding objects. A sensor having at least one of a high-absorption structure or a deep-groove isolation structure can provide more accurate vehicle navigation or reduce the likelihood of the vehicle contacting objects, compared to other sensors that do not have at least one of a high-absorption structure or a deep-groove isolation structure. The vehicle is an automated guided vehicle (AGV) or at least one of different types of vehicles. According to some embodiments, the vehicle operates in an environment with near-infrared light radiation. Other structures and configurations of the sensor are also within the scope of this disclosure.

[0123] Figure 18 A cross-sectional view of a semiconductor structure 1800 according to a partial embodiment is illustrated. The semiconductor structure 1800 includes at least some elements, structures, layers, features, etc., of at least one of semiconductor structures 100 or 1600. In some embodiments, the semiconductor structure 1800 includes a connection structure 1802. The connection structure 1802 comprises a conductive material (e.g., a metallic material or other suitable material). According to some embodiments, the semiconductor structure 1800 is connected to an external circuit via the connection structure 1802. According to some embodiments, the connection structure 1802 includes at least one of a metal pad or a metal terminal. Other structures and configurations of the connection structure 1802 are also within the scope of this disclosure.

[0124] In some embodiments, the semiconductor structure 1800 includes a first interconnect layer 1804. The first interconnect layer 1804 is located beneath at least one of the substrate 102 or the connection structure 1802. The first interconnect layer 1804 includes a patterned dielectric layer and a conductive layer providing interconnections (e.g., wiring) between at least one of various doped features, circuits, inputs / outputs, etc., of the semiconductor structure 1800. In some embodiments, the first interconnect layer 1804 includes an interlayer dielectric and a multilayer interconnect structure (e.g., at least one of contacts, vias, metal wires, or other types of structures). Other structures and configurations of the first interconnect layer 1804 are also within the scope of this disclosure. For illustrative purposes, the first interconnect layer 1804 includes conductors 1813, the location and configuration of which can vary according to design requirements.

[0125] In some embodiments, the second dielectric layer 108 or the first dielectric layer 112 ( Figure 18 At least one of the following (not shown) is located between the first interconnect layer 1804 and the substrate 102. In some embodiments, the first interconnect layer 1804 includes a second dielectric layer 108 or a first dielectric layer 112 (not shown). Figure 18At least one of the following (not shown). In some embodiments, at least one of the second dielectric layer 108 or the first dielectric layer 112 is not between the first interconnect layer 1804 and the substrate 102.

[0126] In some embodiments, the semiconductor structure 1800 includes a first wafer and a second wafer. The first wafer corresponds to a sensor wafer, while the second wafer corresponds to a logic wafer (e.g., an application-specific integrated circuit (ASIC) logic wafer). Other structures and configurations of the first and second wafers are also within the scope of this disclosure. The first wafer includes at least one of a first interconnect layer 1804, a connection structure 1802, and a first connection layer 1806, or at least some elements, structures, layers, features, etc., of semiconductor structures 100 and 1600. The second wafer includes at least one of a second connection layer 1808, a second interconnect layer 1810, or a second substrate 1812.

[0127] According to some embodiments, a first interconnect layer 1806 of a first wafer is connected to a second interconnect layer 1808 of a second wafer, for example, via an adhesive. The first interconnect layer 1806 includes a first conductive structure 1816 (e.g., a conductive structure (e.g., wiring) providing interconnection between at least one of various doped features, circuits, inputs / outputs, etc., of the semiconductor structure 1800). Other structures and configurations of the first interconnect layer 1806 and the first conductive structure 1816 are also within the scope of this disclosure. The second interconnect layer 1808 includes a second conductive structure 1818 (e.g., a conductive structure (e.g., wiring) providing interconnection between at least one of various doped features, circuits, inputs / outputs, etc., of the semiconductor structure 1800). Other structures and configurations of the second interconnect layer 1808 and the second conductive structure 1818 are also within the scope of this disclosure. In some embodiments, at least some of the first conductive structures 1816 are connected to at least some of the second conductive structures 1818.

[0128] The second interconnect layer 1810 is located beneath the second interconnect layer 1808. The second interconnect layer 1810 includes patterned dielectric and conductive layers that provide interconnections (e.g., wiring) between at least one of various doped features, circuits, and inputs / outputs of the semiconductor structure 1800. In some embodiments, the second interconnect layer 1810 includes an interlayer dielectric and a multilayer interconnect structure (e.g., at least one of contacts, vias, metal wires, or different types of structures). Other structures and configurations of the second interconnect layer 1810 are also within the scope of this disclosure. For illustrative purposes, the second interconnect layer 1810 includes conductors 1820, the location and configuration of which can vary according to design requirements.

[0129] In some embodiments, the second substrate 1812 is located below the second interconnect layer 1810. The second substrate 1812 includes at least one of the following: an epitaxial layer, a silicon-on-insulator structure, a wafer, or a die formed from a wafer. The second substrate 1812 includes at least one of the following materials: silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonybide, silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium gallium phosphide (InGaP), indium phosphide (InP), indium arsenide (InAs), indium antimonybide (InSb), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or other suitable materials. In some embodiments, the second substrate 1812 includes at least one doped region. Other structures and configurations of the second substrate 1812 are also within the scope of this disclosure. At least one or more shallow trench isolation (STI) regions 1826 and one or more doped well regions 1824 are disposed in the second substrate 1812. In some embodiments, at least one of the doped well regions 1824 includes a source / drain region 1814, or a source region or drain region is formed in the doped well region 1824. In some embodiments, a polysilicon structure 1822 covers at least one of the one or more doped well regions 1824. In some embodiments, the second substrate 1812 includes one or more transistors, wherein the polysilicon structure 1822 serves as the gate of the transistor, and the source / drain region 1814 serves as the source / drain region of the transistor. Other structures and configurations of the second substrate 1812, the one or more shallow trench isolation regions 1826, the doped well regions 1824, and the source / drain regions 1814 are also within the scope of this disclosure.

[0130] According to some embodiments, at least one of the one or more layers, features, structures, elements, etc. disclosed herein is in direct contact with another of the one or more layers, features, structures, elements, etc. disclosed herein. According to some embodiments, at least one of the one or more layers, features, structures, elements, etc. disclosed herein is not in direct contact with another of the one or more layers, features, structures, elements, etc. disclosed herein (e.g., there are one or more intermediate, separate layers, features, structures, and elements, etc.).

[0131] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first element in a substrate. The semiconductor structure includes a gap-filling layer. A first portion of the gap-filling layer covers the first element. The first portion of the gap-filling layer has tapered sidewalls. A first portion of the substrate separates the first portion of the gap-filling layer from the first element.

[0132] In some embodiments, a first portion of the substrate has a first tapered sidewall, and the tapered sidewall of a first portion of the gap-filling layer is aligned with the first tapered sidewall.

[0133] In some embodiments, a second portion of the gap-filling layer covers the first element; the second portion of the gap-filling layer has tapered sidewalls; and a first portion of the substrate has a second tapered sidewall, wherein the tapered sidewalls of the second portion of the gap-filling layer are aligned with the second tapered sidewalls.

[0134] In some embodiments, the first tapered sidewall of the first portion of the substrate has a first slope; the second tapered sidewall of the first portion of the substrate has a second slope; and the second slope is opposite in polarity to the first slope.

[0135] In some embodiments, a second portion of the gap-filling layer is laterally offset from the first element; and a second portion of the substrate separates the second portion of the gap-filling layer from the first element.

[0136] In some embodiments, the semiconductor structure includes: a second element located in a substrate, wherein: a second portion of a gap-filling layer is laterally offset from the second element; and the second portion of the gap-filling layer is between the first element and the second element.

[0137] In some embodiments, at least one of the following is true: the first element is a first photodiode; or the second element is a second photodiode.

[0138] In some embodiments, the semiconductor structure includes a buffer layer between a first portion of the substrate and a first portion of the gap-filling layer.

[0139] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first element in a substrate. The semiconductor structure includes a gap-filling layer. A first portion of the gap-filling layer covers the first element. A second portion of the gap-filling layer is laterally offset from the first element. A first portion of the substrate separates the second portion of the gap-filling layer from the first element.

[0140] In some embodiments, the semiconductor structure includes: a second element located in a substrate, wherein: a second portion of a gap-filling layer is laterally offset from the second element; and the second portion of the gap-filling layer is between the first element and the second element.

[0141] In some embodiments, the second portion of the substrate separates the second portion of the gap-filling layer from the second element.

[0142] In some embodiments, the second portion of the gap-filling layer has a tapered sidewall.

[0143] In some embodiments, at least one of the following is true: the first element is a first photodiode; or the second element is a second photodiode.

[0144] In some embodiments, the first portion of the gap-filling layer has tapered sidewalls.

[0145] In some embodiments, a second portion of the substrate separates a first portion of the gap-filling layer from the first element; and the tapered sidewalls of the second portion of the substrate are aligned with the tapered sidewalls of the first portion of the gap-filling layer.

[0146] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first recess in a substrate, wherein the first recess covers a first element in the substrate. The method also includes forming a first trench in the substrate, wherein the first trench is located between a first element and a second element in the substrate. The method further includes forming a gap-filling layer in the first recess and the first trench, such that a first portion of the gap-filling layer covers the first element, and a second portion of the gap-filling layer is located between the first element and the second element.

[0147] In some embodiments, forming the first groove includes forming a first groove having tapered sidewalls.

[0148] In some embodiments, the method for forming a semiconductor structure includes: forming a second groove in a substrate, wherein the second groove covers a first element and has tapered sidewalls; and forming a gap-filling layer in the second groove such that a third portion of the gap-filling material covers the first element.

[0149] In some embodiments, forming the first trench includes forming a first trench having tapered sidewalls.

[0150] In some embodiments, forming the first groove includes: forming a hard mask layer on a substrate; patterning the hard mask layer to produce a patterned hard mask layer; and etching the substrate using the patterned hard mask layer to form the first groove.

[0151] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose or benefits as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them without departing from the spirit and scope of this disclosure.

[0152] Although this disclosure has been described using language specific to structural features or method steps, it should be understood that the scope of the appended claims is not limited to the specific features or steps described above. Rather, the specific features and steps described above are exemplary forms for implementing at least some of the claims.

[0153] Various steps are provided in the embodiments herein. The order of some or all of the steps described in this disclosure should not be construed as implying that these steps must necessarily be in sequence. Alternative orderings will be appreciated with the aid of this description. Furthermore, it should be understood that not all steps are necessarily present in every embodiment provided in this disclosure. Moreover, it should be understood that not all steps are necessary in some embodiments.

[0154] It should be understood that, for example for the purposes of simplification and ease of understanding, the layers, features, elements, etc. depicted in this disclosure are shown with specific dimensions (e.g., structural dimensions or orientations) relative to each other, and in some embodiments, their actual dimensions are substantially different from those shown in this disclosure. Furthermore, there are various techniques available for forming the layers, regions, features, elements, etc. mentioned in this disclosure (e.g., etching techniques, planarization techniques, implantation techniques, doping techniques, spin coating techniques, sputtering techniques, growth techniques, or at least one of deposition techniques such as chemical vapor deposition).

[0155] Furthermore, the term "embodiment" in this disclosure is used as an example, instance, illustration, etc., and is not necessarily advantageous. As used in this disclosure, "or" is intended to mean an inclusive "or" rather than an exclusive "or". Additionally, "a" and "an" as used in this disclosure and the appended claims are generally interpreted as "one or more" unless otherwise stated or clearly indicated from the context as singular. Furthermore, at least one of A and B generally refers to A or B, or both A and B. Moreover, to a certain extent, terms such as "comprising," "having," "including," "comprise," or similar terms are used, which are intended to include in a manner similar to the term "comprising." Additionally, unless otherwise stated, "first," "second," etc., do not imply temporal, spatial, or sequential aspects. Rather, such terms are used only as identifiers, names, etc., for features, elements, components, etc. For example, a first element and a second element generally correspond to element A and element B, or two different elements, or two similar elements, or the same element.

[0156] Furthermore, although this disclosure has been illustrated and described by way of one or more embodiments, equivalent changes and modifications will arise for those skilled in the art upon reading and understanding of this disclosure and the accompanying drawings. This disclosure includes all such modifications and changes and is limited only by the scope of the appended claims. In particular, regarding the various functions performed by the foregoing elements (e.g., elements, methods, etc.), unless otherwise stated, the terminology used to describe such elements is intended to correspond to any element that performs the specific function of the described element (e.g., functionally equivalent), even if it is not structurally equivalent to the disclosed structure. Additionally, while specific features of this disclosure may be disclosed only for one of several embodiments, such features may be combined with one or more other features of other embodiments if they are desirable and advantageous for any given or particular application.

Claims

1. A semiconductor structure, characterized by, Comprising: a first element in a substrate; a gap fill layer, wherein: a first portion of the gap fill layer covers the first element; the first portion of the gap fill layer is a deep trench isolation structure and has a tapered sidewall; the first portion of the gap fill layer includes an air gap disposed between a bottom of the first portion of the gap fill layer and a top surface of the substrate; a first portion of the substrate separates the first portion of the gap fill layer from the first element; and a distance between the top surface of the substrate and the bottom of the first portion of the gap fill layer covering the first element is between 500 angstroms and 10,000 angstroms; a buffer layer disposed at least between the first portion of the substrate and the first portion of the gap fill layer and at least partially and laterally extending to a perimeter of the air gap to cover the air gap, wherein the buffer layer includes a high dielectric constant dielectric material, a material of the substrate includes silicon, gallium arsenide, gallium nitride, or indium antimonide, the gap fill layer includes a metallic material, the high dielectric constant dielectric material of the buffer layer directly contacts the material of the substrate and the metallic material of the gap fill layer, and a perimeter of the air gap is surrounded by the metallic material of the gap fill layer; a gate below the substrate; and a source / drain region below the gate.

2. The semiconductor structure of claim 1, wherein, The first portion of the substrate has a first tapered sidewall, and the tapered sidewall of the first portion of the gap fill layer is aligned with the first tapered sidewall.

3. The semiconductor structure of claim 2, wherein: a second portion of the gap fill layer covers the first element; the second portion of the gap fill layer has a tapered sidewall; and the first portion of the substrate has a second tapered sidewall, wherein the tapered sidewall of the second portion of the gap fill layer is aligned with the second tapered sidewall.

4. The semiconductor structure of claim 3, wherein: the first tapered sidewall of the first portion of the substrate has a first slope; the second tapered sidewall of the first portion of the substrate has a second slope; and the second slope is opposite in polarity to the first slope.

5. The semiconductor structure of claim 1, wherein: a second portion of the gap fill layer is laterally offset from the first element; and a second portion of the substrate separates the second portion of the gap fill layer from the first element.

6. The semiconductor structure of claim 5, wherein, Comprising: a second element in the substrate, wherein: the second portion of the gap fill layer is laterally offset from the second element; and the second portion of the gap fill layer is between the first element and the second element.

7. The semiconductor structure of claim 6, wherein, At least one of: the first element is a first photodiode; or the second element is a second photodiode.

8. The semiconductor structure of claim 1, wherein, wherein the high-k dielectric material of the buffer layer comprises hafnium silicon oxynitride (HfSiON), hafnium silicate (HfSiOx), hafnium aluminum oxide (HfAlO x ), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3).

9. A semiconductor structure, characterized by Comprising: a first element in a substrate; a gap fill layer, wherein: a first portion of the gap fill layer is a deep trench isolation structure and covers the first element; The first portion of the gap fill layer includes an air gap disposed between a bottom of the first portion of the gap fill layer and a top surface of the substrate; A second portion of the gap fill layer is laterally offset from the first element; A first portion of the substrate separates the second portion of the gap fill layer from the first element; and A distance between the top surface of the substrate and the bottom of the first portion of the gap fill layer covering the first element is between 500 angstroms and 10,000 angstroms; A buffer layer is disposed at least between the first portion of the substrate and the first portion of the gap fill layer and at least partially and laterally extends to a periphery of the air gap to cover the air gap, wherein the buffer layer includes a high-k dielectric material, a material of the substrate includes silicon, gallium arsenide, gallium nitride, or indium antimonide, the gap fill layer includes a metallic material, the high-k dielectric material of the buffer layer directly contacts the material of the substrate and the metallic material of the gap fill layer, and a periphery of the air gap is surrounded by the metallic material of the gap fill layer; A gate is located below the substrate; and A source / drain region is located below the gate.

10. The semiconductor structure of claim 9, wherein, includes: a second element located in the substrate, wherein: the second portion of the gap fill layer is laterally offset from the second element; and the second portion of the gap fill layer is between the first element and the second element.

11. The semiconductor structure of claim 10, wherein, A second portion of the substrate separates the second portion of the gap fill layer from the second element.

12. The semiconductor structure of claim 9, wherein, The second portion of the gap fill layer has a tapered sidewall.

13. The semiconductor structure of claim 10, wherein, at least one of: the first element is a first photodiode; or the second element is a second photodiode.

14. The semiconductor structure of claim 9, wherein, The first portion of the gap fill layer has a tapered sidewall.

15. The semiconductor structure of claim 14, wherein: a second portion of the substrate separates the first portion of the gap fill layer from the first element; and a tapered sidewall of the second portion of the substrate is aligned with the tapered sidewall of the first portion of the gap fill layer.

16. A method of manufacturing a semiconductor structure, characterized by, includes: forming a first recess in a substrate, wherein the first recess covers a first element in the substrate; forming a first trench in the substrate, wherein the first trench is between the first element and a second element in the substrate; forming a buffer layer in the first recess and the first trench; forming a gap fill layer in the first recess and the first trench and over the buffer layer such that a first portion of the gap fill layer covers the first element, the first portion of the gap fill layer is a deep trench isolation structure, and includes an air gap disposed between a bottom of the first portion of the gap fill layer and a top surface of the substrate, and a second portion of the gap fill layer is between the first element and the second element, wherein a distance between the top surface of the substrate and the bottom of the first portion of the gap fill layer covering the first element is between 500 angstroms and 10,000 angstroms, and wherein the buffer layer is disposed at least between the first portion of the substrate and the first portion of the gap fill layer and at least partially extends to a periphery of the air gap to cover the air gap, the buffer layer comprises a high dielectric constant dielectric material, a material of the substrate comprises silicon, gallium arsenide, gallium nitride, or indium antimonide, the gap fill layer comprises a metallic material, the high dielectric constant dielectric material of the buffer layer directly contacts the material of the substrate and the metallic material of the gap fill layer, and a periphery of the air gap is surrounded by the metallic material of the gap fill layer; forming an interconnect layer over a transistor, wherein the transistor has a gate and a source / drain region below the gate; and adhering the interconnect layer to the substrate after forming the interconnect layer over the transistor, wherein the transistor is separated from the substrate by the interconnect layer.

17. The method of claim 16, wherein, Forming the first recess includes forming the first recess with a tapered sidewall.

18. The method of claim 17, wherein, comprising: forming a second recess in the substrate, wherein the second recess covers the first element and has a tapered sidewall; and forming the gap fill layer in the second recess such that a third portion of the gap fill layer covers the first element.

19. The method of claim 16, wherein, Forming the first trench includes forming the first trench with a tapered sidewall.

20. The method of claim 16, wherein, Forming the first recess includes: forming a hard mask layer on the substrate; patterning the hard mask layer to produce a patterned hard mask layer; and etching the substrate using the patterned hard mask layer to form the first recess.

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