Semiconductor devices and their manufacturing methods

Abstract

A semiconductor device includes a substrate, a capacitor structure disposed on the substrate, and an interconnect structure. The capacitor structure is disposed on the substrate and located in a capacitor structure region, and includes a lower electrode plate, an upper electrode plate, a stacked dielectric layer, and an intermediate dielectric layer. The upper electrode plate is disposed above the lower electrode plate, and the stacked dielectric layer is disposed between the lower electrode plate and the upper electrode plate. The intermediate dielectric layer is disposed between the lower electrode plate and the upper electrode plate, and is located only in the capacitor structure region. The dielectric constant of the intermediate dielectric layer is higher than the dielectric constant of the stacked dielectric layer. The interconnect structure includes at least one plug and a metal stack, and the interconnect structure is located in a connection region adjacent to the capacitor structure region and is disposed on at least one side of the intermediate dielectric layer.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a semiconductor device having a high-voltage capacitor structure. Background Technology

[0002] For semiconductor devices with high-voltage components, these components are typically electrically connected to a high-voltage source, such as a 1kV to 15kV DC or AC voltage source. When the high-voltage component is a capacitor structure integrated into the interconnect fabrication process, the dielectric layer in the capacitor structure is usually composed of the inter-metal dielectric (IMD) layer of the semiconductor device. Since the withstand voltage of a capacitor structure or semiconductor device is related to the thickness of the dielectric layer in the capacitor structure, increasing the thickness of the dielectric layer is a common practice to increase the withstand voltage of the capacitor structure or semiconductor device.

[0003] However, while the above approach can increase the voltage withstand capability of capacitor structures or semiconductor devices, it also introduces other technical problems. For example, since the dielectric layer in the capacitor structure is composed of the inter-metal dielectric layer of the semiconductor device, increasing the thickness of the dielectric layer in the capacitor structure will inevitably increase the thickness of the inter-metal dielectric layer as well, causing unnecessary warping of the semiconductor device substrate. Furthermore, the change in the thickness of the inter-metal dielectric layer also affects the fabrication process of the inter-metal dielectric layer, thus negatively impacting the original fabrication process of the semiconductor device.

[0004] Therefore, it is necessary to provide an improved semiconductor device and its manufacturing method to overcome the deficiencies in the prior art. Summary of the Invention

[0005] Therefore, the present invention provides a semiconductor device and a method for manufacturing the same, in order to solve the technical problems faced by the prior art.

[0006] According to an embodiment of the present invention, a semiconductor device is provided, including a substrate, a capacitor structure disposed on the substrate, and an interconnect structure. The capacitor structure is disposed on the substrate and located in a capacitor structure region, and includes a lower electrode plate, an upper electrode plate, a stacked dielectric layer, and an intermediate dielectric layer. The upper electrode plate is disposed above the lower electrode plate, and the stacked dielectric layer is disposed between the lower electrode plate and the upper electrode plate. The intermediate dielectric layer is disposed between the lower electrode plate and the upper electrode plate, and is located only in the capacitor structure region. The dielectric constant of the intermediate dielectric layer is higher than the dielectric constant of the stacked dielectric layer. The interconnect structure includes at least one plug and a metal stack, and the interconnect structure is located in a connection region adjacent to the capacitor structure region and is disposed on at least one side of the intermediate dielectric layer.

[0007] According to another embodiment of the present invention, a method for fabricating a semiconductor device is provided. The method includes: providing a substrate; forming a lower electrode plate on the substrate; forming at least one sub-dielectric layer on the lower electrode plate; forming a dielectric layer on the at least one sub-dielectric layer; patterning the dielectric layer to form an intermediate dielectric layer, wherein the intermediate dielectric layer exposes a portion of the at least one sub-dielectric layer; etching the portion of the at least one sub-dielectric layer not covered by the intermediate dielectric layer to form a hole; filling at least one plug into the hole; and forming an upper electrode plate on the intermediate dielectric layer.

[0008] According to an embodiment of the present invention, by providing an intermediate dielectric layer with a high dielectric constant between the stacked dielectric layer and the upper electrode plate, the breakdown voltage of the capacitor structure and the semiconductor device can be increased without increasing the distance between the upper electrode plate and the lower electrode plate in the capacitor structure, thereby improving the withstand voltage capability of the corresponding semiconductor device. Attached Figure Description

[0009] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0010] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0011] Figure 3 This is a schematic cross-sectional view of a semiconductor device after the formation of an intermediate dielectric layer, according to an embodiment of the present invention.

[0012] Figure 4 This is a cross-sectional schematic diagram of a semiconductor device after a patterned intermediate dielectric layer, according to an embodiment of the present invention.

[0013] Figure 5 This is a schematic cross-sectional view of a semiconductor device after the plug has been formed, according to an embodiment of the present invention.

[0014] Figure 6 This is a schematic cross-sectional view of a semiconductor device after the upper electrode plate forming the capacitor structure, according to an embodiment of the present invention.

[0015] Figure 7 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0016] The annotations in the attached figures are explained as follows:

[0017] 100: Semiconductor device; 102: Substrate; 104: Capacitor structure region; 106: Interconnect region; 108: Interconnect structure; 110: Transistor; 112: Insulating structure; 114: Front metal dielectric layer; 116: Sub-dielectric layer; 118: Sub-dielectric layer; 120: Sub-dielectric layer; 122: Sub-dielectric layer; 130: Stacked dielectric layer; 132: Dielectric layer; 134: Intermediate dielectric layer; 136: Outer surface; 138: Intermediate dielectric layer; 140: Outer surface; 148: Conductive layer; 150: Lower electrode plate; 152: Upper electrode plate; 154: Outer surface; 156: Capacitor dielectric layer; 160: Top dielectric layer; 162: Protective shield; 200: Semiconductor device; 300: Semiconductor device; 700: Fabrication method; 702: Step; 704: Step; 706: Step; 708: Step; 710: Step; 712: Step; D1: Depth; M1, M2~M n-1 : Intermediate metal layer; M n Top metal layer; P1: Conductive contact structure; T0: Thickness; T1: Thickness; T2: Thickness; V1, V2 ~ V n-1 : Plug; W1: Width; W2: Width; W3: Width Detailed Implementation

[0018] This invention provides several different embodiments that can be used to implement different features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting.

[0019] In this invention, the description of "a first component forming on or above a second component" can refer to either "the first component and the second component are in direct contact" or "there are other components between the first component and the second component" so that the first component and the second component are not in direct contact. Furthermore, various embodiments of this invention may use repeated component symbols and / or textual annotations. The use of these repeated component symbols and textual annotations is for the purpose of making the description more concise and clear, rather than to indicate any correlation between different embodiments and / or configurations.

[0020] Furthermore, regarding the spatially related descriptive terms mentioned in this invention, such as "below," "above," "low," "high," "below," "above," "under," "above," "bottom," "top," and similar terms, for ease of description, their usage is to describe the relative relationship between one component or feature and another (or more) components or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientation of the semiconductor device during manufacturing, use, and operation. For example, when the semiconductor device is rotated 180 degrees, a component that was originally positioned "above" other components will become positioned "below" other components. Therefore, as the orientation of the semiconductor device changes (rotates 90 degrees or other angles), the spatially related descriptions used to describe its orientation should also be interpreted accordingly.

[0021] Although this invention uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that such elements, components, regions, layers, and / or sections should not be limited by such terminology. Such terminology is only used to distinguish one element, component, region, layer, and / or section from another, and does not in itself imply or represent any prior ordinal number of the elements, nor does it represent the arrangement order of one element with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of this invention, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section.

[0022] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific specification.

[0023] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means or connections.

[0024] It should be noted that the "dielectric constant (ε)" referred to in this invention... r"Relative permittivity" refers to the relative permittivity, the value of which is measured at room temperature (25℃) and an electric field of 1kHz.

[0025] Although the invention is described below by way of specific embodiments, the principles of the invention can also be applied to other embodiments. Furthermore, to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details fall within the scope of knowledge of those skilled in the art.

[0026] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device 100 includes a substrate 102 and a high-voltage component region, such as a capacitor structure region 104, and an interconnect region 106, such as an interconnect structure 108. The interconnect region 106 may also include a transistor 110. Wherein, if the high-voltage component is a capacitor structure, the capacitor structure 104 may include a lower electrode plate 150, an upper electrode plate 152, a capacitor dielectric layer 156 (composed of a portion of the stacked dielectric layer 130) disposed between the lower electrode plate 150 and the upper electrode plate 152, and an intermediate dielectric layer 134 disposed between the upper electrode plate 152 and the lower electrode plate 150. According to an embodiment of the present invention, the intermediate dielectric layer 134 is preferably a single-layer structure directly contacting the upper electrode plate 152 and the stacked dielectric layer 130, and the relative permittivity of the intermediate dielectric layer 134 is higher than that of the stacked dielectric layer 130. By additionally providing an intermediate dielectric layer 134 between the upper electrode plate 152 and the capacitor dielectric layer 156, the breakdown voltage of the capacitor structure and semiconductor device 100 within the capacitor structure region 104 can be improved. For example, when a high DC or AC voltage is applied to the electrode plate 152, the capacitor structure and semiconductor device 100 within the capacitor structure region 104 can still maintain a high breakdown voltage. In another embodiment, the intermediate dielectric layer 134 can be disposed between any two adjacent sub-dielectric layers 116, 118, 120, and the intermediate dielectric layer 134 is located only within the capacitor structure region 104. Referring again... Figure 1The semiconductor device 100 is disposed on a substrate 102, such as a silicon substrate, a ceramic substrate, or a silicon-on-insulator (SOI) substrate. The substrate 102 may include an insulating structure 112, such as shallow trench isolation (STI), allowing the substrate 102 to be isolated into different regions. Different semiconductor components, such as transistor 110, may be disposed on the surface of the substrate 102, but are not limited thereto. A pre-metal dielectric (PMD) 114 may be disposed on the surface of the substrate 102, which may cover the transistor 110, and may contain conductive contact structures P1 electrically connected to the substrate 102 or the transistor 110. A stacked dielectric layer 130 may be disposed above the pre-metal dielectric layer 114, and the stacked dielectric layer 130 may include multiple sub-dielectric layers, such as sub-dielectric layers 116, 118, 120, and 122. Interconnect structures 108 can be provided in the sub-dielectric layers 116, 118, 120, and 122, wherein the interconnect structure 108 may include at least a metal stack and at least one plug. For example, the metal stack may include intermediate metal layers M1, M2 to M... n-1 and top metal layer M n The conductor stack, and at least one plug may include multiple plugs V1, V2 to V3. n-1 And the value of n can be any positive integer greater than or equal to 7, for example, equal to 7. The intermediate metal layers M1, M2~M... in the interconnect structure 108 n-1 and top metal layer M n It can be electrically connected to the corresponding plugs V1, V2~V n-1 Furthermore, the interconnect structure 108 can serve as a transmission path for electrical signals of the semiconductor device 100. In cases where the semiconductor device 100 includes high-voltage components such as capacitors, the interconnect structure 108 can also be configured as a Faraday cage to shield the electric field from the high-voltage components.

[0027] For the capacitor structure within the capacitor structure region 104, according to one embodiment of the present invention, the lower electrode plate 150 and the upper electrode plate 152 may each include a pair of sub-electrodes. However, according to another embodiment of the present invention, the lower electrode plate 150 and the upper electrode plate 152 may each be a single electrode without any sub-electrodes. The capacitor dielectric layer 156 and the intermediate dielectric layer 134 disposed between the lower electrode plate 150 and the upper electrode plate 152 affect the breakdown voltage of the capacitor structure within the capacitor structure region 104. The capacitor dielectric layer 156 may be composed of a portion of the stacked dielectric layer 130, and the thickness ratio between the stacked dielectric layer 130 and the intermediate dielectric layer 134 may be between approximately 10:1 and 30:1, but is not limited thereto. According to an embodiment of the present invention, by extending at least one outer side 136 of the intermediate dielectric layer 134 beyond at least one outer side 154 of the upper electrode plate 152, the overall width W2 of the intermediate dielectric layer 134 is greater than the sum of the widths W1 of the upper electrode plate 152. Furthermore, by making the thickness T1 of the intermediate dielectric layer 134 covered by the upper electrode plate 152 greater than the thickness T2 of the intermediate dielectric layer 134 not covered by the upper electrode plate 152, the capacitor structure in the capacitor structure region 104 and the breakdown voltage of the semiconductor device 100 can be further improved.

[0028] Furthermore, according to one embodiment of the present invention, the intermediate dielectric layer 134 is only disposed within the capacitor structure region 104 and does not extend outward to the interconnect structure 108. In one embodiment, the top metal layer M... n It will not directly contact the intermediate dielectric layer 134, but will directly contact the stacked dielectric layer 130. Therefore, the high voltage from the upper electrode plate 152 will not be transmitted to the top metal layer M via the stacked dielectric layer 130. n This also improves the breakdown voltage of the semiconductor device 100, reduces the resistance-capacitance delay (RC-Delay) of the interconnect region 106, and simplifies the manufacturing process.

[0029] A top dielectric layer 160 may also be disposed above the stacked dielectric layer 130, and the top dielectric layer 160 may surround the upper electrode plate 152 and the top metal layer M. n And directly contact the upper electrode plate 152 and the stacked dielectric layer 130, so that the upper electrode plate 152 and the top metal layer M n It can be embedded in the top dielectric layer 160. A protective shield 162 can also be provided above the top dielectric layer 160. The protective shield 162 and the top dielectric layer 160 can have openings to accommodate solder pads (not shown) that are electrically connected to the upper electrode plate 152.

[0030] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 2 The semiconductor device 200 shown is similar to... Figure 1 The semiconductor device 100 and semiconductor device 200 shown also include high-voltage components, such as capacitor structure region 104. However, in addition to the intermediate dielectric layer 134, semiconductor device 200 also includes another intermediate dielectric layer 138. The intermediate dielectric layer 138 is embedded in the stacked dielectric layer 130, for example, embedded in a sub-dielectric layer 118, and the dielectric constant of the intermediate dielectric layer 138 is higher than the average dielectric constant of the entire stacked dielectric layer 130, or higher than the dielectric constant of any of the sub-dielectric layers 116, 118, or 120 of the stacked dielectric layer 130. The ratio of the thickness of the stacked dielectric layer 130 disposed between the lower electrode plate 150 and the upper electrode plate 152 to the thickness of the intermediate dielectric layer 138 can be between 10:1 and 30:1, but is not limited to this. Furthermore, at least one outer side 140 of the intermediate dielectric layer 138 extends beyond at least one outer side 154 of the upper electrode plate 152, such that the overall width W3 of the intermediate dielectric layer 138 is greater than the sum of the widths W1 of the upper electrode plate 152. By providing at least two intermediate dielectric layers 134 and 138 between the lower electrode plate 150 and the upper electrode plate 152, the breakdown voltage of the capacitor structure 104 can be further improved.

[0031] To enable those skilled in the art to implement the invention described herein, the method for manufacturing the semiconductor device of the present invention is further described in detail below.

[0032] Figure 3 This is a schematic cross-sectional view of a semiconductor device after the formation of an intermediate dielectric layer, according to an embodiment of the present invention. Figure 7 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. (Refer to...) Figure 3 The manufacturing process performs step 702 of method 700 to provide a semiconductor device 300, which includes at least a front metal dielectric layer 114, a stacked dielectric layer 130, an interconnect structure 108, and a lower electrode plate 150. Optionally, the semiconductor device 300 may further include a transistor 110, a conductive contact structure P1, and intermediate metal layers M1, M2, and M3. n-1 And components such as plugs V1 and V2. The sub-dielectric layers 116, 118, and 120 in the front metal dielectric layer 114 and the stacked dielectric layer 130 can, for example, be formed on the substrate 102 by chemical vapor deposition. The sub-dielectric layers 116, 118, and 120 can have the same or different compositions; for example, they can all be silicon oxide (SiO2). Furthermore, the lower electrode plate 150 and the intermediate metal layer M1 disposed on the surface of the front metal dielectric layer 114 can be formed via the same process, therefore the lower electrode plate 150 and the intermediate metal layer M1 can have the same composition.

[0033] Next, step 704 is performed to form a dielectric layer 132 on the stacked dielectric layer 130. For example, chemical vapor deposition can be used to form a oriented dielectric layer 132 on the surface of the stacked dielectric layer 130, with a thickness T0 of about 0.5 to 1.0 micrometers (μm), for example, 0.7 μm, but not limited thereto. The dielectric layer 132 can be a monolayer structure that directly contacts the stacked dielectric layer 130, and the dielectric constant of the dielectric layer 132 is higher than the average dielectric constant of the entire stacked dielectric layer 130, or higher than the dielectric constant of each sub-dielectric layer 116, 118, 120 in the stacked dielectric layer 130. For example, the dielectric layer 132 can be silicon nitride (Si3N4), silicon oxynitride (SiON), or silicon carbide (SiC), while each sub-dielectric layer 116, 118, 120 can be silicon oxide (SiO2), but not limited thereto. According to one embodiment of the present invention, a specific region of the stacked dielectric layer 130 can serve as a capacitor dielectric layer 156. Therefore, in the case where the stacked dielectric layer 130 includes sub-dielectric layers 116, 118, and 120, the capacitor dielectric layer 156 will also include sub-dielectric layers 116, 118, and 120.

[0034] Figure 4 This is a schematic cross-sectional view of a semiconductor device after a patterned intermediate dielectric layer, according to an embodiment of the present invention. (Refer to...) Figure 4 Step 706 involves etching the dielectric layer 132 to form a patterned intermediate dielectric layer 134. The dielectric layer 132 within the interconnect region 106 can be removed using appropriate photolithography and etching processes. During the formation of the intermediate dielectric layer 134, a portion of the sub-dielectric layer 120 is also etched away, creating a depression of depth D1 on the surface of the sub-dielectric layer 120. Next, a deposition process and a planarization process can be performed to form another sub-dielectric layer 122 that fills the depression and surrounds the intermediate dielectric layer 134. In one embodiment, the thicknesses T1 and T2 of the intermediate dielectric layer 134 can be approximately 0.3 to 0.8 micrometers (μm). For example, the thicknesses T1 and T2 of the intermediate dielectric layer 134 are preferably greater than 0.35 micrometers (μm) to avoid damage during subsequent etching of the conductive layer 148. The dielectric constant of the intermediate dielectric layer 134 is higher than that of the sub-dielectric layer 122.

[0035] Figure 5 This is a schematic cross-sectional view of a semiconductor device after the plug has been formed, according to an embodiment of the present invention. (Refer to...) Figure 5 Step 708 is performed, forming plugs electrically connected to the interconnect structure 108 in the stacked dielectric layer 130. Photolithography and etching processes can be performed to form holes in the sub-dielectric layers 120 and 122 not covered by the intermediate dielectric layer 134, wherein the holes can penetrate the sub-dielectric layers 120 and 122 and expose the intermediate metal layer M. n-1Next, processes such as metal deposition and metal planarization are performed to form plug V-shaped structures within the holes. n-1 Among them, the plug V n-1 The top surface of the intermediate dielectric layer 134 is roughly flush with the top surface of the intermediate dielectric layer 134. A conductive layer 148, such as a conductive metal layer, is deposited comprehensively on the intermediate dielectric layer 134 and the sub-dielectric layer 122.

[0036] Figure 6 This is a schematic cross-sectional view of a semiconductor device after the upper electrode plate of the capacitor structure is formed, according to an embodiment of the present invention. After fabricating... Figure 5 After the structure shown, refer to Figure 6 Then, step 710 can be performed to form an upper electrode plate 152 on the patterned intermediate dielectric layer 134, and simultaneously form an electrical connection to the plug V. n-1 Top metal layer M n To obtain such Figure 6 The structure shown can be fabricated simultaneously by performing photolithography and etching processes to etch the conductive layer 148, thereby obtaining the upper electrode plate 152 and the top metal layer M. n Due to the upper electrode plate 152 and the top metal layer M n They can be formed through the same process, therefore the upper electrode plate 152 and the top metal layer M n They can have the same composition. During the etching process, the upper electrode plate 152 and the top metal layer M are not affected. n The intermediate dielectric layer 134 and the sub-dielectric layer 122 that are covered will also be partially etched away. Therefore, the intermediate dielectric layer 134 can have different thicknesses, such as thickness T1 and thickness T2.

[0037] After completion Figure 6 After the structure shown, refer to Figure 1 Then, step 712 can be performed to form the top dielectric layer 160, which covers the patterned intermediate dielectric layer 134, the upper electrode plate 152, and the top metal layer M. n A top dielectric layer 160 can be formed by performing a deposition and planarization process. Then, another deposition and planarization process can be performed to form a protective mask 162 covering the top dielectric layer 160. The top dielectric layer 160 may be composed of silicon oxide, and the protective mask 162 may be composed of silicon nitride, but is not limited thereto.

[0038] According to the above embodiments of the present invention, by providing an intermediate dielectric layer 134 with a high relative permittivity between the lower electrode plate 150 and the upper electrode plate 152, the breakdown voltage of the capacitor structure and the semiconductor devices 100 and 200 can be increased without increasing the distance between the upper electrode plate 152 and the lower electrode plate 150 in the capacitor structure, and without affecting the original interconnect structure 108 process, thereby improving the withstand voltage capability of the corresponding semiconductor devices 100 and 200.

[0039] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, characterized by comprising: The semiconductor device comprises: a substrate; a capacitor structure disposed on the substrate and located in a capacitor structure region, wherein the capacitor structure comprises: a lower electrode plate; an upper electrode plate disposed on the lower electrode plate; a stack dielectric layer disposed between the lower electrode plate and the upper electrode plate; an intermediate dielectric layer disposed between the lower electrode plate and the upper electrode plate, wherein the intermediate dielectric layer is located only in the capacitor structure region and has a dielectric constant higher than that of the stack dielectric layer, wherein the upper electrode plate covers part of the intermediate dielectric layer, and the thickness of the part of the intermediate dielectric layer covered by the upper electrode plate is greater than that of other parts of the intermediate dielectric layer; and an interconnection structure comprising at least one plug and a metal stack, wherein the interconnection structure is located in a wire region adjacent to the capacitor structure region, and the interconnection structure is disposed on at least one side of the intermediate dielectric layer. The thickness ratio between the stack dielectric layer and the intermediate dielectric layer is 10:1 to 30:

1.

2. The semiconductor device according to claim 1, wherein The composition of the stack dielectric layer comprises silicon oxide, and the composition of the intermediate dielectric layer comprises silicon nitride, silicon oxynitride or silicon carbide.

3. The semiconductor device according to claim 1, wherein The outer side surface of the intermediate dielectric layer extends beyond the outer side surface of the upper electrode plate.

4. The semiconductor device according to claim 1, wherein The intermediate dielectric layer is disposed between the stack dielectric layer and the upper electrode plate.

5. The semiconductor device according to claim 1, wherein The intermediate dielectric layer is a single-layer structure and directly contacts the stack dielectric layer and the upper electrode plate.

6. The semiconductor device according to claim 1, wherein The stack dielectric layer comprises a plurality of sub-dielectric layers, and the intermediate dielectric layer is disposed between two adjacent sub-dielectric layers.

7. The semiconductor device according to claim 1, wherein The stack dielectric layer comprises a plurality of sub-dielectric layers, and the capacitor structure further comprises another intermediate dielectric layer disposed between two adjacent sub-dielectric layers, and the another intermediate dielectric layer has a dielectric constant higher than that of the stack dielectric layer.

8. The semiconductor device according to claim 1, wherein The thickness ratio between the stack dielectric layer and the another intermediate dielectric layer is 10:1 to 30:

1.

9. The semiconductor device according to claim 8, wherein The semiconductor device further comprises a top dielectric layer, wherein the top dielectric layer surrounds the upper electrode plate and directly contacts the upper electrode plate, the intermediate dielectric layer and the stack dielectric layer.

10. The semiconductor device according to claim 1, wherein The metal stack comprises a top metal layer and at least one intermediate metal layer, wherein the top metal layer is disposed in the top dielectric layer, and the top metal layer and the at least one intermediate metal layer directly contact the stack dielectric layer.

11. The semiconductor device according to claim 10, wherein The at least one plug is disposed in the stack dielectric layer and electrically connected to the metal stack.

12. The semiconductor device according to claim 11, wherein The manufacturing method comprises:

13. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a lower electrode plate on the substrate; forming at least one sub-dielectric layer on the lower electrode plate; forming a dielectric layer on the at least one sub-dielectric layer; patterning the dielectric layer to form an intermediate dielectric layer, wherein the intermediate dielectric layer exposes part of the at least one sub-dielectric layer; etching the part of the at least one sub-dielectric layer not covered by the intermediate dielectric layer to form a hole; filling at least one plug into the hole; and ​ After forming the intermediate dielectric layer and after forming the hole, an upper electrode plate is formed on the intermediate dielectric layer, wherein the upper electrode plate covers part of the intermediate dielectric layer, and the outer side of the intermediate dielectric layer extends beyond the outer side of the upper electrode plate, wherein the thickness of the part of the intermediate dielectric layer covered by the upper electrode plate is greater than the thickness of the part of the intermediate dielectric layer extending beyond the outer side of the upper electrode plate.

14. The method of producing a semiconductor device according to Claim 13, wherein The composition of the at least one sub-dielectric layer comprises silicon oxide, and the composition of the intermediate dielectric layer comprises silicon nitride, silicon oxynitride or silicon carbide.

15. The method of producing a semiconductor device according to Claim 13, wherein Before forming the plug, the method further comprises forming another sub-dielectric layer on the intermediate dielectric layer, wherein the another sub-dielectric layer surrounds the intermediate dielectric layer.

16. The method of producing a semiconductor device according to Claim 15, wherein The step of etching the part of the at least one sub-dielectric layer not covered by the intermediate dielectric layer to form the hole comprises etching through the another sub-dielectric layer and the sub-dielectric layer.

17. The method of producing a semiconductor device according to Claim 15, wherein After forming the upper electrode plate, the method further comprises forming a top dielectric layer, and the top dielectric layer directly contacts the upper electrode plate and the another sub-dielectric layer.

18. The method of producing a semiconductor device according to Claim 13, wherein The method further comprises forming a top metal layer directly contacting the plug, and the top metal layer and the upper electrode plate are formed simultaneously.

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