Non-volatile memory device and method of manufacturing the same

Abstract

A nonvolatile memory device and a manufacturing method thereof are provided. The nonvolatile memory device includes a substrate, a module structure including a first insulating pattern and a plurality of gate electrodes alternately stacked in a first direction on the substrate, and a word line cut region extending in a second direction different from the first direction and cutting the module structure, wherein the word line cut region includes a common source line, and the common source line includes a second insulating pattern extending in the second direction, and a conductive pattern extending in the second direction and in contact with the second insulating pattern and a cross section in the second direction.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0001822, filed on January 7, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a non-volatile storage device and a method for manufacturing the same. Background Technology

[0004] Semiconductor memory devices can be broadly classified into volatile memory devices and non-volatile memory devices. Non-volatile memory devices have increased integration density to meet consumer demands for increased performance and / or lower prices. Furthermore, in the case of two-dimensional or planar memory devices, the integration density is determined by the area occupied by each memory cell. Therefore, a three-dimensional memory device has recently been developed in which the unit memory cell is vertically arranged. Summary of the Invention

[0005] An aspect of the present invention provides a non-volatile storage device with improved product reliability.

[0006] The present invention also provides a method for manufacturing non-volatile memory devices that can produce non-volatile memory devices with improved product reliability.

[0007] However, the aspects of the inventive concept are not limited to those set forth herein. These and other aspects of the inventive concept will become more apparent to those skilled in the art from the following detailed description of the inventive concept.

[0008] According to one aspect of the present invention, a non-volatile memory device is provided, comprising: a substrate; a mold structure including a first insulating pattern and a plurality of gate electrodes alternately stacked along a first direction on the substrate; and a word line dicing region extending along a second direction different from the first direction and dicing the mold structure, wherein the word line dicing region includes a common source line, and the common source line includes a second insulating pattern extending along the second direction and a conductive pattern extending along the second direction and contacting the second insulating pattern and a cross section along the second direction.

[0009] According to one aspect of the present invention, a non-volatile memory device is provided, comprising: a substrate; a mold structure including a first insulating pattern and a plurality of gate electrodes alternately stacked on the substrate along a first direction; a plurality of channel structures penetrating the mold structure; a plurality of pad electrodes electrically connected to the plurality of channel structures to provide a voltage; and a plurality of word line dicing regions extending along a second direction different from the first direction and dicing the mold structure, wherein each of the plurality of word line dicing regions includes a common source line, each of the common source lines including a second insulating pattern extending along the second direction and a conductive pattern extending along the second direction and contacting the second insulating pattern and a cross section along the second direction, and at least one of the common source lines is spaced apart in the first direction from a gate electrode stacked at the lowermost part along the first direction.

[0010] According to one aspect of the present invention, a non-volatile memory device is provided, comprising: a substrate; a mold structure including a first insulating pattern and a plurality of gate electrodes alternately stacked on the substrate along a first direction; a plurality of channel structures penetrating the mold structure, each of the plurality of channel structures including, at its lowest level, a first semiconductor pattern, an information storage film for exposing the first semiconductor pattern, a second semiconductor pattern formed along the information storage film and the first semiconductor pattern, a fill pattern in the second semiconductor pattern, and channel pads on the information storage film, the second semiconductor pattern, and the fill pattern; a word line dicing region extending along a second direction different from the first direction and dicing the mold structure, the word line dicing region being... The cut region includes a common source line spacer and a common source line inside the common source line spacer, the common source line spacer being along the sidewall of the word line cut region and exposing the substrate, the common source line including a second insulating pattern extending in the second direction, and a conductive pattern extending in the second direction and contacting the second insulating pattern and the cross section in the second direction; a first interlayer insulating film on the mold structure and surrounding at least some of the plurality of channel structures and at least a portion of the word line cut region; a bit line contact on the channel pad; a second interlayer insulating film surrounding the bit line contact; and a bit line on the second interlayer insulating film and electrically connected to the bit line contact.

[0011] According to one aspect of the present invention, a method for manufacturing a non-volatile memory device is provided, the method comprising: forming a substrate; alternately stacking a first insulating pattern and a plurality of gate electrodes on the substrate along a first direction to form a pattern structure; forming a plurality of channel structures penetrating the pattern structure; dicing the pattern structure to isolate the plurality of channel structures along a second direction intersecting the first direction, and forming a word line dicing region extending along a third direction intersecting the first and second directions; forming a common source line spacer along the sidewalls of the word line dicing region; filling the interior of the common source line spacer with an insulating material; forming a passivation layer on the insulating material; removing some areas of the insulating material and the passivation layer to expose the common source line spacer to the some areas; forming a conductive material on the exposed common source line spacer and the unremoved areas of the passivation layer; removing conductive material from the areas other than the conductive material in the word line dicing region; removing the passivation layer; and removing the remaining insulating material other than the insulating material in the word line dicing region to form a common source line. Attached Figure Description

[0012] The above and other aspects and features of the inventive concept will become clearer from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0013] Figure 1 These are example circuit diagrams illustrating non-volatile memory devices according to some embodiments.

[0014] Figure 2 This is an example layout diagram used to illustrate non-volatile storage devices.

[0015] Figure 3 This is an example layout diagram used to illustrate non-volatile storage devices.

[0016] Figure 4 It is along Figure 3 A cross-sectional view taken from line A-A'.

[0017] Figure 5 It is along Figure 3 The cross-sectional view taken by line B-B'.

[0018] Figure 6 This is an example layout diagram illustrating a non-volatile storage device according to some embodiments.

[0019] Figure 7 This is an example layout diagram illustrating a non-volatile storage device according to some embodiments.

[0020] Figures 8 to 12 According to some embodiments Figure 7An example cross-sectional view of a non-volatile storage device taken along line B-B'.

[0021] Figure 13 According to some embodiments Figure 7 Another example cross-sectional view of a non-volatile storage device taken along line B-B'.

[0022] Figures 14 to 22 This is an example cross-sectional view illustrating intermediate steps of a method for manufacturing a non-volatile storage device according to some embodiments.

[0023] Figure 23 and Figure 24 According to some embodiments Figure 7 An example cross-sectional view of a non-volatile storage device taken along line B-B'.

[0024] Figure 25 and Figure 26 According to some embodiments Figure 7 Other example cross-sectional views taken from line B-B'.

[0025] Figure 27 These are example block diagrams illustrating a memory device including a non-volatile memory device according to some embodiments.

[0026] Figure 28 It is along Figure 7 Another example cross-sectional view taken from line B-B'. Detailed Implementation

[0027] Figure 1 These are example circuit diagrams illustrating non-volatile memory devices according to some embodiments.

[0028] refer to Figure 1 According to some embodiments, the memory cell array of a non-volatile memory device may include a common source line CSL, multiple bit lines BL, and / or multiple cell strings CSTR.

[0029] Multiple bit lines BL1 to BL3 can be arranged in a two-dimensional manner. For example, bit lines BL1 to BL3 can be spaced apart from each other and extend along a first direction X. Multiple cell strings CSTRs can be connected in parallel to each bit line BL. The cell strings CSTRs can be connected together to a common source line CSL. That is, multiple cell strings CSTRs can be disposed between the bit line BL and the common source line CSL. In some embodiments, multiple common source lines CSL can be arranged in a two-dimensional manner. For example, common source lines CSL can be spaced apart from each other and each extend along a second direction Y. The same voltage can be applied to the common source line CSL, or different voltages can be applied to the common source line CSL, and the common source line CSL can be controlled individually.

[0030] Each cell string (CSTR) may include a ground select transistor (GST) connected to a common source line (CSL), a string select transistor (SST) connected to each of multiple bit lines (BL1 to BL3), and multiple memory cell transistors (MCTs) disposed between the ground select transistor (GST) and the string select transistor (SST). Each memory cell transistor (MCT) may include a data storage element. The ground select transistor (GST), the string select transistor (SST), and the memory cell transistors (MCTs) may be connected in series with each other. The common source line (CSL) may be commonly connected to the source of the ground select transistor (GST). Multiple gate electrodes (e.g., the ground select line (GSL), multiple word lines (WL1 to WLn), and the string select line (SSL) may be disposed between the common source line (CSL) and each of the bit lines (BL1 to BL3). The ground select line (GSL) may be used as the gate electrode of the ground select transistor (GST), the multiple word lines (WL1 to WLn) may be used as the gate electrodes of the memory cell transistors (MCTs), and the string select line (SSL) may be used as the gate electrode of the string select transistor (SST).

[0031] Figure 2 This is an example layout diagram used to illustrate non-volatile storage devices.

[0032] refer to Figure 2 The non-volatile storage device 1 may include a cell array region CAR and / or an extension region ETR.

[0033] A cell array comprising multiple memory cells can be formed in a cell array region (CAR). The cell array may include multiple memory cells, multiple word lines WL1 to WLn electrically connected to the respective memory cells, and multiple bit lines (not shown). For example, a module structure, multiple channel structures CS, and / or bit lines 140, as described below, can be formed in the cell array region (CAR).

[0034] The extended region ETR can be arranged around the cell array region CAR. Each of the multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, and serial select line SSL), the module structure described later, and at least some of the multiple channel structures CS can be progressively stacked in the extended region ETR. Furthermore, multiple pad electrodes (not shown) connected to the multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, and serial select line SSL) can be formed in the extended region ETR. For example, some of the multiple pad electrodes (not shown) can be electrically connected to the... Figure 27 Some of the pad electrodes in the page buffer 530.

[0035] Multiple channel structures CS or multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or serial select line SSL) in the non-volatile memory device 1 can be separated by a word line cleaving region WLC. That is, the word line cleaving region WLC extends along a second direction Y intersecting with the bit lines (not shown) and can cut the desired boundaries. Figure 4 The module structure MS is described in the diagram. A common source line spacer 150 can be formed along the sidewall of the word line dicing region WLC. The common source line spacer 150 can be made of silicon oxide, silicon nitride, or silicon oxynitride. Additionally, the interior of the word line dicing region WLC and the interior of the common source line spacer 150 can be filled with a conductive material to form a common source line CSL on which a conductive pattern is formed. The conductive material can be made of, but is not limited to, metallic materials such as tungsten (W), aluminum (Al), or copper (Cu). Some of the multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) of the non-volatile memory device 1 can be diced along a third direction Z (e.g., string select line SSL) to form a string select line dicing region SLC. The string select line dicing region SLC can be filled with an insulating film (not shown).

[0036] At this point, defects 300 and 302 may occur in the extended region ETR, in which multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) or at least some of the module structures to be described later are progressively stacked.

[0037] For example, current or charge leakage may occur between the common source line CSL, formed by a conductive pattern, and the multiple gate electrodes of the extended region ETR (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL). For example, defect 300 may occur due to leakage between the common source line CSL in the extended region ETR and the nth word line WLn. Alternatively, for example, defect 302 may occur due to leakage between the common source line CSL in the extended region ETR and the second word line WL2. The common source line CSL in the extended region ETR is not formed by a conductive pattern, but may be formed by a non-conductive insulating pattern, thereby eliminating defects (e.g., 300 and 302) between the common source line CSL in the extended region ETR and at least some of the gate electrodes of the multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL).

[0038] Figure 3 Another example is shown where current or charge leakage may occur between the common source line CSL formed by the conductive pattern and the multiple gate electrodes of the extended region ETR (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL).

[0039] Figure 3 This is an example layout diagram used to illustrate non-volatile storage devices. For reference, it will be omitted. Figure 2 The description repeats the content, and the main description is related to... Figure 2 The difference.

[0040] refer to Figure 3 ,and Figure 2 Unlike other non-volatile memory devices, non-volatile memory devices can have an H-cut shape, in which the cut region of the common source line CSL is formed in the extended region ETR of the non-volatile memory device 2.

[0041] More specifically, a portion of the common source line CSL can be cut to form a first sub-common source line CSL and a second sub-common source line CSL. That is, the first sub-common source line CSL and the second sub-common source line CSL can be spaced apart from each other along a first direction X. Therefore, some of the gate electrodes surrounding the first and second sub-common source lines CSL (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) can have an H-shape. Some of the gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) can be electrically connected to each other through the spacer between the first and second sub-common source lines CSL.

[0042] and Figure 2 Similar to the previous example, defects 304 and 306 may occur in the progressively stacked extended region ETR between at least some of the gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) or the module structure described below. For example, current or charge leakage may occur between the common source line CSL formed by conductive patterns and the multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) of the extended region ETR. For example, defect 304 may occur due to leakage between the common source line CSL and the nth word line WLn in the extended region ETR. In this case, although the defect appears Figure 2 On the sidewall of the common source line CSL, but defect 304 may occur along the extension direction of the common source line CSL (i.e., along...). Figure 3 The first direction (X) appears. Alternatively, for example, defect 306 may occur due to leakage between the common source line CSL and the second word line WL2 in the extended region ETR. In this case, similarly, with Figure 2 Unlike other defects, defect 306 may extend along the common source line CSL (i.e., along...). Figure 3 The first direction (X) appears in the middle.

[0043] The common source line (CSL) in the extended region ETR is not formed by a conductive pattern, but can be formed using a non-conductive insulating pattern, thereby eliminating defects (e.g., 304 and 306) between the common source line (CSL) and at least some of the gate electrodes (e.g., ground select line (GSL), multiple word lines WL1 to WLn, or string select line (SSL)) in the extended region ETR. Figure 4 and Figure 5 By comparing the cross-sections in the cell array region CAR and the extended region ETR of the non-volatile memory device 2, the defects in the extended region ETR are explained. Although it will be based on... Figure 3 Using a cross-section of non-volatile memory device 2 as an example for illustration Figure 4 and Figure 5 The cross-section, but Figure 4 and Figure 5 The cross-section is not limited to this, and can also be obtained by, for example... Figure 2 Cross-sectional description of storage device 1 Figure 4 and Figure 5 The cross section.

[0044] Figure 4 It is along Figure 3 A cross-sectional view taken from line A-A'.

[0045] Reference Figure 3 and Figure 4 This diagram illustrates a cross-section of the cell array region CAR of the non-volatile memory device 2. The non-volatile memory device 2 includes a substrate 100, a mode structure MS, multiple channel structures CS, a bit line 140, and / or a common source line CSL.

[0046] For example, substrate 100 may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, substrate 100 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. A mode structure MS may be formed on substrate 100. Mode structure MS may include a first insulating pattern 110 and a plurality of gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) alternately stacked on substrate 100 along a third direction Z. For example, each of the first insulating pattern 110 and the plurality of gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) may have a layered structure extending along a second direction Y and a first direction X.

[0047] Multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) may include ground select line GSL, multiple word lines WL1 to WLn, and string select line SSL sequentially stacked on substrate 100. The ground select line GSL may be the gate electrode disposed at the lowermost position of the multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) along a third direction Z. The string select line SSL may be the gate electrode disposed at the uppermost position of the multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) along a third direction. The multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) may include a conductive material. However, for example, multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) may include, but are not limited to, metals such as tungsten (W), cobalt (Co), and nickel (Ni), and semiconductor materials such as silicon. The first insulating pattern 110 may include an insulating material. For example, the first insulating pattern 110 may include, but is not limited to, silicon oxide.

[0048] Multiple channel structures CS can penetrate the mode structure MS. Additionally, the multiple channel structures CS can extend in directions intersecting multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL). For example, each channel structure CS can have a cylindrical shape (e.g., a cylinder) extending in a third direction Z. Each channel structure CS can include a first semiconductor pattern 220 and an information storage film 230. The first semiconductor pattern 220 can penetrate the mode structure MS. For example, the first semiconductor pattern 220 can extend in a third direction Z. Although the first semiconductor pattern 220 is shown as having a cup shape, this is only an example. For example, the first semiconductor pattern 220 can have various shapes, such as cylindrical, quad barrel, and solid-filled shapes. The first semiconductor pattern 220 can include, for example, but not limited to, semiconductor materials, such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures.

[0049] The information storage film 230 may be located between the first semiconductor pattern 220 and each of a plurality of gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL). For example, the information storage film 230 may extend along a side surface of the first semiconductor pattern 220. The information storage film 230 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a higher dielectric constant than silicon oxide. Although not shown, the information storage film 230 may include multiple films. For example, the information storage film 230 may include a tunnel insulating film, a charge storage film, and / or a barrier insulating film sequentially stacked on the first semiconductor pattern 220.

[0050] The tunnel insulating film may include, for example, silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)). The charge storage film may include, for example, silicon nitride. The barrier insulating film may include, for example, silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)). Each channel structure CS may also include a fill pattern 210. The fill pattern 210 may be formed to fill the interior of a cup-shaped first semiconductor pattern 220. For example, the first semiconductor pattern 220 may extend along the side and bottom surfaces of the fill pattern 210. The fill pattern 210 may include, for example, but not limited to, silicon oxide. Each channel structure CS may also include a channel pad 200 at the uppermost part of the channel structure CS along the third direction Z. The channel pad 200 may be formed to connect to the upper part of the first semiconductor pattern 220. For example, the channel pad 200 can be formed in the first interlayer insulating film 120, wherein the first interlayer insulating film 120 is formed on the mold structure MS.

[0051] Although the channel pad 200 is shown as formed on Figure 4 The first semiconductor pattern 220 is located on the upper surface of the first semiconductor pattern 220, but this is only an example. For example, the upper portion of the first semiconductor pattern 220 may be formed to extend along the side surface of the channel pad 200. The channel pad 200 may include, for example, but not limited to, doped polysilicon.

[0052] Multiple channel structures (CS) can be arranged in a zigzag pattern. That is, they can be arranged to intersect each other along the first direction X and the second direction Y. Arranging multiple channel structures (CS) in a zigzag pattern can improve the integration of non-volatile memory devices.

[0053] Each of the multiple channel structures CS may include a second semiconductor pattern 240 directly connected to the substrate 100. The second semiconductor pattern 240 may be disposed at the lowermost part of the first semiconductor pattern 220 along the third direction Z. The second semiconductor pattern 240 may be an epitaxial layer grown from the substrate 100 using a selective epitaxial growth (SEG) process. That is, the first semiconductor pattern 220 can be electrically connected to the substrate 100 through the second semiconductor pattern 240. The width of the channel structure CS through the mold structure MS may decrease towards the upper surface of the substrate 100. This may be attributed to the characteristics of the etching process used to form the mold structure MS.

[0054] Subsequently, multiple bit lines 140 may extend side-by-side, spaced apart from each other. For example, each bit line 140 may extend along a second direction Y. Each bit line 140 may be electrically connected to multiple channel structures CS. For example, the bit lines 140 may be electrically connected to multiple channel structures CS via bit line contacts 160. The bit line contacts 160 may penetrate, for example, a second interlayer insulating film 130, to electrically connect the bit lines 140 to each of the multiple channel structures CS.

[0055] The first interlayer insulating film 120 and the second interlayer insulating film 130 mentioned above can be made of high-density plasma (HDP) oxide film, tetraethyl orthosilicate (TEOS), or a combination thereof, but are not limited thereto. In addition, the first interlayer insulating film 120 and the second interlayer insulating film 130 can be, but are not limited to, silicon nitride, silicon oxynitride, or low-k materials with low dielectric constant.

[0056] The module structure MS can be cut by the word line cut region WLC. The word line cut region WLC can extend in a direction intersecting the bit line 140 (e.g., a first direction X). For example, the word line cut region WLC can extend in the first direction X to cut the module structure MS.

[0057] Therefore, multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or serial select line SSL) can be cut by the word line cut area WLC.

[0058] The word line cutting area WLC can be like Figure 2 and Figure 3 As shown, it is formed on the cell array region CAR and the extended region ETR. The width of the word line cut region WLC of the cut mold structure MS can decrease towards the upper surface of the substrate 100. This may be attributed to the characteristics of the etching process used to form the word line cut region WLC.

[0059] Common source line CSL and / or common source line spacer 150 may be formed in word line cut region WLC.

[0060] The common source line spacer 150 can be made of silicon oxide, silicon nitride, or oxide nitride. The common source line CSL can be made of a conductive material. That is, the common source line CSL can be formed by a conductive pattern. For example, the common source line CSL can include a metallic material, such as tungsten (W), aluminum (Al), or copper (Cu).

[0061] like Figure 4 As shown, the defect may not appear in the cell array region CAR of non-volatile memory device 2. However, the defect may appear in the extended region ETR of non-volatile memory device 2. This will be achieved through... Figure 5 This needs to be explained.

[0062] For reference, the following description will be omitted. Figures 2 to 4 The explanation will repeat the content of the previous one, and the main difference will be explained.

[0063] Figure 5 It is along Figure 3 The cross-sectional view taken by line B-B'.

[0064] refer to Figure 3 and Figure 5 In the extended region ETR of the non-volatile memory device 2, defects 308 and 310 may occur between the common source line CSL and at least some of the gate electrodes or mode structures MS among the multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn or serial select line SSL).

[0065] For example, current or charge leakage may occur between the common source line CSL formed by the conductive pattern and the multiple gate electrodes of the extended region ETR (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL).

[0066] For example, defect 308 may occur due to leakage between the word line cut-off region WLC, the second word line WL2, and the third word line WL3 in the extended region ETR. Alternatively, for example, defect 310 may occur due to leakage between the common source line CSL, the first word line WL1, and the second word line WL2 in the extended region ETR.

[0067] The common source line CSL in the extended region ETR is not formed by a conductive pattern, and the word line cut region WLC can be filled with a non-conductive insulating material and formed by an insulating pattern, thereby eliminating defects (e.g., 308 and 310) between the common source line CSL in the extended region ETR and at least some of the gate electrodes among the multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn or string select line SSL).

[0068] The above description is shown. Figure 2 , Figure 3 and Figure 5 The defects shown are for illustrative purposes only; the shapes of the defects are not limited to those described above, and the number and location of defects are certainly not limited to those described above. Figure 2 , Figure 3 and Figure 5 Those shown.

[0069] The following will describe non-volatile memory devices according to some embodiments for overcoming the above-described deficiencies, and methods for manufacturing non-volatile memory devices according to some embodiments. Furthermore, aside from descriptions repeated above, the main differences will be explained.

[0070] Figure 6This is an example layout diagram illustrating a non-volatile memory device according to some embodiments. For reference, the number and arrangement of multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL), multiple channel structures CS, and word line cut regions WLC in the non-volatile memory device according to some embodiments are not limited to... Figure 6 Those.

[0071] According to some embodiments, a non-volatile memory device 3 includes a common source line CSL in a word line dicing region WLC. The word line dicing region WLC, according to some embodiments, extends along a first direction X and can be diced with multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL). In the common source line CSL, according to some embodiments, the material formed in the cell array region CAR may be different from the material formed in the extension region ETR. That is, the common source line CSL of the cell array region CAR performing memory operations may be filled with conductive material to form a conductive pattern. The common source line CSL of the cell array region CAR may include a conductive pattern extending along the first direction X. The conductive material used to form the conductive pattern may include, but is not limited to, metals such as tungsten (W), cobalt (Co), and nickel (Ni) or semiconductor materials such as silicon.

[0072] According to some embodiments, the extended region ETR of the common source line CSL can be filled with a non-conductive material to form an insulating pattern. The common source line CSL of the extended region ETR can include an insulating pattern extending along a first direction X. The insulating material used to form the insulating pattern can include, but is not limited to, spin-coated hard mask (SOH), amorphous carbon layer (ACL), silicon oxide, etc.

[0073] The common source line CSL in the word line cut-out region WLC of the extended region ETR of the non-volatile memory device 3 according to some embodiments can be formed by an insulating pattern, thereby reducing the frequency of defects or eliminating defects between the common source line CSL and multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) in the extended region ETR. That is, when... Figure 2 and Figure 3When the common source line CSL of the extended region ETR is formed by conductive patterns, as in non-volatile memory devices 1 and 2, the number of defects occurring between the common source line CSL of the extended region ETR and multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) can be reduced, or all defects can be eliminated in non-volatile memory device 3 according to some embodiments. Therefore, defects formed in non-volatile memory device 3 according to some embodiments can be reduced or eliminated, and the reliability of non-volatile memory device 3 according to some embodiments and semiconductor devices or systems including non-volatile memory device 3 according to embodiments can be improved.

[0074] Figure 7 This is an example layout diagram illustrating a non-volatile memory device according to some embodiments. For reference, the number and arrangement of multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL), multiple channel structures CS, and word line cut regions WLC in the non-volatile memory device according to some embodiments are not limited to... Figure 7 Those shown.

[0075] refer to Figure 7 ,and Figure 6 Unlike the non-volatile storage device 3 in some embodiments, the non-volatile storage device 4 in some embodiments may have a shape in which some common source lines in the common source line CSL of the extended region ETR are disconnected.

[0076] In other words, reference Figure 7 ,and Figure 6 Unlike other non-volatile memory devices, the non-volatile memory device 4 can have an H-shaped cut, in which the disconnected region of the common source line CSL is formed in the extended region ETR of the non-volatile memory device 4. For example, some common source lines in the common source line CSL are disconnected, and a first sub-common source line CSL and a second sub-common source line CSL can be formed. That is, the first sub-common source line CSL and the second sub-common source line CSL can be spaced apart from each other along a first direction X. Therefore, some of the gate electrodes of the plurality of gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or serial select line SSL) surrounding the first sub-common source line CSL and the second sub-common source line CSL can have an H-shape. Some of the gate electrodes of the plurality of gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or serial select line SSL) can be electrically connected to each other through the spacer region between the first sub-common source line CSL and the second sub-common source line CSL.

[0077] For reference, the disconnected common source line CSL in the extended region ETR includes an insulating pattern. Therefore, the first sub-common source line CSL and the second sub-common source line CSL can respectively become the first sub-insulating pattern CSL_a and the second sub-insulating pattern CSL_b. The common source line CSL formed in the word line cut-off region WLC in the extended region ETR of the non-volatile memory device 4 according to some embodiments can be formed by an insulating pattern, thereby reducing the frequency of defects or eliminating defects between the common source line CSL in the extended region ETR and multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL). That is, when... Figure 2 and Figure 3 When the common source line CSL of the extended region ETR is formed by conductive patterns, as in non-volatile memory devices 1 and 2, the number of defects occurring between the common source line CSL of the extended region ETR and multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) can be reduced, or all defects can be eliminated in non-volatile memory device 4 according to some embodiments. Therefore, defects formed in non-volatile memory device 4 according to some embodiments can be reduced or eliminated, and the reliability of non-volatile memory device 4 according to some embodiments and semiconductor devices or systems including non-volatile memory device 4 according to some embodiments can be improved.

[0078] The number and stacking configuration of the plurality of gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) shown in semiconductor devices 3 and 4 according to some embodiments are not limited to Figure 6 and Figure 7 The examples shown are not limited to those. Furthermore, the arrangement of the channel structures CS of semiconductor devices 3 and 4 according to some embodiments is not limited to those shown. Figure 6 and Figure 7 Those shown.

[0079] Figures 8 to 12 According to some embodiments Figure 7 Example cross-sectional view of a non-volatile storage device taken along line B-B'. Figure 13 According to some embodiments Figure 7 Another example cross-sectional view of a non-volatile storage device taken along line B-B'. For reference, Figures 8 to 13 The description of line B-B' in the diagram can certainly be applied to... Figure 6 The cross section at the same location in the middle.

[0080] Figure 7 and Figure 8 It includes the formation Figure 7A cross-sectional view of the non-volatile storage device 4 along line B-B', including the insulation pattern of the common source line CSL of the extended region ETR. This cross-section will be omitted in the description. Figure 5 The explanation will repeat the previous parts, and the main difference will be explained.

[0081] According to some embodiments, the common source line CSL of the extended region ETR of the non-volatile memory device 4 can be filled with insulating material to form an insulating pattern extending along the first direction X. At this time, with... Figure 5 Unlike other methods, because the extended region ETR of the common source line CSL according to some embodiments is filled with insulating material, there is no leakage between the common source line CSL and the multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL). That is, there are no defects between the common source line CSL and the multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL), or the frequency of defect occurrence can be reduced.

[0082] refer to Figure 8 and Figure 9 According to some embodiments Figure 9 Non-volatile storage devices and according to some embodiments Figure 8 The difference between the non-volatile memory devices is that the second semiconductor pattern 240 may not be formed between the lowest level of the channel structure CS along the third direction z and the substrate 100. This is due to the presence or absence of the second semiconductor pattern 240, as described in some embodiments... Figure 9 Description of non-volatile memory devices and Figure 8 The description is the same, therefore it will not be provided. Figure 8 This is a repetitive explanation of the content.

[0083] refer to Figure 8 and Figure 10 According to some embodiments Figure 10 Non-volatile storage devices and according to some embodiments Figure 8 The difference in non-volatile memory devices is that some of the upper, lower, and sidewall surfaces of multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL) can be surrounded by a blocking insulating film 600.

[0084] The barrier insulating film 600 can conformally cover the upper surface, lower surface, and sidewalls of multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL).

[0085] The barrier insulating film 600 can reduce or prevent the release of trapped charge in the information storage film 230 to multiple gate electrodes (e.g., multiple word lines WL1 to WLn), and can reduce or prevent the charge of multiple gate electrodes (e.g., multiple word lines WL1 to WLn) from being captured by the information storage film 230.

[0086] The barrier insulating film 600 may be formed of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), high-k materials, or composite layers stacked by combinations thereof. High-k materials may include, but are not limited to, at least one of aluminum oxide (Al2O3), yttrium oxide (Y2O3), and zirconium oxide (ZrO2).

[0087] Due to the presence or absence of the blocking insulating film 600, according to some embodiments Figure 10 Description of non-volatile memory devices and Figure 8 The description is the same, therefore it will not be provided. Figure 8 This is a repetitive explanation of the content.

[0088] refer to Figure 8 and Figure 11 According to some embodiments Figure 11 Non-volatile storage devices and according to some embodiments Figure 8 The difference in non-volatile memory devices is that a floating gate 650 surrounded by a barrier insulating film 600 may also be included between multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or serial select line SSL) and the channel structure CS. The barrier insulating film 600 may conformally cover some of the upper surface, lower surface, and sidewalls of the floating gate 650.

[0089] The barrier insulating film 600 can reduce or prevent the release of charge trapped in the floating gate 650 to multiple gate electrodes (e.g., multiple word lines WL1 to WLn), and can reduce or prevent the charge of multiple gate electrodes (e.g., multiple word lines WL1 to WLn) from being trapped by the floating gate 650. The floating gate 650 according to some embodiments may be, but is not limited to, polysilicon. Furthermore, according to some embodiments... Figure 11 In a non-volatile memory device including a floating gate 650, the information storage film 230 may be a silicon oxide layer.

[0090] Due to the presence or absence of the floating grid 650 surrounded by the barrier insulating film 600, according to some embodiments Figure 11 Description of non-volatile memory devices and Figure 8 The description is the same, therefore it will not be provided. Figure 8 This is a repetitive explanation of the content.

[0091] refer to Figure 8 and Figure 12 According to some embodiments Figure 12 Non-volatile storage devices and according to some embodiments Figure 8 The difference in non-volatile memory devices is that an additional common source line spacer 152 is included between the common source line spacer 150 and the common source line CSL, which includes insulating material. The additional common source line spacer 152 may be made of silicon oxide, silicon nitride, or silicon oxynitride.

[0092] Due to the presence or absence of additional common source line spacers 152, according to some embodiments Figure 12 Description of non-volatile memory devices and Figure 8 The description is the same, therefore it will not be provided. Figure 8 This is a repetitive explanation of the content.

[0093] refer to Figure 7 and Figure 13 According to some embodiments, the common source line CSL of the extended region ETR may include an air gap 430 in the insulation pattern.

[0094] The air gap 430 is a void defined and surrounded by an outer insulating pattern, and can have a lower dielectric constant than silicon oxide. This allows for more efficient reduction or prevention of leakage current that may occur between the common source line CSL and multiple gate electrodes (e.g., ground select line GSL, multiple word lines WL1 to WLn, or string select line SSL).

[0095] Figures 14 to 22 This is an example cross-sectional view illustrating intermediate steps of a method for manufacturing a non-volatile storage device according to some embodiments. For reference, Figures 14 to 22 It was explained together Figure 7 Sections A-A' and B-B'. Figures 14 to 22 The explanation can certainly be used as Figure 6 The explanation. Furthermore, Figures 14 to 22 It also illustrates the manufacturing process according to some embodiments. Figure 8 An intermediate step in a method for non-volatile storage devices. According to some embodiments... Figures 14 to 22 The intermediate steps of the method for manufacturing non-volatile memory devices can, of course, be applied to the manufacturing process according to some embodiments. Figures 9 to 13 Methods for non-volatile storage devices.

[0096] In the following description, in some embodiments where the processes for sections A-A' and B-B' are repeated, the process for section A-A' will be primarily explained. Of course, the process for section A-A' is also applied to section B-B'.

[0097] refer to Figure 14A first insulating pattern 110a and a plurality of gate electrodes (e.g., ground select lines GSLa and GSLb, multiple word lines WL1a to WLna and WL1b to WLnb, or string select lines SSLa and SSLb) can be alternately stacked on the substrate 100 along a third direction Z. For example, the substrate 100, the first insulating patterns 110a and 110b, the ground select lines GSLa and GSLb, the first insulating patterns 110a and 110b, the first word lines WL1a and WL1b, and the first insulating patterns 110a and 110b can be stacked sequentially. The first insulating patterns 110a and 110b and the plurality of gate electrodes (e.g., ground select lines GSLa and GSLb, multiple word lines WL1a to WLna and WL1b to WLnb, or string select lines SSLa and SSLb) can form the module structures MSa and MSb. Second insulating patterns 120a and 120b can be formed on the module structures MSa and MSb. Subsequently, multiple channel structures CSa and CSb can be formed from the through-mold structures MSa and MSb and the second insulating patterns 120a and 120b. The description of the multiple channel structures CSa and CSb is consistent with... Figure 4 The descriptions of the multiple channel structures CS are identical, therefore, these descriptions will not be provided. Subsequently, the module structures MSa and MSb can be cut to form word line cut regions WLCa and WLCb extending along the first direction X. The word line cut regions WLCa and WLCb can expose the substrate 100, and each of the multiple channel structures CSa and CSb is separated along the second direction Y.

[0098] According to some embodiments, common source line spacers 150a and 150b and insulating patterns 400a and 400b can be formed in word line cut regions WLCa and WLCb. For example, common source line spacers 150a and 150b can be conformally formed on the sidewalls of word line cut regions WLCa and WLCb, the uppermost part of each of the plurality of channel structures CSa and CSb along the third direction Z, and the second insulating patterns 120a and 120b. Insulating patterns 400a and 400b are formed along common source line spacers 150a and 150b and can be formed by filling the interior of word line cut regions WLCa and WLCb with insulating material.

[0099] refer to Figure 15 Air gaps 430a and 430b can be formed inside insulating patterns 400a and 400b. Air gap 430b can be... Figure 13 The air gap formed in the middle is 430.

[0100] Alternative locations, for reference Figure 16In the process of forming insulating patterns 400a and 400b by filling the interior of word line cutting areas WLCa and WLCb with insulating material, the insulating material may be recessed into recesses 440a and 440b in the word line cutting areas WLCa and WLCb. This can be naturally formed during the process of filling the interior of word line cutting areas WLCa and WLCb with insulating material.

[0101] refer to Figure 17 According to some embodiments of the method for manufacturing a non-volatile storage device, air gaps 430a and 430b and recesses 440a and 440b may be formed inside insulating patterns 400a and 400b.

[0102] In the second direction Y, the widths of the word line cutting regions WLCa and WLCb can be wider than the widths of the multiple channel structures CSa and CSb. Therefore, in the process of filling the interior of the word line cutting regions WLCa and WLCb with insulating material, the lowermost parts of the word line cutting regions WLCa and WLCb along the third direction Z can be entirely filled with insulating material, but the upper parts of the word line cutting regions WLCa and WLCb do not need to be entirely filled with insulating material. That is to say, as... Figure 17 As shown, since the insulating material is formed along the upper sidewall of the word line cutting areas WLCa and WLCb, air gaps 430a and 430b are formed in the word line cutting areas WLCa and WLCb, and recesses 440a and 440b can also be formed at the uppermost part of the word line cutting areas WLCa and WLCb.

[0103] In the following figures, for ease of explanation, a method for manufacturing a non-volatile memory device according to some embodiments will be described, in which air gaps 430a and 430b and recesses 440a and 440b are not formed. Therefore, the description in the following figures can of course be provided as a method for manufacturing a non-volatile memory device according to some embodiments, in which air gaps 430a and 430b and recesses 440a and 440b are formed.

[0104] refer to Figure 18 Passivation layers 410a and 410b can be formed on insulating patterns 400a and 400b. Passivation layers 410a and 410b can protect insulating pattern 400b when conductive material is subsequently formed. Passivation layers 410a and 410b can be formed from plasma-reinforced tetraethyl orthosilicate (PE-TEOS), but are not limited to this.

[0105] refer to Figure 7 and Figure 19The insulating pattern 400a and passivation layer 410a can be removed using a mask via photolithography and etching processes to fill conductive material only in the word line cut regions WLCa of the cell array region CAR of the non-volatile memory device according to some embodiments. At this time, a trench T can be formed by performing another etching process, such that the word line cut regions WLCa in the cell array region CAR are also formed inside the substrate 100.

[0106] refer to Figure 20 The conductive material can be filled inside the word line dicing region WLCa on the first interlayer insulating film 120a, the channel structure CSa, and the passivation layer 410b. The conductive material can also be filled inside the trench T. The aforementioned conductive material can form a conductive pattern in the word line dicing region WLCa.

[0107] refer to Figure 21 Except for the common source line spacer 150a in the word line dicing region WLCa and the conductive pattern 420a in the word line dicing region WLCa, the remaining conductive material is removed. That is, the multiple channel structures CSa, the first interlayer insulating film 120a, the uppermost part of the word line dicing region WLCa, and the conductive patterns 420a and 420b on the passivation layer 410b can be removed. In addition, the passivation layer 410b can also be removed.

[0108] Subsequently, all remaining insulating material except for the common source line spacer 150b in the word line cut-out region WLCb and the insulating pattern 400b in the word line cut-out region WLCb is removed. That is, the multiple channel structures CSb, the first interlayer insulating film 120b, and the insulating pattern 400b on the uppermost part of the word line cut-out region WLCb can be removed.

[0109] refer to Figure 22 The second interlayer insulating films 130a and 130b can be formed on the top of the first interlayer insulating films 120a and 120b, the multiple channel structures CSa and CSb, and the word line cutting areas WLCa and WLCb.

[0110] Subsequently, the bit line contact portion penetrating the second interlayer insulating films 130a and 130b can be like... Figure 8 The bit line contact portion 160 is formed in the same way. The bit line contact portion 160 can be connected to multiple channel structures CSa and CSb. Thereafter, as Figure 8 As shown, bit lines 140 can be formed on the second interlayer insulating films 130a and 130b and the bit line contact portion 160. That is to say, as Figure 8 As shown, bit line 140 can be electrically connected to multiple channel structures CS through bit line contact portion 160.

[0111] Figure 23 and Figure 24According to some embodiments Figure 7 Example cross-sectional view of a non-volatile storage device taken along line B-B'.

[0112] refer to Figure 23 ,and Figure 8 Unlike other non-volatile memory devices, according to some embodiments, the non-volatile memory device may also include a base substrate 10 below the substrate 100 and a peripheral circuit structure PS. This may be referred to as a cell-on-periphery (COP) structure.

[0113] For example, the base substrate 10 may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the base substrate 10 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0114] The peripheral circuit structure PS can be formed on the base substrate 10. The peripheral circuit structure PS can constitute the peripheral circuitry controlling the operation of each memory cell. For example, the peripheral circuit structure PS may include components that will be used later... Figure 27 The description includes the line decoder 520, page buffer 530, control logic device 550, etc. For example, such as... Figure 23 As described herein, the peripheral circuit structure PS may include peripheral circuit elements PT and wiring structure PW.

[0115] In some embodiments, the peripheral circuit device PT may include a transistor. For example, the peripheral circuit element PT may include a peripheral circuit gate electrode 12, a peripheral circuit gate insulating film 14, a gate spacer 16, and a source / drain region 18.

[0116] In some embodiments, the peripheral circuit element PT can be a high-voltage transistor. While some embodiments in which the peripheral circuit element PT is a transistor have been described, these are merely examples, and the technical concept of the invention is not limited thereto. For example, the peripheral circuit element PT can include not only various active elements (e.g., transistors) but also various passive elements (e.g., capacitors, resistors, and inductors).

[0117] In some embodiments, a third interlayer insulating film 20 may be formed on the base substrate 10. The third interlayer insulating film 20 may be formed to cover peripheral circuit elements PT on the base substrate 10. Although the third interlayer insulating film 20 is shown as a single film, this is only for illustrative purposes, and the third interlayer insulating film 20 may of course be a multi-film formed by stacking multiple insulating films. The third interlayer insulating film 20 may include, but is not limited to, for example, silicon oxide.

[0118] The wiring structure PW may include peripheral circuit wiring 22 and peripheral circuit contacts 24. The peripheral circuit wiring 22 and peripheral circuit contacts 24 may be formed in, for example, a third interlayer insulating film 20. The peripheral circuit wiring 22 can be connected to the peripheral circuit element PT via the peripheral circuit contacts 24. The peripheral circuit wiring 22 may include, but is not limited to, metals (e.g., copper (Cu) or aluminum (Al)). The peripheral circuit contacts 24 may include, for example, but not limited to, silicon (e.g., polysilicon) or metals (e.g., tungsten (W) or copper (Cu)).

[0119] Will not be provided Figure 23 The explanation of the COP structure is provided to avoid later... Figure 24 and Figure 28 Repeated explanations in the text.

[0120] refer to Figure 24 According to some embodiments Figure 23 Unlike non-volatile memory devices, the common source line 800 can also be disposed between the third interlayer insulating film 20 and the substrate 100.

[0121] The common source line plate 800 may include tungsten silicide (WSi). Since the materials forming the common source line plate 800 and the substrate 100 are different, the etching rates of the corresponding common source line plate 800 and substrate 100 are different in manufacturing processes such as etching. Therefore, a step can be formed at the point where the common source line plate 800 and substrate 100 intersect with the word line dicing region WLC.

[0122] Figure 25 and Figure 26 According to some embodiments Figure 7 Other example cross-sectional views taken from line B-B'. Figure 27 These are example block diagrams illustrating a memory device including a non-volatile memory device according to some embodiments.

[0123] refer to Figure 25 and Figure 27 The non-volatile memory system 5, which includes non-volatile memory devices according to some embodiments, may include: a cell array 510, a line decoder 520, a page buffer 530, an input / output circuit 540, a control logic device 550, and a voltage generator 560 (including non-volatile memory devices according to some embodiments).

[0124] Cell array 510 can be connected to line decoder 520 via word line WL, serial select line SSL, and ground select line GSL. Additionally, cell array 510 can be connected to page buffer 530 via bit line BL. Furthermore, cell array 510 may include... Figure 6 and Figure 7The non-volatile memory device described herein, according to some embodiments, is described below. A row decoder 520 can select one of the memory blocks of the cell array 510 in response to an address ADDR. The row decoder 520 can select one of the word lines WL of the selected memory block. The row decoder 520 can transmit word line voltages to the word lines of the selected memory block.

[0125] Depending on the operating mode, page buffer 530 can operate as a write driver or a sense amplifier. During a programming operation, page buffer 530 can transmit a bit line voltage corresponding to the data to be programmed to the bit lines of cell array 510. During a read operation, page buffer 530 can detect data stored in the selected memory cell via the bit lines. Page buffer 530 can float the bit line BL. Page buffer 530 may include a plurality of pad electrodes (not shown) electrically connected to a plurality of channel structures in cell array 510 to provide voltage.

[0126] Input / output circuitry 540 can transfer write data to be input to page buffer 530 during programming operations. Input / output circuitry 540 can output read data DATA provided from page buffer 530 to the outside during read operations. Input / output circuitry 540 can transmit input addresses or commands to control logic device 550. Control logic device 550 can control page buffer 530 and line decoder 520 in response to externally sent command CMD. Control logic device 550 can control page buffer 530, voltage generator 560, etc., in response to externally provided command CMD to access selected memory cells. Under the control of control logic device 550, voltage generator 560 can generate various types of word line voltages to be supplied to each word line WL, and voltages to be supplied to blocks (e.g., well regions) in which memory cells are formed.

[0127] At this time, the common source line CSL of the non-volatile memory devices in the cell array 510 according to some embodiments can be as follows: Figure 25 The surface shown is formed at a distance from the substrate 100 along the third direction Z.

[0128] In some embodiments of a non-volatile memory device adjacent to page buffer 530, according to some embodiments, multiple channel structures CS may include dummy regions not connected to bit line 140. When formed as Figure 8When word line cut regions WLC are shown in the dummy regions to contact the substrate 100, defects are likely to occur in multiple gate electrodes (e.g., ground select lines GSLa and GSLb, multiple word lines WL1a to Wlna and WL1b to WLnb, or string select lines SSLa and SSLb). In some embodiments of non-volatile memory devices adjacent to page buffer 530 according to some embodiments, in dummy regions where multiple channel structures CS are not connected to bit lines 140, by forming as Figure 25 The word line cut area WLC shown, which is spaced apart from the substrate 100 along the third direction Z, can reduce the possibility of defects.

[0129] refer to Figure 26 According to some embodiments Figure 25 Unlike non-volatile memory devices, they may also include a barrier insulating film 600 surrounding some of the upper surface, lower surface, and sidewalls of multiple gate electrodes (e.g., ground select lines GSL1 and GSLb, multiple word lines WL1a to WL1a and WL1b to WLnb, or string select lines SSLa and SSLb). The description relating to the barrier insulating film 600 is as follows... Figure 10 The description is the same as in [the previous section], therefore this description will not be provided.

[0130] Figure 28 It is along Figure 7 Another example cross-sectional view taken from line B-B'.

[0131] refer to Figure 28 ,and Figure 27 Unlike other methods, it provides a COP structure. The description of the COP structure will omit... Figure 23 and Figure 25 The description is a repetition of the previous one.

[0132] According to some embodiments, the peripheral circuit structure PS may include: a cell array 510, a line decoder 520, a page buffer 530, an input / output circuit 540, a control logic device 550, and a voltage generator 560 (including the above-mentioned components). Figure 27 (The non-volatile storage device described in some embodiments).

[0133] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without fundamentally departing from the principles of the inventive concept. Therefore, the preferred embodiments of the inventive concept disclosed herein are for general and descriptive purposes only and not for limiting purposes.

Claims

1. A nonvolatile memory device, comprising: a substrate; a cell structure including a first insulating pattern and a plurality of gate electrodes alternately stacked in a first direction on the substrate; and a word line cut region extending in a second direction different from the first direction and cutting the cell structure, wherein the word line cut region includes a common source line, and the common source line includes a second insulating pattern extending in the second direction, and a conductive pattern extending in the second direction and in contact with a cross section of the second insulating pattern in the second direction. the cell structure includes a cell array region, and an extension region having a stepped structure, and 2. The nonvolatile memory device of claim 1, wherein, the second insulating pattern is in the extension region of the cell structure. the cell array region of the cell structure is in the conductive pattern.

3. The nonvolatile memory device of claim 2, wherein, the second insulating pattern includes a first sub-insulating pattern and a second sub-insulating pattern spaced apart in the second direction, and 4. The nonvolatile memory device of claim 1, wherein, gate electrodes of the plurality of gate electrodes surrounding the first sub-insulating pattern and the second sub-insulating pattern have an H shape. the second insulating pattern includes an air gap.

5. The nonvolatile memory device of claim 1, wherein, a peripheral circuit structure including peripheral circuit elements electrically connected to the cell structure is under the substrate.

6. The nonvolatile memory device of claim 1, wherein, the second insulating pattern includes an amorphous carbon layer ACL.

7. The nonvolatile memory device of claim 1, wherein, the second insulating pattern includes a spin-on hard mask SOH.

8. The nonvolatile memory device of claim 1, wherein, 9. A nonvolatile memory device, comprising: a substrate; a cell structure including a first insulating pattern and a plurality of gate electrodes alternately stacked in a first direction on the substrate; a plurality of channel structures penetrating the cell structure; a plurality of pad electrodes electrically connected to the plurality of channel structures to supply a voltage; and a plurality of word line cut regions extending in a second direction different from the first direction and cutting the cell structure, wherein each of the plurality of word line cut regions includes a common source line, each of the common source lines includes a second insulating pattern extending in the second direction, and a conductive pattern extending in the second direction and in contact with a cross section of the second insulating pattern in the second direction, and at least one of the common source lines is spaced apart from a gate electrode of the plurality of gate electrodes stacked at a lowermost portion in the first direction in the first direction. the cell structure includes a cell array region, and an extension region having a stepped structure, the second insulating pattern is in the extension region of the cell structure.

10. The nonvolatile memory device of claim 9, wherein, the cell array region of the cell structure is in the conductive pattern. the second insulating pattern includes a first sub-insulating pattern and a second sub-insulating pattern spaced apart in the second direction, and 11. The nonvolatile memory device of claim 10, wherein, gate electrodes surrounding the first sub-insulating pattern and the second sub-insulating pattern have an H shape.

12. The nonvolatile memory device of claim 9, wherein, the second insulating pattern includes an air gap. the second insulating pattern includes an amorphous carbon layer.

13. The nonvolatile memory device of claim 9, wherein, the second insulating pattern includes a spin-on hard mask.

14. The nonvolatile memory device of claim 9, wherein, at least one of the common source lines is adjacent to the plurality of pad electrodes.

15. The nonvolatile memory device of claim 9, wherein, 17. A nonvolatile memory device, comprising:

16. The nonvolatile memory device of claim 9, wherein, a substrate; a cell structure including a first insulating pattern and a plurality of gate electrodes alternately stacked in a first direction on the substrate; ​ ​ a plurality of trench structures penetrating the mold structure, each of the plurality of trench structures including, at a lowermost level, a first semiconductor pattern, an information storage film for exposing the first semiconductor pattern, a second semiconductor pattern along the information storage film and the first semiconductor pattern, a fill pattern in the second semiconductor pattern, and a trench pad on the information storage film, the second semiconductor pattern, and the fill pattern; a word line cut region extending along a second direction different from the first direction and cutting the mold structure, the word line cut region including a common source line spacer along a sidewall of the word line cut region and exposing the substrate, and a common source line inside the common source line spacer, the common source line including a second insulating pattern extending along the second direction, and a conductive pattern extending along the second direction and in contact with a cross section of the second insulating pattern along the second direction; a first interlayer insulating film on the mold structure and around at least some of the plurality of trench structures and at least a portion of the word line cut region; a bit line contact on the trench pad; a second interlayer insulating film around the bit line contact; and a bit line formed on the second interlayer insulating film and electrically connected to the bit line contact. The second insulating pattern includes an air gap.

18. The nonvolatile memory device of claim 17, wherein, The second insulating pattern includes an amorphous carbon layer.

19. The nonvolatile memory device of claim 17, wherein, The second insulating pattern includes a spin-on hard mask.

20. The nonvolatile memory device of claim 17, wherein, ​

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