A battery pack equalization circuit with a security mechanism

Abstract

The present invention discloses a battery pack balancing circuit with a safety mechanism. The battery pack includes a plurality of series-connected single cells; the circuit includes a plurality of balancing circuits, an MCU module, and a power supply module; each single cell is respectively connected to a corresponding balancing circuit; each balancing circuit respectively includes a balancing switch circuit, a balancing control circuit, and a balancing detection circuit; for each balancing circuit, the balancing switch circuit is respectively connected to the positive and negative terminals of the single cell B, and is respectively connected to the balancing control circuit and the balancing detection circuit; the balancing control circuit and the balancing detection circuit are connected; the balancing control circuit and the balancing detection circuit are respectively connected to the MCU module; the balancing detection circuit is connected to the power supply module; the MCU module and the power supply module are connected. The present invention can reduce the failure probability of the balancing circuit, improve the reliability of the balancing circuit, and reduce the occurrence probability of safety accidents through a hardware control circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of battery management, and in particular to a battery pack equalization circuit with a safety mechanism. Background Art

[0002] The Battery Management System (BMS) is a battery protection device and a bridge between the battery and the load terminal. It is used to provide overcharge, over-discharge, over-temperature and other protection functions for the battery according to the actual use status of the battery monitored online to ensure the safe use of the battery. At present, the battery management system BMS is widely used in many fields such as electric vehicles, communication base stations, robots, consumer electronics, etc.

[0003] In actual battery applications, multiple single cells are usually connected in series to form a battery pack to provide electrical energy for the load. However, since the performance of single cells is not absolutely consistent, it is easy for there to be differences in the power between single cells. If the difference is serious, the single cells with lower power cannot be fully charged or always enter the over-discharge state first, and the single cells with higher power always enter the over-charge state first. This will not only reduce the cycle life of the battery pack, but also cause safety accidents due to frequent overcharging and over-discharging. Therefore, in the battery management system BMS, it is necessary to use a balancing circuit to reduce the power difference between single cells or maintain the power difference from continuing to increase, so as to extend the overall cycle life of the battery pack as much as possible and reduce the probability of safety accidents.

[0004] At present, in the existing passive balancing technical solution, each single cell in the battery pack is respectively configured with a balancing circuit. According to the balancing control strategy, the on and off of the corresponding balancing circuit is controlled only by software. This technical solution has the following technical problems:

[0005] First, when multiple adjacent balancing circuits are turned on at the same time, the switch in the lowest balancing switch circuit (i.e., the balancing switch circuit connected to the single cell closest to the negative end of the battery pack) will be subjected to the sum of the voltages of the several higher single cells adjacent to it. This sum of voltages may exceed the maximum specification value of the switch, and thus the switch will be broken down by the high voltage, resulting in a high failure rate.

[0006] Second, since the balancing resistor generates a lot of heat, when several adjacent balancing circuits are turned on at the same time, heat accumulation will occur, which will cause the software to frequently control the on and off of the balancing circuit to reduce heat accumulation, thus reducing the balancing effect on the battery, or even failing to achieve a good balancing effect;

[0007] Therefore, there is an urgent need to develop a circuit that can effectively improve the reliability of the equalization circuit and the equalization effect on the battery, and reduce the probability of safety accidents. Summary of the Invention

[0008] The object of the present invention is to provide a battery pack equalization circuit with a safety mechanism in view of the technical defects existing in the prior art.

[0009] To this end, the present invention provides a battery pack equalization circuit with a safety mechanism. The battery pack includes a plurality of series-connected single cells B;

[0010] The battery pack equalization circuit includes a plurality of equalization circuits, an MCU module, and a power supply module;

[0011] Among them, each single cell B is respectively connected to an equalization circuit correspondingly;

[0012] Each equalization circuit includes an equalization switch loop, an equalization control loop, and an equalization detection loop;

[0013] For each equalization circuit, the equalization switch loop is respectively connected to the positive and negative electrodes of the single cell B, and is respectively connected to the equalization control loop and the equalization detection loop;

[0014] The equalization control loop and the equalization detection loop are connected;

[0015] The equalization control loop and the equalization detection loop are respectively connected to the MCU module;

[0016] The equalization detection loop is connected to the power supply module;

[0017] Among them, the MCU module and the power supply module are connected.

[0018] Preferably, for the equalization switch loop of each equalization circuit, its input terminal 1 is respectively connected to the positive electrode B+ of a single cell B, so that the single cell B can achieve equalization through shunting of the equalization switch loop;

[0019] For the equalization switch loop of each equalization circuit, its input terminal 2 is respectively connected to the negative electrode B- of the single cell B correspondingly, so that the single cell B can achieve equalization through shunting of the equalization switch loop;

[0020] For the equalization switch loop of each equalization circuit, its input terminal 3 is respectively connected to the output terminal P3 of the equalization control loop in the equalization circuit, for receiving the control signal P3 output by the equalization control loop in the equalization circuit where it is located. The equalization control loop is used to control the on / off of the equalization switch loop;

[0021] For the equalization switch loop of each equalization circuit, its input terminal 4 is respectively connected to the output terminal P4 of the equalization control loop in this equalization circuit, for receiving the control signal P4 output by the equalization control loop in this equalization circuit, and this equalization control loop is used to control the on / off of the equalization switch loop;

[0022] For the equalization switch loop of each equalization circuit, its output terminal TB is respectively connected to the input terminal 1 of the equalization detection loop in this equalization circuit, for outputting an equalization detection control signal TB to the equalization detection loop.

[0023] Preferably, for the equalization control loop of each equalization circuit, its input terminal 1 is respectively and correspondingly connected to the positive terminal B+ of the single cell B, for receiving the voltage and current provided by the positive terminal of the single cell B;

[0024] For the equalization control loop of each equalization circuit, its input terminal 2 is respectively connected to the negative terminal of the single cell B, for receiving the voltage and current provided by the negative terminal of this single cell;

[0025] For the equalization control loop of each equalization circuit, its input terminal 3 is respectively connected to the positive terminal of the single cell adjacent to the higher position of the single cell B, for receiving the voltage and current provided by the positive terminal of the single cell adjacent to the higher position of this single cell B;

[0026] For other single cells B except for the single cell connected to the negative terminal BP- of the battery pack, the equalization control loops of the equalization circuits of these other single cells all have an input terminal 4, which is respectively connected to the output terminal P2 of the equalization control loop corresponding to the single cell adjacent to the lower position of the single cell B, for receiving the control signal P2 sent by the equalization control loop of the single cell adjacent to the lower position of the single cell B;

[0027] For the equalization control loop of each equalization circuit, its input terminal 5 is respectively connected to an output terminal of the MCU module, for receiving an equalization start signal CB sent by the MCU module for this equalization control loop, and corresponding to control the opening and cutoff of this equalization circuit according to this equalization start signal CB;

[0028] For other single cells B except for the single cell connected to the positive terminal BP+ of the battery pack, the equalization control loops of the equalization circuits of these other single cells B all have an output terminal P2, which is respectively connected to the input terminal 4 of the equalization control loop of the single cell adjacent to the higher position of the single cell B, for outputting a control signal P2 to the equalization control loop corresponding to the single cell adjacent to the higher position of the single cell B;

[0029] Wherein, for each single cell B not connected to the positive terminal BP+ of the battery pack, the single cell adjacent to it and closer to the positive terminal BP+ of the battery pack is defined as the single cell adjacent to the higher position of the single cell B;

[0030] For each single cell B that is not connected to the negative extreme BP- of the battery pack, the adjacent single cell that is closer to the negative extreme BP- of the battery pack is defined as the lower adjacent single cell of single cell B.

[0031] Preferably, for the equalization detection circuit of each equalization circuit, its input terminal 1 is respectively connected to the output terminal TB of the equalization switch circuit in the equalization circuit, for receiving the output signal TB of the equalization switch circuit in the equalization circuit, and according to the signal state of signal TB, outputting the corresponding state equalization detection signal MB to the MCU module;

[0032] For the equalization detection circuit of each equalization circuit, its input terminal 2 is respectively connected to the positive extreme B+ of single cell B, for receiving the voltage and current of single cell B;

[0033] For the equalization detection circuit of each equalization circuit, its input terminal 3 is respectively connected to an output terminal of the MCU module, for receiving the equalization start signal output by the MCU module to the equalization control circuit of single cell B;

[0034] For other single cells B except for the single cells connected to the negative extreme BP- of the battery pack, the equalization detection circuit of the equalization circuit of each single cell B has an input terminal 4, which is respectively connected to an output terminal CB of the MCU module, for receiving the equalization start signal output by the MCU module to the equalization control circuit of the lower adjacent cell of single cell B;

[0035] For the equalization detection circuit of each equalization circuit, its input terminal 5 is respectively connected to the output terminal VDD of the power supply module, for receiving the DC power supply provided by the power supply module;

[0036] For the equalization detection circuit of each equalization circuit, its detection output terminal MB is respectively connected to an input terminal of the MCU module, for outputting the equalization detection signal MB to the MCU module, and providing the equalization state of the equalization switch circuit in the equalization circuit for the MCU module.

[0037] Preferably, for the MCU module, it includes a plurality of input terminals, and each input terminal is respectively connected to the detection output terminal MB of the equalization detection circuit of an equalization circuit, for receiving the equalization detection signals MB output by a plurality of equalization detection circuits;

[0038] For the MCU module, its power input terminal VCC is connected to the output terminal VDD of the power supply module, for receiving the DC power supply provided by the power supply module;

[0039] The MCU module includes multiple output terminals, and each output terminal is respectively connected to the input terminal 5 of the balance control loop of a balance circuit, for providing a balance start signal CB to multiple balance control loops;

[0040] For the power supply module, its output terminal VDD is connected to the input terminal 5 of the balance detection loop in multiple balance circuits and the power input terminal VCC of the MCU module, for providing a DC power supply.

[0041] Preferably, for any single battery Bn-m that is not connected to the positive extreme BP+ and the negative extreme BP- of the battery pack, the balance switch loop connected to the single battery Bn-m includes: a balance resistor RBn-m, a switching transistor Q21, and a switching transistor Q22, where:

[0042] The first pin of the balance resistor RBn-m is connected to the positive extreme Bn-m+ of the single battery Bn-m;

[0043] The second pin of the balance resistor RBn-m serves as the output terminal TB of the balance switch loop and is connected to the (n-m)th input terminal of the MCU module, for providing the balance state of the balance switch loop where it is located to the MCU module;

[0044] The second pin of the balance resistor RBn-m is also connected to the collector C of the switching transistor Q21;

[0045] The base B of the switching transistor Q21 serves as the input terminal 3 of the balance switch loop and is connected to the output terminal P3 of the balance control loop;

[0046] The emitter E of the switching transistor Q21 is connected to the collector E of the switching transistor Q22;

[0047] The base B of the switching transistor Q22 serves as the input terminal 4 of the balance switch loop and is connected to the output terminal P4 of the balance control loop;

[0048] The collector C of the switching transistor Q21 is connected to the negative extreme Bn-m- of the single battery Bn-m;

[0049] Wherein, n is the number of single batteries connected in series in the battery pack, and n is a natural number greater than 3; m is a natural number greater than or equal to 1 and less than or equal to n-2.

[0050] Preferably, the balance control loop connected to the single battery Bn-m includes: resistors R20 to R26, resistor R28, resistor R30, diode D1, capacitors C21 to C22, switching transistors Q23 to Q27, and optocoupler Q28, where:

[0051] The first pin of resistor R21, as the output terminal P3 of the equalization control circuit of the single cell Bn-m, is connected to the first pin of capacitor C21 and the base B of switch Q21 which serves as the input terminal 3 in the equalization control circuit to which the single cell Bn-m is connected;

[0052] The second pin of resistor R21 is connected to terminal P5;

[0053] Terminal P5 is respectively connected to the first pin of resistor R23 and the collector C of switch Q26;

[0054] The second pin of capacitor C21 is connected to the anode of diode D1;

[0055] The anode of diode D1 is also respectively connected to the emitter E of switch Q23, the second pin of capacitor C22, the second pin of resistor R24, the emitter E of switch Q25 and the source S of switch Q27;

[0056] The second pin of resistor R23 is respectively connected to the first pin of resistor R24, the first pin of capacitor C22 and the base B of switch Q23;

[0057] The collector C of switch Q23 is connected to the second pin of resistor R22;

[0058] The first pin of resistor R22, as the output terminal P4 of the equalization control circuit of the single cell Bn-m, is connected to the base B of switch Q22 which serves as the input terminal 4 in the equalization switch circuit of the single cell Bn-m;

[0059] The cathode of diode D1, as the input terminal 2 of the equalization control circuit of the single cell Bn-m, is connected to the negative terminal Bn-m- of the single cell Bn-m;

[0060] The first pin of resistor R25, as the input terminal 3 of the equalization control circuit of the single cell Bn-m, is connected to the positive terminal Bn-m+1+ of the higher adjacent single cell Bn-m+1 of the single cell Bn-m;

[0061] The second pin of resistor R25 is respectively connected to the gate G of switch Q27 and the collector C of switch Q25;

[0062] The drain D of switch Q27, as the output terminal P2 of the equalization control circuit of the single cell Bn-m, is used to provide the control signal P2 for the equalization control circuit of the higher adjacent single cell Bn-m+1 of the single cell Bn-m;

[0063] The base B of switch Q25 is connected to terminal P1;

[0064] The P1 terminal is also respectively connected to the emitter E of the switching transistor Q26, the first pin of the resistor R28, and the second pin of the optocoupler Q28;

[0065] The base B of the switching transistor Q26 is connected to the first pin of the resistor R26;

[0066] The second pin of the resistor R26 serves as the input terminal 4 of the equalization control loop of the single cell Bn-m, and is connected to the output terminal P2 of the equalization control loop of the adjacent lower single cell Bn-m-1 of the single cell Bn-m, for receiving the control signal P2 input by the equalization control loop of the adjacent lower single cell Bn-m+1;

[0067] The second pin of the resistor R28 is connected to the negative terminal Bn-m- of the single cell Bn-m;

[0068] The first pin of the optocoupler Q28 is connected to the second pin of the resistor R20;

[0069] The third pin of the optocoupler Q28 is connected to the second pin of the resistor R30;

[0070] The fourth pin of the optocoupler Q28 is connected to the ground terminal GND;

[0071] The first pin of the resistor R20 serves as the input terminal 1 of the equalization control loop, and is connected to the positive terminal Bn-m+ of the single cell Bn-m;

[0072] The first pin of the resistor RC2 serves as the input terminal 5 of the equalization control loop, and is connected to the (n-m)-th output terminal of the MCU module, for receiving the equalization start signal CBn-m output by the MCU module.

[0073] Preferably, for the single cell B connected to the negative terminal BP- of the battery pack, the equalization control loop in the equalization circuit of this single cell is basically the same as that of the single cell Bn-m equalization control loop, except that a resistor R27 is connected between the second pin of the resistor R26 and the second pin of the resistor R28;

[0074] For the single cell B connected to the positive terminal BP+ of the battery pack, the equalization control loop in its equalization circuit is basically the same as that of the single cell Bn-m equalization control loop, except that the resistors R25, the switching transistor Q25, and the switching transistor Q27 are not connected.

[0075] Preferably, the equalization detection loop of the single cell Bn-m includes: resistors R40 to R47, switching transistors Q40 to Q43, and an optocoupler Q40, where:

[0076] The first pin of the resistor R40 serves as the input terminal 2 of the equalization detection loop, and is connected to the positive terminal Bn-m+ of the single cell Bn-m;

[0077] The second pin of resistor R40 is connected to the first pin of optocoupler Q40;

[0078] The second pin of optocoupler Q40 serves as input terminal 1 of the equalization detection circuit and is connected to the output terminal TB of the equalization switch circuit of the single cell Bn-m for receiving the equalization detection signal TB output by the equalization switch circuit;

[0079] The third pin of optocoupler Q40 is connected to the first pin of resistor R47;

[0080] The fourth pin of optocoupler Q40 is connected to the collector C of switch transistor Q41;

[0081] The base B of switch transistor Q41 is connected to the second pin of resistor R41;

[0082] The emitter E of switch transistor Q41 serves as the detection output terminal MB of the equalization detection circuit of the single cell Bn-m and is respectively connected to the first pin of resistor R42, the first pin of resistor R43, and the second pin of resistor R44;

[0083] The first pin of resistor R41 serves as input terminal 3 of the equalization detection circuit of the single cell Bn-m and is connected to the (n-m)th output terminal of the MCU module for receiving the equalization start signal CBn-m output by the MCU module to the equalization control circuit of the single cell Bn-m;

[0084] The second pin of resistor R42 is connected to the ground terminal GND;

[0085] The second pin of resistor R43 is connected to the ground terminal GND;

[0086] The first pin of resistor R44 is connected to the collector C of switch transistor Q43;

[0087] The emitter E of switch transistor Q43 is connected to the first pin of resistor R45;

[0088] The base B of switch transistor Q43 is connected to the collector C of switch transistor Q42;

[0089] The converged endpoint of the second pin of resistor R45 and the second pin of resistor R47 serves as input terminal 5 of the equalization detection circuit and is connected to the output terminal VDD of the power supply module for receiving the DC power supply of 5V;

[0090] The base B of switch transistor Q42 is connected to the first pin of resistor R46;

[0091] The emitter E of switch transistor Q42 is connected to the ground terminal GND;

[0092] The second pin of resistor R46, as the input terminal 4 of the balancing detection circuit, is connected to the (n - m - 1)-th output terminal CB of the MCU module, and is used to receive the balancing start signal CBn - m - 1 output by the MCU module to the balancing control circuit of the lower adjacent single battery Bn - m - 1 of the single battery Bn - m.

[0093] As can be seen from the technical solutions provided by the present invention above, compared with the prior art, the present invention provides a battery pack balancing circuit with a safety mechanism. Its design is scientific. Through the hardware control circuit, any adjacent multiple single batteries cannot be simultaneously balanced, reducing the failure probability of the balancing circuit, improving the reliability of the balancing circuit, thereby reducing battery damage caused by the failure of the balancing circuit, effectively improving the balancing effect on the battery, reducing the occurrence probability of safety accidents, and having great practical significance.

[0094] By applying the present invention, when the original MCU module for executing the existing balancing control strategy outputs any multiple adjacent balancing start signals due to software errors, it can automatically, according to the specified priority levels, only turn on the balancing circuit corresponding to one single battery closer to the negative extreme of the battery pack, and stop the balancing circuits corresponding to other single batteries closer to the positive extreme of the battery pack, effectively avoiding the simultaneous turning on of the balancing circuits corresponding to multiple adjacent single batteries. Therefore, not only is the failure probability of the balancing switch in the balancing circuit being broken down by high voltage significantly reduced, but also the probability of the balancing circuit failing due to heat accumulation of the heating elements in the balancing circuit is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0095] Figure 1 It is a block diagram of the structure of a battery pack balancing circuit with a safety mechanism provided by the present invention;

[0096] Figure 2 It is a circuit connection schematic diagram of one balancing switch circuit and its corresponding balancing control circuit in a battery pack balancing circuit with a safety mechanism provided by the present invention;

[0097] Figure 3 It is a circuit schematic diagram of the balancing detection circuit in a battery pack balancing circuit with a safety mechanism provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0098] To make the technical means implemented by the present invention easier to understand, the following further detailed description of the present application is given in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the relevant application, rather than limiting the application. Additionally, it should be noted that only parts related to the present application are shown in the drawings for the sake of convenience of description.

[0099] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The following will describe this application in detail with reference to the drawings and in combination with the embodiments.

[0100] See Figures 1 to 3 , the present invention provides a battery pack balancing circuit with a safety mechanism, and the battery pack includes a plurality of series-connected single cells B;

[0101] The battery pack balancing circuit includes a plurality of balancing switch circuits 100, a plurality of balancing control circuits 200, a plurality of balancing detection circuits 300, an MCU module 400, and a power supply module 500;

[0102] Among them, for each single cell B that is not connected to the positive extreme BP+ of the battery pack (i.e., not at the Figure 1 tail end of the battery pack shown), the adjacent single cell that is closer to the positive extreme BP+ of the battery pack is defined as the high-order adjacent single cell of the single cell B;

[0103] For each single cell B that is not connected to the negative extreme BP- of the battery pack (i.e., not at the Figure 1 head end of the battery pack shown), the adjacent single cell that is closer to the negative extreme BP- of the battery pack is defined as the low-order adjacent single cell of the single cell B;

[0104] Among them, each single cell B is respectively connected to a corresponding balancing circuit;

[0105] Each balancing circuit respectively includes a balancing switch circuit 100, a balancing control circuit 200, and a balancing detection circuit 300;

[0106] For each balancing circuit, the balancing switch circuit 100 is respectively connected to the positive extreme and the negative extreme of the single cell B, and is respectively connected to the balancing control circuit 200 and the balancing detection circuit 300;

[0107] The balancing control circuit 200 and the balancing detection circuit 300 are connected;

[0108] The balancing control circuit 200 and the balancing detection circuit 300 are respectively connected to the MCU module 400;

[0109] The balancing detection circuit 300 is connected to the power supply module 500;

[0110] The MCU module 400 and the power supply module 500 are connected.

[0111] In the present invention, specifically, for the equalization switch loop 100 of each equalization circuit, its input terminal 1 is respectively connected to the positive terminal B+ of a single cell B, enabling the single cell B to achieve equalization through current shunting by the equalization switch loop 100, and the current flowing through the equalization switch loop 100 is the equalization current;

[0112] For the equalization switch loop 100 of each equalization circuit, its input terminal 2 is respectively and correspondingly connected to the negative terminal B- of the single cell B, enabling the single cell B to achieve equalization through current shunting by the equalization switch loop 100;

[0113] For the equalization switch loop 100 of each equalization circuit, its input terminal 3 is respectively connected to the output terminal P3 of the equalization control loop 200 in this equalization circuit, for receiving the control signal P3 output by the equalization control loop 200 in the corresponding equalization circuit, and this equalization control loop 200 is used to control the on / off of the equalization switch loop 100;

[0114] For the equalization switch loop 100 of each equalization circuit, its input terminal 4 is respectively connected to the output terminal P4 of the equalization control loop 200 in this equalization circuit, for receiving the control signal P4 output by the equalization control loop 200 in the corresponding equalization circuit, and this equalization control loop 200 is used to control the on / off of the equalization switch loop 100;

[0115] For the equalization switch loop 100 of each equalization circuit, its output terminal TB is respectively connected to the input terminal 1 of the equalization detection loop 300 in this equalization circuit, for outputting an equalization detection control signal TB to the equalization detection loop 300, thereby controlling the signal state (such as high / low change) of the detection signal MB at the output terminal MB of the equalization detection loop 300;

[0116] In the present invention, specifically, for the equalization control loop 200 of each equalization circuit, its input terminal 1 is respectively and correspondingly connected to the positive terminal B+ of the single cell B, for receiving the voltage and current provided by the positive terminal of the single cell B;

[0117] For the equalization control loop 200 of each equalization circuit, its input terminal 2 is respectively connected to the negative terminal of the single cell B, for receiving the voltage and current provided by the negative terminal of this single cell;

[0118] For the equalization control loop 200 of each equalization circuit, its input terminal 3 is respectively connected to the positive terminal of the single cell B adjacent to the higher position of the single cell B, for receiving the voltage and current provided by the positive terminal of the single cell B adjacent to the higher position of this single cell B;

[0119] For other single cells B except the single cell B (i.e., B1) connected to the negative extreme BP- of the battery pack, the balancing control loops 200 of the balancing circuits of these other single cells B each have an input terminal 4, which are respectively connected to the output terminals P2 of the balancing control loops 200 corresponding to the lower adjacent single cells of the single cell B, for receiving the control signal P2 sent by the balancing control loop 200 of the lower adjacent single cell of the single cell B, so as to further control the state of the signals output from the output terminals P3 and P4 of this balancing control loop 200 according to this control signal P2;

[0120] In terms of specific implementation, for the single cell B (i.e., B1) connected to the negative extreme BP- of the battery pack, the input terminal 4 it has is fixed to a low level state.

[0121] It should be noted that in the technical solution of the present invention, for the input terminal 4 of the balancing control loop 200 of the single cell B1, since there is no balancing control loop 200 of an adjacent lower single cell, this input terminal 4 will be fixed to a low level state and is not related to the external input signal.

[0122] For the balancing control loop 200 of each balancing circuit, its input terminal 5 is respectively connected to an output terminal of the MCU module 400, for receiving a balancing start signal CB sent by the MCU module 400 for this balancing control loop 200, and corresponding to controlling the opening and cutoff of this balancing circuit (specifically including the balancing switch loop 100, the balancing control loop 200, and the balancing detection loop 300) according to this balancing start signal CB;

[0123] For other single cells B except the single cell B (i.e., Bn) connected to the positive extreme BP+ of the battery pack, the balancing control loops 200 of the balancing circuits of these other single cells B each have an output terminal P2, which are respectively connected to the input terminals 4 of the balancing control loops 200 of the higher adjacent single cells of the single cell B, for outputting the control signal P2 to the balancing control loop 200 corresponding to the higher adjacent single cell of the single cell B, so as to further control the signal states of the output terminal P3 and the output terminal P4 of the balancing control loop 200 corresponding to the higher adjacent single cell of the single cell B, so that the balancing circuit (specifically including the balancing switch loop 100, the balancing control loop 200, and the balancing detection loop 300) of the higher adjacent single cell of the single cell B can stop balancing;

[0124] It should be noted that in the technical solution of the present invention, for the balancing control loop 200 of the single cell Bn (i.e., the single cell B connected to the positive extreme BP+ of the battery pack), its output terminal P2 has no balancing control loop 200 of an adjacent higher single cell, so there is no need for the output terminal P2 to output the control signal P2, and this P2 terminal is an irrelevant output terminal.

[0125] For the present invention, it should be noted that when the equalization control loop 200 in the equalization circuit corresponding to a single battery B controls the connected equalization switch loop 100 to conduct, so as to equalize the single battery B, the equalization control loop 200 of the high - order adjacent single battery of the single battery B should be controlled to turn off the equalization switch loop 100 connected to the equalization control loop 200, and stop equalizing the high - order adjacent single battery of the single battery B.

[0126] In the present invention, specifically, for the equalization detection loop 300 of each equalization circuit, its input terminal 1 is respectively connected to the output terminal TB of the equalization switch loop 100 in the equalization circuit, for receiving the output signal TB of the equalization switch loop 100 in the equalization circuit, and outputting an equalization detection signal MB in the corresponding state to the MCU module 400 according to the signal state of the signal TB;

[0127] For the equalization detection loop 300 of each equalization circuit, its input terminal 2 is respectively connected to the positive terminal B+ of the single battery B, for receiving the voltage and current of the single battery B;

[0128] For the equalization detection loop 300 of each equalization circuit, its input terminal 3 is respectively connected to an output terminal of the MCU module 400, for receiving the equalization start signal output by the MCU module 400 to the equalization control loop 200 of the single battery B;

[0129] For other single batteries B except the single battery (i.e., B1) connected to the negative terminal BP - of the battery pack, the equalization detection loop 300 of the equalization circuit of each single battery B has an input terminal 4, which is respectively connected to an output terminal CB of the MCU module 400, for receiving the equalization start signal output by the MCU module 400 to the equalization control loop 200 of the low - order adjacent battery of the single battery B;

[0130] For the equalization detection loop 300 of each equalization circuit, its input terminal 5 is respectively connected to the output terminal VDD of the power supply module 500, for receiving the DC power supply (such as 5V) provided by the power supply module 500;

[0131] For the equalization detection loop 300 of each equalization circuit, its detection output terminal MB is respectively connected to an input terminal of the MCU module 400, for outputting the equalization detection signal MB to the MCU module 400, and providing the equalization state of the equalization switch loop 100 in the equalization circuit for the MCU module 400.

[0132] In the present invention, specifically, for the MCU module 400, it includes a plurality of input terminals, and each input terminal is respectively connected to the detection output terminal MB of the balance detection circuit 300 of a balance circuit, for receiving the balance detection signals MB output by a plurality of balance detection circuits 300;

[0133] For the MCU module 400, its power input terminal VCC is connected to the output terminal VDD of the power supply module 500, for receiving the DC power supply provided by the power supply module 500 (for example, 5V);

[0134] The MCU module 400 includes a plurality of output terminals, and each output terminal is respectively connected to the input terminal 5 of the balance control circuit 200 of a balance circuit, for providing a balance start signal CB to a plurality of balance control circuits 200;

[0135] It should be noted that for any single battery B in the battery pack (including the single battery Bn-m located at non-head and non-tail positions in the battery pack, as well as the first single battery B1 and the last single battery Bn), the MCU module 400 is used to determine the state of the balance circuit of the single battery B by comparing the level states of the balance start signal CB provided to the balance circuit of the single battery B and the balance detection signal MB output by the balance detection circuit in the balance circuit of the single battery B. The determination logic and the corresponding balance circuit states are specifically as follows:

[0136] 1. Balance-on state: The balance start signal CB is at a high level and the balance detection signal MB is at a high level, indicating that the balance switch circuit 100 of the single battery B is turned on, and the balance circuit is in the balance-on state;

[0137] 2. Balance-off state: The balance start signal CB is at a low level and the balance detection signal MB is 0V, indicating that the balance switch circuit 100 of the single battery B is turned off, and the balance circuit is in the balance-off state;

[0138] 3. Balance-invalid state: The balance start signal CB is at a high level and the balance detection signal MB is at a low level, indicating that the balance start signal CB is invalid. At this time, the balance switch circuit 100 corresponding to the single battery B is in the balance-off state;

[0139] 4. Balance-fault state: The balance start signal CB is at a high level and the balance detection signal MB is 0V, or the balance start signal CB is at a low level and the balance detection signal MB is at a high level, indicating that a fault has occurred in the balance circuit of the single battery B;

[0140] In the present invention, the power supply module 500 has its output terminal VDD connected to the input terminal 5 of the equalization detection circuit 300 in multiple equalization circuits and the power input terminal VCC of the MCU module 400, and is used to provide a 5V DC power supply.

[0141] In the present invention, in terms of specific implementation, refer to Figure 1 As shown, the battery pack includes n single cells, where n is a natural number greater than or equal to 1.

[0142] In Figure 1 , for the single cell B in the battery pack, n is the number of batteries connected in series in the battery pack, and correspondingly there are n equalization circuits (specifically including n equalization switch circuits 100, n equalization control circuits 200, and n equalization detection circuits 300), where n is a natural number greater than 3; m represents the position of any single cell in the battery pack, and the maximum value of m is equal to n - 2.

[0143] It should be noted that in the present invention, m is a natural number greater than or equal to 1 and less than or equal to n - 2. For example, the value of m can be 1, 2,... or n - 2, and the values increase in sequence. The larger the value of m, the closer the single cell is to the positive extreme BP+ of the battery pack, and vice versa, the closer it is to the negative extreme BP- of the battery pack.

[0144] In terms of specific implementation, for the battery pack, the single cell Bn is at the highest position in the battery pack, and the positive extreme Bn+ of the single cell Bn is connected to the positive extreme B+ of the battery pack; the single cell B1 is at the lowest position in the battery pack, and the negative extreme B1- of the single cell B1 is connected to the negative extreme B- of the battery pack.

[0145] For the battery pack, the single cell Bn - m is at the middle position in the battery pack, and it is any single cell B that is not connected to the positive extreme BP+ and the negative extreme BP- of the battery pack;

[0146] The positive extreme Bn - m+ of the single cell Bn - m is connected to the negative extreme Bn - m+1- of the adjacent higher - position single cell;

[0147] The negative extreme Bn - m- of Bn - m is connected to the positive extreme Bn - m-1+ of the adjacent lower - position single cell; for example: the positive extreme Bn - 1+ of Bn - 1 is connected to the negative extreme Bn- of Bn, and the negative extreme B2- of B2 is connected to the positive extreme B1+ of B1.

[0148] In the present invention, it should be noted that each single battery has an equalization circuit respectively. For example, the single battery Bn-m that is not connected to the positive extreme BP+ and negative extreme BP- of the battery pack corresponds to the (n - m)th equalization circuit, and the (n - m)th equalization circuit only includes the (n - m)th equalization switch loop 100, the (n - m)th equalization control loop 200, and the (n - m)th equalization detection loop 300, and does not include the MCU module 400 and the MCU module 500.

[0149] See Figure 1 As shown, taking the (n - m)th equalization circuit in Figure 1 as an example, that is, the equalization circuit of the single battery Bn-m that is not connected to the positive extreme BP+ and negative extreme BP- of the battery pack, a specific explanation is given below.

[0150] See Figure 1 For the single battery Bn-m that is not connected to the BP+ and negative extreme BP- of the battery pack, its corresponding (n - m)th equalization switch loop 100 has its input terminal 1 connected to the positive extreme Bn-m+ of the single battery Bn-m, enabling the single battery Bn-m to achieve equalization through shunting by the (n - m)th equalization switch loop 100, and the current flowing through the equalization switch loop 100 is the equalization current;

[0151] The (n - m)th equalization switch loop 100 has its input terminal 2 connected to the negative extreme Bn-m- of the single battery Bn-m, enabling the single battery Bn-m to achieve equalization through shunting by the (n - m)th equalization switch loop 100;

[0152] The (n - m)th equalization switch loop 100 has its input terminal 3 connected to the output terminal P3 of the (n - m)th equalization control loop 200, for receiving the control signal P3 output by the equalization control loop 200, and this equalization control loop 200 is used to control the on / off of the (n - m)th equalization switch loop 100;

[0153] The (n - m)th equalization switch loop 100 has its input terminal 4 connected to the output terminal P4 of the (n - m)th equalization control loop 200, for receiving the control signal P4 output by the equalization control loop 200, and this equalization control loop 200 is used to control the on / off of the (n - m)th equalization switch loop 100;

[0154] The output terminal TB of the (n - m)th equalization switch loop 100 is connected to the input terminal 1 of the (n - m)th equalization detection loop 300, for outputting an equalization detection control signal TB to the equalization detection loop 300, thereby being used to control the signal state (such as high / low change) of the detection signal MB at the output terminal MB of the (n - m)th equalization detection loop 300;

[0155] See Figure 1, for the (n - m)-th equalization control loop 200, its input terminal 1 is connected to the positive terminal Bn - m+ of the single cell Bn - m, and is used to receive the driving voltage Bn - m+ provided by the positive terminal of the single cell Bn - m;

[0156] For the (n - m)-th equalization control loop 200, its input terminal 2 is connected to the negative terminal Bn - m- of the single cell Bn - m, and is used to receive the driving voltage Bn - m- provided by the negative terminal of the single cell Bn - m;

[0157] For the (n - m)-th equalization control loop 200, its input terminal 3 is connected to the positive terminal Bn - m+1+ of the high-temperature adjacent single cell Bn - m+1 (i.e., the high-position adjacent cell of the single cell Bn - m), and is used to receive the driving voltage Bn - m+1+ provided by the positive terminal of the high-temperature adjacent single cell Bn - m+1;

[0158] For the (n - m)-th equalization control loop 200, its input terminal 4 is connected to the output terminal P2 of the equalization control loop 200 of the low-position adjacent single cell Bn - m-1, and is used to receive the control signal P2 sent by the equalization control loop 200 of the low-position adjacent single cell Bn - m-1 (i.e., the (n - m - 1)-th equalization control loop), so as to further control the state of the signals output from the output terminals P3 and P4 of the (n - m)-th equalization control loop 200 according to this control signal P2;

[0159] For the (n - m)-th equalization control loop 200, its input terminal 5 is connected to the output terminal of the MCU module 400, and is used to receive the equalization start signal CBn - m sent by the MCU module 400 for this equalization control loop 200. According to this equalization start signal CBn - m, it correspondingly controls the on and off of the (n - m)-th equalization circuit of the single cell Bn - m (specifically including the (n - m)-th equalization switch loop 100, the (n - m)-th equalization control loop 200, and the (n - m)-th equalization detection loop 300);

[0160] For the (n - m)-th equalization control loop 200, its output terminal P2 is connected to the input terminal 4 of the equalization control loop of the high-position adjacent single cell Bn - m+1 (i.e., the (n - m + 1)-th equalization control loop 200), and is used to output the control signal P2 to the equalization control loop 200 of the high-position adjacent single cell Bn - m+1 (i.e., the (n - m + 1)-th equalization control loop 200), so as to further control the signal states of the output terminal P3 and the output terminal P4 ( Figure 1 not shown in the figure) of the equalization control loop of the high-position adjacent single cell Bn - m+1, so that the (n - m + 1)-th equalization circuit of the high-position adjacent single cell Bn - m+1 (specifically including the (n - m + 1)-th equalization switch loop 100, the (n - m + 1)-th equalization control loop 200, and the (n - m + 1)-th equalization detection loop 300) stops equalization;

[0161] For the present invention, it should be noted that when the (n - m)-th equalization control loop 200 controls the connected (n - m)-th equalization switch loop 100 to conduct, so as to equalize the single battery Bn - m, the adjacent (n - m + 1)-th equalization control loop 200 should be controlled to turn off the (n - m + 1)-th equalization switch loop 100 and stop equalizing the adjacent single battery Bn - m + 1.

[0162] See Figure 1 , for the (n - m)-th equalization detection loop 300, its input terminal 1 is connected to the output terminal TB of the (n - m)-th equalization switch loop 100, and is used to receive the output signal TB of the (n - m)-th equalization switch loop 100, and output an equalization detection signal MB corresponding to the signal state to the MCU module 400 according to the signal state of the signal TB;

[0163] For the (n - m)-th equalization detection loop 300, its input terminal 2 is connected to the positive terminal Bn - m+ of the single battery Bn - m, and is used to receive the voltage and current of the single battery Bn - m;

[0164] For the (n - m)-th equalization detection loop 300, its input terminal 3 is connected to the (n - m)-th output terminal of the MCU module 400, and is used to receive the equalization start signal CBn - m output by the MCU module 400 to the equalization detection loop 300 (i.e., the (n - m)-th equalization detection loop) of the single battery Bn - m;

[0165] For the (n - m)-th equalization detection loop 300, its input terminal 4 is connected to the (n - m - 1)-th output terminal CB of the MCU module 400, and is used to receive the equalization start signal CBn - m - 1 output by the MCU module 400 to the equalization control loop 200 (i.e., the (n - m)-th equalization control loop) of the adjacent lower single battery Bn - m - 1 (i.e., the adjacent lower battery of the single battery Bn - m);

[0166] For the (n - m)-th equalization detection loop 300, its input terminal 5 is connected to the output terminal VDD of the power supply module 500, and is used to receive the DC power supply (such as 5V) provided by the power supply module 500;

[0167] For the (n - m)-th equalization detection loop 300, its detection output terminal MB is connected to the (n - m)-th input terminal (i.e., the corresponding input terminal) of the MCU module 400, and is used to output the equalization detection signal MB to the MCU module 400 to provide the equalization state of the (n - m)-th equalization switch loop 100 for the MCU module 400;

[0168] In the present invention, for the single battery Bn-m that is not connected to the positive extreme BP+ and negative extreme BP- of the battery pack, that is, the single battery Bn-m located at the non-head and non-tail positions of the battery pack (i.e., not the first single battery B1 and the last single battery Bn in the series-connected battery pack), there are two equilibrium states of the n-mth equalization switch circuit 100 connected to this single battery Bn-m, which are specifically as follows:

[0169] I. Equalization is enabled. At this time, the equalization detection signal MB output by the n-mth equalization detection circuit 300 is at a high level, indicating that equalization is being performed on the single battery Bn-m;

[0170] II. Equalization is disabled. At this time, the equalization detection signal MBn-m output by the n-mth equalization detection circuit 300 is at a low level, indicating that equalization is not being performed on the single battery Bn-m.

[0171] See Figure 1 , for the MCU module 400, its n-mth input terminal is connected to the output terminal MB of the n-mth equalization detection circuit 300, and is used to receive the equalization detection signal MB output by the n-mth equalization detection circuit 300;

[0172] For the MCU module 400, its power input terminal VCC is connected to the output terminal VDD of the power supply module 500, and is used to receive the DC power supply provided by the power supply module 500 (for example, 5V);

[0173] For the MCU module 400, its n-mth output terminal is connected to the input terminal 5 of the n-mth equalization control circuit 200, and is used to provide an equalization start signal CBn-m to the n-mth equalization control circuit 200;

[0174] In the present invention, it should be noted that among any three adjacent single-cell batteries Bn-m+1, Bn-m, and Bn-m-1, the single-cell battery Bn-m+1 is at the highest position in the battery pack (i.e., closer to the positive terminal BP+ of the battery pack) and is the higher adjacent battery of the single-cell battery Bn-m; the single-cell battery Bn-m-1 is at the lowest position in the battery pack (i.e., closer to the negative terminal BP- of the battery pack) and is the lower adjacent battery of the single-cell battery Bn-m; if the equalization start signals (including CBn-m+1, CBn-m, and CBn-m-1)) of the equalization circuits corresponding to these three single-cell batteries are all at high level, in the present invention, through the hardware circuit control logic, the equalization circuit of the single-cell battery Bn-m-1 closer to the negative terminal BP- of the battery pack (i.e., the (n-m-1)th equalization circuit) has the highest equalization priority, that is, only the equalization of the single-cell battery Bn-m-1 is allowed to be turned on, and the equalization of the other two adjacent single-cell batteries at higher positions (i.e., the single-cell battery Bn-m+1 and the single-cell battery Bn-m) is not allowed. The working principle is as follows:

[0175] When the equalization start signals CBn-m+1, CBn-m, and CBn-m-1 are all at low level, the corresponding equalization circuits are in the equalization cut-off state, that is, the equalization switch loop 100 in each equalization circuit is in the equalization cut-off state; at this time, the output terminal P2 of the equalization control loop 200 in each equalization circuit is at low level, the output terminal P3 is at low level, and the output terminal P4 is in a high impedance state, so that the equalization switch loop 100 is in the equalization cut-off state, and the equalization of the single-cell batteries Bn-m+1, Bn-m, and Bn-m-1 is not performed;

[0176] When the equalization start signals CBn-m+1, CBn-m, and CBn-m-1 all change from low level to high level, the output terminal P2 of each equalization control loop 200 will change from low level to high impedance state. Among them, the output terminal P2 of the (n - m - 1)-th equalization control loop 200 will cause the output terminal P3 of the (n - m)-th equalization control loop 200 to continue to maintain low level and the output terminal P4 to continue to maintain high impedance state, so that the (n - m)-th equalization switch loop 100 continues to maintain the equalization cut-off state. At the same time, the output terminal P2 of the (n - m)-th equalization control loop 200 will cause the output terminal P3 of the (n - m + 1)-th equalization control loop 200 to continue to maintain low level and the output terminal P4 to continue to maintain high impedance state, so that the (n - m + 1)-th equalization switch loop 100 continues to maintain the equalization cut-off state, thereby preventing both the single cell Bn-m+1 and the single cell Bn-m from performing equalization. However, since the equalization start signal CBn-m-1 is at high level, the output terminal P3 of the (n - m - 1)-th equalization control loop 200 changes from low level to high level and the output terminal P4 changes from high impedance state to low level, causing the equalization switch loop 100 to change from the equalization cut-off state to the equalization conduction state, enabling equalization of the single cell Bn-m-1.

[0177] It should be noted that for any three adjacent single cells Bn-m+1, Bn-m, and Bn-m-1, the equalization start signal CB corresponding to the low-order single cell B adjacent to the single cell Bn-m-1 should be at low level in order to turn on the equalization circuit corresponding to the single cell Bn-m-1.

[0178] In the present invention, it should be noted that the MCU module 400 is used to store the equalization control strategy and the judgment logic of the equalization circuit state. Among them, the equalization control strategy does not fall within the protection scope of the present invention and is an existing conventional equalization control technology, so no specific explanation is given to it. In the present invention, only the signal state of the equalization start signal output after the MCU module 400 executes the equalization control strategy is utilized, and the priority level of this signal is specified through the hardware circuit control logic.

[0179] It should be noted that for the single cell Bn-m located at a non-head or tail position in the battery pack, similarly, the MCU module 400 determines the state of the equalization circuit of the single cell Bn-m by comparing the level states of the equalization start signal CBn-m and the equalization detection signal MBn-m. Its judgment logic and the corresponding equalization circuit state are as follows:

[0180] 1. Equalization on state: The equalization start signal CBn-m is at high level and the equalization detection signal MBn-m is at high level, indicating that the (n - m)-th equalization switch circuit 100 of the single cell Bn-m is conducting and is in the equalization on state;

[0181] 2. Balanced cut-off state: The balanced start signal CBn-m is at a low level and the balanced detection signal MBn-m is 0V, indicating that the (n - m)-th balanced switch circuit 100 of the single battery Bn-m is cut off and in the balanced cut-off state;

[0182] 3. Balanced invalid state: The balanced start signal CBn-m is at a high level and the balanced detection signal MBn-m is at a low level, indicating that the balanced start signal CBn-m is invalid. At this time, the (n - m)-th balanced switch circuit 100 of the single battery Bn-m is in the balanced cut-off state;

[0183] 4. Balanced fault state: The balanced start signal CBn-m is at a high level and the balanced detection signal MBn-m is 0V, or the balanced start signal CBn-m is at a low level and the balanced detection signal MBn-m is at a high level, indicating that a fault has occurred in the (n - m)-th balanced circuit of the single battery Bn-m;

[0184] In the present invention, the power supply module 500 has its output terminal VDD connected to the input terminal 3 of the (n - m)-th balanced detection circuit 300 and the power input terminal VCC of the MCU module 400, and is used to provide a 5V DC power supply.

[0185] To more clearly understand the technical solution of the present invention, the working principle of a battery pack balanced circuit with a safety mechanism provided by the present invention is described as follows:

[0186] 1. When all the multiple (i.e., n) balanced start signals CB output by the MCU module 400 are at a low level, the priorities of the n balanced start signals CB are the same, and can enable all the multiple (i.e., n) balanced control circuits 200 to respectively control their corresponding balanced switch circuits 100 to be in the balanced stop state, without balancing all the multiple (i.e., n) single batteries. At this time, the balanced detection signals MB at the output terminals MB of all the multiple (i.e., n) balanced detection circuits 300 are all at a low level;

[0187] 2. When the balanced start signals CB output by the MCU module 400 for the balanced circuits of any three non-adjacent single batteries are all at a high level, the priorities of the three balanced start signals CB are the same, and can make the output terminal P3 of their respective balanced control circuits 200 be at a high level and the output terminal P4 be at a low level, so as to make their respective balanced switch circuits 100 conduct and start balancing these three single batteries;

[0188] III. When the MCU module 400 receives high-level equalization start signals CBn-m and CBn-m-1 output by any two adjacent equalization control loops 200, the equalization start signal CBn-m-1 output by the MCU module 400 to the equalization circuit of the single cell Bn-m-1 closer to the negative extreme BP- of the battery pack (i.e., the (n-m-1)th equalization circuit) has the highest priority, which can make the output terminal P3 of the (n-m)th equalization control loop 200 become low level and the output terminal P4 become high impedance state, so that the (n-m)th equalization switch loop 100 is in the equalization stop state, and no longer equalizes the (n-m)th single cell with a higher position (closer to the positive extreme BP+ of the battery pack), but only equalizes the (n-m-1)th single cell with a lower position (closer to the negative extreme BP- of the battery pack); at this time, the equalization detection signal MB at the output terminal MB of the (n-m)th equalization detection loop 300 becomes low level, while the equalization detection signal MB at the output terminal MB of the (n-m-1)th equalization detection loop 300 is high level;

[0189] Similarly, if the equalization circuits of any three adjacent single cells are turned on simultaneously, the two single cells with higher positions cannot be equalized, but only the single cell with a lower position (closer to the negative extreme BP- of the battery pack) is equalized. For example, when the MCU module 400 simultaneously sends high-level equalization start signals CB to the equalization circuits of three adjacent single cells B2, B3, and B4, only the single cell B2 with a lower position can be equalized, while the single cells B3 and B4 with higher positions (closer to the positive extreme BP+ of the battery pack) cannot be equalized, and the single cell B4 has the highest position.

[0190] It should be noted that the equalization circuit of the present invention has no influence on the original equalization strategy set in the MCU module 400. Even if the MCU module 400 simultaneously outputs equalization start signals CB for adjacent single cells, the equalization circuit of the present invention only equalizes the single cells with lower positions and automatically stops equalizing the single cells with higher positions.

[0191] To more clearly understand the technical solution of the present invention, the following specific embodiments are used to illustrate the technical solution of the present invention.

[0192] Embodiment

[0193] Taking three arbitrarily adjacent single cells Bn-m+1, single cell Bn-m, and single cell Bn-m-1 as an example, among these three single cells, the single cell Bn-m+1 has the highest position in the battery pack (closer to the positive extreme BP+ of the battery pack), and the single cell Bn-m-1 has the lowest position in the battery pack (closer to the negative extreme BP- of the battery pack).

[0194] In the present invention, in terms of specific implementation, refer to Figure 2 As shown, for any single battery Bn-m that is not connected to the positive extreme BP+ and negative extreme BP- of the battery pack, that is, the single battery Bn-m located at a non-head-and-tail position in the battery pack (i.e., not the first single battery B1 and the last single battery Bn in the battery pack), the equalization switch circuit 100 (i.e., the (n - m)-th equalization switch circuit 100) connected to this single battery Bn-m includes: an equalization resistor RB, a switching transistor Q21, and a switching transistor Q22, where:

[0195] The first pin of the equalization resistor RB is connected to the positive extreme Bn-m+ of the single battery Bn-m;

[0196] The second pin of the equalization resistor RB serves as the output terminal TB of the equalization switch circuit 100 and is connected to the (n - m)-th input terminal of the MCU module 400, for providing the equalization state of the equalization switch circuit 100 where it is located to the MCU module 400;

[0197] The second pin of the equalization resistor RB is also connected to the collector C of the switching transistor Q21;

[0198] The base B of the switching transistor Q21 serves as the input terminal 3 of the equalization switch circuit 100 and is connected to the output terminal P3 of the equalization control circuit 200;

[0199] The emitter E of the switching transistor Q21 is connected to the collector E of the switching transistor Q22;

[0200] The base B of the switching transistor Q22 serves as the input terminal 4 of the equalization switch circuit 100 and is connected to the output terminal P4 of the equalization control circuit 200;

[0201] The collector C of the switching transistor Q21 is connected to the negative extreme Bn-m- of the single battery Bn-m.

[0202] It should be noted that for the first single battery B1 and the last single battery Bn (i.e., the single batteries at both ends) in the battery pack, the equalization switch circuits 100 connected to them have the same circuit structure as the equalization switch circuit 100 of the single battery Bn-m, except for the specifically connected single batteries being different.

[0203] In the present invention, in terms of specific implementation, the working principle of the equalization switch circuit 100 is as follows:

[0204] 1. When the input terminal P3 of the (n - m)-th equalization control loop 200 and the input terminal P4 of the (n - m)-th equalization control loop 200 of the single cell Bn - m are both at high level, both the switching transistor Q21 and the switching transistor Q22 are turned on. The single cell Bn - m discharges through the positive terminal Bn - m +, the equalization resistor RB, the switching transistor Q21, the switching transistor Q22 and the negative terminal Bn - m - for equalization. At this time, the current flowing through the (n - m)-th equalization switch loop 100 is the equalization current, and the magnitude of the equalization current can be adjusted by the magnitude of the resistance value of the equalization resistor RB. The (n - m)-th equalization switch loop 100 is in the equalization on state; in the equalization on state, the equalization detection control signal TB output by the output terminal TB of the (n - m)-th equalization switch loop 100 is at low level.

[0205] 2. When any one of the input terminal 3 of the (n - m)-th equalization control loop 200 and the input terminal 4 of the (n - m)-th equalization control loop 200 is at low level, the switching transistor Q21 and the switching transistor Q22 are not all turned on. Then the single cell Bn - m will not discharge through the positive terminal Bn - m +, the equalization resistor RB, the switching transistor Q21, the switching transistor Q22 and the negative terminal Bn - m - for equalization. At this time, the equalization current in the (n - m)-th equalization switch loop 100 is zero, and the (n - m)-th equalization switch loop 100 is in the equalization stop state; in the equalization stop state, the equalization detection control signal TB output by the output terminal TB of the (n - m)-th equalization switch loop 100 is at high level.

[0206] In the present invention, in terms of specific implementation, refer to Figure 2 As shown, for any single cell Bn - m that does not connect to either the positive terminal BP + or the negative terminal BP - of the battery pack, that is, for the single cell Bn - m located at a non - head - and - tail position in the battery pack (i.e., not the first single cell B1 and the last single cell Bn in the battery pack), the equalization control loop 200 (i.e., the (n - m)-th equalization control loop 200) connected to this single cell Bn - m includes: resistors R20 - R26, resistor R28, resistor R30, diode D1, capacitors C21 - C22, switching transistors Q23 - Q27 and optocoupler Q28, where:

[0207] The first pin of the resistor R21, as the output terminal P3 of the equalization control loop 200 of the single cell Bn - m, is connected to the first pin of the capacitor C21 and the base B of the switching transistor Q21 that serves as the input terminal 3 in the equalization control loop 100 connected to the single cell Bn - m.

[0208] The second pin of the resistor R21 is connected to the P5 terminal.

[0209] The P5 terminal is respectively connected to the first pin of the resistor R23 and the collector C of the switching transistor Q26;

[0210] The second pin of the capacitor C21 is connected to the anode of the diode D1;

[0211] The anode of the diode D1 is also respectively connected to the emitter E of the switching transistor Q23, the second pin of the capacitor C22, the second pin of the resistor R24, the emitter E of the switching transistor Q25, and the source S of the switching transistor Q27;

[0212] The second pin of the resistor R23 is respectively connected to the first pin of the resistor R24, the first pin of the capacitor C22, and the base B of the switching transistor Q23;

[0213] The collector C of the switching transistor Q23 is connected to the second pin of the resistor R22;

[0214] The first pin of the resistor R22 serves as the output terminal P4 of the equalization control circuit 200 of the single cell Bn-m, and is connected to the base B of the switching transistor Q22 which serves as the input terminal 4 in the equalization switch circuit 100 of the single cell Bn-m;

[0215] The cathode of the diode D1 serves as the input terminal 2 of the equalization control circuit 200 of the single cell Bn-m, and is connected to the negative terminal Bn-m- of the single cell Bn-m;

[0216] The first pin of the resistor R25 serves as the input terminal 3 of the equalization control circuit 200 of the single cell Bn-m, and is connected to the positive terminal Bn-m+1+ of the single cell Bn-m+1;

[0217] The second pin of the resistor R25 is respectively connected to the gate G of the switching transistor Q27 and the collector C of the switching transistor Q25;

[0218] The drain D of the switching transistor Q27 serves as the output terminal P2 of the equalization control circuit 200 of the single cell Bn-m, and is used to provide the control signal P2 to the (n-m+1)-th equalization control circuit 200 (the equalization control circuit 200 of the high-order adjacent single cell Bn-m+1 of the single cell Bn-m);

[0219] The base B of the switching transistor Q25 is connected to the P1 terminal;

[0220] The P1 terminal is also respectively connected to the emitter E of the switching transistor Q26, the first pin of the resistor R28, and the second pin of the optocoupler Q28;

[0221] The base B of the switching transistor Q26 is connected to the first pin of the resistor R26;

[0222] The second pin of resistor R26, as the input terminal 4 of the equalization control circuit 200 of the single battery Bn-m, is connected to the output terminal P2 of the (n-m-1)th equalization control circuit 200 (the equalization control circuit 200 of the lower adjacent single battery Bn-m-1 of the single battery Bn-m), for receiving the control signal P2 input by the (n-m-1)th equalization control circuit 200 (the equalization control circuit of the single battery Bn-m+1).

[0223] The second pin of resistor R28 is connected to the negative terminal Bn-m- of the single battery Bn-m.

[0224] The first pin of optocoupler Q28 is connected to the second pin of resistor R20.

[0225] The third pin of optocoupler Q28 is connected to the second pin of resistor R30.

[0226] The fourth pin of optocoupler Q28 is connected to the ground terminal GND.

[0227] The first pin of resistor R20, as the input terminal 1 of the equalization control circuit 200, is connected to the positive terminal Bn-m+ of the single battery Bn-m.

[0228] The first pin of resistor R30, as the input terminal 5 of the equalization control circuit 200, is connected to the (n-m)th output terminal of the MCU module 400, for receiving the equalization start signal CBn-m output by the MCU module 400.

[0229] In the present invention, in terms of specific implementation, for the single battery B (i.e., B1) connected to the negative terminal BP- of the battery pack, the equalization control circuit 200 in the equalization circuit of this single battery is basically the same as the equalization control circuit 200 of the single battery Bn-m, except that a resistor R27 is connected between the second pin of resistor R26 and the second pin of resistor R28.

[0230] It should be noted that for resistor R27, in actual application, this resistor is only used in the equalization control circuit 200 of the single battery B1, and in the equalization control circuits of other single batteries, the resistor R27 does not need to be soldered.

[0231] In the present invention, in terms of specific implementation, for the single battery B connected to the positive terminal BP+ of the battery pack, the equalization control circuit 200 in its equalization circuit is basically the same as the equalization control circuit 200 of the single battery Bn-m, except that the resistor R25, the switching transistor Q25, and the switching transistor Q27 are not connected.

[0232] It should be noted that, in actual applications, it is not necessary to weld the resistor R25, the switch tube Q25 and the switch tube Q27 in the balancing control circuit 200 of the single cell Bn (i.e., the single cell B connected to the positive terminal BP+ of the battery pack), but it is necessary to weld the three components in the balancing control circuits of other single cells.

[0233] In the present invention, in specific implementation, the working principle of the balancing control circuit 200 of the single battery Bn-m is as follows:

[0234] 1. When the balancing start signal CBn-m of the nm-th balancing control circuit 200 is at a low level, the optical coupler Q28 is turned off, and the P1 terminal is pulled down to the negative terminal Bn-m- of the single battery Bn-m by the resistor R28, so that the switch tube Q25 is turned off, and the gate G of the switch tube Q27 is applied with the positive terminal Bn-m+1+ voltage of the single battery Bn-m+1 through the resistor R25 and is turned on, so that the output terminal P2 of the nm-th balancing control loop 200 is connected to the negative terminal Bn-m- of the single battery Bn-m through the switch tube Q27 and the diode D1 and is in a low level state, so that the switch tube Q26 ( Figure 2 (not shown) is turned on, so that the P5 terminal in the (n-m+1)th balancing control loop is connected to the P1 terminal;

[0235] In this state, if the balancing start signal CBn-m-1 output by the MCU module 400 to the nm-1 balancing control loop 200 is at a low level, then the switch tube Q27 ( Figure 2 The output terminal P2 of the equalization control loop 200 is also at a low level, so that the switch tube Q26 of the nm-th equalization control loop 200 is turned on, and the P5 terminal and the P1 terminal are connected. Since the low-level equalization start signal CBn-m-1 turns off the optical coupler Q28, the P5 terminal is pulled down to the negative terminal Bn-m- of the single battery Bn-m by the resistors R23, R24 and the diode D1, and the P1 terminal is also pulled down to the negative terminal Bn-m- of the single battery Bn-m by the resistor R28 and the diode D1. Therefore, the voltages at the P5 and P1 terminals are both equal to zero, and the switch tube Q23 is turned off, so that the output terminal P4 of the nm-th balancing control loop 200 is in a high impedance state, thereby turning off the switch tube Q22 in the nm-th balancing switch loop 100. At the same time, the voltage at the output terminal P3 of the nm-th balancing control loop 200 is also zero, so that the switch tube Q21 in the nm-th balancing switch loop 100 is turned off. At this point, the nm-th balancing switch loop 100 is controlled to be in a balancing stop state.

[0236] If the equalization start signal CBn-m-1 output by the MCU module 400 to the (n - m - 1)-th equalization control loop is at a high level, then the switching transistor Q27 ( Figure 2 not shown) in the (n - m - 1)-th equalization control loop 200 is turned off, and its output terminal P2 is in a high-impedance state, causing the switching transistor Q26 in the (n - m)-th equalization control loop 200 to be turned off, disconnecting the connection between the P5 terminal and the P1 terminal; Therefore, the P5 terminal is pulled low to the negative terminal Bn-m- of the monomer battery Bn-m by the resistor R23 and the resistor R24, making the voltage at the output terminal P3 of the (n - m)-th equalization control loop 200 zero. At the same time, the switching transistor Q23 is turned off to make the output terminal P4 of the (n - m)-th equalization control loop 200 in a high-impedance state, causing the switching transistors Q21 - Q22 in the (n - m)-th equalization switch loop 100 to be turned off, controlling the equalization switch loop 100 to be in an equalization stop state;

[0237] It should be noted that when all the n equalization start signals CB output by the MCU module 400 to the n monomer batteries are at a low level, the switching transistors Q27 in the n equalization control loops 200 of the n monomer batteries are all in a conducting state, so that the switching transistors Q26 are all in a conducting state, connecting the P5 terminal and the P1 terminal;

[0238] II. When the equalization start signal CBn-m of the (n - m)-th equalization control circuit 200 is at a high level, the optocoupler Q28 is turned on, and the P1 terminal becomes a high level through the voltage division of the resistor R20 and the resistor R28;

[0239] Since the P1 terminal is in a high-level state, the switching transistor Q25 is turned on, causing the switching transistor Q27 to be turned off, making the output terminal P2 of the (n - m)-th equalization control loop 200 in a high-impedance state, thereby causing the switching transistor Q26 ( Figure 2 not shown) in the (n - m + 1)-th equalization control loop to be turned off, disconnecting the P5 terminal and the P1 terminal in the (n - m + 1)-th equalization control loop;

[0240] In this state, if the equalization start signal CBn-m-1 of the (n - m - 1)-th equalization control loop 200 is at a low level, the switching transistor Q27 ( Figure 2 not shown) in the (n - m - 1)-th equalization control loop 200 is turned on, and its output terminal P2 is also at a low level, causing the switching transistor Q26 in the (n - m)-th equalization control loop 200 to be turned on, connecting the P5 terminal and the P1 terminal; Since the voltage at the P1 terminal is at a high level, the P5 terminal is also at a high level, making the output terminal P3 of the (n - m)-th equalization control loop 200 at a high level; At the same time, the switching transistor Q23 is turned on, making the output terminal P4 of the (n - m)-th equalization control loop 200 also at a high level. Therefore, the switching transistors Q21 - Q22 in the (n - m)-th equalization switch loop 100 are all turned on; At this time, the (n - m)-th equalization switch loop 100 is in an equalization on state;

[0241] If the equalization start signal CBn-m-1 of the (n - m - 1)-th equalization control loop is at a high level, then the switching transistor Q27 ( Figure 2 not shown) in the (n - m - 1)-th equalization control loop 200 is turned off, and its output terminal P2 is in a high-impedance state, causing the switching transistor Q26 in the (n - m)-th equalization control loop 200 to be turned off, disconnecting the connection between the P5 terminal and the P1 terminal; therefore, the P5 terminal is pulled down to the negative terminal Bn-m- of the single-cell battery Bn-m by the resistor R23 and the resistor R24, making the voltage of the output terminal P3 of the (n - m)-th equalization control loop 200 zero. At the same time, the switching transistor Q23 is turned off to make the output terminal P4 of the (n - m)-th equalization control loop 200 in a high-impedance state, causing the switching transistors Q21 - Q22 in the (n - m)-th equalization switch loop 100 to be turned off, controlling the equalization switch loop 100 to change from the equalization-on state to the equalization-off state;

[0242] It should be noted that when the equalization start signals CBn-m and CBn-m-1 output by the MCU module 400 to the equalization circuits of any two adjacent single-cell batteries Bn-m and Bn-m-1 are both at a high level, the equalization start signal CBn-m-1 of the equalization circuit of the single-cell battery Bn-m-1 closer to the negative terminal B- of the battery pack (i.e., the (n - m - 1)-th equalization circuit) has the highest priority. Only the single-cell battery Bn-m-1 is allowed to start equalization. The output terminal P2 of the (n - m - 1)-th equalization control loop 200 of the single-cell battery Bn-m-1 is in a high-impedance state, thereby causing the switching transistor Q26 in the (n - m)-th equalization control loop 200 of the single-cell battery Bn-m to be turned off, so that the output terminal P3 of the (n - m)-th equalization control loop 200 is at a low level and the output terminal P4 is in a high-impedance state, automatically changing the (n - m)-th equalization switch loop 100 from the equalization-on state to the equalization-off state, and only making the (n - m - 1)-th equalization switch loop 100 in the equalization-on state. This not only reduces the heat generation of the multiple equalization resistors caused by simultaneously turning on any adjacent equalization switch loops 100, avoids the accumulation of heat, but also reduces the probability of the equalization switch loop failure caused thereby, and does not require frequent stop and start of equalization measures due to heat accumulation, thereby improving the equalization effect on the single-cell battery.

[0243] It should be noted that when any adjacent equalization start signals are both at a high level due to the wrong equalization strategy of the MCU module 400, the equalization circuit of the present invention only responds to the equalization start signal with the highest priority and regards the equalization start signal adjacent to the equalization start signal with the highest priority as an invalid signal; in addition, when any non-adjacent equalization start signals are both at a high level, the corresponding equalization switch loops 100 are all in the equalization-on state.

[0244] In the present invention, in terms of specific implementation, refer to Figure 3 As shown, for the single battery Bn-m that does not connect to the positive extreme BP+ and negative extreme BP- of the battery pack, the equalization detection circuit 300 of the single battery Bn-m includes: resistors R40 to R47, switching transistors Q40 to Q43, and optocoupler Q40, where:

[0245] The first pin of resistor R40, as the input terminal 2 of the equalization detection circuit 300, is connected to the positive extreme Bn-m+ of the single battery Bn-m;

[0246] The second pin of resistor R40 is connected to the first pin of optocoupler Q40;

[0247] The second pin of optocoupler Q40, as the input terminal 1 of the equalization detection circuit 300, is connected to the output terminal TB of the equalization switch circuit 100 of the single battery Bn-m, for receiving the equalization detection signal TB output by the equalization switch circuit 100;

[0248] The third pin of optocoupler Q40 is connected to the first pin of resistor R47;

[0249] The fourth pin of optocoupler Q40 is connected to the collector C of switching transistor Q41;

[0250] The base B of switching transistor Q41 is connected to the second pin of resistor R41;

[0251] The emitter E of switching transistor Q41, as the detection output terminal MB of the equalization detection circuit 300 of the single battery Bn-m, is respectively connected to the first pin of resistor R42, the first pin of resistor R43, and the second pin of resistor R44;

[0252] It should be noted that the equalization detection signal MB output by the detection output terminal MB of the equalization detection circuit 300 has three states: high level, low level, and 0V.

[0253] The first pin of resistor R41, as the input terminal 3 of the equalization detection circuit 300 of the single battery Bn-m, is connected to the (n-m)th output terminal of the MCU module 400, for receiving the equalization start signal CBn-m output by the MCU module 400 to the equalization control circuit 200 (i.e., the (n-m)th equalization control circuit 200) of the single battery Bn-m;

[0254] The second pin of resistor R42 is connected to the ground terminal GND;

[0255] The second pin of resistor R43 is connected to the ground terminal GND;

[0256] The first pin of resistor R44 is connected to the collector C of switching transistor Q43;

[0257] The emitter E of the switching transistor Q43 is connected to the first pin of the resistor R45;

[0258] The base B of the switching transistor Q43 is connected to the collector C of the switching transistor Q42;

[0259] The end point after the second pin of the resistor R45 and the second pin of the resistor R47 are combined is used as the input terminal 5 of the balancing detection circuit 300, and is connected to the output terminal VDD of the power supply module 500 to receive a DC power supply of 5V;

[0260] The base B of the switching transistor Q42 is connected to the first pin of the resistor R46;

[0261] The emitter E of the switching transistor Q42 is connected to the ground terminal GND;

[0262] The second pin of the resistor R46 is used as the input terminal 4 of the balancing detection circuit 300, and is connected to the (n - m - 1)th output terminal CB of the MCU module 400 to receive the balancing start signal CBn - m - 1 output by the MCU module 400 to the adjacent lower - level single - cell battery Bn - m - 1 of the single - cell battery Bn - m in the balancing control circuit 200 (i.e., the (n - m)th balancing control circuit 200);

[0263] In the present invention, specifically, the working principle of the balancing detection circuit 300 of the single - cell battery Bn - m is as follows:

[0264] 1. When the (n - m - 1)th balancing start signal CBn - m - 1 output by the MCU module 400 to the balancing control circuit 200 of the single - cell battery Bn - m - 1 (i.e., the (n - m)th balancing control circuit 200) is at a low level, the switching transistors Q41 and Q42 are cut off;

[0265] If the (n - m)th balancing start signal CBn - m is at a high level and the balancing switch circuit 100 is in the balancing - on state, its output terminal TBn - m is at a low level, and the optocoupler Q40 is turned on; since the balancing start signal CBn - m is at a high level, after voltage division by the resistors R41 - R43, the output terminal MB of the (n - m)th balancing detection circuit 300 is at a high level; since the balancing start signal CBn - m is at a high level and the balancing state detection signal MB is also at a high level, therefore, the MCU module 400 determines that the (n - m)th balancing switch circuit 100 is in the balancing - on state.

[0266] When the (n - m)-th equalization enable signal CBn - m is at a low level and the equalization switch circuit 100 is in an equalization cut-off state, its output terminal TB is in a high-impedance state, the optocoupler Q40 is cut off, and the output terminal MB of the (n - m)-th equalization detection circuit 300 is pulled low to 0V by resistors R42 to R43; since the equalization enable signal CBn - m is at a low level and the equalization state detection signal MB is 0V, the MCU module 400 determines that the (n - m)-th equalization switch circuit 100 is in an equalization cut-off state.

[0267] When the (n - m)-th equalization enable signal CBn - m is at a high level and the equalization switch circuit 100 is in an equalization cut-off state, its output terminal TB is in a high-impedance state, the optocoupler Q40 is cut off, and the output terminal MB of the (n - m)-th equalization detection circuit 300 is pulled low to 0V by resistors R42 to R43; since the equalization enable signal CBn - m is at a high level and the equalization state detection signal MB is 0V, the MCU module 400 determines that the (n - m)-th equalization switch circuit 100 or the (n - m)-th equalization control circuit 200 is in an equalization fault state.

[0268] When the (n - m)-th equalization enable signal CBn - m is at a low level and the equalization switch circuit 100 is in a turn-on cut-off state, its output terminal TB is at a low level, the optocoupler Q40 is turned on, making the output terminal MB of the (n - m)-th equalization detection circuit 300 at a high level; since the equalization enable signal CBn - m is at a low level and the equalization state detection signal MB is at a high level, the MCU module 400 determines that the (n - m)-th equalization switch circuit 100 or the (n - m)-th equalization control circuit 200 is in an equalization fault state.

[0269] Second, when the (n - m - 1)-th equalization enable signal CBn - m - 1 is at a high level (with the highest priority), the switching transistors Q41 and Q42 are turned on, and the output voltage VDD of the power supply module 500 is divided by resistors R42 to R44 to make the output terminal MB of the (n - m)-th equalization detection circuit 300 at a low level;

[0270] Since the output terminal MB of the (n - m)-th equalization detection circuit 300 is at a low level, the MCU module 400 determines that the (n - m)-th equalization switch circuit 100 and the equalization control circuit 100 are in an equalization invalid state.

[0271] It should be noted that since the (n - m - 1)-th equalization enable signal CBn - m - 1 is at a high level and has the highest priority, the (n - m)-th equalization switch circuit 100 is in a cut-off state, then the output terminal TB of the (n - m)-th equalization switch circuit 100 is in a high-impedance state, making the optocoupler Q40 cut off. At this time, regardless of whether the (n - m)-th equalization enable signal CBn - m is at a high level or a low level, it will not affect the low-level signal state of the output terminal MB of the (n - m)-th equalization detection circuit 300.

[0272] In the present invention, specifically in implementation, it should be noted that the chip MCU of the MCU module 400 can adopt the brands, series and models that are currently widely used, such as the MC9S12 series of NXP, the TC235 of the TC2 series of Infineon, etc. The model of the chip MCU is not within the protection scope of the present invention.

[0273] In the present invention, specifically in implementation, it should be noted that the power supply module 500 is a power supply circuit commonly used in existing BMS technical solutions. Technical personnel can easily obtain and apply it without innovation. The technical solution of this power supply circuit does not belong to the technical solution of the present invention, so no specific explanation is given here.

[0274] Compared with the prior art, the battery pack equalization circuit with a safety mechanism provided by the present invention has the following beneficial effects:

[0275] 1. For the technical solution of the present invention, the hardware circuit design is scientific, and the electronic components are commonly used models, which are easy to select and the component prices are low;

[0276] 2. Since the hardware circuit of the technical solution of the present invention has low power consumption, surface mount small-power electronic components can be used. Therefore, the circuit board occupies a small space, greatly reducing the material cost. Therefore, the technical solution of the present invention has strong practical value and market promotion value.

[0277] In summary, compared with the prior art, a battery pack equalization circuit with a safety mechanism provided by the present invention is scientifically designed. It can make any adjacent multiple single cells not be able to start equalization simultaneously through the hardware control circuit, reduce the failure probability of the equalization circuit, improve the reliability of the equalization circuit, thereby reducing the battery damage caused by the failure of the equalization circuit, effectively improving the equalization effect on the battery, and reducing the occurrence probability of safety accidents, having great practical significance.

[0278] By applying the present invention, when the original MCU module for executing the existing equalization control strategy outputs any multiple adjacent equalization start signals due to software errors, it can automatically, according to the specified priority level, only turn on the equalization circuit corresponding to one single cell closer to the negative extreme of the battery pack, and stop the equalization circuits corresponding to other single cells closer to the positive extreme of the battery pack, effectively avoiding the simultaneous activation of the equalization circuits corresponding to multiple adjacent single cells. Therefore, not only is the failure probability of the equalization switch in the equalization circuit being broken down by high voltage significantly reduced, but also the probability of the failure of the equalization circuit caused by heat accumulation of the heating elements in the equalization circuit is reduced.

[0279] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A battery pack balancing circuit, characterized in that, The battery pack includes a plurality of single cells B connected in series; the battery pack balancing circuit includes a plurality of balancing circuits, an MCU module (400), and a power supply module (500); wherein, each single cell B is correspondingly connected to one balancing circuit; each balancing circuit includes a balancing switch circuit (100), a balancing control circuit (200), and a balancing detection circuit (300); for each balancing circuit, the balancing switch circuit (100) is respectively connected to the positive and negative electrodes of the single cell B, and is respectively connected to the balancing control circuit (200) and the balancing detection circuit (300); the balancing control circuit (200) is connected to the balancing detection circuit (300); the balancing control circuit (200) and the balancing detection circuit (300) are respectively connected to the MCU module (400); the balancing detection circuit (300) is connected to the power supply module (500); wherein, the MCU module (400) is connected to the power supply module (500). For any single battery Bn-m that is not connected to the positive terminal BP+ or the negative terminal BP- of the battery pack, the equalization control circuit (200) connected to the single battery Bn-m includes: resistors R20 to R26, resistor R28, resistor R30, diode D1, capacitors C21 to C22, switching transistors Q23 to Q27, and optocoupler Q28, where: The first pin of resistor R21 serves as the output terminal P3 of the equalization control circuit (200) of the single battery Bn-m, and is connected to the first pin of capacitor C21 and the base B of switching transistor Q21 that serves as input terminal 3 in the equalization control circuit (200) connected to the single battery Bn-m; The second pin of resistor R21 is connected to terminal P5; Terminal P5 is respectively connected to the first pin of resistor R23 and the collector C of switching transistor Q26; The second pin of capacitor C21 is connected to the anode of diode D1; The anode of diode D1 is also respectively connected to the emitter E of switching transistor Q23, the second pin of capacitor C22, the second pin of resistor R24, the emitter E of switching transistor Q25, and the source S of switching transistor Q27; The second pin of resistor R23 is respectively connected to the first pin of resistor R24, the first pin of capacitor C22, and the base B of switching transistor Q23; The collector C of switching transistor Q23 is connected to the second pin of resistor R22; The first pin of resistor R22 serves as the output terminal P4 of the equalization control circuit (200) of the single battery Bn-m, and is connected to the base B of switching transistor Q22 that serves as input terminal 4 in the equalization switch circuit (100) of the single battery Bn-m; The cathode of diode D1 serves as input terminal 2 of the equalization control circuit (200) of the single battery Bn-m, and is connected to the negative terminal Bn-m- of the single battery Bn-m; The first pin of resistor R25 serves as input terminal 3 of the equalization control circuit (200) of the single battery Bn-m, and is connected to the positive terminal Bn-m+1+ of the higher adjacent single battery Bn-m+1 of the single battery Bn-m; The second pin of resistor R25 is respectively connected to the gate G of switching transistor Q27 and the collector C of switching transistor Q25; The drain D of switching transistor Q27 serves as the output terminal P2 of the equalization control circuit (200) of the single battery Bn-m, and is used to provide the control signal P2 to the equalization control circuit (200) of the higher adjacent single battery Bn-m+1 of the single battery Bn-m; The base B of switching transistor Q25 is connected to terminal P1; Terminal P1 is also respectively connected to the emitter E of switching transistor Q26, the first pin of resistor R28, and the second pin of optocoupler Q28; The base B of switching transistor Q26 is connected to the first pin of resistor R26; The second pin of resistor R26 serves as input terminal 4 of the equalization control circuit (200) of the single battery Bn-m, and is connected to the output terminal P2 of the equalization control circuit (200) of the lower adjacent single battery Bn-m-1 of the single battery Bn-m, and is used to receive the control signal P2 input by the equalization control circuit (200) of the lower adjacent single battery Bn-m+1;The second pin of resistor R28 is connected to the negative terminal Bn-m- of the single cell Bn-m; the first pin of optocoupler Q28 is connected to the second pin of resistor R20; the third pin of optocoupler Q28 is connected to the second pin of resistor R30; the fourth pin of optocoupler Q28 is connected to the ground terminal GND; the first pin of resistor R20, as the input terminal 1 of the balancing control circuit (200), is connected to the positive terminal Bn-m+ of the single cell Bn-m; the first pin of resistor R30, as the input terminal 5 of the balancing control circuit (200), is connected to the (n-m)-th output terminal of the MCU module (400) for receiving the balancing start signal CBn-m output by the MCU module (400). The balancing detection circuit (300) of the single cell Bn-m includes resistors R40 to R47, switching transistors Q40 to Q43, and optocoupler Q40, where: The first pin of resistor R40, as the input terminal 2 of the balancing detection circuit (300), is connected to the positive terminal Bn-m+ of the single cell Bn-m; The second pin of resistor R40 is connected to the first pin of optocoupler Q40; The second pin of optocoupler Q40, as the input terminal 1 of the balancing detection circuit (300), is connected to the output terminal TB of the balancing switch circuit (100) of the single cell Bn-m, for receiving the balancing detection control signal TB output by the balancing switch circuit (100); The third pin of optocoupler Q40 is connected to the first pin of resistor R47; The fourth pin of optocoupler Q40 is connected to the collector C of switching transistor Q41; The base B of switching transistor Q41 is connected to the second pin of resistor R41; The emitter E of switching transistor Q41, as the detection output terminal MB of the balancing detection circuit (300) of the single cell Bn-m, is respectively connected to the first pin of resistor R42, the first pin of resistor R43, and the second pin of resistor R44; The first pin of resistor R41, as the input terminal 3 of the balancing detection circuit (300) of the single cell Bn-m, is connected to the (n-m)-th output terminal of the MCU module (400), for receiving the balancing start signal CBn-m output by the MCU module (400) to the balancing control circuit (200) of the single cell Bn-m; The second pin of resistor R42 is connected to the ground terminal GND; The second pin of resistor R43 is connected to the ground terminal GND; The first pin of resistor R44 is connected to the collector C of switching transistor Q43; The emitter E of switching transistor Q43 is connected to the first pin of resistor R45; The base B of switching transistor Q43 is connected to the collector C of switching transistor Q42; The end point after the bus connection of the second pin of resistor R45 and the second pin of resistor R47, as the input terminal 5 of the balancing detection circuit (300), is connected to the output terminal VDD of the power supply module (500), for receiving the DC power supply of 5V; The base B of switching transistor Q42 is connected to the first pin of resistor R46; The emitter E of switching transistor Q42 is connected to the ground terminal GND; The second pin of resistor R46, as the input terminal 4 of the balancing detection circuit (300), is connected to the (n-m-1)-th output terminal CB of the MCU module (400), for receiving the balancing start signal CBn-m-1 output by the MCU module (400) to the balancing control circuit (200) of the lower adjacent single cell Bn-m-1 of the single cell Bn-m.

2. The battery pack balancing circuit according to claim 1, characterized in that, For the equalization switch loop (100) of each equalization circuit, its input terminal 1 is respectively connected to the positive terminal B+ of a single cell B, so that the single cell B can achieve equalization by shunting through the equalization switch loop (100); for the equalization switch loop (100) of each equalization circuit, its input terminal 2 is respectively connected to the negative terminal B- of the single cell B, so that the single cell B can achieve equalization by shunting through the equalization switch loop (100); for the equalization switch loop (100) of each equalization circuit, its input terminal 3 is respectively connected to the output terminal P3 of the equalization control loop (200) in the equalization circuit, for receiving the control signal P3 output by the equalization control loop (200) in the equalization circuit where it is located, and the equalization control loop (200) is used to control the on / off of the equalization switch loop (100); for the equalization switch loop (100) of each equalization circuit, its input terminal 4 is respectively connected to the output terminal P4 of the equalization control loop (200) in the equalization circuit, for receiving the control signal P4 output by the equalization control loop (200) in the equalization circuit, and the equalization control loop (200) is used to control the on / off of the equalization switch loop (100); for the equalization switch loop (100) of each equalization circuit, its output terminal TB is respectively connected to the input terminal 1 of the equalization detection loop (300) in the equalization circuit, for outputting an equalization detection control signal TB to the equalization detection loop (300).

3. The battery pack balancing circuit according to claim 1, characterized in that, For the equalization control loop (200) of each equalization circuit, its input terminal 1 is respectively connected to the positive terminal B+ of the single cell B to receive the voltage and current provided by the positive terminal of the single cell B; for the equalization control loop (200) of each equalization circuit, its input terminal 2 is respectively connected to the negative terminal of the single cell B to receive the voltage and current provided by the negative terminal of the single cell B; for the equalization control loop (200) of each equalization circuit, its input terminal 3 is respectively connected to the positive terminal of the adjacent higher-position single cell of the single cell B to receive the voltage and current provided by the positive terminal of the adjacent higher-position single cell of the single cell B; for other single cells B except the single cell connected to the negative terminal BP- of the battery pack, the equalization control loops (200) of the equalization circuits of these other single cells all have an input terminal 4, which is respectively connected to the output terminal P2 of the equalization control loop (200) corresponding to the adjacent lower-position single cell of the single cell B to receive the control signal P2 sent by the equalization control loop (200) of the adjacent lower-position single cell of the single cell B; for the equalization control loop (200) of each equalization circuit, its input terminal 5 is respectively connected to an output terminal of the MCU module (400) to receive an equalization start signal CB sent by the MCU module (400) for this equalization control loop (200), and according to this equalization start signal CB, the corresponding equalization circuit is controlled to be turned on and off; for other single cells B except the single cell connected to the positive terminal BP+ of the battery pack, the equalization control loops (200) of the equalization circuits of these other single cells B all have an output terminal P2, which is respectively connected to the input terminal 4 of the equalization control loop (200) of the adjacent higher-position single cell of the single cell B to output the control signal P2 to the equalization control loop (200) corresponding to the adjacent higher-position single cell of the single cell B; wherein, for each single cell B not connected to the positive terminal BP+ of the battery pack, the adjacent single cell closer to the positive terminal BP+ of the battery pack is defined as the adjacent higher-position single cell of the single cell B; for each single cell B not connected to the negative terminal BP- of the battery pack, the adjacent single cell closer to the negative terminal BP- of the battery pack is defined as the adjacent lower-position single cell of the single cell B.

4. The battery pack balancing circuit according to claim 1, characterized in that, For the equalization detection circuit (300) of each equalization circuit, its input terminal 1 is respectively connected to the output terminal TB of the equalization switch circuit (100) in this equalization circuit, for receiving the output signal TB of the equalization switch circuit (100) in this equalization circuit, and according to the signal state of the signal TB, outputting an equalization detection signal MB corresponding to the state to the MCU module (400); for the equalization detection circuit (300) of each equalization circuit, its input terminal 2 is respectively connected to the positive terminal B+ of the single cell B, for receiving the voltage and current of the single cell B; for the equalization detection circuit (300) of each equalization circuit, its input terminal 3 is respectively connected to an output terminal of the MCU module (400), for receiving the equalization start signal output by the MCU module (400) to the equalization control circuit (200) of the single cell B; for the single cells B other than the single cell connected to the negative terminal BP- of the battery pack, the equalization detection circuit (300) of the equalization circuit of each single cell B has an input terminal 4, which is respectively connected to an output terminal CB of the MCU module (400), for receiving the equalization start signal output by the MCU module (400) to the equalization control circuit (200) of the lower adjacent cell of the single cell B; for the equalization detection circuit (300) of each equalization circuit, its input terminal 5 is respectively connected to the output terminal VDD of the power supply module (500), for receiving the DC power supply provided by the power supply module (500); for the equalization detection circuit (300) of each equalization circuit, its detection output terminal MB is respectively connected to an input terminal of the MCU module (400), for outputting the equalization detection signal MB to the MCU module (400), and providing the equalization state of the equalization switch circuit (100) in this equalization circuit to the MCU module (400).

5. The battery pack balancing circuit according to claim 4, characterized in that, For the MCU module (400), it includes a plurality of input terminals, and each input terminal is respectively connected to the detection output terminal MB of the equalization detection circuit (300) of an equalization circuit, for receiving the equalization detection signals MB output by a plurality of equalization detection circuits (300); for the MCU module (400), its power input terminal VCC is connected to the output terminal VDD of the power supply module (500), for receiving the DC power supply provided by the power supply module (500); for the MCU module (400), it includes a plurality of output terminals, and each output terminal is respectively connected to the input terminal 5 of the equalization control circuit (200) of an equalization circuit, for providing the equalization start signal CB to a plurality of equalization control circuits (200); for the power supply module (500), its output terminal VDD is connected to the input terminal 5 of the equalization detection circuit (300) in a plurality of equalization circuits and the power input terminal VCC of the MCU module (400), for providing the DC power supply.

6. The battery pack balancing circuit according to any one of claims 1 to 5, characterized in that, The equalization switch circuit (100) connected to the single cell Bn-m includes: an equalization resistor RBn-m, a switching transistor Q21, and a switching transistor Q22, where: the first pin of the equalization resistor RBn-m is connected to the positive terminal Bn-m+ of the single cell Bn-m; the second pin of the equalization resistor RBn-m serves as the output terminal TB of the equalization switch circuit (100) and is connected to the input terminal 1 of the (n-m)-th equalization detection circuit for outputting an equalization detection control signal TB to the (n-m)-th equalization detection circuit; the second pin of the equalization resistor RBn-m is also connected to the collector C of the switching transistor Q21; the base B of the switching transistor Q21 serves as the input terminal 3 of the equalization switch circuit (100) and is connected to the output terminal P3 of the equalization control circuit (200); the emitter E of the switching transistor Q21 is connected to the emitter E of the switching transistor Q22; the base B of the switching transistor Q22 serves as the input terminal 4 of the equalization switch circuit (100) and is connected to the output terminal P4 of the equalization control circuit (200); the collector C of the switching transistor Q21 is connected to the negative terminal Bn-m- of the single cell Bn-m; where n is the number of single cells connected in series in the battery pack, and n is a natural number greater than 3; m is a natural number greater than or equal to 1 and less than or equal to n-2.

7. The battery pack balancing circuit according to claim 1, characterized in that, For the single cell B connected to the negative terminal BP- of the battery pack, the structure of the equalization control circuit (200) in the equalization circuit of this single cell is basically the same as that of the equalization control circuit (200) of the single cell Bn-m, except that a resistor R27 is connected between the second pin of the resistor R26 and the second pin of the resistor R28; for the single cell B connected to the positive terminal BP+ of the battery pack, the structure of the equalization control circuit (200) in its equalization circuit is basically the same as that of the equalization control circuit (200) of the single cell Bn-m, except that the resistor R25, the switching transistor Q25, and the switching transistor Q27 are not connected.

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