A battery pack balancing circuit with parity control logic

Abstract

The present invention discloses a battery pack equalization circuit with parity control logic. The battery pack includes a plurality of series-connected single cells B. The equalization circuit includes a plurality of equalization modules, an MCU module, and a power supply module. Each equalization module respectively includes an equalization switch circuit, an equalization control circuit, and an equalization detection circuit. Each single cell B is respectively connected corresponding to an equalization module. For each equalization module, the equalization switch circuit is respectively connected to the positive and negative electrodes of a single cell B, and is respectively connected to the equalization control circuit and the equalization detection circuit; the equalization control circuit and the equalization detection circuit are connected; the equalization control circuit and the equalization detection circuit are respectively connected to the MCU module; the equalization control circuit and the equalization detection circuit are respectively connected to the power supply module; the MCU module and the power supply module are connected. The present invention can reduce the failure rate of the equalization circuit and improve the reliability of the equalization circuit through the redundant protection mechanism of the hardware control circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of battery management, and in particular to a battery pack equalization circuit with odd-even control logic. Background Art

[0002] The Battery Management System (BMS) is a battery protection device and a bridge between the battery and the load terminal. It is used to provide overcharge, over-discharge, over-temperature and other protection functions for the battery according to the actual use status of the battery monitored online to ensure the safe use of the battery. At present, the battery management system BMS is widely used in many fields such as electric vehicles, communication base stations, robots, consumer electronics, etc.

[0003] In actual battery applications, multiple single cells are usually connected in series to form a battery pack to provide electrical energy for the load. However, since the performance of single cells is not absolutely consistent, it is easy for there to be differences in the power between single cells. If the difference is serious, the single cells with lower power cannot be fully charged or always enter the over-discharge state first, and the single cells with higher power always enter the over-charge state first. This will not only reduce the cycle life of the battery pack, but also cause safety accidents due to frequent overcharging and over-discharging. Therefore, in the battery management system BMS, it is necessary to use a balancing circuit to reduce the power difference between single cells or maintain the power difference from continuing to increase, so as to extend the overall cycle life of the battery pack as much as possible and reduce the probability of safety accidents.

[0004] For the existing passive balancing technology solution, each single cell in the battery pack is equipped with a balancing circuit, and the software of the monitoring system controls the on and off of the corresponding balancing circuit. The main problems are as follows:

[0005] First, when multiple adjacent balancing circuits are turned on at the same time, the switch in the lowest balancing switch circuit (i.e., the balancing switch circuit connected to the single cell closest to the negative end of the battery pack) will be subjected to the sum of the voltages of the several higher single cells adjacent to it. This sum of voltages may exceed the maximum specification value of the switch, and thus the switch will be broken down by the high voltage, resulting in a high failure rate.

[0006] Second, when multiple adjacent balancing circuits are turned on at the same time, heat accumulation will occur due to the high heat generated by the balancing resistors in the balancing circuits, causing the monitoring system software to frequently control the on and off of the balancing circuits to reduce heat accumulation, which reduces the balancing effect on the batteries and may even fail to achieve a good balancing effect. Summary of the invention

[0007] The object of the present invention is to provide a battery pack equalization circuit with odd-even control logic in view of the technical defects existing in the prior art.

[0008] To this end, the present invention provides a battery pack equalization circuit with odd-even control logic. The battery pack includes a plurality of series-connected single cells B;

[0009] The equalization circuit includes a plurality of equalization modules, an MCU module and a power supply module;

[0010] Wherein, each equalization module respectively includes an equalization switch circuit, an equalization control circuit and an equalization detection circuit;

[0011] Wherein, each single cell B is correspondingly connected to an equalization module;

[0012] For each equalization module, the equalization switch circuit is respectively connected to the positive and negative electrodes of a single cell B, and is respectively connected to the equalization control circuit and the equalization detection circuit;

[0013] The equalization control circuit and the equalization detection circuit are connected;

[0014] The equalization control circuit and the equalization detection circuit are respectively connected to the MCU module 400;

[0015] The equalization control circuit and the equalization detection circuit are respectively connected to the power supply module;

[0016] Wherein, the MCU module and the power supply module are connected.

[0017] Preferably, for each equalization module, its input terminal 1 is respectively connected to the positive electrode B+ of a single cell B, so that the single cell B can achieve equalization through shunting of this equalization module, and the current flowing through this equalization module is the equalization current;

[0018] For each equalization module, its input terminal 2 is connected to the negative electrode B- of the single cell B, so that the single cell B can achieve equalization through shunting of this equalization module;

[0019] For each equalization module, its input terminal 3 is respectively correspondingly connected to an output terminal CB of the MCU module, and is used for receiving the equalization start signal output by the MCU module 400 to the equalization module of the higher-order adjacent single cell B of this single cell B, so as to control the opening and cutoff of the equalization module of this single cell B;

[0020] For each equalization module, its input terminal 4 is respectively correspondingly connected to an output terminal CB of the MCU module, and is used for receiving the equalization start signal CB sent by the MCU module for this equalization module;

[0021] For each equalization module, its input terminal 5 is respectively connected to an output terminal CB of the MCU module, for receiving an equalization start signal output by the MCU module 400 to the equalization module of the lower adjacent single cell of the present single cell B, and for controlling the turn-on and turn-off of the present equalization module;

[0022] For each equalization module, its input terminal 6 is connected to the output terminal VDD of the power supply module, for receiving a DC power supply of 5V;

[0023] For each equalization module, its output terminal MB is respectively connected to an input terminal of the MCU module, for outputting an equalization detection signal MB of the equalization module to the MCU module 400, and for providing the equalization state of the present equalization module to the MCU module;

[0024] Wherein, for a single cell B not connected to the positive extreme B+ of the battery pack, the adjacent single cell closer to the positive extreme B+ of the battery pack is defined as the upper adjacent single cell of the single cell B;

[0025] For a single cell B not connected to the negative extreme B- of the battery pack, the adjacent single cell closer to the negative extreme B- of the battery pack is defined as the lower adjacent single cell of the single cell B.

[0026] Preferably, for the equalization switch circuit in each equalization module, its input terminal 1, as the input terminal 1 of the present equalization module, is respectively connected to the positive extreme B+ of a single cell B, for receiving the voltage and current of the single cell B;

[0027] For the equalization switch circuit in each equalization module, its input terminal 2, as the input terminal 2 of the present equalization module, is specifically connected to the negative extreme B- of the single cell B, for receiving the voltage and current of the single cell B;

[0028] For the equalization switch circuit in each equalization module, its input terminal 3 is connected to the output terminal CK of the equalization control circuit in the present equalization module, for receiving an equalization control signal CK sent by the equalization control circuit in the present equalization module;

[0029] For the equalization switch circuit in each equalization module, its output terminal TB is connected to the input terminal 2 of the equalization detection circuit in the present equalization module, for sending an equalization detection signal TB to the equalization detection circuit in the present equalization module, and for controlling the change of the signal state of the output terminal MB of the equalization detection circuit in the present equalization module.

[0030] Preferably, for the equalization control circuit in each equalization module, its input terminal 1, as the input terminal 1 of the second equalization module, is respectively connected to the positive extreme B+ of the single cell B, for receiving the voltage and current of the single cell B;

[0031] For the equalization control loop in each equalization module, its input terminal 2, as the input terminal 2 of this equalization module, is specifically connected to the negative terminal B- of the single cell B to receive the voltage and current of the single cell B;

[0032] For the equalization control loop in each equalization module, its input terminal 3 is connected to an output terminal CB of the MCU module to receive the equalization start signal output by the MCU module 400 to the equalization module of the high adjacent single cell of the single cell B;

[0033] For the equalization control loop in each equalization module, its input terminal 4 is connected to an output terminal CB of the MCU module to receive the equalization start signal CB sent by the MCU module for this equalization control loop;

[0034] For the equalization control loop in each equalization module, its input terminal 5 is connected to an output terminal CB of the MCU module to receive the equalization start signal output by the MCU module 400 to the equalization module of the low adjacent single cell of the single cell B;

[0035] For the equalization control loop in each equalization module, its input terminal 6 is connected to the output terminal VDD of the power supply module to receive the 5V DC power supply sent by the power supply module;

[0036] For the equalization control loop in each equalization module, its output terminal CK is connected to the input terminal 3 of the equalization switch loop in this equalization module to send the equalization control signal CK to the equalization switch loop in this equalization module to control the opening and cutoff of the equalization switch loop in this equalization module.

[0037] Preferably, for the equalization detection loop in each equalization module, its input terminal 1, as the input terminal 1 of the second equalization module, is respectively connected to the positive terminal B+ of the single cell B to receive the voltage and current of the single cell B;

[0038] For the equalization detection loop in each equalization module, its input terminal 2 is connected to the output terminal TB of the equalization switch loop in this equalization module to receive the equalization detection signal TB sent by the equalization switch loop in this equalization module;

[0039] For the equalization detection loop in each equalization module, its input terminal 3 is connected to an output terminal CB of the MCU module to receive the equalization start signal output by the MCU module 400 to the equalization module of the high adjacent single cell of the single cell B;

[0040] For the equalization detection loop in each equalization module, its input terminal 4 is connected to an output terminal CB of the MCU module to receive the equalization start signal CB sent by the MCU module to this equalization detection loop;

[0041] For the balance detection circuit in each balance module, its input terminal 5 is connected to an output terminal CB of the MCU module, and is used to receive the balance start signal output by the MCU module 400 to the balance module of the adjacent lower single battery of the single battery B;

[0042] For the balance detection circuit in each balance module, its input terminal 6 is connected to the output terminal VDD of the power supply module, and is used to receive the 5V DC power supply sent by the power supply module;

[0043] For the balance detection circuit in each balance module, its output terminal MB2 is connected to an input terminal IN of the MCU module, and is used to send a balance detection signal MB to the MCU module.

[0044] Preferably, its power input terminal VCC is connected to the output terminal VDD of the power supply module, and is used to receive the 5V DC power supply;

[0045] The MCU module includes a plurality of input terminals IN, and each input terminal IN is respectively connected to the output terminal MB of a balance module, and is used to correspondingly receive a balance detection signal MB sent by a balance module, and then judge the balance state of the balance module of the single battery B according to the signal state of the balance detection signal MB specified by the preset parity control logic;

[0046] The MCU module includes a plurality of output terminals CB;

[0047] Each output terminal CB is respectively connected to the input terminal 3 of a balance module, and is used to send a balance start signal CB to each balance module respectively, and control the opening and closing of the balance module;

[0048] For the power supply module, its output terminal VDD is respectively connected to the input terminal 6 of a plurality of balance modules and the power input terminal VCC of the MCU module, and is used to provide a 5V DC power supply.

[0049] Preferably, for any single battery B that is not connected to the positive terminal B+ and the negative terminal B- of the battery pack m , the corresponding balance switch circuit connected thereto includes: a balance resistor RB2, resistors R21 to R23, a balance switch tube Q21, and a diode D22, wherein:

[0050] The first pin of the balance resistor RB2 and the first pin of the resistor R23 serve as the input terminal 1 of the balance switch circuit corresponding to the single battery B m and are both connected to the positive terminal B m of the single battery B m + to receive the voltage and current of the single battery B m ;

[0051] The second pin of the balancing resistor RB2 serves as the output terminal TB of the balancing switch circuit corresponding to the single cell Bm m ;

[0052] The output terminal TB of the balancing switch circuit corresponding to the single cell Bm m is also respectively connected to the collector C of the balancing switch transistor Q21, the cathode of the diode D22, and the second pin of the resistor R23, and is used to provide a balancing detection signal TB for the balancing detection circuit corresponding to the single cell B m ; m ;

[0053] The anode of the diode D22, the emitter E of the balancing switch transistor Q21, and the second pin of the resistor R22 serve as the input terminal 2 of the balancing switch circuit corresponding to the single cell Bm, and are all connected to the negative terminal B2- of the single cell B2, and are used to receive the voltage and current of the single cell B m ;

[0054] The base B of the balancing switch transistor Q21 is respectively connected to the first pin of the resistor R22 and the cathode of the diode D21;

[0055] The anode of the diode D21 is connected to the first pin of the resistor R21;

[0056] The second pin of the resistor R21 serves as the input terminal 3 of the balancing switch circuit corresponding to the single cell Bm, and is connected to the output terminal CK of the balancing control circuit corresponding to the single cell Bm m and is used to receive the balancing control signal CK sent by this balancing control circuit m ;

[0057] where m is any natural number less than or equal to n; for the single cell B in the battery pack, n is the number of single cells connected in series in the battery pack.

[0058] Preferably, for the single cell B m the corresponding balancing control circuit includes: resistors R201 to R208, diode D, switching transistors Q201 to Q204, and optocoupler Q205, where:

[0059] The second pin of the resistor R201 serves as the input terminal 4 of the balancing control circuit corresponding to the single cell B m and is connected to the m-th output terminal CB of the MCU module m and is used to receive the balancing start signal CB sent by the MCU module m ;

[0060] The first pin of the resistor R201 is connected to the base B of the switching transistor Q201;

[0061] The emitter E of the switching transistor Q201 is connected to the ground terminal GND;

[0062] The collector C of the switching transistor Q201 is connected to the second pin of the resistor R202;

[0063] The first pin of the resistor R202 is connected to the base B of the switching transistor Q202;

[0064] The emitter E of the switching transistor Q202 is connected to the second pin of the resistor R206;

[0065] The first pin of the resistor R206 serves as the input terminal 6 of the equalization control circuit corresponding to the single cell B m and is connected to the VDD terminal of the power supply module for receiving a 5V DC power supply;

[0066] The collector C of the switching transistor Q202 is connected to the CT terminal;

[0067] The CT terminal is respectively connected to the collector C of the switching transistor Q203, the collector C of the switching transistor Q204, and the third pin of the optocoupler Q205;

[0068] The base B of the switching transistor Q203 is respectively connected to the first pin of the resistor R203 and the first pin of the resistor R210;

[0069] The emitter E of the switching transistor Q203 is connected to the ground terminal GND;

[0070] The second pin of the resistor R203 serves as the input terminal 5 of the equalization control circuit corresponding to the single cell B m and is connected to the (m + 1)-th output terminal CB of the MCU module m+1 to receive the equalization start signal CB sent by the MCU module m+1 ;

[0071] The second pin of the resistor R210 is connected to the ground terminal GND;

[0072] The base B of the switching transistor Q204 is respectively connected to the first pin of the resistor R204 and the first pin of the resistor R209;

[0073] The emitter E of the switching transistor Q204 is connected to the ground terminal GND;

[0074] The second pin of the resistor R204 serves as the input terminal 3 of the equalization control circuit corresponding to the single cell B m and is connected to the output terminal CB of the MCU module m-1 for receiving the equalization start signal CB sent by the MCU module m-1 ;

[0075] The second pin of resistor R209 is connected to the ground terminal GND;

[0076] The fourth pin of optocoupler Q205 is connected to the first pin of resistor R205;

[0077] The first pin of optocoupler Q205 is connected to the second pin of resistor R207;

[0078] The second pin of optocoupler Q205 serves as the output terminal CK of the balancing control loop corresponding to the single cell B m and is connected to the single cell B m to the input terminal 3 of the balancing switch loop corresponding to the single cell B m ;

[0079] The second pin of optocoupler Q205 is also connected to the anode of diode D;

[0080] The cathode of diode D is connected to the second pin of resistor R208;

[0081] The first pin of resistor R208 serves as the input terminal 2 of the balancing control loop corresponding to the single cell B m and is connected to the single cell B m at its negative terminal B m - for receiving the voltage and current of the single cell B m ;

[0082] The first pin of resistor R207 serves as the input terminal 1 of the balancing control loop corresponding to the single cell B m and is connected to the single cell B m at its positive terminal B m + for receiving the voltage and current of the single cell B m ;

[0083] The second pin of resistor R205 is connected to the ground terminal GND.

[0084] Preferably, for the single cell B m the corresponding balancing detection loop includes: resistors R50 to R55, switching transistor Q51, optocoupler Q50, AND gates U21 to U22, and OR gate U23, where:

[0085] The first pin of resistor R50 serves as the input terminal 1 of the balancing detection loop corresponding to the single cell B m and is connected to the single cell B m at its positive terminal B m + for receiving the voltage and current of the single cell B m ;

[0086] The second pin of resistor R50 is connected to the first pin of optocoupler Q50;

[0087] The second pin of optocoupler Q50 serves as the input terminal 2 of the equalization detection circuit corresponding to the single cell B and is connected to the single cell B m The output terminal TB of the equalization switch circuit corresponding to the connection m is used to receive the equalization detection signal TB sent by the equalization switch circuit corresponding to the single cell B m ; m m ;

[0088] The third pin of optocoupler Q50 is connected to the first pin of resistor R51;

[0089] The fourth pin of optocoupler Q50, the first pin of resistor R52, the first pin of resistor R54, and the emitter E of switch transistor Q51 are all connected to the output terminal MB of the equalization detection circuit corresponding to the single cell B m m and are connected;

[0090] The single cell B m The output terminal MB of the equalization detection circuit corresponding to the connection m is connected to the m-th input terminal IN of the MCU module m to provide the equalization detection signal MB for the MCU module m ;

[0091] The second pins of resistor R52 and resistor R54 are respectively connected to the ground terminal GND;

[0092] The second pin of resistor R51 and the first pin of resistor R53 serve as the input terminal 5 of the second equalization detection circuit and are respectively connected to the power supply terminal VDD of the power supply module to receive a 5V DC power supply;

[0093] The second pin of resistor R53 is connected to the collector C of switch transistor Q51;

[0094] The base B of switch transistor Q51 is connected to the first pin of resistor R55;

[0095] The second pin of resistor R55 is connected to the third pin of OR gate U23 to receive the control signal issued by the OR gate U23;

[0096] The first pin of OR gate U23 is connected to the third pin of AND gate U21 to receive the control signal issued by the AND gate U21;

[0097] The second pin of OR gate U23 is connected to the third pin of AND gate U22 to receive the control signal issued by the AND gate U22;

[0098] The first pin of AND gate U21 serves as the single cell B​​m The input terminals 3 of the corresponding balanced detection circuits are all connected to the (m - 1)-th output terminal CB of the MCU module m-1 , and are used to receive the balanced start signal CB output by the MCU module to the adjacent lower single battery B m m-1 m-1 ;

[0099] The second pin of AND gate U21 and the first pin of AND gate U22, as the input terminal 4 of the second balanced detection circuit, are both connected to the output terminal CB of the MCU module m , and are used to receive the balanced start signal CB2 output by the MCU module to the corresponding balanced detection circuit connected to single battery B m ;

[0100] The second pin of AND gate U22, as the input terminal 5 of the second balanced detection circuit, is connected to the output terminal CB of the MCU module m+1 , and is used to receive the balanced start signal CB output by the MCU module to the adjacent higher single battery of single battery B m m+1 .

[0101] As can be seen from the technical solutions provided by the present invention above, compared with the prior art, the present invention provides a battery pack balancing circuit with parity control logic, which is scientifically designed. Through the redundant protection mechanism of the hardware control circuit, the odd and even adjacent single batteries cannot be balanced simultaneously, thereby reducing the failure rate of the balancing circuit, improving the reliability of the balancing circuit, reducing the battery damage caused by the failure of the balancing circuit, and reducing the occurrence probability of safety accidents, which has great practical significance. Description of the Drawings

[0102] Figure 1 is a schematic block diagram of a battery pack balancing circuit with parity control logic provided by the present invention

[0103] Figure 2 is a schematic block diagram of the second balancing module in a battery pack balancing circuit with parity control logic provided by the present invention

[0104] Figure 3a For any single battery B in the present invention m , it is the schematic diagram of the corresponding m-th balancing switch circuit

[0105] Figure 3b is the schematic diagram of the second balancing switch circuit corresponding to single battery B2 in the specific embodiment of the present invention, that is, m is 2

[0106] Figure 4a ​​​In the present invention, for any single cell B m , the schematic diagram of the m-th equalization control loop corresponding thereto;

[0107] Figure 4b In the present invention, in a specific embodiment, the schematic diagram of the 2nd equalization control loop corresponding to the single cell B2, that is, m is 2.

[0108] Figure 5a In the present invention, for any single cell B m , the schematic diagram of the m-th equalization detection loop corresponding thereto;

[0109] Figure 5b In the present invention, in a specific embodiment, the schematic diagram of the 2nd equalization detection loop corresponding to the single cell B2, that is, m is 2. Detailed implementation manners

[0110] To make the technical means implemented by the present invention easier to understand, the present application will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the relevant application, rather than limiting the application. In addition, it should be noted that, for the sake of convenience of description, only the parts related to the present application are shown in the drawings.

[0111] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and embodiments.

[0112] Refer to Figures 1 to 5b , the present invention provides a battery pack equalization circuit with odd-even control logic, and the battery pack includes a plurality of series-connected single cells B;

[0113] The equalization circuit includes a plurality of equalization modules 100, an MCU module 200, and a power supply module 300;

[0114] Among them, each equalization module 100 includes an equalization switch loop 1001, an equalization control loop 1002, and an equalization detection loop 1003 respectively;

[0115] Among them, each single cell B is respectively connected corresponding to an equalization module 100.

[0116] For each equalization module 100, the equalization switch loop 1001 is respectively connected to the positive and negative electrodes of a single cell B, and is respectively connected to the equalization control loop 1002 and the equalization detection loop 1003;

[0117] The equalization control loop 1002 and the equalization detection loop 1003 are connected;

[0118] The balancing control circuit 1002 and the balancing detection circuit 1003 are respectively connected to the MCU module 400;

[0119] The balancing control circuit 1002 and the balancing detection circuit 1003 are respectively connected to the power supply module 300;

[0120] Among them, the MCU module 200 is connected to the power supply module 300.

[0121] In the present invention, for each single cell B that is not connected to the positive terminal B+ of the battery pack (i.e., not at the end of the battery pack shown), the adjacent single cell that is closer to the positive terminal B+ of the battery pack is defined as the high-order adjacent single cell of the single cell B; Figure 1 For each single cell B that is not connected to the negative terminal B- of the battery pack (i.e., not at the beginning of the battery pack shown), the adjacent single cell that is closer to the negative terminal B- of the battery pack is defined as the low-order adjacent single cell of the single cell B;

[0122] In the present invention, for each single cell B that is not connected to the negative terminal B- of the battery pack (i.e., not at the beginning of the battery pack shown), the adjacent single cell that is closer to the negative terminal B- of the battery pack is defined as the low-order adjacent single cell of the single cell B; Figure 1 For each single cell B that is not connected to the negative terminal B- of the battery pack (i.e., not at the beginning of the battery pack shown), the adjacent single cell that is closer to the negative terminal B- of the battery pack is defined as the low-order adjacent single cell of the single cell B;

[0123] In the present invention, in terms of specific implementation, refer to Figure 1 As shown, the battery pack includes n single cells, where n is a natural number greater than or equal to 1.

[0124] In Figure 1 , for the single cell B in the battery pack, n is the number of batteries connected in series in the battery pack, and correspondingly there are n balancing modules 100.

[0125] Figure 1 In, the larger the value of n, it means that the position of the single cell in the battery pack is lower and it is closer to the negative terminal B- of the battery pack. On the contrary, the higher the position in the battery pack, the closer it is to the positive terminal B+ of the battery pack.

[0126] In the present invention, the single cell B n is at the lowest position in the battery pack, that is, the negative terminal B n of is connected to the negative terminal B- of the battery pack; the single cell B1 is at the highest position in the battery pack, that is, the positive terminal B1+ of B1 is connected to the positive terminal B+ of the battery pack. n It should be noted that each single cell B has a balancing module 100 respectively, that is, there are n balancing modules 100 for n single cells; the MCU module 200 has n balancing start signal output terminals CB (including the balancing start signal output terminals CB1 to CB

[0127] ) and are respectively connected to the corresponding balancing modules 100 for sending the balancing start signal CB. For example, as n )Figure 1 As shown, the single cells B1 to B n respectively correspond to the 1st to the nth equalization modules 100, and the 1st to the nth equalization modules 100 respectively correspond to the output terminals CB1 to CB of the MCU module 200 n .

[0128] It should be noted that, at the input terminal of each equalization module 100, in addition to being connected to the respective corresponding single cell B and receiving the respective corresponding equalization start signal CB, it is also necessary to receive the equalization start signals CB corresponding to all adjacent equalization modules 100. Among them, for the equalization module 100 of any single cell that is not connected to the positive extreme B+ or the negative extreme B- of the battery pack, it will receive the equalization start signals CB corresponding to two adjacent equalization modules 100. And for the single cell B1 connected to the positive extreme B+ of the battery pack and the single cell B n connected to the negative extreme B- of the battery pack, since their equalization modules have only one adjacent equalization module, they only receive the equalization start signal CB corresponding to the adjacent equalization module 100.

[0129] For example, Figure 1 for the 2nd equalization module 100 in, in addition to receiving the equalization start signal CB2, it also needs to receive the equalization start signal CB1 corresponding to the 1st equalization module 100 and the equalization start signal CB3 corresponding to the 3rd equalization module 100; similarly, the 3rd equalization module 100 receives the equalization start signals CB2, CB3, and CB4 at the same time, and the 4th equalization module 100 receives the equalization start signals CB3, CB4, and CB5 at the same time, and so on.

[0130] It should be noted that the output terminal MB of each equalization module 100 is respectively connected to the input terminal IN of the MCU module 200, and is used to send an equalization status signal MB to the MCU module 200, so that the MCU module 200 can judge the equalization status of each equalization module 100 in real time.

[0131] In the present invention, specifically, for each equalization module 100, its input terminal 1 (specifically including the input terminal 1 of the equalization switch circuit 1001, the input terminal 1 of the equalization detection circuit 1003, and the input terminal 1 of the equalization control circuit 1003) is respectively connected to the positive extreme B+ of a single cell B, so that the single cell B can achieve equalization through the shunt of this equalization module 100, and the current flowing through this equalization module 100 is the equalization current;

[0132] For each equalization module 100, its input terminal 2 (specifically including the input terminal 2 of the equalization detection circuit 1003 and the input terminal 2 of the equalization control circuit 1002) is connected to the negative terminal B- of the single battery B, enabling the single battery B to achieve equalization through shunting by this equalization module 100;

[0133] For each equalization module 100, its input terminal 3 (specifically including the input terminal 3 of the equalization detection circuit 1003 and the input terminal 3 of the equalization control circuit 1002) is respectively connected to an output terminal CB of the MCU module 200, for receiving the equalization start signal (specifically the equalization start signal output to the equalization control circuit 1002 in the equalization module 100) output by the MCU module 400 to the equalization module 100 of the high - level adjacent single battery of this single battery B, thereby controlling the on - off of the equalization module 100 of this single battery B;

[0134] Among them, for the single battery B1 connected to the positive terminal B+ of the battery pack, since there is no high - level adjacent battery, the input terminal 3 of the corresponding equalization module 100 is floating and will not receive the equalization start signal CB.

[0135] For each equalization module 100, its input terminal 4 (specifically including the input terminal 4 of the equalization detection circuit 1003 and the input terminal 4 of the equalization control circuit 1002) is respectively connected to an output terminal CB of the MCU module 200, for receiving the equalization start signal CB sent by the MCU module 200 for this equalization module 100 (specifically the equalization control circuit 1002 in this equalization module 100);

[0136] For each equalization module 100, its input terminal 5 (specifically including the input terminal 5 of the equalization detection circuit 1003 and the input terminal 5 of the equalization control circuit 1002) is respectively connected to an output terminal CB of the MCU module 200, for receiving the equalization start signal (specifically the equalization start signal output to the equalization control circuit 1002 in the equalization module 100) output by the MCU module 400 to the equalization module 100 of the low - level adjacent single battery of this single battery B, for controlling the on - off of this equalization module;

[0137] Among them, for the single battery B connected to the negative terminal B- of the battery pack n , since there is no low - level adjacent battery, the input terminal 5 of the corresponding equalization module 100 is floating and will not receive the equalization start signal CB.

[0138] For each equalization module 100, its input terminal 6 (specifically including the input terminal 6 of the equalization detection circuit 1003 and the input terminal 6 of the equalization control circuit 1002) is connected to the output terminal VDD of the power supply module 300, for receiving the DC power supply of 5V;

[0139] For each equalization module 100, its output terminal MB (specifically, the output terminal MB of the equalization detection circuit 1003) is respectively connected to an input terminal of the MCU module 200, and is used to output the equalization detection signal MB of the equalization module 100 to the MCU module 400, so as to provide the equalization state of this equalization module 100 for the MCU module 200. The signal states of the equalization detection signal MB include three types: high level, low level, and 0V;

[0140] In the present invention, specifically in implementation, for the equalization switch circuit 1001 in each equalization module 100, its input terminal 1, as the input terminal 1 of this equalization module 100, is respectively connected to the positive electrode B+ of a single battery B, and is used to receive the voltage and current of the single battery B;

[0141] For the equalization switch circuit 1001 in each equalization module 100, its input terminal 2, as the input terminal 2 of this equalization module 100, is specifically connected to the negative electrode B- of the single battery B, and is used to receive the voltage and current of the single battery B;

[0142] For the equalization switch circuit 1001 in each equalization module 100, its input terminal 3 is connected to the output terminal CK of the equalization control circuit 1002 in this equalization module 100, and is used to receive the equalization control signal CK sent by the equalization control circuit 1002 in this equalization module 100;

[0143] For the equalization switch circuit 1001 in each equalization module 100, its output terminal TB is connected to the input terminal 2 of the equalization detection circuit 1003 in this equalization module 100, and is used to send the equalization detection signal TB to the equalization detection circuit 1003 in this equalization module 100, and control the change of the signal state of the output terminal MB of the equalization detection circuit 1003 in this equalization module 100.

[0144] In the present invention, specifically in implementation, for the equalization control circuit 1002 in each equalization module 100, its input terminal 1, as the input terminal 1 of the second equalization module 100, is respectively connected to the positive electrode B+ of the single battery B, and is used to receive the voltage and current of the single battery B;

[0145] For the equalization control circuit 1002 in each equalization module 100, its input terminal 2, as the input terminal 2 of this equalization module 100, is specifically connected to the negative electrode B- of the single battery B, and is used to receive the voltage and current of the single battery B;

[0146] For each equalization control loop 1002 in the equalization module 100, its input terminal 3 is connected to an output terminal CB of the MCU module 200, and is used to receive the equalization start signal output by the MCU module 400 to the equalization module 100 of the high adjacent single battery of the single battery B (specifically, the equalization start signal output to the equalization control loop 1002 in the equalization module 100);

[0147] For each equalization control loop 1002 in the equalization module 100, its input terminal 4 is connected to an output terminal CB of the MCU module 200, and is used to receive the equalization start signal CB sent by the MCU module 200 for this equalization control loop 1002;

[0148] For each equalization control loop 1002 in the equalization module 100, its input terminal 5 is connected to an output terminal CB of the MCU module 200, and is used to receive the equalization start signal output by the MCU module 400 to the equalization module 100 of the low adjacent single battery of the single battery B (specifically, the equalization start signal output to the equalization control loop 1002 in the equalization module 100);

[0149] For each equalization control loop 1002 in the equalization module 100, its input terminal 6 is connected to the output terminal VDD of the power supply module 300, and is used to receive the 5V DC power supply sent by the power supply module 300;

[0150] For each equalization control loop 1002 in the equalization module 100, its output terminal CK is connected to the input terminal 3 of the equalization switch loop 1001 in this equalization module 100, and is used to send the equalization control signal CK2 to the equalization switch loop 1001 in this equalization module 100 to control the opening and cutoff of the equalization switch loop 1001 in this equalization module 100.

[0151] In the present invention, specifically in implementation, for each equalization detection loop 1003 in the equalization module 100, its input terminal 1, as the input terminal 1 of the second equalization module 100, is respectively connected to the positive terminal B+ of the single battery B, and is used to receive the voltage and current of the single battery B;

[0152] For each equalization detection loop 1003 in the equalization module 100, its input terminal 2 is connected to the output terminal TB of the equalization switch loop 1001 in this equalization module 100, and is used to receive the equalization detection signal TB sent by the equalization switch loop 1001 in this equalization module 100;

[0153] For the equalization detection circuit 1003 in each equalization module 100, its input terminal 3 is connected to an output terminal CB of the MCU module 200, and is used to receive the equalization start signal output by the MCU module 400 to the equalization module 100 of the high adjacent single battery of the single battery B (specifically, the equalization start signal output to the equalization control circuit 1002 in the equalization module 100);

[0154] For the equalization detection circuit 1003 in each equalization module 100, its input terminal 4 is connected to an output terminal CB of the MCU module 200, and is used to receive the equalization start signal CB sent by the MCU module 200 to this equalization detection circuit 1003;

[0155] For the equalization detection circuit 1003 in each equalization module 100, its input terminal 5 is connected to an output terminal CB of the MCU module 200, and is used to receive the equalization start signal output by the MCU module 400 to the equalization module 100 of the low adjacent single battery of the single battery B (specifically, the equalization start signal output to the equalization control circuit 1002 in the equalization module 100);

[0156] For the equalization detection circuit 1003 in each equalization module 100, its input terminal 6 is connected to the output terminal VDD of the power supply module 300, and is used to receive the 5V DC power supply sent by the power supply module 300;

[0157] For the equalization detection circuit 1003 in each equalization module 100, its output terminal MB2 is connected to an input terminal IN of the MCU module 200, and is used to send the equalization detection signal MB to the MCU module 200.

[0158] See Figure 1 、 Figure 2 As shown, taking the second equalization module in Figure 1 、 Figure 2 as an example, that is, the equalization module of the single battery B2 that is not connected to the positive extreme B+ and negative extreme B- of the battery pack, a specific explanation is made. It should be noted that the working principle and structural design of any other single battery that is not connected to the positive extreme B+ and negative extreme B- of the battery pack are the same as those of the single battery B2.

[0159] In Figure 2 for the second equalization module 100, its input terminal 1 (specifically including the input terminal 1 of the equalization switch circuit 1001, the input terminal 1 of the equalization detection circuit 1003, and the input terminal 1 of the equalization control circuit 1003) is connected to the positive extreme B2+ of the single battery B2, so that the single battery B2 can achieve equalization through shunting by the second equalization module 100, and the current flowing through the equalization module 100 is the equalization current;

[0160] The second balancing module 100, whose input terminal 2 (specifically including the input terminal 2 of the balancing detection circuit 1003 and the input terminal 2 of the balancing control circuit 1002) is connected to the negative terminal B2- of the single battery B2, enables the single battery B2 to achieve balancing through shunting by the second balancing module 100;

[0161] The second balancing module 100, whose input terminal 3 (specifically including the input terminal 3 of the balancing detection circuit 1003 and the input terminal 3 of the balancing control circuit 1002) is connected to the output terminal CB1 of the MCU module 200, is used to receive the balancing start signal CB1 sent by the MCU module 200 (that is, used to receive the balancing start signal output by the MCU module 400 to the balancing module 100 of the high adjacent single battery of the single battery B2, specifically the balancing start signal output to the balancing control circuit 1002 in the balancing module 100), so as to control the opening and closing of the second balancing module of the single battery B2;

[0162] The second balancing module 100, whose input terminal 4 (specifically including the input terminal 4 of the balancing detection circuit 1003 and the input terminal 4 of the balancing control circuit 1002) is connected to the output terminal CB2 of the MCU module 200, is used to receive the balancing start signal CB2 sent by the MCU module 200 for this balancing module 100 (specifically the balancing control circuit 1002 in this balancing module 100);

[0163] The second balancing module 100, whose input terminal 5 (specifically including the input terminal 5 of the balancing detection circuit 1003 and the input terminal 5 of the balancing control circuit 1002) is connected to the output terminal CB3 of the MCU module 200, receives the balancing start signal CB3 sent by the MCU module 200 (that is, used to receive the balancing start signal output by the MCU module 400 to the balancing module 100 of the low adjacent single battery of the single battery B2, specifically the balancing start signal output to the balancing control circuit 1002 in the balancing module 100), and is used to control the opening and closing of the second balancing module of the single battery B2;

[0164] The second balancing module 100, whose input terminal 6 (specifically including the input terminal 6 of the balancing detection circuit 1003 and the input terminal 6 of the balancing control circuit 1002) is connected to the output terminal VDD of the power supply module 300, is used to receive the DC power supply of 5V;

[0165] The output terminal MB of the second balancing module 100 (specifically the output terminal MB of the balancing detection circuit 1003) is connected to the second input terminal of the MCU module 200, and is used to output the balancing detection signal MB of the balancing module 100 to the MCU module 400, so as to provide the MCU module 200 with the balancing state of this balancing module 100. The MB signal state includes three types: high level, low level, and 0V;

[0166] In the present invention, in terms of specific implementation, in Figure 2 for the second equalization module 100, the input terminal 1 of the second equalization switch circuit 1001 thereof serves as the input terminal 1 of the second equalization module 100 and is specifically connected to the positive terminal B2+ of the single cell B2 for receiving the voltage and current of the single cell B2;

[0167] The input terminal 2 of the second equalization switch circuit 1001 serves as the input terminal 2 of the second equalization module 100 and is specifically connected to the negative terminal B2- of the single cell B2 for receiving the voltage and current of the single cell B2;

[0168] The input terminal 3 of the second equalization switch circuit 1001 is connected to the output terminal CK2 of the second equalization control circuit 1002 (i.e., the equalization control circuit 1002 in this equalization module 100) for receiving the equalization control signal CK2 sent by the second equalization control circuit 1002;

[0169] The output terminal TB2 of the second equalization switch circuit 1001 is connected to the input terminal 2 of the second equalization detection circuit 1003 (i.e., the equalization detection circuit 1003 in this equalization module 100) for sending the equalization detection signal TB2 to the second equalization detection circuit 1003 and controlling the change of the signal state of the output terminal MB2 of the second equalization detection circuit 1003;

[0170] In the present invention, in terms of specific implementation, for the second equalization module 100, the input terminal 1 of the second equalization control circuit 1002 thereof serves as the input terminal 1 of the second equalization module 100 and is specifically connected to the positive terminal B2+ of the single cell B2 for receiving the voltage and current of the single cell B2;

[0171] The input terminal 2 of the second equalization control circuit 1002 serves as the input terminal 2 of the second equalization module 100 and is specifically connected to the negative terminal B2- of the single cell B2 for receiving the voltage and current of the single cell B2;

[0172] The input terminal 3 of the second equalization control circuit 1002 is connected to the output terminal CB1 of the MCU module 200 for receiving the equalization start signal CB1 sent by the MCU module 200 (i.e., for receiving the equalization start signal output by the MCU module 400 to the equalization module 100 of the high - level adjacent single cell of the single cell B2, specifically the equalization start signal output to the equalization control circuit 1002 in the equalization module 100);

[0173] The input terminal 4 of the second equalization control loop 1002 is connected to the output terminal CB2 of the MCU module 200, and is used to receive the equalization start signal CB2 sent by the MCU module 200 for this equalization control loop 1002;

[0174] The input terminal 5 of the second equalization control loop 1002 is connected to the output terminal CB3 of the MCU module 200, and is used to receive the equalization start signal CB3 sent by the MCU module 200 (that is, used to receive the equalization start signal output by the MCU module 400 to the equalization module 100 of the low adjacent single cell of the single cell B2, specifically the equalization start signal output to the equalization control loop 1002 in the equalization module 100);

[0175] The input terminal 6 of the second equalization control loop 1002 is connected to the output terminal VDD of the power supply module 300, and is used to receive the 5V DC power supply sent by the power supply module 300;

[0176] The output terminal CK2 of the second equalization control loop 1002 is connected to the input terminal 3 of the second equalization switch loop 1001 (that is, the equalization switch loop 1001 in this equalization module 100), and is used to send the equalization control signal CK2 to the second equalization switch loop 1001 to control the opening and closing of the second equalization switch loop 1001;

[0177] In the present invention, specifically in implementation, for the second equalization module 100, the input terminal 1 of the second equalization detection loop 1003 thereof serves as the input terminal 1 of the second equalization module 100, and is specifically connected to the positive terminal B2+ of the single cell B2, and is used to receive the voltage and current of the single cell B2;

[0178] The input terminal 2 of the second equalization detection loop 1003 is connected to the output terminal TB2 of the second equalization switch loop 1001 (that is, the equalization switch loop 1001 in this equalization module 100), and is used to receive the equalization detection signal TB2 sent by the second equalization switch loop 1001;

[0179] The input terminal 3 of the second equalization detection loop 1003 is connected to the output terminal CB1 of the MCU module 200, and is used to receive the equalization start signal CB1 sent by the MCU module 200 (that is, used to receive the equalization start signal output by the MCU module 400 to the equalization module 100 of the high adjacent single cell of the single cell B2, specifically the equalization start signal output to the equalization control loop 1002 in the equalization module 100);

[0180] The input terminal 4 of the second equalization detection circuit 1003 is connected to the output terminal CB2 of the MCU module 200, and is used to receive the equalization start signal CB2 sent by the MCU module 200 to this equalization detection circuit 1003;

[0181] The input terminal 5 of the second equalization detection circuit 1003 is connected to the output terminal CB3 of the MCU module 200, and is used to receive the equalization start signal CB3 sent by the MCU module 200 (that is, used to receive the equalization start signal output by the MCU module 400 to the equalization module 100 of the low adjacent single battery of the single battery B2, specifically the equalization start signal output to the equalization control circuit 1002 in the equalization module 100);

[0182] The input terminal 6 of the second equalization detection circuit 1003 is connected to the output terminal VDD of the power supply module 300, and is used to receive the 5V DC power supply sent by the power supply module 300;

[0183] The output terminal MB2 of the second equalization detection circuit 1003 is connected to the input terminal IN2 of the MCU module 200, and is used to send the equalization detection signal MB2 to the MCU module 200;

[0184] In the present invention, specifically in implementation, for the MCU module 200, its power input terminal VCC is connected to the output terminal VDD of the power supply module 300, and is used to receive the 5V DC power supply.

[0185] In the present invention, specifically in implementation, in Figure 1 the MCU module 200 includes multiple (for example, n) input terminals IN, and each input terminal IN is respectively connected to the output terminal MB of an equalization module 100, and is used to correspondingly receive the equalization detection signal MB sent by an equalization module 100, and then according to the signal state of the equalization detection signal MB specified by the preset parity control logic (see Tables 1 to 4), to judge the equalization state of the equalization module 100 of any one single battery B (that is, B m );

[0186] For the MCU module 200, the preset parity control logic it has is specifically: the parity of m, the state of the equalization start signal CB m the state of the equalization detection signal TB m the state of the equalization detection signal MB m the state and the corresponding relationship between the equalization state of the equalization module 100 of any one single battery B m (that is, the mth equalization module) are pre-stored and set, and can be seen in Tables 1 to 4.

[0187] Specifically in implementation, such as Figure 2As shown, the input terminal IN2 of the MCU module 200 is connected to the output terminal MB2 of the second equalization module 100, and the input terminal IN3 of the MCU module 200 is connected to the output terminal MB3 of the third equalization module 100;

[0188] Figure 1 Among them, the MCU module 200 includes a plurality of (for example, n) output terminals CB;

[0189] Each output terminal CB is respectively connected to the input terminal 3 of an equalization module 100, and is used to send an equalization start signal CB to each equalization module 100 respectively, for controlling the opening and closing of the equalization module 100 corresponding to any single battery B;

[0190] Specifically, as Figure 2 shown, the output terminal CB2 of the MCU module 200 is connected to the input terminal 4 of the second equalization module 100, and the output terminal CB3 of the MCU module 200 is connected to the input terminal 4 of the third equalization module 100;

[0191] The power supply module 300, whose output terminal VDD is respectively connected to the input terminal 6 of a plurality of equalization modules 100 and the power input terminal VCC of the MCU module 200, is used to provide a 5V DC power supply;

[0192] Specifically, as Figure 2 shown, the output terminal VDD of the power supply module 300 is connected to the input terminal 6 of the second equalization module 100;

[0193] It should be noted that the MCU module 200 is used to store the equalization control strategy and the equalization state judgment logic. Among them, the equalization control strategy does not belong to the protection scope of the present invention, so no specific explanation is made for it. In the present invention, only the signal state of the equalization start signal CB output after the MCU module 200 executes the equalization control strategy is used to control the equalization state of the corresponding equalization circuit 100. The equalization state includes:

[0194] 1. Equalization opening state: conforming to the "odd - even different opening" control logic, there is an equalization current in the m - th equalization module 100;

[0195] It should be noted that for the n equalization modules 100, the first equalization module 100 is the equalization module corresponding to the single battery B1 at the positive extreme B + of the battery pack; the n - th equalization module 100 is the equalization module corresponding to the single battery B n correspondingly connected;

[0196] For the single battery B in the battery pack, n is the number of batteries connected in series in the battery pack. For any single battery B in the battery pack m, m represents the position of any single battery in the battery pack, and m is any natural number less than or equal to n. When m is odd, the single battery B m corresponds to the odd-position equalization module 100 (such as the 1st, 3rd, 5th equalization modules), and when m is even, the single battery B m corresponds to the even-position equalization module 100 (such as the 2nd, 4th, 6th equalization modules).

[0197] 2. Equalization cut-off state: Meeting the "odd-even not on simultaneously" control logic, there is no equalization current in the m-th equalization module 100;

[0198] 3. Equalization invalid state: Not meeting the "odd-even not on simultaneously" control logic, there is no equalization current in the m-th equalization module 100;

[0199] 4. Equalization fault state: The m-th equalization module 100 fails to correctly respond to the "odd-even not on simultaneously" control logic.

[0200] In the technical solution of the present invention, the odd-even control logic and the circuit working principle are as follows:

[0201] I. Equalization start and cut-off states: When the signal states of the n (for example, n is 6) odd-even adjacent equalization start signals CB output by the MCU module 200 are as shown in Table 1 (taking 6 adjacent single batteries B m as an example, m is any natural number less than or equal to n, the same below), it indicates that CB m meets the signal state combination specified by the "odd-even not on simultaneously" control logic. Then, the equalization module 100 corresponding to the high-level CB m is in the equalization on state, while the equalization module 100 corresponding to the low-level CB m is in the equalization cut-off state;

[0202] Table 1: Equalization start and cut-off states.

[0203]

[0204] In Table 1, m is any natural number less than or equal to n, and n is equal to 6 at this time.

[0205] In Table 1, among the six adjacent single cells B1 to B6, the equalization start signals of the corresponding six equalization modules 100 are CB1 to CB6 respectively, which conform to the signal state combination specified by the "odd-even different start" control logic; when the signal states of the equalization start signals CB1, CB3, and CB5 with odd m are high levels, and the signal states of the equalization start signals CB2, CB4, and CB6 with even m are low levels, the 1st, 3rd, and 5th equalization modules 100 are in the equalization on state, while the 2nd, 4th, and 6th equalization modules 100 are in the equalization off state;

[0206] Since the equalization start signals CB1, CB3, and CB5 are high levels, the output terminals CK1, CK3, and CK5 of the 1st, 3rd, and 5th equalization control circuits 1002 are all high levels (see Figure 2 ), after the 1st, 3rd, and 5th equalization switch circuits 1001 are turned on, the equalization detection signals TB m output from their respective output terminals TB are low levels (CK1, CK3, CK5, TB1, TB3, and TB5 are not shown in Figure 2 ), correspondingly, the equalization detection signals MB n output from the output terminals MB of the 1st, 3rd, and 5th equalization detection circuits 1003 m are high levels, then the MCU module 200 can determine that the 1st, 3rd, and 5th equalization modules 100 are in the equalization on state by judging the high-level CB m and the high-level equalization detection signal MB m ;

[0207] Since the equalization start signals CB2, CB4, and CB6 are low levels, the output terminals CK2, CK4, and CK6 of the 2nd, 4th, and 6th equalization control circuits 1002 are all low levels, making the 1st, 3rd, and 5th equalization switch circuits 1001 cut off, and the equalization detection signals TB1, TB3, and TB5 output from their respective output terminals TB m are high levels (CK4, CK6, TB4, and TB6 are not shown in Figure 2 ), correspondingly, the equalization detection signals MB m output from the output terminals MB of the 1st, 3rd, and 5th equalization detection circuits 1003 m are 0V, then the MCU module 200 can determine that the 1st, 3rd, and 5th equalization modules 100 are in the equalization off state by judging the low-level equalization start signal CB m and the 0V equalization detection signal MB m .

[0208] II. Balancing invalid state: When the signal states of n (e.g., n equals 6) parity - adjacent balancing start signals CB output by the MCU module 200 m are as shown in Table 2, it indicates that CB m does not fully conform to the signal state combinations specified by the "odd - even different - on" control logic. Then, the balancing modules 100 corresponding to multiple adjacent high - level balancing start signals CB m are in the balancing invalid state, while the balancing modules 100 corresponding to the low - level CB m adjacent to the high - level CB m are in the balancing cut - off state;

[0209] Table 2: Balancing invalid state.

[0210]

[0211] In Table 2, among the 6 adjacent single - cell batteries B1 - B6, the balancing start signals of the corresponding 6 balancing modules 100 are CB1 - CB6 respectively, which do not conform to the signal state combinations specified by the "odd - even different - on" control logic: When the signal states of 4 parity - adjacent balancing start signals CB1, CB2, CB3, and CB4 are all high - level, the 1st to 4th balancing modules 100 are all cut off. At this time, these 4 balancing modules 100 are all in the balancing invalid state. And the balancing start signal CB5 of the 5th balancing module 100 adjacent to the 4th balancing start signal CB4 is low - level. The balancing start signals CB4 and CB5 conform to the signal state combinations specified by the "odd - even different - on" control logic, so the 5th balancing module 100 is in the balancing cut - off state, rather than the balancing invalid state; Similarly, if the balancing start signal CB7 is low - level (not shown in Table 2), the balancing start signals CB5 and CB6 conform to the signal state combinations specified by the "odd - even different - on" control logic, then the 6th balancing module 100 is in the balancing on state;

[0212] Since the balancing start signals CB1, CB2, CB3, and CB4 are all high - level, the 1st to 4th balancing modules 100 are in the balancing invalid state. Then, the output terminals CK1, CK2, CK3, and CK4 of the 1st to 4th balancing control loops 1002 are all low - level (see Figure 2 ), making the 1st to 4th balancing switch loops 1001 cut off, and the balancing detection signals TB1, TB2, TB3, and TB4 output by their respective output terminals TB m are high - level (CK1, CK3, CK4, TB1, TB3, and TB4 are not shown in Figure 2 ). Correspondingly, the balancing detection signals MB m output by the output terminals MB of the 1st to 4th balancing detection loops 1003m is at a low level, the MCU module 200 determines the high-level CB m and the low-level equalization detection signal MB m can determine that the first to fourth equalization modules 100 are in an ineffective equalization state.

[0213] III. Equalization fault state: When the n (for example, n equals 6) equalization start signals CB m output by the MCU module 200, the equalization detection signal TB m and the equalization detection signal MB m are in the signal states shown in Table 3 and Table 4, it indicates that the mth equalization circuit is in an equalization fault state; where m is any natural number less than or equal to n.

[0214] In Table 3, among the 6 adjacent single cells B1 - B6, the equalization start signals of the corresponding 6 equalization modules 100 are CB1 - CB6 respectively, which conform to the signal state combination specified by the "odd - even different turn - on" control logic;

[0215] When two adjacent equalization start signals CB1 is at a low level and CB2 is at a high level, since the equalization start signal CB1 is at a low level, the first equalization module 100 should not be turned on and is in an equalization cut - off state. The equalization detection signal TB1 should be at a high level, and the equalization detection signal MB1 should be 0V; however, when the equalization detection signal MB1 is at a high level or a low level, it indicates that the first equalization module 100 is in an equalization fault state. At this time, the equalization detection signal TB1 is at a low level;

[0216] Since the equalization start signal CB2 is at a high level, the second equalization module 100 should be turned on and is in an equalization on state. The equalization detection signal TB2 should be at a low level, and the equalization detection signal MB2 should be at a high level; however, when the equalization detection signal MB2 is at a low level or 0V, it indicates that the second equalization module 100 is in an equalization fault state. At this time, the equalization detection signal TB2 is at a high level;

[0217] Table 3: Equalization fault state (conforming to odd - even control logic).

[0218]

[0219] In Table 4, among the 6 adjacent single cells B1 - B6, the equalization start signals of the corresponding 6 equalization modules 100 are CB1 - CB6 respectively, which do not conform to the signal state combination specified by the "odd - even different turn - on" control logic;

[0220] Table 4: Equalization fault state (not conforming to odd - even control logic).

[0221]

[0222]

[0223] When the signal states of two adjacent even and odd equalization start signals CB1 and CB2 are at high level, the first to second equalization modules 100 are all cut off. At this time, these two equalization modules 100 are all in the equalization invalid state, and the equalization detection signals TB1 and TB2 should be at high level. However, when the equalization detection signals MB1 and MB2 are at high or low level, it indicates that the first to second equalization modules 100 are in the equalization fault state. At this time, the equalization detection signals TB1 and TB2 are at low level;

[0224] Similarly, when the signal states of three adjacent even and odd equalization start signals CB4, CB5, and CB6 are all at high level, the equalization detection signals MB4, MB5, and MB6 are at high level or 0V, indicating that the fourth to sixth equalization modules 100 are in the equalization fault state. At this time, the equalization detection signals TB4 to TB6 are at low level;

[0225] It should be noted that according to the even-odd control logic, the MCU module 200 determines the equalization state of the m-th equalization module 100 by judging the signal combination state of the equalization start signal CB m and the equalization detection signal MB m .

[0226] To more clearly understand the technical solution of the present invention, the following combines specific embodiments to illustrate the technical solution of the present invention.

[0227] Embodiment

[0228] See Figure 2 、 Figure 3a and Figure 3b As shown, in the present invention, in terms of specific implementation, see Figure 2 As shown, for any single battery B m (that is, not the first single battery B1 and the last single battery B n ) in the battery pack that is not connected to the positive terminal B+ and the negative terminal B- of the battery pack, the corresponding connected equalization module 100 is the same.

[0229] Figure 3a For the single battery B m , it is the schematic diagram of the corresponding m-th equalization switch circuit 1001; Figure 3b In the specific embodiment, it is the schematic diagram of the second equalization switch circuit 1001 corresponding to the single battery B2, that is, m is 2.

[0230] For the single battery B m, the corresponding connected equalization module 100 includes an m-th equalization switch circuit 1001, an m-th equalization control circuit 1002, and an m-th equalization detection circuit 1003.

[0231] In the present invention, in terms of specific implementation, refer to Figure 3a As shown, for the single cell B m , the corresponding connected equalization switch circuit 1001 (i.e., the m-th equalization switch circuit 1001) includes: an equalization resistor RB2, resistors R21 to R23, an equalization switch transistor Q21, and a diode D22, where:

[0232] The first pin of the equalization resistor RB2 and the first pin of the resistor R23, as the input terminal 1 of the equalization switch circuit 1001 (i.e., the m-th equalization switch circuit 1001) corresponding to the single cell B m , are both connected to the positive terminal B m of the single cell B m +, for receiving the voltage and current of the single cell B m ;

[0233] The second pin of the equalization resistor RB2, as the output terminal TB of the equalization switch circuit 1001 corresponding to the single cell Bm m ;

[0234] The output terminal TB of the equalization switch circuit 1001 corresponding to the single cell Bm m , is also respectively connected to the collector C of the equalization switch transistor Q21, the cathode of the diode D22, and the second pin of the resistor R23, for providing an equalization detection signal TB m to the equalization detection circuit 1003 (i.e., the m-th equalization detection circuit 1003) corresponding to the single cell B m ;

[0235] The anode of the diode D22, the emitter E of the equalization switch transistor Q21, and the second pin of the resistor R22, as the input terminal 2 of the equalization switch circuit 1001 corresponding to the single cell Bm, are all connected to the negative terminal B2- of the single cell B2, for receiving the voltage and current of the single cell B m ;

[0236] The base B of the equalization switch transistor Q21 is respectively connected to the first pin of the resistor R22 and the cathode of the diode D21;

[0237] The anode of the diode D21 is connected to the first pin of the resistor R21;

[0238] The second pin of resistor R21, as the input terminal 3 of the balancing switch circuit 1001 corresponding to the single cell Bm, is connected to the output terminal CK of the balancing control circuit 1002 (i.e., the mth balancing control circuit 1002) corresponding to the single cell Bm m , for receiving the balancing control signal CK sent by the balancing control circuit 1002 m , and this control signal can control the on and off of the balancing switch circuit 1001 corresponding to the single cell Bm;

[0239] In the present invention, specifically, the working principle of the balancing switch circuit 1001 (i.e., the mth balancing switch circuit 1001) corresponding to the single cell Bm is as follows:

[0240] I. Balancing on: When the balancing control signal CK output by the output terminal CK of the mth balancing control circuit 1002 m is at a high level, the switching transistor Q21 conducts, and the single cell B m discharges through the positive terminal B m +, the balancing resistor RB2, the balancing switching transistor Q21 and the negative terminal B m - for balancing. At this time, the current flowing through the mth balancing switch circuit 1001 is the balancing current, and the magnitude of the balancing current can be adjusted by the magnitude of the resistance value of the balancing resistor RB2. The second balancing switch circuit 1001 is in the balancing on state; in the balancing on state, since the balancing switching transistor Q21 conducts, the output terminal TB of the second balancing switch circuit 100 m is at a low level, and its voltage amplitude is equal to the saturation conduction voltage drop of the balancing switching transistor Q21. m is at a low level, and its voltage amplitude is equal to the saturation conduction voltage drop of the balancing switching transistor Q21.

[0241] II. Balancing off: When the balancing control signal CK output by the output terminal CK of the mth balancing control circuit 1002 m is at a low level, the balancing switching transistor Q21 cuts off, and the single cell B m cannot discharge through the positive terminal B m +, the balancing resistor RB2, the balancing switching transistor Q21 and the negative terminal B m - for balancing. At this time, no balancing current flows through the mth balancing switch circuit 1001, and the mth balancing switch circuit 1001 is in the balancing off state; in the balancing off state, since the balancing switching transistor Q21 cuts off, the output terminal TB of the mth balancing switch circuit 100 m is pulled up to a high level through the balancing resistor RB2 and the resistor R23, and its voltage amplitude is equal to the single cell B m m ​The voltage value.

[0242] It should be noted that if the input terminal 1 of the m-th equalization switch circuit 1001 is connected to the negative terminal B m of the single battery B m -, and its input terminal 2 is connected to the positive terminal B m of the single battery B m +, then the equalization switch tube Q21 will be damaged due to reverse voltage, resulting in the permanent failure of the equalization switch circuit 1001, and even exhausting the power of the single battery B m ; in order to avoid this kind of failure, the m-th equalization switch circuit 1001 provided by the present invention also has an anti-reverse connection protection mechanism, which can avoid the circuit failure phenomenon caused by reverse connection. The anti-reverse connection protection mechanism is specifically as follows:

[0243] When reverse connection occurs, the anode of the diode D22 is connected to the positive terminal B m of the single battery B m +, the first pin of the resistor R23 is connected to the negative terminal B m of the single battery B m -, at this time the single battery B m discharges through the diode D22 and the resistor R23, and the voltage between the emitter E and the collector C of the equalization switch tube Q21 is equal to the conduction voltage drop of the diode D22; in order to make the diode D21 cut off reliably, in the specific implementation of the present invention, the voltage value of the equalization control signal CK m is less than the voltage value of the single battery B m , the resistor R22 makes the voltage between the emitter E and the base B of the equalization switch tube Q21 equal, both equal to the voltage value of the single battery B m , so that the voltage borne by the equalization switch tube Q21 is within the specified voltage range, avoiding the phenomenon of failure due to excessive reverse voltage.

[0244] It should be noted that the diode D22 can be selected as a light-emitting diode, which is convenient for the operator to immediately discover and eliminate the fault when reverse connection occurs.

[0245] Figure 4a For any single battery B m , the schematic diagram of the corresponding m-th equalization control circuit 1002; Figure 4b In a specific embodiment, it is the schematic diagram of the second equalization control circuit 1002 corresponding to the single battery B2, that is, m is 2.

[0246] In the present invention, in the specific implementation, refer to Figure 4a , Figure 4b shown, for any single battery B m, the corresponding connected equalization control loop 1002 (i.e., the m-th equalization control loop 1002) includes: resistors R201 to R208, diode D200, switching transistors Q201 to Q204, and optocoupler Q205, where:

[0247] The second pin of resistor R201 serves as the input terminal 4 of the equalization control loop 1002 corresponding to the single cell B m , and is connected to the m-th output terminal CB of the MCU module 200 m , for receiving the equalization start signal CB sent by the MCU module 200 m ;

[0248] The first pin of resistor R201 is connected to the base B of switching transistor Q201;

[0249] The emitter E of switching transistor Q201 is connected to the ground terminal GND;

[0250] The collector C of switching transistor Q201 is connected to the second pin of resistor R202;

[0251] The first pin of resistor R202 is connected to the base B of switching transistor Q202;

[0252] The emitter E of switching transistor Q202 is connected to the second pin of resistor R206;

[0253] The first pin of resistor R206 serves as the input terminal 6 of the equalization control loop 1002 corresponding to the single cell B m , and is connected to the VDD terminal of the power supply module 300, for receiving a 5V DC power supply;

[0254] The collector C of switching transistor Q202 is connected to the CT terminal;

[0255] The CT terminal is respectively connected to the collector C of switching transistor Q203, the collector C of switching transistor Q204, and the third pin of optocoupler Q205;

[0256] The base B of switching transistor Q203 is respectively connected to the first pin of resistor R203 and the first pin of resistor R210;

[0257] The emitter E of switching transistor Q203 is connected to the ground terminal GND;

[0258] The second pin of resistor R203 serves as the input terminal 5 of the equalization control loop 1002 corresponding to the single cell B m , and is connected to the (m + 1)-th output terminal CB of the MCU module 200 m+1 , for receiving the equalization start signal CB sent by the MCU module 200 m+1 ;

[0259] The second pin of resistor R210 is connected to the ground terminal GND;

[0260] The base B of switching transistor Q204 is respectively connected to the first pin of resistor R204 and the first pin of resistor R209;

[0261] The emitter E of switching transistor Q204 is connected to the ground terminal GND;

[0262] The second pin of resistor R204 serves as the input terminal 3 of the equalization control circuit 1002 corresponding to the single battery B m and is connected to the output terminal CB of the MCU module 200 m-1 for receiving the equalization start signal CB sent by the MCU module 200 m-1 ;

[0263] The second pin of resistor R209 is connected to the ground terminal GND;

[0264] The fourth pin of optocoupler Q205 is connected to the first pin of resistor R205;

[0265] The first pin of optocoupler Q205 is connected to the second pin of resistor R207;

[0266] The second pin of optocoupler Q205 serves as the output terminal CK of the equalization control circuit 1002 corresponding to the single battery B m and is connected to the input terminal 3 of the equalization switch circuit 1001 corresponding to the single battery B m to provide the equalization control signal CK m which can control the turn-on and turn-off of the equalization switch circuit 1001 corresponding to the single battery B m ; m The second pin of optocoupler Q205 is also connected to the anode of diode D200;

[0267] The cathode of diode D200 is connected to the second pin of resistor R208;

[0268] The first pin of resistor R208 serves as the input terminal 2 of the equalization control circuit 1002 corresponding to the single battery B

[0269] and is connected to the negative terminal B m of the single battery B m to receive the voltage and current of the single battery B m ; m The first pin of resistor R207 serves as the input terminal 1 of the equalization control circuit 1002 corresponding to the single battery B

[0270] and is connected to the single battery B m ; mThe positive terminal B m +, for receiving the single cell B m voltage and current;

[0271] The second pin of resistor R205 is connected to the ground terminal GND.

[0272] In the present invention, specifically, for the single cell B (i.e., B1) connected to the positive terminal B+ of the battery pack, the structure of the equalization control circuit 1002 of this single cell is basically the same as that of the equalization control circuit 1002 of the single cell Bm, except that its input terminal 3 is floating (i.e., vacant) and not connected to other modules.

[0273] In the present invention, specifically, for the single cell B (i.e., B n ) connected to the negative terminal B- of the battery pack, the structure of the equalization control circuit 1002 of this single cell is basically the same as that of the equalization control circuit 1002 of the single cell Bm, except that its input terminal 5 is floating (i.e., vacant) and not connected to other modules or parts.

[0274] In the present invention, specifically, the working principle of the equalization control circuit 1002 corresponding to the single cell Bm (i.e., the m-th equalization control circuit 1002) is as follows:

[0275] I. Equalization start: The adjacent even and odd equalization start signals CBm m-1 , CB m , CB m+1 meet the signal state combination specified by the "even-odd different start" control logic. That is, if the equalization start signal CB m is at a high level and the equalization start signals CB m-1 and CB m+1 are at a low level, then the switching transistors Q201 and Q202 are turned on and the switching transistors Q203 and Q204 are turned off. The voltage at the CT terminal is pulled up to the power supply VDD through the conducting switching transistor Q202 and the resistor R206, causing the optocoupler Q205 to conduct. Then, the equalization control output terminal CK m of the second equalization control circuit 1002 becomes high level through the voltage division of the resistor R207, optocoupler Q205, diode D200, and resistor R208, controlling the opening of the equalization switch circuit 1001 to perform equalization for the single cell B m .

[0276] II. Equalization cut-off: The adjacent even and odd equalization start signals CB m-1 , CB m , CB m+1 meet the signal state combination specified by the "even-odd different start" control logic. That is, if the equalization start signal CBm is at a low level and the equalization start signal CB m-1 、CB m+1 is at a high level, then the switching transistors Q201 and Q202 are cut off and the switching transistors Q203 and Q204 are turned on; because the switching transistors Q203 and Q204 are turned on, the CT terminal is pulled down to a low level, causing the optocoupler Q205 to be cut off, so the equalization control output terminal CK m of the m-th equalization control loop 1002 is in a high-impedance state, causing the equalization switch loop 1001 to be cut off and unable to equalize the single-cell battery B m for equalization.

[0277] III. Equalization invalid: The adjacent even and odd equalization start signals CB m-1 、CB m 、CB m+1 do not conform to the signal state combination specified by the "even and odd not both on" control logic, that is, if the equalization start signal CB m-1 、CB m is at a high level and the equalization start signal CB m+1 is at a low level, then the switching transistors Q201, Q202, and Q204 are turned on and the switching transistor Q203 is cut off; because the switching transistor Q204 is turned on, the CT terminal is pulled down to a low level, causing the optocoupler Q205 to be cut off, so the equalization control output terminal CK m of the second equalization control loop 1002 is in a high-impedance state, causing the equalization switch loop 1001 to be cut off and unable to equalize the single-cell battery B m for equalization;

[0278] Similarly, for the (m - 1)-th equalization module 100, its input terminal 4 receives the equalization start signal CB m-1 , and its input terminal 5 receives the equalization start signal CB m ; for the (m - 1)-th equalization control loop 1002, since the equalization start signal CB m is at a high level, it will cause the switching transistor Q203 in the (m - 1)-th equalization control loop 1002 to be turned on, pulling down the CT terminal in the first equalization control loop 1002 to a low level, causing the optocoupler Q205 in the (m - 1)-th equalization control loop 1002 to be cut off, so the equalization control output terminal CK m-1 (not shown) of the (m - 1)-th equalization control loop 1002 is in a high-impedance state, causing the (m - 1)-th equalization switch loop 1001 to be cut off and unable to equalize the single-cell battery B m-1 for equalization;

[0279] For example, for the first equalization module 100 (see Figure 1) Its input terminal 4 receives the equalization start signal CB1, and its input terminal 5 receives the equalization start signal CB2; for the first equalization control loop 1002, since the equalization start signal CB2 is at a high level, the switching transistor Q203 in the first equalization control loop 1002 will be turned on, pulling down the CT terminal in the first equalization control loop 1002 to a low level, causing the optocoupler Q205 in the first equalization control loop 1002 to turn off. Therefore, the equalization control output terminal CK1 (not shown) of the first equalization control loop 1002 is in a high-impedance state, causing the first equalization switch loop 1001 to turn off and unable to equalize the single-cell battery B1;

[0280] For the present invention, when the equalization start signals CB m-1 , CB m , CB m+1 do not conform to the signal state combination specified by the "odd-even different on" control logic (where m can be 2, for example), the high-level equalization start signals CB m-1 , CB m respectively turn off the corresponding (m - 1)-th and m-th equalization modules 100, and will not equalize the single-cell battery B m-1 and the single-cell battery B m . At this time, both equalization modules 100 are in an equalization invalid state;

[0281] It should be noted that since the equalization start signal CB m+1 is at a low level, for the (m + 1)-th equalization control loop 1002 in the (m + 1)-th equalization module 100, its equalization control output terminal CK3 (not shown) is in a high-impedance state, causing the (m + 1)-th equalization switch loop 1001 to turn off and unable to equalize the single-cell battery B m+1 . At this time, the (m + 1)-th equalization module 100 is in an equalization cut-off state rather than an equalization invalid state;

[0282] In summary, if the equalization start signals CB m-1 , CB m , CB m+1 are all at a high level, then the (m - 1)-th, m-th, and (m + 1)-th equalization modules 100 are all in an equalization invalid state and cannot equalize the single-cell batteries B m-1 , B m , B m+13 .

[0283] Figure 5a is the schematic diagram of the corresponding m-th equalization detection loop 1003 for any single-cell battery B m ; Figure 5b is the schematic diagram of the second equalization detection loop 1003 corresponding to the single-cell battery B2 in a specific embodiment, that is, m is 2.

[0284] In the present invention, specifically, as shown in Figure 5a and Figure 5b For any single cell B m , the corresponding connected balancing detection circuit 1003 (i.e., the m-th balancing detection circuit 1003) includes: resistors R50 - R55, switching transistor Q51, optocoupler Q50, AND gates U21 - U22, and OR gate U23, where:

[0285] The first pin of resistor R50 serves as input terminal 1 of the balancing detection circuit 1003 corresponding to the connection of single cell B m , and is connected to the positive terminal B m + of single cell B m for receiving the voltage and current of single cell B m ;

[0286] The second pin of resistor R50 is connected to the first pin of optocoupler Q50;

[0287] The second pin of optocoupler Q50 serves as input terminal 2 of the balancing detection circuit 1003 corresponding to the connection of single cell B m , and is connected to the output terminal TB m of the corresponding connected balancing switch circuit 1001 of single cell B m for receiving the balancing detection signal TB m sent by the corresponding connected balancing switch circuit 1001 of single cell B m ;

[0288] The third pin of optocoupler Q50 is connected to the first pin of resistor R51;

[0289] The fourth pin of optocoupler Q50, the first pin of resistor R52, the first pin of resistor R54, and the emitter E of switching transistor Q51 are all connected to the output terminal MB m of the balancing detection circuit 1003 corresponding to the connection of single cell B m ;

[0290] The output terminal MB m of the balancing detection circuit 1003 corresponding to the connection of single cell B m is connected to the m-th input terminal IN m of the MCU module 200 for providing the balancing detection signal MB m to the MCU module 200. The state of the balancing detection signal MB m has three types: high level, low level, and 0V;

[0291] The second pins of resistors R52 and R54 are respectively connected to the ground terminal GND;

[0292] The second pin of resistor R51 and the first pin of resistor R53, as the input terminal 5 of the second equalization detection circuit 1003, are respectively connected to the power supply terminal VDD of the power supply module 300 for receiving a 5V DC power supply;

[0293] The second pin of resistor R53 is connected to the collector C of switch transistor Q51;

[0294] The base B of switch transistor Q51 is connected to the first pin of resistor R55;

[0295] The second pin of resistor R55 is connected to the third pin of OR gate U23 for receiving the control signal sent by OR gate U23. The states of this control signal are two: high level and low level;

[0296] The first pin of OR gate U23 is connected to the third pin of AND gate U21 for receiving the control signal sent by AND gate U21. The states of this control signal are two: high level and low level;

[0297] The second pin of OR gate U23 is connected to the third pin of AND gate U22 for receiving the control signal sent by AND gate U22. The states of this control signal are two: high level and low level;

[0298] The first pin of AND gate U21, as the input terminal 3 of the equalization detection circuit 1003 corresponding to the single cell B m is connected to the (m - 1)th output terminal CB of the MCU module 200, m for receiving the equalization start signal CB output by the MCU module 200 to the adjacent lower - level single cell B m of the single cell B m-1 ; m-1 ;

[0299] The second pin of AND gate U21 and the first pin of AND gate U22, as the input terminal 4 of the second equalization detection circuit 1003, are both connected to the output terminal CB of the MCU module 200 m for receiving the equalization start signal CB2 output by the MCU module 200 to the equalization detection circuit 1003 corresponding to the single cell B m ;

[0300] The second pin of AND gate U22, as the input terminal 5 of the second equalization detection circuit 1003, is connected to the output terminal CB of the MCU module 200 m+1 for receiving the equalization start signal CB output by the MCU module 200 to the adjacent higher - level single cell of the single cell B m ; m+1 ;

[0301] In the present invention, in terms of specific implementation, for the single cell B (i.e., B1) connected to the positive terminal B+ of the battery pack, the structure of the equalization detection circuit 1003 of this single cell is basically the same as that of the equalization detection circuit 1003 of the single cell Bm, except that its input terminal 3 is suspended (i.e., vacant) and is not connected to other modules or parts.

[0302] In the present invention, in terms of specific implementation, for the single cell B (i.e., B n ) connected to the negative terminal B- of the battery pack, the structure of the equalization detection circuit 1003 of this single cell is basically the same as that of the equalization detection circuit 1003 of the single cell Bm, except that its input terminal 5 is suspended (i.e., vacant) and is not connected to other modules or parts.

[0303] In the present invention, in terms of specific implementation, for any single cell B m , the corresponding connected equalization detection circuit 1003 (i.e., the mth equalization detection circuit 1003) has the following working principle:

[0304] I. Equalization enabled state: When the equalization enable signal CB m is at a high level and CB m-1 , CB m+1 are at low levels, CB m-1 ~ CB m+1 conform to the signal state combination specified by the "odd-even different enable" control logic. The control signals output by the 3rd pins of the AND gate U21 and the AND gate U22 are both at low levels, making the control signal output by the 3rd pin of the OR gate U23 also at a low level, then the switching transistor Q51 is cut off; if at this time the equalization detection signal TB m is at a low level (the 2nd equalization module 100 is in the equalization enabled state), then the optocoupler Q50 is turned on, making the output terminal MB2 of the mth equalization detection circuit 1003 divide the power supply voltage VDD through the resistor R51 and the resistor R52 and become a high level;

[0305] When the equalization enable signals CB m-1 , CB m , CB m+1 conform to the signal state combination specified by the "odd-even different enable" control logic, if the equalization enable signal CB m is at a high level and the equalization detection signal MB m is at a high level, so the MCU module 200 determines that the mth equalization module 100 is in the equalization enabled state;

[0306] If the equalization enable signal CB m is at a high level while the equalization detection signal MB mIf it is at a low level or 0V, then the MCU module 200 determines that the m-th equalization module 100 has failed.

[0307] II. Equalization cut-off state: When the equalization enable signals CB m-1 , CB m , CB m+1 are all at low levels, or when CB m is at a low level and CB1 and CB3 are at high levels, CB m-1 to CB3 conform to the "odd-even different turn-on" control logic, and the control signals output from the 3rd pins of the AND gate U21 and the AND gate U22 are both at low levels, causing the control signal output from the 3rd pin of the OR gate U23 to also be at a low level, then the switching transistor Q51 is cut off; if the equalization detection signal TB2 is at a high level at this time (the m-th equalization module 100 is in the equalization cut-off state), then the optocoupler Q50 is cut off, causing the output end MB m of the m-th equalization detection circuit 1003 to be pulled down to 0V through the resistor R52 and the resistor R54;

[0308] When the equalization enable signals CB m-1 , CB m , CB m+1 conform to the signal state combination specified by the "odd-even different turn-on" control logic, if the equalization enable signal CB m is at a low level and the equalization detection signal MB m is 0V, then the MCU module 200 determines that the m-th equalization module 100 is in the equalization cut-off state;

[0309] If the equalization enable signal CB m is at a low level while the equalization detection signal MB m is at a high level or a low level, then the MCU module 200 determines that the m-th equalization module 100 has failed.

[0310] III. Equalization invalid state: When the equalization enable signals CB m-1 , CB m , CB m+1 are all at high levels, or when CB m-1 , CB m are at high levels and CB3 is at a low level, or when CB m , CB m+1 are at high levels and CB m-1When it is at a low level, CB1~CB3 do not conform to the signal state combination specified by the "odd-even different turn-on" control logic, and the control signals output from the 3rd pins of the AND gate U21 and the AND gate U22 are both at a high level, making the control signal output from the 3rd pin of the OR gate U23 also at a high level, then the switching transistor Q51 conducts; if the equalization detection signal TB m is at a high level (the mth equalization module 100 is not turned on), then the optocoupler Q50 is cut off; the output end MB of the mth equalization detection loop 1003 m is divided by the power supply voltage VDD through the resistor R53, the switching transistor Q51 and the resistor R54 and becomes a low level;

[0311] When the equalization turn-on signal CB m-1 、CB m 、CB m+1 do not conform to the signal state combination specified by the "odd-even different turn-on" control logic, if the equalization turn-on signal CB m is at a high level and the equalization detection signal MB m is at a low level, so the MCU module 200 determines that the mth equalization module 100 is in an ineffective equalization state;

[0312] If the equalization turn-on signal CB m is at a high level, while the equalization detection signal MB m is at a high level or 0V, then the MCU module 200 determines that the mth equalization module 100 has a fault.

[0313] In the present invention, specifically in implementation, it should be noted that the chip MCU of the MCU module 200 can apply the brands, series and models that are currently widely used, such as the MC9S12 series of NXP, the TC235 of the TC2 series of Infineon, etc. The model of the chip MCU is not within the protection scope of the present invention.

[0314] In the present invention, specifically in implementation, it should be noted that the power supply module 300 is a power supply circuit commonly used in existing BMS technical solutions. Technical personnel can easily obtain and apply it without innovation. The technical solution of this power supply circuit does not belong to the technical solution of the present invention, so no specific explanation is given here.

[0315] As can be seen from the technical solutions provided by the present invention above, compared with the prior art, the present invention provides a passive equalization circuit with odd-even control logic, which is scientifically designed. When the monitoring system software that controls the on-off of the equalization circuit makes a mistake and outputs any adjacent odd-even equalization start signals CB mWhen it is at a high level, it can automatically control the opening and stopping of the equalization circuit according to the "odd-even different opening" control logic, which not only reduces the failure probability of the equalization switch being broken down by high voltage, but also reduces the probability of the equalization circuit failing due to heat accumulation of the heating elements in the equalization circuit;

[0316] For the technical solution of the present invention, the hardware circuit design is scientific, and the electronic components are commonly used models, which are easy to select and the component prices are low;

[0317] In addition, since the hardware circuit of the technical solution of the present invention has low power consumption, surface-mounted low-power electronic components can be used, so the circuit board occupies a small space, greatly reducing the material cost. Therefore, the technical solution of the present invention has strong practical value and market promotion value.

[0318] In summary, compared with the prior art, a battery pack equalization circuit with odd-even control logic provided by the present invention has a scientific design. When a control error occurs in the monitoring system software for controlling the on-off of the equalization circuit, through the redundant protection mechanism of the hardware control circuit, the odd-even adjacent single cells cannot be turned on for equalization at the same time, thereby reducing the failure rate of the equalization circuit, improving the reliability of the equalization circuit, also reducing the battery damage caused by the failure of the equalization circuit, and reducing the occurrence probability of safety accidents, which has great practical significance.

[0319] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A battery pack balancing circuit, characterized in that, The battery pack includes multiple single cells B connected in series; the equalization circuit includes multiple equalization modules (100), an MCU module (200), and a power supply module (300); wherein each equalization module (100) respectively includes an equalization switch circuit (1001), an equalization control circuit (1002), and an equalization detection circuit (1003); wherein each single cell B is correspondingly connected to an equalization module (100); for each equalization module (100), the equalization switch circuit (1001) is respectively connected to the positive and negative electrodes of a single cell B, and is respectively connected to the equalization control circuit (1002) and the equalization detection circuit (1003); the equalization control circuit (1002) and the equalization detection circuit (1003) are connected; the equalization control circuit (1002) and the equalization detection circuit (1003) are respectively connected to the MCU module (200); the equalization control circuit (1002) and the equalization detection circuit (1003) are respectively connected to the power supply module (300); wherein the MCU module (200) and the power supply module (300) are connected; For any single cell Bm that is not connected to the positive terminal B+ and negative terminal B- of the battery pack, the corresponding balancing control circuit (1002) includes: resistors R201 to R208, diode D(200), switching transistors Q201 to Q204, and optocoupler Q205, where: The second pin of resistor R201, as the input terminal 4 of the balancing control circuit (1002) corresponding to single cell Bm, is connected to the m-th output terminal CBm of the MCU module (200) for receiving the balancing start signal CBm sent by the MCU module (200); The first pin of resistor R201 is connected to the base B of switching transistor Q201; The emitter E of switching transistor Q201 is connected to the ground terminal GND; The collector C of switching transistor Q201 is connected to the second pin of resistor R202; The first pin of resistor R202 is connected to the base B of switching transistor Q202; The emitter E of switching transistor Q202 is connected to the second pin of resistor R206; The first pin of resistor R206, as the input terminal 6 of the balancing control circuit (1002) corresponding to single cell Bm, is connected to the VDD terminal of the power supply module (300) for receiving a 5V DC power supply; The collector C of switching transistor Q202 is connected to the CT terminal; The CT terminal is respectively connected to the collector C of switching transistor Q203, the collector C of switching transistor Q204, and the third pin of optocoupler Q205; The base B of switching transistor Q203 is respectively connected to the first pin of resistor R203 and the first pin of resistor R210; The emitter E of switching transistor Q203 is connected to the ground terminal GND; The second pin of resistor R203, as the input terminal 5 of the balancing control circuit (1002) corresponding to single cell Bm, is connected to the (m + 1)-th output terminal CBm+1 of the MCU module (200) for receiving the balancing start signal CBm+1 sent by the MCU module (200); The second pin of resistor R210 is connected to the ground terminal GND; The base B of switching transistor Q204 is respectively connected to the first pin of resistor R204 and the first pin of resistor R209; The emitter E of switching transistor Q204 is connected to the ground terminal GND; The second pin of resistor R204, as the input terminal 3 of the balancing control circuit (1002) corresponding to single cell Bm, is connected to the output terminal CBm-1 of the MCU module (200) for receiving the balancing start signal CBm-1 sent by the MCU module (200); The second pin of resistor R209 is connected to the ground terminal GND; The fourth pin of optocoupler Q205 is connected to the first pin of resistor R205; The first pin of optocoupler Q205 is connected to the second pin of resistor R207; The second pin of optocoupler Q205, as the output terminal Ckm of the balancing control circuit (1002) corresponding to single cell Bm, is connected to the input terminal 3 of the balancing switch circuit (1001) corresponding to single cell Bm; The second pin of optocoupler Q205 is also connected to the anode of diode D(200).The cathode of diode D(200) is connected to the second pin of resistor R208; the first pin of resistor R208 serves as input terminal 2 of the equalization control circuit (1002) corresponding to the single cell Bm, and is connected to the negative terminal Bm- of the single cell Bm for receiving the voltage and current of the single cell Bm; the first pin of resistor R207 serves as input terminal 1 of the equalization control circuit (1002) corresponding to the single cell Bm, and is connected to the positive terminal Bm+ of the single cell Bm for receiving the voltage and current of the single cell Bm; the second pin of resistor R205 is connected to the ground terminal GND; The single cell Bm, and the corresponding balancing detection circuit (1003) connected thereto includes: resistors R50 to R55, a switching transistor Q51, an optocoupler Q50, AND gates U21 to U22, and an OR gate U23, wherein: the first pin of resistor R50, as the input terminal 1 of the balancing detection circuit (1003) corresponding to the single cell Bm, is connected to the positive terminal Bm+ of the single cell Bm, and is used to receive the voltage and current of the single cell Bm; the second pin of resistor R50 is connected to the first pin of optocoupler Q50; the second pin of optocoupler Q50, as the input terminal 2 of the balancing detection circuit (1003) corresponding to the single cell Bm, is connected to the output terminal TBm of the balancing switch circuit (1001) corresponding to the single cell Bm, and is used to receive the balancing detection signal TBm sent by the balancing switch circuit (1001) corresponding to the single cell Bm; the third pin of optocoupler Q50 is connected to the first pin of resistor R51; the fourth pin of optocoupler Q50, the first pin of resistor R52, the first pin of resistor R54, and the emitter E of switching transistor Q51 are all connected to the output terminal MBm of the balancing detection circuit (1003) corresponding to the single cell Bm; the output terminal MBm of the balancing detection circuit (1003) corresponding to the single cell Bm is connected to the m-th input terminal INm of the MCU module (200), and is used to provide the balancing detection signal MBm for the MCU module (200); the second pins of resistors R52 and R54 are respectively connected to the ground terminal GND; the second pin of resistor R51 and the first pin of resistor R53, as the input terminal 5 of the second balancing detection circuit (1003), are respectively connected to the power supply terminal VDD of the power supply module (300), and are used to receive a 5V DC power supply; the second pin of resistor R53 is connected to the collector C of switching transistor Q51; the base B of switching transistor Q51 is connected to the first pin of resistor R55; the second pin of resistor R55 is connected to the third pin of OR gate U23, and is used to receive the control signal sent by the OR gate U23; the first pin of OR gate U23 is connected to the third pin of AND gate U21, and is used to receive the control signal sent by the AND gate U21; the second pin of OR gate U23 is connected to the third pin of AND gate U22, and is used to receive the control signal sent by the AND gate U22; the first pin of AND gate U21, as the input terminal 3 of the balancing detection circuit (1003) corresponding to the single cell Bm, is connected to the (m-1)-th output terminal CBm-1 of the MCU module (200), and is used to receive the balancing start signal CBm-1 output by the MCU module (200) to the lower adjacent single cell Bm-1 of the single cell Bm;The second pin of AND gate U21 and the first pin of AND gate U22, as the input terminal 4 of the second equalization detection circuit (1003), are both connected to the output terminal CBm of the MCU module (200), and are used to receive the equalization start signal CBm output by the MCU module (200) to the equalization detection circuit (1003) corresponding to the monomer battery Bm; the second pin of AND gate U22, as the input terminal 5 of the second equalization detection circuit (1003), is connected to the output terminal CBm+1 of the MCU module (200), and is used to receive the equalization start signal CBm+1 output by the MCU module (200) to the high-order adjacent monomer battery of the monomer battery Bm.

2. The battery pack balancing circuit according to claim 1, characterized in that, For each equalization module (100), its input terminal 1 is respectively connected to the positive electrode B+ of a single cell B, enabling the single cell B to achieve equalization through shunting by this equalization module (100), and the current flowing through this equalization module (100) is the equalization current; for each equalization module (100), its input terminal 2 is connected to the negative electrode B- of the single cell B, enabling the single cell B to achieve equalization through shunting by this equalization module (100); for each equalization module (100), its input terminal 3 is respectively correspondingly connected to an output terminal CB of the MCU module (200), for receiving the equalization start signal output by the MCU module (200) to the equalization module (100) of the higher adjacent single cell of this single cell B, thereby controlling the on and off of the equalization module (100) of this single cell B; for each equalization module (100), its input terminal 4 is respectively correspondingly connected to an output terminal CB of the MCU module (200), for receiving the equalization start signal CB sent by the MCU module (200) for this equalization module (100); For each equalization module (100), its input terminal 5 is respectively connected to an output terminal CB of the MCU module (200), and is used to receive the equalization start signal output by the MCU module (200) to the equalization module (100) of the lower adjacent single cell of the single cell B of this battery pack, so as to control the opening and cutoff of this equalization module; for each equalization module (100), its input terminal 6 is connected to the output terminal VDD of the power supply module (300) to receive the DC power supply of 5V; for each equalization module (100), its output terminal MB is respectively connected to an input terminal of the MCU module (200), and is used to output the equalization detection signal MB of the equalization module (100) to the MCU module (200) to provide the equalization state of this equalization module (100) for the MCU module (200); wherein, for the single cell B that is not connected to the positive extreme B+ of the battery pack, the adjacent single cell that is closer to the positive extreme B+ of the battery pack is defined as the upper adjacent single cell of the single cell B; for the single cell B that is not connected to the negative extreme B- of the battery pack, the adjacent single cell that is closer to the negative extreme B- of the battery pack is defined as the lower adjacent single cell of the single cell B.

3. The battery pack balancing circuit according to claim 2, characterized in that, For the equalization switch circuit (1001) in each equalization module (100), its input terminal 1, as the input terminal 1 of this equalization module (100), is respectively connected to the positive extreme B+ of a single cell B to receive the voltage and current of the single cell B; for the equalization switch circuit (1001) in each equalization module (100), its input terminal 2, as the input terminal 2 of this equalization module (100), is specifically connected to the negative extreme B- of the single cell B to receive the voltage and current of the single cell B; for the equalization switch circuit (1001) in each equalization module (100), its input terminal 3 is connected to the output terminal CK of the equalization control circuit (1002) in this equalization module (100) to receive the equalization control signal CK sent by the equalization control circuit (1002) in this equalization module (100); for the equalization switch circuit (1001) in each equalization module (100), its output terminal TB is connected to the input terminal 2 of the equalization detection circuit (1003) in this equalization module (100) to send the equalization detection signal TB to the equalization detection circuit (1003) in this equalization module (100) to control the change of the signal state of the output terminal MB of the equalization detection circuit (1003) in this equalization module (100).

4. The battery pack balancing circuit according to claim 2, characterized in that, For the equalization control loop (1002) in each equalization module (100), its input terminal 1, as the input terminal 1 of the present equalization module (100), is respectively connected to the positive electrode B+ of the single cell B to receive the voltage and current of the single cell B; for the equalization control loop (1002) in each equalization module (100), its input terminal 2, as the input terminal 2 of the present equalization module (100), is specifically connected to the negative electrode B- of the single cell B to receive the voltage and current of the single cell B; for the equalization control loop (1002) in each equalization module (100), its input terminal 3 is connected to an output terminal CB of the MCU module (200) to receive the equalization start signal output by the MCU module (200) to the equalization module (100) of the higher adjacent single cell of the single cell B; for the equalization control loop (1002) in each equalization module (100), its input terminal 4 is connected to an output terminal CB of the MCU module (200) to receive the equalization start signal CB sent by the MCU module (200) for the present equalization control loop (1002); for the equalization control loop (1002) in each equalization module (100), its input terminal 5 is connected to an output terminal CB of the MCU module (200) to receive the equalization start signal output by the MCU module (200) to the equalization module (100) of the lower adjacent single cell of the single cell B; for the equalization control loop (1002) in each equalization module (100), its input terminal 6 is connected to the output terminal VDD of the power supply module (300) to receive the 5V DC power supply sent by the power supply module (300); for the equalization control loop (1002) in each equalization module (100), its output terminal CK is connected to the input terminal 3 of the equalization switch loop (1001) in the present equalization module (100) to send the equalization control signal CK to the equalization switch loop (1001) in the present equalization module (100) to control the opening and closing of the equalization switch loop (1001) in the present equalization module (100).

5. The battery pack balancing circuit according to claim 2, characterized in that, For the equalization detection circuit (1003) in each equalization module (100), its input terminal 1, as the input terminal 1 of the present equalization module (100), is respectively connected to the positive electrode B+ of the single cell B for receiving the voltage and current of the single cell B; for the equalization detection circuit (1003) in each equalization module (100), its input terminal 2 is connected to the output terminal TB of the equalization switch circuit (1001) in the present equalization module (100) for receiving the equalization detection signal TB sent by the equalization switch circuit (1001) in the present equalization module (100); for the equalization detection circuit (1003) in each equalization module (100), its input terminal 3 is connected to an output terminal CB of the MCU module (200) for receiving the equalization start signal output by the MCU module (200) to the equalization module (100) of the higher adjacent single cell of the single cell B; for the equalization detection circuit (1003) in each equalization module (100), its input terminal 4 is connected to an output terminal CB of the MCU module (200) for receiving the equalization start signal CB sent by the MCU module (200) to the present equalization detection circuit (1003); for the equalization detection circuit (1003) in each equalization module (100), its input terminal 5 is connected to an output terminal CB of the MCU module (200) for receiving the equalization start signal output by the MCU module (200) to the equalization module (100) of the lower adjacent single cell of the single cell B; for the equalization detection circuit (1003) in each equalization module (100), its input terminal 6 is connected to the output terminal VDD of the power supply module (300) for receiving the 5V DC power supply sent by the power supply module (300); for the equalization detection circuit (1003) in each equalization module (100), its output terminal MB is connected to an input terminal IN of the MCU module (200) for sending the equalization detection signal MB to the MCU module (200).

6. The battery pack balancing circuit according to claim 2, characterized in that, The MCU module (200), whose power input terminal VCC is connected to the output terminal VDD of the power supply module (300), is used to receive a 5V DC power supply; the MCU module (200) includes multiple input terminals IN, and each input terminal IN is respectively connected to the output terminal MB of an equalization module (100) correspondingly, and is used to receive an equalization detection signal MB sent by an equalization module (100) correspondingly, and then judge the equalization state of the equalization module (100) of the single battery B according to the signal state of the equalization detection signal MB specified by the preset parity control logic; the MCU module (200) includes multiple output terminals CB; each output terminal CB is respectively connected to the input terminal 3 of an equalization module (100), and is used to send an equalization start signal CB to each equalization module (100) respectively to control the turn-on and turn-off of the equalization module (100); for the power supply module (300), its output terminal VDD is respectively connected to the input terminal 6 of multiple equalization modules (100) and the power input terminal VCC of the MCU module (200), and is used to provide a 5V DC power supply.

7. The battery pack balancing circuit according to any one of claims 1 to 6, characterized in that, For any single battery Bm that is not connected to the positive terminal B+ or the negative terminal B- of the battery pack, the corresponding balanced switching circuit (1001) connected thereto includes: a balancing resistor RB2, resistors R21 to R23, a balanced switching transistor Q21, and a diode D22, where: the first pin of the balancing resistor RB2 and the first pin of the resistor R23, as the input terminal 1 of the balanced switching circuit (1001) corresponding to the single battery Bm, are both connected to the positive terminal Bm+ of the single battery Bm for receiving the voltage and current of the single battery Bm; the second pin of the balancing resistor RB2 serves as the output terminal TBm of the balanced switching circuit (1001) corresponding to the single battery Bm; the output terminal TBm of the balanced switching circuit (1001) corresponding to the single battery Bm is further connected to the collector C of the balanced switching transistor Q21, the cathode of the diode D22, and the second pin of the resistor R23, for providing a balanced detection signal TBm to the balanced detection circuit (1003) corresponding to the single battery Bm; the anode of the diode D22, the emitter E of the balanced switching transistor Q21, and the second pin of the resistor R22, as the input terminal 2 of the balanced switching circuit (1001) corresponding to the single battery Bm, are all connected to the negative terminal B2- of the single battery B2 for receiving the voltage and current of the single battery Bm; the base B of the balanced switching transistor Q21 is respectively connected to the first pin of the resistor R22 and the cathode of the diode D21; the anode of the diode D21 is connected to the first pin of the resistor R21; the second pin of the resistor R21, as the input terminal 3 of the balanced switching circuit (1001) corresponding to the single battery Bm, is connected to the output terminal Ckm of the balanced control circuit (1002) corresponding to the single battery Bm for receiving the balanced control signal Ckm sent by the balanced control circuit (1002); where m is any natural number less than or equal to n; for the single battery B in the battery pack, n is the number of single batteries connected in series in the battery pack.

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