A silicon carbide power component, drive circuit and control method

Abstract

The present application relates to a silicon carbide power component, a driving circuit and a control method. A silicon carbide power component is controlled by a driver and has a gate-to-source voltage and a source voltage, wherein the source voltage decreases according to the increase of the gate-to-source voltage, or the source voltage increases according to the decrease of the gate-to-source voltage, thereby suppressing a surge generated by the change of the gate-to-source voltage, thereby suppressing the crosstalk phenomenon of the silicon carbide power component.

Description

Technical Field

[0001] The present invention relates to a power component, a driving circuit and a control method, and in particular to a silicon carbide power component, a driving circuit and a control method. Background Art

[0002] Silicon carbide power components have the advantages of high operating voltage, high operating temperature, low on-resistance and high switching frequency, especially silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) and silicon carbide insulated gate bipolar transistor (SiC IGBT), which are suitable for use in the recently demanding electric vehicles and 5G communications fields. Related technologies can be found in U.S. invention patent announcements No. US9,018,640 B1, No. US9,373,713 B2, No. US10,020,368 B2, No. US10,483,389 B2, etc.

[0003] However, compared with traditional silicon power components, the gate and source voltage resistance range of silicon carbide power components is narrow, and the ability to withstand negative voltage is poor. At high switching frequencies, crosstalk is prone to occur in the bridge arm circuit. This problem has been described in A Magnetic Coupling Based Gate Driver for Crosstalk Suppression of SiC MOSFETs published by Binfeng Zhang et al. in IEEE Transactions On Industrial Electronics, Vol. 64, No. 11, November 2017. At present, the crosstalk phenomenon of silicon carbide power components cannot be effectively solved. In view of this, traditional silicon carbide power components still need to be improved. Summary of the invention

[0004] The purpose of the present invention is to improve the problem that the existing silicon carbide power components are prone to crosstalk.

[0005] To achieve the above-mentioned purpose, the present invention provides a control method for a silicon carbide power component, which includes the following steps: providing a silicon carbide power component, which is controlled by a driver and has a gate-to-source voltage and a source voltage, and the source voltage has at least a high level, a low level and an intermediate level between the high level and the low level; and the driver alternately outputs an upper bridge drive signal and a lower bridge drive signal to a gate of the silicon carbide power component, wherein when the gate-to-source voltage rises according to the upper bridge drive signal or the lower bridge drive signal, the source voltage is reduced from the intermediate level to the low level or from the high level to the intermediate level, and when the gate-to-source voltage drops according to the upper bridge drive signal or the lower bridge drive signal, the source voltage is increased from the low level to the intermediate level or from the intermediate level to the high level.

[0006] To achieve the above-mentioned purpose, the present invention also provides a silicon carbide power component, which is controlled by a driver and has a gate-to-source voltage and a source voltage, wherein the source voltage decreases as the gate-to-source voltage increases, or the source voltage increases as the gate-to-source voltage decreases, thereby suppressing a surge caused by a change in the gate-to-source voltage.

[0007] To achieve the above-mentioned purpose, the present invention further provides a driving circuit, including: a silicon carbide power component having a gate-to-source voltage and a source voltage; a driver for controlling the silicon carbide power component; and a compensation module for controlling the source voltage to drop according to the increase of the gate-to-source voltage, or controlling the source voltage to rise according to the decrease of the gate-to-source voltage, thereby suppressing a surge generated by the change of the gate-to-source voltage.

[0008] The present invention controls the source voltage to suppress the surge caused by the change of the gate-source voltage, thereby solving the problem of crosstalk in silicon carbide semiconductor power components. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] 『 Figure 1 ' is a schematic diagram of a circuit structure of an embodiment of the present invention applied to a half-bridge circuit.

[0010] 『 Figure 2 ' is a schematic diagram of voltage output of the silicon carbide power component according to the present invention.

[0011] 『 Figure 3 ' is a logic schematic block diagram of an embodiment of the present invention.

[0012] 『 Figure 4 ' is a logic schematic block diagram of another embodiment of the present invention.

[0013] 『 Figure 5' is a schematic diagram of the circuit structure of an embodiment of the present invention.

[0014] 『 Figure 6 ' is a logic schematic block diagram of another embodiment of the present invention.

[0015] 『 Figure 7 ' is a schematic diagram of the circuit structure of another embodiment of the present invention.

[0016] 『 Figure 8 ",for" Figure 7 』Logical schematic block diagram.

[0017] 『 Fig. 9 ', based on ' Figure 7 』A schematic diagram of voltage output of an embodiment of the present invention.

[0018] 『 Fig.10 ' is a schematic diagram of the operation flow of an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The detailed description and technical contents of the present invention are now described as follows with reference to the accompanying drawings:

[0020] The present invention shows a control method of a silicon carbide power component, which is applied to a driving circuit including a silicon carbide power component, wherein the silicon carbide power component can be an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction gate field-effect transistor (JFET) or other power components. The silicon carbide power component is controlled by a driver and has a gate-to-source voltage (Vgs) and a source voltage (Vs).

[0021] Please refer to Figure 1' is a schematic diagram of an embodiment of the present invention applied to a half-bridge circuit. The silicon carbide power component is applied to a half-bridge circuit as an example. The half-bridge circuit includes a controller 10, an upper bridge arm circuit 20 and a lower bridge arm circuit 30. The upper bridge arm circuit 20 includes a first driver 21, a first silicon carbide power component 22, a first inductor 23, a first resistor 24 and a plurality of first capacitors 25. The first inductor 23 and the first resistor 24 are connected in series between the first driver 21 and the first silicon carbide power component 22. The first capacitor 25 includes a gate-drain capacitor 251, a gate-source capacitor 252 and a drain-source capacitor 253. The lower bridge arm circuit 30 includes a second driver 31, a second silicon carbide power component 32, a second inductor 33, a second resistor 34 and a plurality of second capacitors 35. The second inductor 33 and the second resistor 34 are connected in series between the second driver 31 and the second silicon carbide power component 32. The second capacitor 35 includes a gate-drain capacitor 351, a gate-source capacitor 352 and a drain-source capacitor 353.

[0022] Please refer to Figure 2 ' is a schematic diagram of the voltage output of a silicon carbide power component according to an embodiment of the present invention, wherein the source voltage (Vs) has at least a high level (H), a low level (L) and an intermediate level (M) between the high level (H) and the low level (L). During driving, the first driver 21 and the second driver 31 alternately output an upper bridge drive signal (Gate signal 1) and a lower bridge drive signal (Gate signal 2) to a gate of the first silicon carbide power component 22 and the second silicon carbide power component 32. In the present invention, when the gate-to-source voltage (Vgs) of the first silicon carbide power component 22 and the second silicon carbide power component 32 rises according to the upper bridge drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal 2), the source voltage (Vs) is controlled to drop from the middle level (M) to the low level (L) or from the high level (H) to the middle level (M); when the gate-to-source voltage (Vgs) of the first silicon carbide power component 22 and the second silicon carbide power component 32 rises according to the upper bridge drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal 2), the gate-to-source voltage (Vgs) of the first silicon carbide power component 22 and the second silicon carbide power component 32 rises according to the upper bridge drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal 2). 2) When decreasing, the source voltage (Vs) is increased from the low level (L) to the middle level (M) or from the middle level (M) to the high level (H).

[0023] like" Figure 2』, at time points (t1) and (t5), the lower bridge driving signal (Gate signal 2) decreases, causing the gate-to-source voltage (Vgs) to generate a negative peak. At this time, the source voltage (Vs) is controlled to rise from the middle level (M) to the high level (H) to suppress or reduce the spike of the gate-to-source voltage (Vgs); at time points (t2) and (t6), the upper bridge driving signal (Gate signal 1) increases, causing the gate-to-source voltage (Vgs) to generate a positive peak. At this time, the source voltage (Vs) is controlled to drop from the middle level (M) to the low level (L) to suppress or reduce the spike of the gate-to-source voltage (Vgs); at time point (t3), the upper bridge driving signal (Gate signal 1) decreases, causing the gate-to-source voltage (Vgs) to produce a negative peak value. At this time, the source voltage (Vs) is controlled to rise from the middle level (M) to the high level (H) to suppress or reduce the surge of the gate-to-source voltage (Vgs); at time point (t4), the lower bridge drive signal (Gate signal 2) increases, causing the gate-to-source voltage (Vgs) to produce a positive peak value. At this time, the source voltage (Vs) is controlled to drop from the middle level (M) to the low level (L). Figure 2 』, Vgs is the gate-source voltage without adopting the method of the present invention, and it can be clearly seen that the surge occurs; Vgs' is the gate-source voltage with adopting the method of the present invention, and it can be clearly seen that the surge is suppressed and improved.

[0024] Please refer to Figure 3 ' is a logic schematic block diagram of an embodiment of the present invention, which is used to illustrate the judgment and operation mechanism of the control method. In this embodiment, the upper bridge drive signal (Gate signal 1) is first judged to be rising or falling through frame 41 or frame 42, and the lower bridge drive signal (Gate signal 2) is judged to be rising or falling through frame 43 or frame 44. After the judgment of frame 41 and frame 43, a first result associated with the rising of the drive signal is transmitted to frame 45, and after the judgment of frame 42 and frame 44, a second result associated with the falling of the drive signal is transmitted to frame 46. In this embodiment, frame 45 and frame 46 are an OR gate. If the output of any of the first results is valid, frame 47 will be triggered, that is, the source voltage (Vs) will be controlled to fall; conversely, if the output of any of the second results is valid, frame 48 will be triggered, that is, the source voltage (Vs) will be controlled to rise, thereby achieving the effect of suppressing or reducing the surge of the gate-to-source voltage (Vgs).

[0025] Please refer to Figure 4 ' is a logic schematic block diagram of another embodiment of the present invention. Compared with ' Figure 3 ', this embodiment has additional frames 491, 492 and 493. When frame 491 detects that the waveform of the upper bridge drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal 2) changes, the output will be changed (i.e., edge trigger). Through frame 492, the rise or fall of the source voltage (Vs) will be delayed by a delay τ. The delay is the duration of the rise or fall of the source voltage (Vs), which eventually triggers frame 493 to allow the rise or fall of the source voltage (Vs) to continue for a period of time τ.

[0026] In the invention, the detection of the upper bridge drive signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2) and the control of the gate-to-source voltage (Vgs) can be performed by a compensation module, and the compensation module includes a first compensation unit and a second compensation unit. The first compensation unit detects the upper bridge drive signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2), and when the gate-to-source voltage (Vgs) rises based on the upper bridge drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal 2), the source voltage (Vs) is controlled to decrease. The second compensation unit detects the upper bridge drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal 2), and when the gate-to-source voltage (Vgs) falls based on the upper bridge drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal 2), the source voltage is controlled to increase (Vs). Please refer to " Figure 5' is a schematic diagram of the circuit structure of an embodiment of the present invention. This embodiment uses a three-level gate driver as an example of the compensation module, including a driver 21, a silicon carbide power component 22, a first inductor 23, a first resistor 24, a plurality of first capacitors 25, a first amplifier 26 and a second amplifier 27. The first inductor 23 and the first resistor 24 are connected in series between the driver 21 and the silicon carbide power component 22. The first capacitor 25 includes a gate-drain capacitor 251, a gate-source capacitor 252 and a drain-source capacitor 253. The driver 21 outputs a driving signal to the silicon carbide power component 22. The driving signal can be a positive voltage or a negative voltage. The first amplifier 26 and the second amplifier 27 receive a first input signal 261 and a second input signal 271, respectively. The first input signal 261 and the second input signal 271 are associated with the driving signal. For example, when the driving signal is the positive voltage, the first input signal 261 and the second input signal 271 are both at a low level, and the source voltage decreases; when the driving signal is the negative voltage, the first input signal 261 and the second input signal 271 are both at a high level, and the source voltage increases (0th order); when the driving signal is the positive voltage, the first input signal 261 and the second input signal 271 are both at a low level, and the source voltage decreases (1st order); after the driving signal changes to the negative voltage or changes to the positive voltage, the first input signal 261 and the second input signal 271 are respectively at the high level and the low level, or the low level and the high level, and the source voltage remains unchanged (2nd order).

[0027] Please refer to Figure 6 ' is a logic schematic block diagram of another embodiment of the present invention, which is illustrated by taking the Cambridge Scanner single-click circuit as an example. Frame 61 (G1 Rising Flag) and frame 62 (G2 Rising Flag) respectively indicate that the upper bridge drive signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2) are rising, frame 63 uses an NOR gate, and frame 64 is a first single-click trigger. Frame 65 (G1 Dropping Flag) and frame 66 (G2 Dropping Flag) respectively indicate that the upper bridge drive signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2) are falling, frame 67 uses an OR gate, and frame 68 is a second single-click trigger. Among them, the first single-click trigger of frame 64 includes a NAND gate 641, a capacitor 642, a resistor 643 and a NOT gate 644, and the second single-click trigger of block 68 includes an OR gate 681, a capacitor 682, a resistor 683 and a NOT gate 684.

[0028] Please refer to Figure 7 ' is a schematic diagram of the circuit structure of another embodiment of the present invention. Compared with ' Figure 5 In this embodiment, a D-type flip-flop 28 is used. The D-type flip-flop 28 is coupled to a logic unit 70. The D-type flip-flop 28 determines an output 283 according to a first input signal 281 and a second input signal 282 generated by the logic unit 70. The logic schematic block diagram of the logic unit 70 is shown in FIG. Figure 8 ', frame 71, 72 represent the upper bridge drive signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2), frame 73 is a delayer, frame 74, 75 are an OR gate, frame 76, 77 are an inverter. After the upper bridge drive signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2) are input into the logic unit 70, a CLK signal, a / CLK signal, a DCLK signal and a / DCLK signal will be generated, wherein the CLK signal and the DCLK signal are the first input signal 281, and are input into the D terminal of the D-type flip-flop 28, and the / CLK signal and the / DCLK signal are the second input signal 282, and are input into the CLK terminal of the D-type flip-flop 28, ' Fig. 9 ' is based on ' Figure 7 』A schematic diagram of voltage output of an embodiment of the present invention.

[0029] Please refer to Fig.10 』 is a flow chart of an embodiment of the present invention. The upper bridge drive signal (Gatesignal 1) and the lower bridge drive signal are regarded as a pulse width modulation signal (PWM signal). When the state of the pulse width modulation signal changes (frame 81), it will be detected and the source voltage (Vs) will be adjusted to rise or fall (frame 82), and the gate-to-source voltage (Vgs) will be caused to change (frame 83), and the change of the gate-to-source voltage (Vgs) will cause the drain-to-source voltage (Vds) to change (frame 84), and cause the gate-to-source voltage (Vgs) to ring (Ringing) phenomenon (frame 85), wherein the change of the drain-to-source voltage (Vds) will produce the Miller effect (Millereffect) (frame 86). Finally, since the source voltage (Vs) will be adjusted based on the change of the pulse width modulation signal, the surge of the gate-to-source voltage (Vgs) will be suppressed or reduced (frame 87).

[0030] In summary, the present invention controls the source voltage to suppress the surge caused by the change of the gate-to-source voltage (Vgs), thereby solving the problem of crosstalk occurring in silicon carbide semiconductor power components.

Claims

1. A control method for a silicon carbide power component, characterized in that: The method includes the following steps: providing a silicon carbide power component, which is controlled by a driver and has a gate-to-source voltage and a source voltage, wherein the source voltage has at least a high level, a low level and an intermediate level between the high level and the low level; and the driver alternately outputs an upper bridge drive signal and a lower bridge drive signal to a gate of the silicon carbide power component, wherein when the gate-to-source voltage rises according to the upper bridge drive signal or the lower bridge drive signal, the source voltage is reduced from the intermediate level to the low level or from the high level to the intermediate level, and when the gate-to-source voltage drops according to the upper bridge drive signal or the lower bridge drive signal, the source voltage is increased from the low level to the intermediate level or from the intermediate level to the high level.

2. A silicon carbide power component, characterized in that: A power device controlled by a driver and having a gate-to-source voltage and a source voltage, wherein the source voltage decreases according to the increase of the gate-to-source voltage, or the source voltage increases according to the decrease of the gate-to-source voltage, thereby suppressing a surge caused by the change of the gate-to-source voltage, and the source voltage has at least a high level, a low level and an intermediate level between the high level and the low level, and the driver alternately outputs an upper bridge drive signal and a lower bridge drive signal to a gate of the silicon carbide power component, wherein when the gate-to-source voltage increases according to the upper bridge drive signal or the lower bridge drive signal, the source voltage decreases from the intermediate level to the low level or from the high level to the intermediate level, and when the gate-to-source voltage decreases according to the upper bridge drive signal or the lower bridge drive signal, the source voltage increases from the low level to the intermediate level or from the intermediate level to the high level.

3. A driving circuit, characterized in that: include: A silicon carbide power device having a gate-to-source voltage and a source voltage; A driver for controlling the silicon carbide power component; and a compensation module, which controls the source voltage to drop according to the increase of the gate-source voltage, or controls the source voltage to rise according to the decrease of the gate-source voltage, thereby suppressing a surge generated by the change of the gate-source voltage, wherein the compensation module receives an upper bridge drive signal and a lower bridge drive signal alternately output by the driver, and controls the source voltage to drop or rise according to the upper bridge drive signal and the lower bridge drive signal causing the gate-source voltage to rise or fall, the compensation module includes a first compensation unit and a second compensation unit, the first compensation unit detects the upper bridge drive signal and the lower bridge drive signal, and controls the source voltage to drop when the gate-source voltage rises based on the upper bridge drive signal or the lower bridge drive signal, the second compensation unit detects the upper bridge drive signal and the lower bridge drive signal, and controls the source voltage to rise when the gate-source voltage drops based on the upper bridge drive signal or the lower bridge drive signal, and the compensation module includes a D-type flip-flop.

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