Drive speed dynamic adjustment circuit and its control method and flyback power converter

Abstract

This application provides a dynamic driving speed adjustment circuit and its control method, as well as a flyback power converter. The dynamic driving speed adjustment circuit includes a detection module and a control module. The detection module detects the operating state of the primary-side quasi-resonant control system. When the detection module detects that the primary-side quasi-resonant control system is in a target operating state, the control module outputs a driving speed adjustment signal corresponding to the target operating state. This signal adjusts the speed of the driving module, slowing down the driving speed of the primary-side field-effect transistor when the primary-side quasi-resonant control system enters a light-load operating mode, during startup, or when the output is in a short-circuit state. This effectively alleviates the problem of excessive stress on the secondary-side field-effect transistor.

Description

Technical Field

[0001] This application belongs to the technical field of flyback power converters, and particularly relates to a dynamic adjustment circuit for drive speed, its control method, and a flyback power converter. Background Technology

[0002] With increasing demands for power efficiency, the use of synchronous rectification on the secondary side of AC / DC chargers or adapters instead of simple diode rectification has become a mainstream and even mandatory solution. Compared to diodes, synchronous rectification of metal-oxide-semiconductor field-effect transistors (MOSFETs) on the secondary side has a lower turn-on voltage, which can reduce conduction losses and improve the efficiency of the primary-side quasi-resonant control system.

[0003] The primary-side quasi-resonant control system using synchronous rectification and a quasi-resonant primary-side controller has the following problems: Under heavy load, the primary-side MOSFET starts conducting after detecting the valley of the first resonant cycle of the primary-side MOSFET drain voltage. As the load decreases, it gradually switches to the valley of the second, third, or even later resonant cycles before turning on the primary-side MOSFET. Since the ringing amplitude of the resonance gradually decays with the increase of the number of rings or the length of the resonant time, the valley voltage corresponding to the primary-side MOSFET turning on becomes very high under light load. If the same drive speed as under heavy load is used to turn on the primary-side MOSFET, its drain voltage drops from a very high voltage to close to 0V. This corresponds to a rapid rise in the drain voltage of the secondary-side MOSFET on the transformer secondary side. Due to the parasitic leakage inductance of the transformer, a significant voltage (VDS) stress is generated between the drain (D) and source (S) of the secondary-side MOSFET, which may even exceed the breakdown voltage of the secondary-side MOSFET, causing the secondary-side MOSFET to be damaged. Alternatively, the excessively high VDS stress may necessitate the selection of a secondary-side MOSFET with a higher withstand voltage, increasing the cost of the primary-side quasi-resonant control system.

[0004] The primary-side quasi-resonant control system using synchronous rectification and a quasi-resonant primary-side controller also has a problem: during startup or output short-circuit operation, the secondary current decays slowly due to the low output voltage VOUT. This results in the secondary current not decaying to zero before entering Continuous Conduction Mode (CCM) operation in the next switching cycle. When the primary MOSFET is turned on, there is a significant VDS stress on the secondary MOSFET due to the previous secondary-side shoot-through. If the same drive speed as during normal heavy load is used to turn on the primary MOSFET, it will generate a voltage exceeding the breakdown voltage of the secondary MOSFET, causing the secondary MOSFET to be damaged. Alternatively, due to the excessively high VDS stress, a secondary MOSFET with a higher withstand voltage needs to be selected, increasing the cost of the primary-side quasi-resonant control system. Summary of the Invention

[0005] The purpose of this application is to provide a dynamic speed adjustment circuit for driving, which aims to solve the problem of excessive stress on the secondary-side field-effect transistors when using a traditional synchronous rectification paired with a quasi-resonant primary-side controller in light-load operating mode, startup process, or output short-circuit state.

[0006] To achieve the above objectives, in a first aspect, embodiments of this application provide a dynamic adjustment circuit for driving speed, applied to a primary-side quasi-resonant control system, wherein the primary-side quasi-resonant control system includes a driving module, a detection module, and a control module;

[0007] The detection module is used to detect the operating status of the primary-side quasi-resonant control system.

[0008] The control module is used to output a drive speed adjustment signal corresponding to the target working state when the detection module detects that the primary-side quasi-resonant control system is in the target working state. The drive speed adjustment signal is used to adjust the speed of the drive module.

[0009] In one possible implementation of the first aspect, when the target operating state is a light-load operating mode, the detection module includes a load detection component for generating a light-load operating signal, the load detection component including a first edge pulse triggering unit, a valley counting and comparison unit, and a first trigger unit;

[0010] The first edge pulse triggering unit is used to generate a first pulse signal on the falling edge of the pulse modulation signal and send it to the first trigger unit to perform periodic zeroing processing on the light load working signal. The valley counting and comparison unit is used to count the valley signal and generate a counting completion signal when the count reaches a first preset value and send it to the first trigger unit to perform setting processing on the light load working signal.

[0011] In another possible implementation of the first aspect, when the target operating state is a light-load operating mode, the detection module includes a load detection component for generating a light-load operating signal, the load detection component including a second edge pulse triggering unit, a first comparator unit, and a second flip-flop unit;

[0012] The second edge pulse triggering unit is used to generate a second pulse signal on the falling edge of the pulse modulation signal and send it to the second trigger unit to perform periodic zeroing processing on the light load operating signal. The first comparator unit is used to compare the magnitude of the loop control signal and the first reference voltage and send the comparison result to the second trigger unit to perform setting processing on the light load operating signal.

[0013] In another possible implementation of the first aspect, when the target operating state is a light-load operating mode, the detection module includes a load detection component for generating a light-load operating signal, the load detection component including a third edge pulse triggering unit, a peak sampling unit, a second comparator unit and a third trigger unit;

[0014] The third edge pulse triggering unit is used to generate a third pulse signal on the falling edge of the pulse modulation signal and send it to the third trigger unit. The peak sampling unit is used to sample the peak voltage of the primary current sampling signal and send it to the second comparator unit. The second comparator unit is used to compare the magnitude of the peak voltage of the primary current sampling signal and the second reference voltage, and send the comparison result to the third trigger unit to set the light load operating signal.

[0015] In another possible implementation of the first aspect, when the target operating state is a startup process or an output short-circuit state, the detection module includes a startup and short-circuit detection component for generating a startup signal. The startup and short-circuit detection component includes a third comparator unit for comparing the magnitude of a loop control signal and a third reference voltage, and generating a startup signal based on the comparison result.

[0016] Secondly, embodiments of this application provide a control method for a dynamic speed adjustment circuit, comprising the following steps:

[0017] The operating status of the primary-side quasi-resonant control system is detected by the detection module.

[0018] When the primary-side quasi-resonant control system is in the target operating state as detected by the detection module, the control module outputs a drive speed adjustment signal corresponding to the target operating state, and adjusts the speed of the drive module through the drive speed adjustment signal.

[0019] In another possible implementation of the second aspect, when the target working state is a light-load working mode, the detection module outputs a light-load working signal, and the control module adjusts the speed of the drive module according to the light-load working signal.

[0020] In another possible implementation of the second aspect, when the target operating state is in the startup process or the output short circuit state, the detection module outputs a startup signal, and the control module adjusts the speed of the drive module according to the startup signal.

[0021] Thirdly, embodiments of this application provide a primary-side quasi-resonant controller, including the aforementioned dynamic adjustment circuit for driving speed, valley detection module, quasi-resonant control module, and driving module;

[0022] The valley detection module is used to detect the valley signal and send it to the quasi-resonant control module. The quasi-resonant control module is used to generate a pulse width modulation signal based on the valley signal, the loop control signal, and the primary side current sampling signal and send it to the drive module. The drive module is used to control the primary side field-effect transistor to turn on or off based on the pulse width modulation signal. The drive module is also used to adjust the drive speed based on the drive speed adjustment signal of the drive speed dynamic adjustment circuit.

[0023] Fourthly, embodiments of this application provide a flyback power converter, including a primary-side quasi-resonant controller module and a secondary-side controller module. The primary-side quasi-resonant controller module includes the primary-side quasi-resonant controller, and the primary-side quasi-resonant controller module is coupled to the secondary-side controller module.

[0024] The primary-side quasi-resonant controller module is used to control the output voltage of the primary winding, and the secondary-side controller module is used to control the output voltage of the secondary winding.

[0025] The beneficial effects of this application embodiment compared with the prior art are as follows: The above-mentioned dynamic adjustment circuit for driving speed detects the working state of the primary-side quasi-resonant control system through the detection module. When the detection module detects that the primary-side quasi-resonant control system is in the target working state, the control module outputs a driving speed adjustment signal corresponding to the target working state to adjust the speed of the driving module. When the primary-side quasi-resonant control system enters the light-load working mode, the start-up process, or the output short-circuit state, the driving speed of the primary-side field-effect transistor is slowed down, thereby effectively alleviating the problem of excessive stress on the secondary-side field-effect transistor. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the drive speed dynamic adjustment circuit provided in the embodiments of this application;

[0028] Figure 2 This is a schematic diagram of a traditional primary-side quasi-resonant control system.

[0029] Figure 3 A schematic diagram of the structure of a first type of load detection component for a drive speed dynamic adjustment circuit provided in an embodiment of this application;

[0030] Figure 4 A schematic diagram of the structure of a first type of dynamic driving speed adjustment circuit provided in an embodiment of this application;

[0031] Figure 5 A schematic diagram of the structure of a second load detection component for a drive speed dynamic adjustment circuit provided in an embodiment of this application;

[0032] Figure 6 A schematic diagram of the structure of a second type of dynamic driving speed adjustment circuit provided in an embodiment of this application;

[0033] Figure 7 A schematic diagram of the third load detection component of the drive speed dynamic adjustment circuit provided in the embodiments of this application;

[0034] Figure 8 A schematic diagram of the structure of a third type of dynamic driving speed adjustment circuit provided in an embodiment of this application;

[0035] Figure 9 A schematic diagram of the start-up and short-circuit detection components of the drive speed dynamic adjustment circuit provided in the embodiments of this application;

[0036] Figure 10 A circuit diagram of the drive module of the dynamic speed adjustment circuit provided in the embodiments of this application;

[0037] Figure 11 A flowchart of the control method for the drive speed dynamic adjustment circuit provided in the embodiments of this application;

[0038] Figure 12A waveform diagram of a primary-side quasi-resonant controller without a dynamic adjustment circuit for driving speed provided in an embodiment of this application;

[0039] Figure 13 This is a waveform diagram of the primary-side quasi-resonant controller with added driving speed dynamic adjustment circuit provided in the embodiments of this application.

[0040] The following are the labeling elements in the figure:

[0041] 1-Detection module, 101-First edge pulse triggering unit, 102-Valley counting and comparison unit, 103-First trigger unit, 104-Second edge pulse triggering unit, 105-First comparator unit, 106-Second trigger unit, 107-Third edge pulse triggering unit, 108-Peak sampling unit, 109-Second comparator unit, 110-Third trigger unit, 2-Control module, 3-Valley detection module, 4-Quasi-resonant control module, 5-Drive module. Detailed Implementation

[0042] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0043] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0044] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0046] Figure 2 A schematic diagram of a traditional primary-side quasi-resonant control system is shown. For ease of explanation, only the parts relevant to this embodiment are shown. Currently, the traditional primary-side quasi-resonant control system generally obtains the valley signal by detecting the voltage divider signal through the valley detection module 3. The quasi-resonant control module 4 outputs a pulse width modulation (PWM) signal based on the valley signal, the loop control signal COMP, or the primary-side current sampling signal CS. The drive module 5 directly drives and controls the primary-side MOSFET to turn on and off based on the PWM signal. Because traditional primary-side quasi-resonant control systems operate at the same speed under normal heavy load, light load, startup, or output short circuit conditions, without speed regulation, the drive speed needs to be set relatively high to achieve optimized heavy load efficiency. However, when the drive speed remains high under light load, startup, or output short circuit conditions, the secondary MOSFET experiences high stress, easily leading to high VDS stress, which may even exceed the breakdown voltage of the secondary MOSFET, causing it to break down. Alternatively, the excessively high VDS stress may necessitate selecting a secondary MOSFET with a higher withstand voltage, increasing the cost of the primary-side quasi-resonant control system.

[0047] Therefore, this application provides a drive speed dynamic adjustment circuit. The drive speed is adjusted by the drive speed adjustment signal slowON output by the drive speed dynamic adjustment circuit. When the primary side quasi-resonant control system enters the light load working mode, the start-up process, or the output short circuit state, the drive speed dynamic adjustment circuit outputs slowON=1, thereby reducing the turn-on speed of the drive module, reducing the VDS stress of the secondary side MOSFET, and ensuring that it does not exceed the breakdown voltage of the secondary side MOSFET.

[0048] Figure 1 The diagram shows a schematic of the drive speed dynamic adjustment circuit provided in the first embodiment of this application. This application shows a drive speed dynamic adjustment circuit applied to a primary-side quasi-resonant control system. The primary-side quasi-resonant control system includes a drive module, a detection module 1, and a control module 2.

[0049] The detection module 1 is used to detect the operating status of the primary-side quasi-resonant control system;

[0050] The control module 2 is used to output a drive speed adjustment signal corresponding to the target working state when the detection module 1 detects that the primary-side quasi-resonant control system is in the target working state. The drive speed adjustment signal is used to adjust the speed of the drive module.

[0051] In this embodiment, the detection module 1 detects the working state of the primary-side quasi-resonant control system, and the control module 2 outputs a drive speed adjustment signal corresponding to the target working state when the detection module 1 detects that the primary-side quasi-resonant control system is in the target working state, thereby adjusting the speed of the drive module.

[0052] In this embodiment, the output load current is detected by a load detection component, which is achieved by using the existing valley signal, loop control signal COMP, or primary current sampling signal CS in the primary-side quasi-resonant controller. When the primary-side quasi-resonant control system is detected to enter a light-load operating mode, a light-load operating signal lightLoad=1 is generated. The startup process and output short-circuit state are detected by a startup and short-circuit detection component, which is achieved by using the existing loop control signal COMP in the primary-side quasi-resonant controller. When the primary-side quasi-resonant control system is detected to be operating in the startup process or in the output short-circuit state, a start signal start=1 is generated.

[0053] The light-load signal (lightLoad) and the start signal (start) are ORed by the control module 2 (i.e., OR gate OR1) to generate a drive speed adjustment signal (slowON). This signal is then output to the drive module 5 to dynamically adjust the drive speed of the MOSFET. When the primary-side quasi-resonant control system is detected to be in a light-load operation, startup process, or output short circuit state that is prone to generating high stress on the secondary-side MOSFET, slowON = 1 is generated to reduce the drive speed of the primary-side MOSFET and avoid excessive VDS stress on the secondary-side MOSFET. When the primary-side quasi-resonant control system is in other normal operating states, slowON = 0, and a faster primary-side MOSFET drive speed is controlled to improve the power supply conversion efficiency.

[0054] Figure 3 This paper shows a schematic diagram of the structure of a first type of load detection component of the drive speed dynamic adjustment circuit provided in an embodiment of this application. Figure 4 The diagram shows a first type of dynamic driving speed adjustment circuit provided in this application embodiment. When the target working state is a light load working mode, the detection module 1 includes a load detection component for generating a light load working signal. The load detection component includes a first edge pulse triggering unit 101, a valley counting and comparison unit 102, and a first trigger unit 103. The first edge pulse triggering unit 101 and the valley counting and comparison unit 102 are all connected to the first trigger unit 103.

[0055] The first edge pulse triggering unit 101 is used to generate a first pulse signal on the falling edge of the pulse modulation signal and send it to the first trigger unit 103 to perform periodic zeroing processing on the light load working signal. The valley counting and comparison unit 102 is used to count the valley signal and generate a counting completion signal when the count reaches a first preset value and send it to the first trigger unit 103 to perform setting processing on the light load working signal.

[0056] In this embodiment, the first edge pulse triggering unit 101 generates a pulse signal XONpulse on the falling edge of the PWM signal ON, and outputs it to the reset terminal R of the first trigger unit 103 to periodically clear the light load signal lightLoad. The valley counting and comparison unit 102 counts the valley signal valley, and when the count reaches a preset value, it generates a valleyCountDone signal, which is output to the set terminal S of the first trigger unit 103 to set the light load signal lightLoad.

[0057] When the output load current is large, the controller's duty cycle corresponds to a state with fewer resonant rings, and the valley count is below the preset value, with both valleyCountDone and lightLoad remaining at 0. As the output load current gradually decreases, the number of resonant rings corresponding to the controller's duty cycle gradually increases, entering a light load operating mode. When the valley count reaches or exceeds the preset value, valleyCountDone flips to 1, setting the light load signal to 1. This, in turn, generates slowON = 1 through control module 2 (i.e., OR gate OR1), controlling drive module 5 to slow down the drive speed. Simultaneously, by changing the preset value of the valley count, the flip point of the drive speed control signal slowON can be changed, thus adjusting the output load current switching point corresponding to slowing down the drive speed.

[0058] Figure 5 This illustration shows a schematic diagram of the structure of a second load detection component of the drive speed dynamic adjustment circuit provided in an embodiment of this application. Figure 6 The diagram shows a second type of dynamic driving speed adjustment circuit provided in this application embodiment. When the target working state is a light load working mode, the detection module 1 includes a load detection component for generating a light load working signal. The load detection component includes a second edge pulse triggering unit 104, a first comparator unit 105, and a second trigger unit 106. The second edge pulse triggering unit 104 and the first comparator unit 105 are both connected to the second trigger unit 106.

[0059] The second edge pulse triggering unit 104 is used to generate a second pulse signal on the falling edge of the pulse modulation signal and send it to the second trigger unit 106 to perform periodic zeroing processing on the light load operating signal. The first comparator unit 105 is used to compare the magnitude of the loop control signal and the first reference voltage and send the comparison result to the second trigger unit 106 to perform setting processing on the light load operating signal.

[0060] In this embodiment, the second edge pulse triggering unit 104 generates a pulse signal XONpulse on the falling edge of the PWM signal ON, and outputs it to the reset terminal R of the second trigger unit 106 to periodically clear the light load signal lightLoad. The loop control signal COMP and the reference voltage Vref are compared by the comparator comp0. When the COMP signal is lower than Vref, COMPlow = 1 is generated and output to the set terminal S of the second trigger unit 106 to set the light load signal lightLoad.

[0061] When the output load current is relatively large, the loop control signal COMP corresponds to a relatively high voltage, higher than the reference voltage Vref. The comparator comp0 outputs COMPlow and lightLoad both remain at 0. As the output load current gradually decreases, the loop control signal COMP voltage gradually decreases. When entering light load operation, the COMP voltage is lower than the reference voltage Vref, and the comparator comp0 output COMPlow flips to 1, setting the light load signal lightLoad to 1. This, in turn, through control module 2 (i.e., OR gate OR1), generates slowON = 1 to control drive module 5 to slow down the drive speed. Simultaneously, by changing the reference voltage Vref, the flip point of the drive speed control signal slowON can be changed, which adjusts the output load current switching point corresponding to slowing down the drive speed.

[0062] Figure 7 This paper shows a schematic diagram of the structure of a third load detection component of the drive speed dynamic adjustment circuit provided in an embodiment of this application. Figure 8 The diagram shows a third type of dynamic driving speed adjustment circuit provided in this application embodiment. When the target working state is a light-load working mode, the detection module 1 includes a load detection component for generating a light-load working signal. The load detection component includes a third edge pulse triggering unit 107, a peak sampling unit 108, a second comparator unit 109, and a third trigger unit 110. The peak sampling unit 108 is connected to the second comparator unit 109, and the third edge pulse triggering unit 107 and the second comparator unit 109 are both connected to the third trigger unit 110.

[0063] The third edge pulse triggering unit 107 is used to generate a third pulse signal on the falling edge of the pulse modulation signal and send it to the third trigger unit 110. The peak sampling unit 108 is used to sample the peak voltage of the primary current sampling signal and send it to the second comparator unit 109. The second comparator unit 109 is used to compare the magnitude of the peak voltage of the primary current sampling signal and the second reference voltage, and send the comparison result to the third trigger unit 110 to set the light load operating signal.

[0064] In this embodiment, the third edge pulse triggering unit 107 generates a pulse signal XONpulse on the falling edge of the PWM signal ON, and outputs it to the reset terminal R of the third flip-flop unit 110 to periodically clear the slowON signal. The primary current sampling signal CS obtains the peak voltage CSP through the peak sampling unit 108, and compares it with the reference voltage Vref through the comparator comp0. When the peak sampling voltage CSP is lower than Vref, CSPlow = 1 is generated and output to the set terminal S of the third flip-flop unit 110 to set the light load signal lightLoad.

[0065] When the output load current is relatively large, the peak value corresponding to the primary-side current sampling signal CS, i.e., the peak sampling voltage CSP obtained by the peak sampling unit 108, is relatively high, higher than the reference voltage Vref. The comparator comp0 output CSPlow and the light-load operating signal lightLoad both remain at 0. As the output load current gradually decreases, the peak value corresponding to the primary-side current sampling signal CS, i.e., the peak sampling voltage CSP obtained by the peak sampling unit 108, gradually decreases, entering the light-load operating mode. When the CSP voltage is lower than the reference voltage Vref, the comparator output CSPlow flips to 1, setting the light-load operating signal lightLoad to 1. This, in turn, generates a drive speed control signal slowON = 1 through the control module 2 (i.e., OR gate OR1), controlling the drive module 5 to slow down the drive speed. Simultaneously, by changing the reference voltage Vref, the flip point of the drive speed control signal slowON can be changed, i.e., adjusting the output load current switching point corresponding to slowing down the drive speed.

[0066] Figure 9 The diagram shows a schematic of the start-up and short-circuit detection component of the drive speed dynamic adjustment circuit provided in this application embodiment. When the target working state is the start-up process or the output short-circuit state, the detection module 1 includes a start-up and short-circuit detection component for generating a start signal. The start-up and short-circuit detection component includes a third comparator unit, which is used to compare the magnitude of the loop control signal and the third reference voltage, and generate a start signal based on the comparison result.

[0067] In this embodiment, the loop control signal COMP is compared with a higher reference voltage Vref1 through a third comparator unit (i.e., comparator comp1) to generate a start signal. When the primary-side quasi-resonant control system is operating during startup or in an output short-circuit state, the loop control signal COMP is at a very high voltage, higher than the reference voltage Vref1, generating a start signal start = 1. This, in turn, generates slowON = 1 through the control module 2 (i.e., OR gate or1), controlling the drive module 5 to slow down the drive speed. When in other normal operating states, the COMP voltage is lower than the reference voltage Vref1, the start signal start remains 0, corresponding to slowON = 0, and the drive module 5 selects a faster drive speed.

[0068] Figure 10 The diagram illustrates the drive module of the dynamic speed adjustment circuit provided in this application embodiment. When the pulse width modulation signal ON = 0, the NMOS transistor NM1 is turned on, pulling GATE down to ground to achieve turn-off control. When the pulse width modulation signal ON = 1, the PMOS transistor PM1 is turned on, and the variable current source IB gradually pulls up GATE to achieve turn-on control. The drive speed adjustment signal slowON controls the current of the variable current source IB to achieve drive speed adjustment. Specifically, when slowON = 1, the current of the variable current source IB is reduced, and the pull-up speed of GATE is slowed down, achieving the goal of slowing down the turn-on speed.

[0069] This application also discloses a primary-side quasi-resonant controller, including the aforementioned driving speed dynamic adjustment circuit, valley bottom detection module 3, quasi-resonant control module 4, and driving module 5. The valley bottom detection module 3 is connected to the quasi-resonant control module 4, the quasi-resonant control module 4 is connected to the driving module 5, and the driving speed dynamic adjustment circuit is connected to the valley bottom detection module 3, the quasi-resonant control module 4, and the driving module 5.

[0070] In this embodiment, the valley bottom signal is detected by the valley bottom detection module and sent to the quasi-resonant control module 4. The quasi-resonant control module 4 generates a pulse width modulation signal based on the valley bottom signal, the loop control signal, and the primary side current sampling signal and sends it to the drive module 5. The drive module 5 controls the primary side field-effect transistor to turn on or off based on the pulse width modulation signal. The drive speed dynamic adjustment circuit outputs a drive speed adjustment signal slowON to control the drive module 5 to slow down the drive speed or select a faster drive speed.

[0071] This application also discloses a flyback power converter, including a primary-side quasi-resonant controller module and a secondary-side controller module. The primary-side quasi-resonant controller module includes the primary-side quasi-resonant controller and is coupled to the secondary-side controller module.

[0072] In this embodiment, the output voltage of the primary winding is controlled by the primary-side quasi-resonant controller module, and the output voltage of the secondary winding is controlled by the secondary-side controller module.

[0073] Figure 11 The flowchart illustrates a control method for a drive speed dynamic adjustment circuit provided in an embodiment of this application. This application discloses a control method for a drive speed dynamic adjustment circuit, comprising the following steps:

[0074] S10. Detect the operating status of the primary-side quasi-resonant control system through the detection module;

[0075] S20. When the primary-side quasi-resonant control system is in the target working state as detected by the detection module, the control module outputs a drive speed adjustment signal corresponding to the target working state, and adjusts the speed of the drive module through the drive speed adjustment signal.

[0076] In this embodiment of the application, the detection module includes a load detection component, that is, the load detection component detects whether the primary-side quasi-resonant control system is in a light-load operating mode. When the load detection component detects that the primary-side quasi-resonant control system is in a light-load operating mode, the load detection component outputs a light-load operating signal at a high level, and vice versa.

[0077] The primary-side quasi-resonant control system is detected to be in the startup process or output short-circuit state by the startup and short-circuit detection components. When the startup and short-circuit detection components detect that the primary-side quasi-resonant control system is in the startup process or output short-circuit state, the startup and short-circuit detection components output a high-level start signal, and vice versa.

[0078] When the light-load working signal output by the load detection component is high or the start signal output by the start and short-circuit detection component is high, the control module outputs a drive speed adjustment signal at a high level, and outputs a drive speed adjustment signal slowON=1, controlling the drive module 5 to slow down the drive speed. Conversely, when the load detection component outputs a drive speed adjustment signal at a low level, the control module outputs a drive speed adjustment signal at a low level, and outputs a drive speed adjustment signal slowON=0, controlling the drive module 5 to select a faster drive speed.

[0079] Figure 12 The diagram shows a waveform of a primary-side quasi-resonant controller without a dynamic speed adjustment circuit provided in this application embodiment. As can be seen from the diagram, when the output current is under heavy load, the controller's operating cycle corresponds to a state with a relatively small number of rings. When the primary-side MOSFET is turned on, the drain voltage PD drops from a relatively low valley voltage VL to 0V, and the stress on the corresponding secondary-side MOSFET drain voltage VD is relatively small.

[0080] When the output current becomes light load, the controller's working cycle corresponds to a state with a relatively large number of rings. Since the ring amplitude decreases as the number of rings / resonance time increases, the drain voltage PD of the primary MOSFET drops from a relatively high valley voltage VH to 0V when the primary MOSFET is turned on. When the drive speed is not adjusted, the drain voltage PD of the primary MOSFET drops from VH to 0V very quickly. When this is mapped to the secondary side of the transformer, it generates significant stress on the drain voltage VD of the secondary MOSFET.

[0081] Figure 13 The diagram shows a waveform of the primary-side quasi-resonant controller with dynamic adjustment of drive speed provided in an embodiment of this application. As can be seen from the diagram, after the output current becomes light load, the load current detection module added in this application counts the valley signal. When the number of valleys exceeds the preset value during light load operation, slowON=1 is generated, which slows down the drive speed so that the drain voltage PD of the primary-side MOSFET slowly drops from VH to 0V when it is turned on. The stress of the drain voltage VD of the secondary-side MOSFET can be kept very low under different output load conditions.

[0082] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0083] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above-described primary-side quasi-resonant control system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0084] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0085] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0086] In the embodiments provided in this application, it should be understood that the disclosed dynamic adjustment circuit and method for drive speed can be implemented in other ways. For example, the drive speed dynamic adjustment circuit embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another primary-side quasi-resonant control system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0087] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0088] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0089] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A dynamic speed adjustment circuit for driving, applied to a primary-side quasi-resonant control system, wherein the primary-side quasi-resonant control system includes a driving module, characterized in that, It includes a detection module (1) and a control module (2); The detection module (1) is used to detect the working state of the primary-side quasi-resonant control system; The control module (2) is used to output a drive speed adjustment signal corresponding to the target working state when the detection module (1) detects that the primary-side quasi-resonant control system is in the target working state. The drive speed adjustment signal is used to adjust the speed of the drive module. The detection module (1) is also used to generate a light-load working signal when the primary-side quasi-resonant control system is detected to enter the light-load working mode; The detection module (1) is also used to generate a start signal when the primary-side quasi-resonant control system is detected to be operating in the start-up process or in the output short-circuit state; The control module (2) is also used to perform an OR operation on the light load working signal and the start signal to generate a drive speed adjustment signal, and output it to the drive module for dynamic adjustment to reduce the drive speed of the drive module. When the target operating state is the start-up process or the output short circuit state, the detection module (1) includes a start-up and short circuit detection component for generating a start-up signal. The start-up and short circuit detection component includes a third comparator unit, which is used to compare the magnitude of the loop control signal and the third reference voltage, and generate a start-up signal based on the comparison result.

2. The dynamic speed adjustment circuit for driving as described in claim 1, characterized in that, When the target working state is a light load working mode, the detection module (1) includes a load detection component for generating a light load working signal. The load detection component includes a first edge pulse triggering unit (101), a valley counting and comparison unit (102), and a first trigger unit (103). The first edge pulse triggering unit (101) is used to generate a first pulse signal on the falling edge of the pulse modulation signal and send it to the first trigger unit (103) to perform periodic zeroing processing on the light load working signal. The valley counting and comparison unit (102) is used to count the valley signal and generate a counting completion signal when the count reaches a first preset value and send it to the first trigger unit (103) to perform setting processing on the light load working signal.

3. The dynamic adjustment circuit for drive speed as described in claim 1, characterized in that, When the target working state is a light load working mode, the detection module (1) includes a load detection component for generating a light load working signal. The load detection component includes a second edge pulse triggering unit (104), a first comparator unit (105), and a second trigger unit (106). The second edge pulse triggering unit (104) is used to generate a second pulse signal at the falling edge of the pulse modulation signal and send it to the second trigger unit (106) to perform periodic zeroing processing on the light load working signal. The first comparator unit (105) is used to compare the magnitude of the loop control signal and the first reference voltage and send the comparison result to the second trigger unit (106) to perform setting processing on the light load working signal.

4. The drive speed dynamic adjustment circuit as described in claim 1, characterized in that, When the target working state is a light load working mode, the detection module (1) includes a load detection component for generating a light load working signal. The load detection component includes a third edge pulse triggering unit (107), a peak sampling unit (108), a second comparator unit (109), and a third trigger unit (110). The third edge pulse triggering unit (107) is used to generate a third pulse signal on the falling edge of the pulse modulation signal and send it to the third trigger unit (110). The peak sampling unit (108) is used to sample the peak voltage of the primary current sampling signal and send it to the second comparator unit (109). The second comparator unit (109) is used to compare the magnitude of the peak voltage of the primary current sampling signal and the second reference voltage, and send the comparison result to the third trigger unit (110) to set the light load working signal.

5. A control method for the drive speed dynamic adjustment circuit according to any one of claims 1-4, characterized in that, Includes the following steps: The operating status of the primary-side quasi-resonant control system is detected by the detection module. When the primary-side quasi-resonant control system is in the target operating state as detected by the detection module, the control module outputs a drive speed adjustment signal corresponding to the target operating state, and adjusts the speed of the drive module through the drive speed adjustment signal.

6. The control method as described in claim 5, characterized in that, When the target working state is in light-load working mode, the detection module outputs a light-load working signal, and the control module adjusts the speed of the drive module according to the light-load working signal.

7. The control method as described in claim 5, characterized in that, When the target operating state is in the startup process or output short circuit state, the detection module outputs a startup signal, and the control module adjusts the speed of the drive module according to the startup signal.

8. A primary-side quasi-resonant controller, characterized in that, It includes the drive speed dynamic adjustment circuit, valley bottom detection module (3), quasi-resonance control module (4) and drive module (5) as described in any one of claims 1-4; The valley detection module (3) is used to detect the valley signal and send it to the quasi-resonant control module (4). The quasi-resonant control module (4) is used to generate a pulse width modulation signal based on the valley signal, the loop control signal and the primary side current sampling signal and send it to the drive module (5). The drive module (5) is used to control the primary side field-effect transistor to turn on or off based on the pulse width modulation signal. The drive module (5) is also used to adjust the drive speed based on the drive speed adjustment signal of the drive speed dynamic adjustment circuit.

9. A flyback power converter, comprising a primary-side quasi-resonant controller module and a secondary-side controller module, characterized in that, The primary-side quasi-resonant controller module includes the primary-side quasi-resonant controller as described in claim 8, and the primary-side quasi-resonant controller module is coupled to the secondary-side controller module; The primary-side quasi-resonant controller module is used to control the output voltage of the primary winding, and the secondary-side controller module is used to control the output voltage of the secondary winding.

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