Communication using edge timing in signals

Abstract

Embodiments of this disclosure relate to communication using edge timing in signals. Systems, methods, and circuits are provided to perform bidirectional communication using edge timing. In an example, one method includes receiving a first signal on a first signal line, the first signal having a first timing edge and a first data edge. The first timing edge and the first data edge are of different types. The first data edge is an edge immediately adjacent to the first timing edge and occurs after a first elapsed time following the first timing edge. The method includes sampling the first signal for a predetermined sampling time after the first timing edge to determine a first data value. A second data value is determined, and a second signal having a second timing edge and a second data edge is generated. A second elapsed time between the second timing edge and the second data edge encodes the second data value. The second signal is transmitted on the second signal line.

Description

Technical Field

[0001] This disclosure relates to the field of communication protocols and technologies, and more particularly to methods, systems and circuit arrangements for communication of status and data between devices. Background Technology

[0002] Many microprocessor applications rely on robust, simple, and low-bandwidth communication paths between two devices. In security-related applications, numerous communication paths are used to ensure the proper functioning of each security-related device. Therefore, it is important that the communication paths in such applications support fast and reliable communication without requiring a large number of pins or additional components. Attached Figure Description

[0003] The following description will only include some examples of circuits, devices, and / or methods by way of example. In this context, reference will be made to the accompanying drawings.

[0004] Figure 1A and Figure 1B An example of a communication system according to the described aspects is shown, which includes two devices that perform communication using edge timing in signals.

[0005] Figure 2 An example of a communication system according to the described aspects is shown, which includes two devices that perform communication using edge timing in signals.

[0006] Figure 3 An example of a communication system according to the described aspects is shown, which includes two devices that perform communication using edge timing in signals.

[0007] Figure 4 A timing diagram of an example written communication protocol is shown, illustrating how communication is performed using edge timing in a signal, based on the described aspects.

[0008] Figure 5 A timing diagram of an example reading communication protocol is shown, based on the described aspects for performing communication using edge timing in a signal.

[0009] Figure 6 An example of a communication system is shown, which includes a chain of master and slave devices that use edge timing in signals to perform communication.

[0010] Figure 7 An example of a communication system is shown, which includes a chain of master and slave devices that use edge timing in signals to perform communication.

[0011] Figure 8An example of a communication device configured to perform communication using edge timing in a signal, according to the described aspects, is shown.

[0012] Figure 9 A timing diagram showing the minimum 0 and minimum 1 times of a communication protocol for performing communication using edge timing in a signal is shown, according to the described aspects.

[0013] Figure 10 An example of a UART-like data frame is shown, based on the aspects described.

[0014] Figure 11 This is a flowchart outlining an example method for performing communication using edge timing in a signal, based on the described aspects. Detailed Implementation

[0015] In some microprocessor device applications, a central or master controller monitors the health or status of many different slave devices, or slave devices under the master controller's control. If any slave device fails, the master controller will take remedial actions, such as ceasing communication with the failed device and / or entering a fail-safe mode for functions performed by the failed device. Each slave device, in turn, monitors the health or status of the master controller and enters a fail-safe mode in the event of a master controller failure. The target response time for such a system is on the order of tens to hundreds of microseconds. Because a slave device failure should not be allowed to disrupt communication with another slave device, a dedicated communication channel is typically installed between each slave device and the master controller. Therefore, continuous monitoring of the status between the master controller and the slave devices requires fast and reliable communication through many communication paths.

[0016] For the purposes of this specification, the terms "master" and "slave" will be used to distinguish between two devices that use edge timing in signals to perform the described communication. It should be understood that the described technology can be performed by any two devices, whether or not they are in a master-slave relationship. Furthermore, although certain functions in the communication technology may belong to one of the master or slave devices, it should be understood that these functions can be performed by the other, either in lieu of or additionally, the master or slave device.

[0017] Communication or data exchange between building blocks or devices is crucial for electronic components or control units. Many different protocols and physical layers are available, depending on requirements for data throughput (baud rate), robustness of data lines (physical layer), and data processing performance (protocol simplicity). However, with the advent and rapid growth of demands for safer and more precise operation of motors and other loads or actuators (internal combustion engines and electric drives), there is a need for a simple, inexpensive, and fast (e.g., up to or above 100 MBits / s) communication interface to facilitate greater data exchange between microcontrollers and sensor or actuator drivers (on-chip or off-chip).

[0018] like Figure 1A and Figure 1B As typically shown herein, this document describes methods, systems, and circuit arrangements for performing a self-synchronizing data communication scheme, wherein the devices use edge timing in signals to perform communication. A master communication device (e.g., device 102) (hereinafter referred to as the "master device") transmits a stream of timing edges with fixed timing defined by a desired baud rate. The fixed timing of the timing edges is independent of the transmitted data bits. Another edge, the data edge, defines the transmitted data value. Figure 1A The diagram illustrates edge-timing-based communication, where the falling edge is the timing edge and the rising edge is the data edge. Figure 1B The diagram illustrates edge-timing-based communication, where the rising edge is the timing edge and the falling edge is the data edge.

[0019] If a master device sends data to a slave communication device (e.g., device 104) (hereinafter referred to as the "slave device"), the master device modulates the timing of the data edges according to the data bits to be transmitted, such that the elapsed time between the timing edge and the data edge encodes the value of the data bit being communicated. For example, if a data bit with a value of 0 is to be transmitted, the timing distance of the data edge relative to the previous timing edge is different compared to the timing of the data edge when transmitting a data bit with a value of 1.

[0020] When the master device retrieves data from the slave device, it sends a signal consisting of a sequence of timing edges and data edges, where the position of the data edges can be transmitted to the retrieving slave device. The signal is modified by the slave device to position the data edges as timing relative to the timing edges that encode the transmitted data value. The modified signal is then sent to the master device.

[0021] In some examples, the master device 102 is a microcontroller that links to the slave device 104 and possibly a chain of multiple slave devices (see [link]). Figure 6 and Figure 7The slave device 104 provides pulse width modulation (PWM) or other control signals. In some examples, the slave device 104 is a gate driver for high-power devices such as fuel injectors, motors, battery control or monitoring devices, or solenoid valves. In some examples, the slave device 104 is an isolated gate driver for a measuring device controlled by the master device 102, which measures the temperature or voltage of another device and generates digital data encoding the measured temperature or voltage.

[0022] Figure 2 An example communication system 200 including a master device and slave devices is illustrated. Each device includes a transmit physical interface 205 and a receive physical interface 206. Two signal line pairs are coupled to each of interfaces 205, 206 and connect the master device to the slave device, one for communication from master to slave and the other for communication from slave to master. In the example, physical interfaces 205, 206 are low-voltage differential swing (LVDS) interfaces, designed to provide relatively high resistance to EMI. LVDS interface pins and drivers are available in many different technologies, including power-oriented and microprocessor technologies, making them well-suited for the system described. It should be noted that other physical interfaces and protocols may be used in other examples. In the figures, the symbol “te” indicates a timing edge and the symbol “de” indicates a data edge, as shown in the figures. Figure 1A and Figure 1B As shown, these edges can be rising edges or falling edges.

[0023] The master device includes a baud rate generation circuit 210 that generates timing edges based on the required baud rate of a master signal transmitted by the master device on interface 205. The master device also includes a data transmitter 220 that generates a master transmit signal, which, when combined with the timing signal output by the baud rate generation circuit 210, results in a signal having a master data edge at the location where data (or mode selection) to be transmitted to the slave device is encoded. An edge combination circuit 230 combines the timing signal with the master transmit signal to generate the master signal. In this example, simple AND or OR combinational logic can be used in the edge combination circuit 230, depending on the edge types used for the timing and data edges. An AND combination can be used when the timing edge is a falling edge. An OR combination can be used when the timing edge is a rising edge.

[0024] The master device receives the received signal or slave signal via receiver interface 206. Selectable filter circuitry 240 processes the received signal to remove noise, and the received signal is provided to baud rate detection circuitry 250, which is coupled to data receiver 260. The use of baud rate detection circuitry 250 provides a more robust system because, although the master device sets the baud rate and may not need to directly recover it, baud rate detector 250 compensates for latency in the communication path between the slave device and the master device, and also supports communication with slave devices that do not use the baud rate set by the master device. The implementation of baud rate detection circuitry 250 can vary depending on the baud rate. When the baud rate is much lower than the clock capability of the device technology (e.g., a maximum clock rate of 200 MHz and a baud rate of 20 Mbits / s), a clock implementation can be selected. When the ratio is not so high, a synchronous implementation (e.g., a delay-based DLL), similar to the implementation of high-speed memory interfaces (e.g., DDR, DDR2, etc.), can be selected. The data receiver 260 detects data in the slave signal based on the timing of the data edge in the slave signal relative to the timing edge / baud rate detected by the baud rate detection circuit device 250.

[0025] The slave device includes, as described above with reference to the master device, an analog filter circuit 240, a baud rate detection circuit 250, a data receiver 260, a data transmitter, and an edge combination circuit 230. For brevity, the functions of these blocks will not be repeated. The slave device includes a path for transmitting the received signal or the master signal to the edge combination circuit 230. This path allows the slave device to operate in a "transparent" mode, where the slave device transmits a signal (output by the data transmitter 220) with a constant transparency value. When combined with the received signal, this transparency value simply allows the received signal to pass through the slave device without any processing or modification by the slave device. When multiple slave devices are included in the reference... Figure 6 and Figure 7 This transparent operating mode is beneficial when discussing the chain. In system 200, the slave device does not include baud rate generation circuitry because the master device defines the baud rates for the uplink and downlink channels, and the slave device uses the timing edges in the received signal to recover that timing.

[0026] Figure 3 A communication system 300 is shown, wherein a slave device includes a baud rate generation circuit device 310, which functions similarly to... Figure 2The baud rate generation circuitry 210. The baud rate can be determined based on the baud rate used by the master device (e.g., via a PLL). The slave device does not include a path to transmit the received signal to the edge combination circuitry 330. Therefore, the slave device generates both timing edges (based on the independent slave device baud rate) and data edges in the slave signals sent by the slave device.

[0027] Figure 4 Example timing diagram 400 for master write mode operation is shown when the timing edge is a falling edge and the data edge is a rising edge. The master signal transmitted by the master device (transmitter output) delivers timing edges at equal intervals (here: 1 bit time), and the data edges have timings based on the data value to be transmitted. A minimum 0 time should be observed to ensure that the receiver can correctly detect the expected timing edge. A minimum 1 time should also be observed to ensure correct detection of the data edge. The length of the minimum 0 time and the minimum 1 time depends on the technology and the implementation of the signal driver and receiver. The remaining bit time can be used to set the level for the output according to the desired data value or level.

[0028] The slave device / receiver defines its sampling point for the data at a defined time following the received timing edge. Delays due to signal propagation and the inherent speed of the components should be respected. In this example, the sampling point is set to approximately half the bit time, but the sampling time can be located at different positions within the bit time. If the transmitter / master baud rate changes (e.g., due to drift, aging, or temperature), the slave device / receiver can automatically adjust the sampling point accordingly to maintain the sampling at the same relative position with respect to the timing edge. Alternatively, if the slave device / receiver has a (fairly accurate) clock source, the delay time can remain similar even if the master / transmitter baud rate changes.

[0029] Figure 5 Example timing diagram 500 for master device read mode operation is shown when the timing edge is a falling edge and the data edge is a rising edge. Assume the master device has requested to read data from the slave device, and the slave device transmits the read data to the master device. The master device continues to provide timing edges in the master signal to allow synchronous operation. The read data provided by the slave device (i.e., the signal sent by the slave device) is used to modify the timing of the data edge in the master signal according to the bit value to be transmitted, while keeping the timing edge in the signal consistent with the timing edge in the master signal. To avoid interference between the data edge sent by the master device (to send a timing edge, the master device must also send a data edge) and the data edge sent by the slave device, the timing of the data edge is changed to read mode timing (t). RThe master device's read mode timing can be similar to (or close to) the timing used to send a 1-bit level (it looks like an idle bus, assuming a 1-bit level is an idle level).

[0030] The slave device can remain in transparent mode as long as it does not transmit its own data, where the slave device signal is equal to the received master device signal. Assume the master signal and the slave transmitted signal are connected via an edge-triggered combinational circuit (see...). Figures 2 to 3 The idle data level (the bits between slave device inputs and outputs are not modified) is 1. Therefore, Figure 2 The master device's data transmitter 220 outputs 1 when it is not outputting its own data. This occurs, for example, when the master device requests data from a slave device.

[0031] Figure 6 A communication system 600 is illustrated, in which multiple (e.g., two are shown, but there could be more) slave devices are daisy-chained and connected to a single master device. In this system, the slave devices can operate in transparent mode to directly output signals received from the previous device. When the master device sends a write data frame, all slave devices receive it almost simultaneously because timing is only increased by the propagation delay through the slave devices. The propagation delay may vary slowly with temperature or power supply voltage, but there is no jitter between frames.

[0032] If the master device has issued a command to write a frame to request data from one of the slave devices, the master device can output a bit stream with read mode timing, and the selected slave device can modify the data stream according to the data to be transmitted. Any slave device that has not received a data request remains in transparent mode and does not modify the data stream. Even if the selected slave device needs some time to react and transmit data on the bus, the master device can continue to output read mode signals while waiting for an acknowledgment.

[0033] A favorable way to indicate the start of a new data frame (for writing and reading data) is to use signaling similar to a UART protocol. If there is no data transmission, bit timing appears as sending a permanent 1 data bit level (idle bit level) on the bus. A first 0 data level indicates that a new data frame has started (SOF = Start of Frame Indication), followed by a defined number of data bits. After the last bit, a stop bit, represented by a 1 data bit level, can be introduced (similar to a typical UART protocol). In other examples, an alternative encoding scheme can be chosen (e.g., with opposite data levels). Other encoding schemes are also possible. UART requires relatively low implementation effort and has a good ratio between data payload and control overhead. The fact that edge-tied communication is self-synchronizing allows for relatively long UART-like data frames (e.g., with 32 bits or more of data payload).

[0034] In many automotive applications, 32-bit wide SPI frames are used for communication between two devices (e.g., a microcontroller and a power control device). The proposed interface can replace the SPI interface in these applications, especially when the SPI baud rate is at its limit (typically no more than a 10MHz shift clock rate for general-purpose pins; higher baud rates are possible, but require more dedicated pins).

[0035] An enumeration process can be used after power-on (e.g., if a slave device forgets its name and its position in the chain when not powered on). This process can occur as follows: A signal including data corresponding to the "first contact" message is sent by the master device, and all slave devices are in transparent mode. The data sent by the master device is eventually received back by the master device, indicating that the chain is intact and the slave devices are powered on and operational. The master device then sends data corresponding to the enumeration request. When the slave device receives this request, it will deactivate its data transmitter.

[0036] The master device then sends a naming message, which may include a name or identifier encoded in the message. The message is received by the first slave device in the chain but not forwarded. If the naming message includes a name or identifier, the first slave device in the chain then adopts that name or identifier. The first slave device in the chain enables its transmitter to acknowledge the name or identifier by adjusting the data edge of the signal. Alternatively, the name or identifier may be encoded in the first slave device in the chain, and in this case, the first slave device in the chain sends the name or identifier back to the master device by adjusting the data edge of the signal. In either case, the newly named slave device then enters transparent mode, making it possible to name the next slave device in the chain. Once the master device receives the unacknowledged naming message, the enumeration is complete. The enumeration process may terminate due to corruption if a timeout criterion (in either the slave device or the master device) is met. In the enumeration process described above, when in transparent mode, as mentioned above, slave devices directly forward the signals they receive. Only one slave device is intended to send its data after the master device requests to read the data. Therefore, only one data word circulates in the chain of slave devices at a time.

[0037] Figure 7 An example communication system 700 is illustrated, which offers several advantages over system 600, namely that multiple data words can circulate simultaneously in the chain. The slave device "directly" forwards the timing edges of the received signals to ensure that synchronization operation is not jittered due to synchronization effects from one device to another. In system 700, the slave device includes a path or mechanism for directly providing received data, detected by data receiver 765, to data transmitter 725. Thus, the slave data transmitter 725 receives data from data receiver 765 or from the slave device's internal processing unit (not shown). In this way, the slave device can receive data from its input in the data receiver and can transmit other data in parallel via its data transmitter 725.

[0038] If the data receiver 765 has received a complete data word, it can directly hand it over to the data transmitter 725 for transmission to the next device (e.g., if the data word is not targeted at a slave device). Alternatively, the data receiver 765 can store the data word, and the slave device can process the word internally (e.g., when the data word is targeted at a slave device). Depending on the content of the received data word, the slave device can modify the received data before retransmitting it (e.g., instructing the slave device to have received the data correctly), or the slave device can send other data (e.g., after a read request from the master device). Therefore, more than one data word can cycle through the chain of slave devices at a time. This approach involves finer bit timing and the possibility of modifying the content of data bits.

[0039] Figure 8 It shows that it can achieve Figure 7 Example slave device 804, which describes the functionality described herein. Slave device 804 includes an edge combination circuit device 830 that functions to “remove” data edges from the received signal and add data edges from the data transmitter 825, while retaining timing edges from the received signal. Figure 9 A timing diagram 900 is shown to help describe the functionality of slave device 804. Minimum 0 and minimum 1 times should be observed to ensure that the self-synchronization mechanism with timing edges operates without jitter due to interference from the device's internal clock or settings.

[0040] To modify received data bits to have a value of 0, an AND function with a mask M0 (a mask to force 0 bits) can be used to generate an intermediate result. The mask M0 can include a timing point t. 0S (Starting time 0) and t 0E The idle level of M0 is 0 between the time (end of 0) and the time (otherwise the idle level of M0 is 1). To modify the received data bits to have a value of 1, a logical OR function with a mask M1 (a mask to force a data value of 1) and an intermediate result can be used. The mask M1 may include the time point t. 1S (Starting time) and t 1E The level is 1 between (the end time of 1) and otherwise the idle level of M1 is 0.

[0041] To set the timing, it is equally important to adhere to the sampling timing. The sampling time should take into account factors such as propagation delay and settling time. To ensure that only one timing edge and one data edge occur within a single bit of time, the timing points for activating and deactivating the mask should be carefully selected. The starting point t of M0... 0S This should happen before the minimum zero time ends, because some other devices might just be emitting a 1 level after the minimum zero time ends. If t 0S If it occurs after the minimum 0 time, there is a risk of a short 1 level. If mask M1 is at point t... 1S Starting too early risks making the minimum zero time too short. A similar effect defines the endpoint t of mask M1. 1E The position of the mask M1 should be ensured here. It must be kept active until the minimum 1 time is reached, and mask M0 should be deactivated before the minimum 1 time begins (to avoid 0-level spikes or excessively short minimum 1 times). Typically, the timing of mask M0 (relative to the first timing edge) is earlier than the timing of mask M1. If this is the case and the minimum 0 and minimum 1 times are adhered to, each slave device in the chain can modify its output data independently of the other slave devices.

[0042] If a communication protocol similar to UART is used (such as...) Figure 10 As shown in the diagram (e.g., using the Start of Frame (SOF) bit as the start of a data frame and the Stop bit as the end of a data frame), an inter-frame idle time can be defined to allow for smooth processing (e.g., decoding the received data before outputting the requested read data with the next output data frame). This inter-frame idle time can include several bit times to allow for a certain response time for the device. Even if the transmission of several data frames between several communication devices does not start and end simultaneously (e.g., the SOF bits of the frames do not occur within the same bit time), the bit times themselves are synchronized with each other due to timing edges.

[0043] Figure 11 A flowchart illustrating an example method 1100 for performing communication using edge timing is shown, which also supports slave devices in a daisy-chain topology. At 1110, the method includes receiving a first signal on a first signal line, the first signal having a first timing edge and a first data edge. The first timing edge is of a different type than the first data edge. The first data edge is an edge immediately adjacent to the first timing edge and occurs after a first elapsed time following the first timing edge. At 1120, the method includes sampling the first signal for a predetermined sampling time after the first timing edge to determine a first data value. At 1130, a second data value is determined and a second signal having a second timing edge and a second data edge is generated. A second elapsed time between the second timing edge and the second data edge encodes the second data value. At 1150, the second signal is transmitted on the second signal line.

[0044] As can be seen from the above description, the described system, circuit device, and method transmit data by using the timing of one type of edge in a signal relative to another type of edge, thereby enabling data communication between two or more devices.

[0045] Although the invention has been described and illustrated with respect to one or more implementations, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components or structures (components, devices, circuits, circuit arrangements, systems, etc.), unless otherwise stated, the terminology used to describe such components (including references to “means”) is intended to correspond to any component or structure that performs the specified function of said component (e.g., i.e., functionally identical), even if structurally different from the disclosed structure, which performs the function in the exemplary implementations of the invention shown herein.

[0046] Examples may include subjects such as methods or means for performing actions or blocks of the method; at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform actions of the methods according to the embodiments and examples described herein or of means or systems for performing communication using edge timing.

[0047] Example 1 is a method comprising receiving a first signal on a first signal line, the first signal having a first timing edge and a first data edge. The first timing edge and the first data edge are of different types, and the first data edge is an edge immediately adjacent to the first timing edge and occurs after a first elapsed time following the first timing edge. The method comprises sampling the first signal for a predetermined sampling time after the first timing edge to determine a first data value. A second data value is determined, and a second signal having a second timing edge and a second data edge is generated. A second elapsed time between the second timing edge and the second data edge encodes the second data value. The second signal is transmitted on the second signal line.

[0048] Example 2 is a communication device configured to receive a first signal and transmit a second signal. The first signal has a first timing edge immediately following a first data edge after a first elapsed time, and the second signal has a second timing edge immediately following a second data edge after a second elapsed time. The communication device includes a baud rate detection circuit, a data receiver, a data transmitter, and an edge combination circuit. The baud rate detection circuit is coupled to a receiver interface and configured to detect the first timing edge in the received first signal. The data receiver is configured to sample the first signal at a predetermined sampling time after each detected first timing edge to determine an encoded first data value. The data transmitter is configured to determine a second data value at an elapsed time after a corresponding second timing edge, the second data value being used to transmit and generate a transmit signal including the second data edge, such that the elapsed time encodes the second data value. The edge combination circuit is configured to combine the transmit signal with a timing signal including the second timing edge.

[0049] Example 3 is a communication system comprising a chain of slave devices and a master device. Each slave device is configured to: receive a signal having a timing edge and a data edge; determine data based on the elapsed time between the timing edge and the data edge; generate a slave signal by combining the received signal with a slave transmit signal, wherein the slave signal includes a timing edge and a slave data edge, wherein the elapsed time between the timing edge and the slave data edge encodes the slave data; and transmit the slave signal to the next device. The master device is configured to generate a master transmit signal having a timing edge and a master data edge, wherein a first elapsed time between the timing edge and the master data edge encodes the master data; transmit the master transmit signal to the first slave device in the chain of slave devices; receive a slave signal from the last slave device in the chain of slave devices, wherein the slave signal has a timing edge and a slave data edge; and determine slave data based on the elapsed time between the timing edge and the slave data edge.

[0050] The description of one or more implementations above provides illustration and description, but is not intended to be exhaustive or to limit the scope of the exemplary embodiments to the precise forms disclosed. Modifications and variations are possible in accordance with the above teachings, or can be obtained from the practice of various implementations of the exemplary embodiments.

[0051] The various illustrative logics, logic blocks, modules, circuit devices, and circuits described in connection with the aspects disclosed herein can be implemented or performed by any combination of general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or designs thereof for performing the functions described herein. The general-purpose processor may be a microprocessor; however, alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine.

[0052] The above description of the embodiments shown in this disclosure, including the content described in the abstract, is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. Although specific embodiments and examples have been described herein for illustrative purposes, various modifications are possible within the scope of such embodiments and examples, as will be recognized by those skilled in the art.

[0053] In this regard, although the disclosed subject matter has been described in conjunction with various embodiments and corresponding drawings, it should be understood where applicable that other similar embodiments may be used, or modifications and additions may be made to the described embodiments to perform the same, similar, alternative, or substitute functions of the disclosed subject matter without departing from the disclosed subject matter. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but should be interpreted broadly and comprehensively in accordance with the appended claims.

[0054] In this disclosure, the same reference numerals are used to denote the same elements, and the structures and devices shown are not necessarily drawn to scale. As used herein, the terms “module,” “component,” “system,” “circuit,” “circuit device,” “element,” “piece,” etc., are intended to denote computer-related entities, hardware, software (e.g., in execution), and / or firmware. For example, a circuit device or similar term can be a processor, a process running on a processor, a controller, an object, an executable program, a storage device, and / or a computer having processing equipment. For instance, an application running on a server and a server can also be a circuit device. One or more circuit devices may reside in a process, and circuit devices may be located on one computer and / or distributed among two or more computers. This document may describe a group of elements or a group of other circuit devices, wherein the term “group” can be interpreted as “one or more.”

[0055] As another example, a circuit device, or similar term, can be a device having specific functions provided by mechanical components operated by electrical or electronic circuitry, wherein the electrical or electronic circuitry can be operated by a software application or firmware application executed by one or more processors. The one or more processors can be internal or external to the device and can execute at least a portion of the software or firmware application. As another example, a circuit device can be a device that provides specific functions through electronic components without mechanical components; the electronic components may include field gates, logic components, hardware-coded logic, register transfer logic, and one or more processors to execute software and / or firmware that at least partially endows the electronic components with functionality.

[0056] It should be understood that when a component is described as being "electrically connected" or "electrically coupled" to another component, it can be physically connected or coupled to the other component, allowing current and / or electromagnetic radiation to flow along the conductive path formed by these components. When components are described as being electrically coupled or connected to each other, there can be conductive, inductive, or capacitive elements between the component and the other component. Furthermore, when electrically coupled or connected to each other, a component can induce voltage or current flow or electromagnetic wave propagation in the other component without physical contact or intervention of the components. Additionally, when voltage, current, or signal is described as being "applied" to a component, the voltage, current, or signal can be conducted to the component through capacitive, electromagnetic, or inductive coupling, whether or not involving physical connection.

[0057] The exemplary use of words is intended to present concepts in a concrete manner. The terms used herein are for the purpose of describing particular examples only and are not intended to limit the examples. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms “comprising,” “including,” “containing,” and / or “comprising”, when used herein, refer to the presence of the stated feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

Claims

1. A method for communication, comprising using a second device: A first signal is received from a first device on a first signal line, wherein the first signal has a first timing edge and a first data edge, wherein the first timing edge is of a different type from the first data edge, and further, wherein the first data edge is an edge that is immediately adjacent to the first timing edge and occurs after a first elapsed time following the first timing edge. The first signal is sampled at a predetermined sampling time after the first timing edge to determine the first data value; The second data value that is to be sent to the third device; Generate a second signal having a second timing edge and a second data edge, wherein a second elapsed time between the second timing edge and the second data edge encodes the second data value; and The second signal is transmitted to the third device on the second signal line.

2. The method according to claim 1, further comprising generating the second signal by the following step: Generate and transmit signals; and Combine the first signal with the transmitted signal. The transmitted signal includes a second data edge at a second elapsed time following the first timing edge, such that when the transmitted signal is combined with the first signal, the second signal includes: i) the second timing edge that coincides with the first timing edge, and ii) the second data edge.

3. The method according to claim 1, further comprising generating the second signal by the following step: Generate and transmit signals; and Combine the first signal with the transmitted signal. The transmitted signal includes a transparency value, which, when combined with the first signal, generates a second signal identical to the first signal, such that the second timing edge and the second data edge coincide with the first timing edge and the first data edge, respectively.

4. The method according to claim 1, further comprising generating the second signal by the following step: Generate and send signal; Generate a timing signal having the second timing edge; and Combine the timing signal with the transmission signal. The transmitted signal includes: The second data edge at the second elapsed time after the second timing edge, or The second data edge occurs at a third elapsed time following the second timing edge, wherein the third elapsed time encodes the first data value. This ensures that when the transmit signal is combined with the timing signal, the second signal includes the second timing edge and the second data edge.

5. The method according to claim 4, further comprising generating the timing signal based on the first signal.

6. The method of claim 1, further comprising generating the second signal by the following step: Generate and transmit signals; and Combine the first signal with the transmitted signal. The transmitted signal includes: The second data edge at the second elapsed time following the first timing edge, or The second data edge at the first elapsed time following the first timing edge. When the transmitted signal is combined with the first signal, the second signal includes: i) a second timing edge that coincides with the first timing edge, and ii) a second data edge.

7. The method according to claim 6, wherein: The transmitted signal includes: 0-bit value transmission signal, wherein the 0-bit value transmission signal includes: A constant level 1 signal when the second data value is 1, or a 0 mask signal when the second data value is 0; and A 1-bit value transmission signal, wherein the 1-bit value transmission signal includes: A constant signal at level 0 when the second data value is 0, or a mask signal at level 1 when the second data value is 1; and Generating the second signal includes: Perform an AND operation between the first signal and the 0-bit value transmission signal to generate an intermediate result signal; and The intermediate result signal is ORed with the 1-bit value transmission signal to generate the second signal.

8. The method according to claim 1, wherein: The first signal includes a readout mode signal having a series of equally spaced first timing edges and first data edges; Generating the second signal includes: Generate a transmit signal having a second data edge at a second elapsed time following the first timing edge; and The first signal is combined with the transmitted signal such that when the transmitted signal is combined with the first signal, the second signal includes: i) a second timing edge that coincides with the first timing edge and ii) a second data edge.

9. The method of claim 1, wherein the predetermined sampling time is selected to fall within a sampling interval of the signal period of the first signal, wherein the sampling interval begins at a first predetermined time after the timing edge and ends at a second predetermined time before a subsequent timing edge.

10. The method according to claim 1, comprising: Using the third device: The identifier is the third data value to be sent to the fourth device; A third signal is generated having a third timing edge and a third data edge, wherein a third elapsed time between the third timing edge and the third data edge encodes the third data value; as well as The third signal is transmitted to the fourth device on the third signal line.

11. The method according to claim 1, further comprising: Determine if data has been requested; When data is requested, a second signal with the second data edge is generated, wherein the second elapsed time encodes the value of the requested data; as well as When data is not requested, a second signal is generated having a second data edge that coincides with the first data edge.

12. A second communication device configured to receive a first signal from a first device and transmit a second signal, the first signal having a first timing edge immediately following a first data edge after a first elapsed time, the second signal having a second timing edge immediately following a second data edge after a second elapsed time, the second communication device comprising: A baud rate detection circuit is coupled to a receiver interface, wherein the baud rate detection circuit is configured to detect the first timing edge in a received first signal. A data receiver is configured to sample the first signal at a predetermined sampling time after each detected first timing edge to determine an encoded first data value; as well as The data transmitter is configured as follows: The identifier is a second data value used to be sent to a third device; as well as A transmission signal is generated, the transmission signal including a second data edge at an elapsed time following the corresponding second timing edge, wherein the elapsed time encodes the second data value; as well as An edge-combining circuit device is configured to combine the transmitted signal with a timing signal including a second timing edge.

13. The second communication device according to claim 12, wherein the timing signal includes the first signal, such that the second timing edge coincides with the corresponding first timing edge.

14. The second communication device of claim 12, further comprising a baud rate generation circuit configured to generate the timing signal, wherein the timing signal includes the second timing edge.

15. The second communication device of claim 14, wherein the baud rate generation circuit is configured to generate the timing signal based on the first signal.

16. The second communication device of claim 14, wherein the edge combination circuit means is configured to perform a logical AND operation on the transmitted signal and the timing signal.

17. The second communication device of claim 14, wherein the edge combination circuit means is configured to perform a logic OR operation on the transmitted signal and the timing signal.

18. The second communication device of claim 12, wherein the data transmitter circuitry is configured to operate in a write mode or a transparent mode, and wherein the data transmitter circuitry is configured to: When in write mode, a second data edge is generated in the transmit signal at a second elapsed time after the first timing edge, such that when the transmit signal is combined with the first signal, the second signal includes: i) the second timing edge that coincides with the first timing edge, and ii) the second data edge, and In transparent mode, the transmit signal is generated to have a constant transparency value, which, when combined with the first signal, generates a second signal identical to the first signal, such that the second timing edge and the second data edge coincide with the first timing edge and the first data edge, respectively.

19. The second communication device according to claim 12, wherein the data transmitter is configured to operate in a write mode or a transparent mode, further wherein the data transmitter is configured to: When in write mode, the second data edge is generated in the transmit signal at the second elapsed time after the second timing edge, and In transparent mode, the second data edge is generated in the transmitted signal at a third elapsed time after the second timing edge, wherein the third elapsed time encodes the first data value. This ensures that when the transmit signal is combined with the timing signal, the second signal includes the second timing edge and the second data edge.

20. A communication system, comprising: A chain of slave devices, where each slave device is configured as follows: Receives signals with timing edges and data edges; The data is determined based on the elapsed time between the timing edge and the data edge; A slave signal is generated by combining a received signal with a slave transmitted signal, wherein the slave signal includes a timing edge and a slave data edge, and the elapsed time between the timing edge and the slave data edge encodes the slave data. as well as Send the subordinate signal to the next device; as well as The master device is configured as follows: A main transmit signal is generated having the timing edge and the main data edge, wherein the first elapsed time between the timing edge and the main data edge encodes the main data; The master transmission signal is sent to the first slave device in the chain of slave devices; Receive a slave signal from the last slave device in the chain of slave devices, wherein the slave signal has the timing edge and the slave data edge; as well as The dependent data is determined based on the elapsed time between the timing edge and the dependent data edge.

21. The communication system of claim 20, wherein each slave device is configured to operate in a write mode or a transparent mode such that: When in the write mode, the slave device generates the slave data edge in the slave signal at a first elapsed time after the timing edge, the first elapsed time encoding the slave data; and In the transparent mode, the slave device generates the slave data edge in the slave signal at a second elapsed time after the timing edge, the second elapsed time encoding the data determined from the received signal.

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