Two-level hybrid memory buffer for multiple streams

Abstract

Embodiments of a two-level hybrid memory buffer for multiple streams in a memory subsystem are described herein. A processing device determines that first write data of a first stream stored in a host buffer component satisfies a threshold for programming a first programming unit. The processing device transfers the first write data from the host buffer component to a staging buffer component, and writes the first write data from the staging buffer component to a first die of a plurality of non-volatile memory NVM dies as the first programming unit. The processing device determines that second write data of a second stream satisfies a threshold for programming a second programming unit, transfers the second write data from the host buffer component to the staging buffer component, and writes the second write data from the staging buffer component to a second die of the plurality of NVM dies as the second programming unit.

Description

Technical Field

[0001] Embodiments of the present invention relate generally to memory subsystems, and more particularly, to a two-level hybrid memory buffer for multiple streams in a memory subsystem. Background Art

[0002] The memory subsystem may be a storage system such as a solid state drive (SSD), and may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present invention will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present invention.

[0004] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the invention is described.

[0005] Figure 2 is a flow chart of an example method of buffering write data for multiple streams from a host system in a two-level memory buffer according to some embodiments of the present invention.

[0006] Figure 3 is a flow chart of an example method of buffering write data and redundant array of independent NAND (RAIN) data in a two-level memory buffer according to some embodiments of the present invention.

[0007] Figure 4 is a flow chart of writing data, obsolete collection data, and RAIN data from multiple streams using a two-level memory buffer according to some embodiments of the present invention.

[0008] Figure 5 is a diagram illustrating eight streams striped across eight channels to a spare die according to some embodiments of the present invention.

[0009] Figure 6 is a diagram illustrating a staging buffer for programming four streams on a single channel according to some embodiments of the present invention.

[0010] Figure 7 is a diagram illustrating a sequence with program operations completed simultaneously across all eight channels according to some embodiments of the present invention.

[0011] Figure 8 is a block diagram of an example computer system in which embodiments of the present invention may operate. DETAILED DESCRIPTION

[0012] Aspects of the present invention relate to a two-stage hybrid memory buffer for multiple streams in a memory subsystem. The memory subsystem is also referred to as a "memory device" or "memory system" hereinafter. An example of a memory subsystem is a storage system, such as a solid state drive (SSD). The memory subsystem may be a hybrid memory / storage subsystem. In general, a host system may utilize a memory subsystem that includes one or more memory components. The memory device may include a non-volatile memory device, such as, for example, a NAND. The host system may provide data stored at the memory subsystem and may request data retrieved from the memory subsystem.

[0013] Conventional memory subsystems use a single write data stream to communicate with the host system. This conventional memory subsystem uses a buffer for data that passes through the NAND controller to the NAND flash memory. The buffer is usually an external dynamic random access memory (DRAM) or an internal on-chip static RAM (SRAM or internal SRAM). The NAND controller obtains the write data from a single stream received from the host and gathers the write data in the external DRAM or gathers the write data in the internal SRAM until there is enough data to send to the NAND flash for programming. When the stored data meets (reaches or exceeds) the programming unit (PU) threshold, there is enough data, where the PU threshold corresponds to the programming unit size of one or more NVM devices. The internal SRAM must support the full bandwidth of the backend and the host. SRAM supplies the highest possible bandwidth at a high cost for performance, and DRAM significantly reduces costs but also reduces performance. When multiple streams are used, problems arise in conventional memory subsystems. In some cases, the memory subsystem is required to support 32 streams and may be increased to even 1024 streams. However, the memory subsystem needs to support all of these different streams being opened and running at the same time, whether the host system is performing sequential writes (e.g., sequential access) or using random writes to randomly access different streams. Conventional memory subsystems with a single buffer (external DRAM or internal SRAM) cannot support a high number of streams with high performance (e.g., sequential writes or random writes). The size of the internal SRAM in these conventional memory subsystems must be large enough to store the data of all streams. Although SRAM has a higher bandwidth than DRAM, the cost of adding a larger internal SRAM to an integrated circuit of a single buffer is too high from the perspective of cost and die area and power. Using DRAM will be cheaper and provide large memory capacity, and performance will be limited by the bandwidth of DRAM. Although a wider DRAM interface can increase DRAM bandwidth, increasing the DRAM interface will increase the cost and power of the integrated circuit and make it more difficult to adapt to small form factors such as M.2 or EDSFF 1UShort.

[0014] Aspects of the present invention address the above and other shortcomings by providing a two-level hybrid memory buffer for supporting multiple streams. The two-level memory buffer may include a host buffer component (e.g., external DRAM) and a staging buffer component (e.g., internal SRAM). The host buffer component may be the main buffer for all data, while the staging buffer component (which may be an on-chip SRAM) may staging the data buffer of the stream before it is written to the NVM memory component of the memory subsystem. Data from the host programming stream may be kept separate into individual programming units (PUs) in the host buffer component (primary buffer) until there is enough data to program the NVM device (e.g., NVM die, flash device, or the like). When the amount of data meets a threshold, there is enough data or there is sufficient data. At that time, the data in the PU may flow to the staging buffer component (e.g., internal SRAM), where the data will be processed with error protection and other features in preparation for writing to the NVM memory. The data in the PU will have a much shorter lifespan in the staging buffer component than the host buffer component. Then, the NVM controller sends the data from the staging buffer component to the NVM device (e.g., flash device). The two-level memory buffer supports streams and allows the memory subsystem to expand the number of streams, such as 32 streams, 64 streams, 128 streams, 512 streams, 1024 streams, etc.

[0015] For example, the host system may communicate with the memory subsystem via a high-speed serial computer bus standard, such as the Peripheral Component Interconnect Express (PCIe) standard or NVM Express (NVMe) using the electrical interface of PCIe. NVMe is an open logical device interface specification for accessing non-volatile storage media attached via an electrical bus. NVMe for solid-state storage devices has low latency and internal parallelism. Multiple streams are part of the NVMe standard, and it is expected that the number of streams supported by the memory subsystem will expand, for example, from 32 streams to 1024 streams. Two-level memory buffers (a mix of DRAM and internal SRAM) support multiple streams (e.g., multiple NVMe streams) and scalability of the number of streams. As the streams begin to expand, the hierarchical buffer component can support more and more NVMe streams while keeping the cost relatively low and meeting the performance and form factor requirements. The hierarchical buffer component stages the data of the back end and all the high bandwidth required to keep the back end running at full efficiency.

[0016] Streams provide a way for a host system to identify different accesses to a memory subsystem, whether it is for read or write access. Streams are separate from each other, and each stream can be considered to be available for a specific host task or application. When the host system uses the memory subsystem to store data, the host system combines all of its data. If the host system can provide a large amount of data for various applications or tasks, the storage medium can be more efficient. Although the data may appear randomly, the host system can identify the data into these different streams and the memory subsystem can put the corresponding data of different streams together in different locations in the NVM backend. Write amplification is an undesirable phenomenon associated with flash memory and SSDs, in which the actual amount of information physically written to the storage medium is a multiple of the logical amount that is intended to be written. Streams can reduce write amplification. When data is stored as a stream, the memory subsystem can easily remove data for a specific stream. For example, the host system may decide to delete a stream, and the memory subsystem can eliminate that data.

[0017] Aspects of the present invention address the above and other shortcomings by buffering RAIN data in two levels of memory buffers. The RAIN parity data for each of these multiple streams can add up in size, and the two levels of memory buffers can store the RAIN data for these multiple streams in a host buffer component and temporarily in a staging buffer component. Intelligence is added to a controller to manage the staging host buffer component and the staging buffer component of the two levels of memory buffers. The controller can use, for example, firmware to control the use of the staging area and manage the data flow, including managing die conflicts in NVM dies (flash devices).

[0018] Figure 1 An example computing environment 100 including a memory subsystem 110 is described according to some embodiments of the present invention. The memory subsystem 110 may include media, such as memory components 112A-112N. The memory components 112A-112N may be volatile memory components, non-volatile memory components, or a combination of such components. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem. In general, the computing environment 100 may include a host system 120 that uses the memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0019] The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing device that includes a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110, so that the host system 120 can read data from the memory subsystem 110 or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc. Examples of physical host interfaces include (but are not limited to) a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access the memory components 112A to 112N. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0020] Memory components 112A to 112N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND-type flash memory. Each of memory components 112A to 112N may include one or more memory cell arrays, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., three-level cells (TLC) or four-level cells (QLC)). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of a memory cell. Each of the memory cells may store one or more data bits (e.g., data blocks) used by the host system 120. Although non-volatile memory components such as NAND-type flash memory are described, memory components 112A to 112N may be based on any other type of memory such as volatile memory. In some embodiments, memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), or non-OR flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point non-volatile memory cell arrays. Cross-point non-volatile memory arrays may perform bit storage based on body resistance changes along with a stacked cross-gate data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memories may perform write-in-place operations, where non-volatile memory cells may be programmed without first erasing the non-volatile memory cells. Furthermore, the memory cells of memory components 112A to 112N may be grouped into memory cell groups, word lines, word line groups, or data blocks, which may refer to units of memory components used to store data.

[0021] The memory system controller 115 (hereinafter referred to as "controller") can communicate with the memory components 112A to 112N to perform operations, such as reading data, writing data, or erasing data at the memory components 112A to 112N and other such operations. The controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, a two-level memory buffer 119, or a combination thereof. The two-level memory buffer 119 may include a local memory 119A and an external memory 119B. In one embodiment, the local memory 119A has one or more SRAM devices or SRAM components, and the external memory 119B has one or more DRAM devices or DRAM components. In other embodiments, the local memory 119A may have other types of memory devices, including DRAM devices. It should be noted that on-chip memory devices are more expensive than external memory devices. The controller 115 may be an SSD controller that manages the hierarchical host buffer components and the hierarchical buffer components of the two-level memory buffer 119. The SSD controller 115 may use, for example, firmware to have intelligence on how to use staging areas and how to manage data flows, including managing die conflicts in NVM dies (flash devices). The controller 115 may be a microcontroller, a dedicated logic circuit system (such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119A. The local memory 119 used to store instructions may be the same or different from the local memory used for the dual-state memory buffer 119. In the illustrative example, the local memory 119A of the controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communications between the memory subsystem 110 and the host system 120). In some embodiments, the local memory 119A may include memory registers for storing memory pointers, extracting data, etc. The local memory 119A may also include a read-only memory (ROM) for storing microcode. Although it has been described, the local memory 119A of the controller 115 is not limited to the local memory 119A. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a controller 115, but in another embodiment of the present invention, the memory subsystem 110 may not include the controller 115, but may rely on external control (eg, provided by an external host or by a processor or controller separate from the memory subsystem).

[0022] In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory components 112A to 112N. The controller 115 may further include a host interface circuit system that communicates with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory components 112A to 112N, and convert responses associated with the memory components 112A to 112N into information for the host system 120.

[0023] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., a DRAM) and address circuitry (e.g., a row decoder and a column decoder) that may receive addresses from the controller 115 and decode the addresses to access the memory components 112A-112N.

[0024] The memory subsystem 110 includes two levels of memory buffers 119 (local memory 119A and external memory 119B) and a two-level buffer controller component 113 that can be used to control data transfer between the host system 120, the two-level component buffers 119, and the memory components 112A to 112N. In some cases, the external memory 119B can be implemented as one of the memory components 112A to 112N, and another or more of the memory components 112A to 112N can be NVM components. In some embodiments, the controller 115 includes at least a portion of the two-level buffer controller component 113. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119A to perform the operations described herein. In some embodiments, the two-level buffer controller component 113 is part of the host system 120, an application, or an operating system.

[0025] The two-stage buffer controller component 113 may determine that the first write data of the first stream stored in the external memory 119B (also referred to herein as the host buffer component) meets the threshold for programming the first programming unit. The size of the first programming unit corresponds to the programming unit size of the NVM die (e.g., the memory component 112A). The two-stage buffer controller component 113 transmits the first write data to the local memory 119A (also referred to herein as the staging buffer component). The two-stage buffer controller component 113 writes the first write data from the local memory 119A (staging buffer component) to the memory component 112A (e.g., the first NVM die) as the first programming unit. The two-stage buffer controller component 113 determines that the second write data of the second stream stored in the external memory 119B (host buffer component) meets the threshold for programming the second programming unit. The two-stage buffer controller component 113 transmits the second write data from the external memory 119B (host buffer component) to the local memory 119A (staging buffer component). Two-stage buffer controller component 113 writes second write data from local memory 119A (staging buffer component) as a second programming unit to a second memory component (eg, a second NVM die in memory component 112A or another NVM die in another memory component 112B-N).

[0026] Figure 2 2 is a flow chart of an example method 200 for buffering write data from multiple streams of a host system in a two-level memory buffer according to some embodiments of the present invention. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1 The memory two-stage buffer controller component 113 is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the processes can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0027] At block 210, processing logic determines that first write data of a first stream stored in a host buffer component satisfies a threshold for programming a first programming unit of an NVM die. It should be noted that the host can write to the individual streams in any order so that the programming unit size can be reached in any order. At block 220, processing logic transfers the first write data from the host buffer component to the staging buffer component. At block 230, processing logic writes the first write data from the staging buffer component to the first NVM die as a first programming unit. At block 240, processing logic determines that second write data of a second stream stored in the host buffer component satisfies a threshold for programming a second programming unit. At block 250, processing logic transfers the second write data from the host buffer component to the staging buffer component. At block 260, processing logic writes the second write data from the staging buffer component to the second NVM die as a second programming unit.

[0028] In another embodiment, processing logic generates first independent NAND redundant array (RAIN) data corresponding to first write data. Processing logic temporarily stores the first RAIN data in a hierarchical buffer component. Processing logic transmits the first RAIN data from the hierarchical buffer component to the host buffer component together with the first write data written to the first die as a first programming unit. The first RAIN data may be transmitted simultaneously or sequentially with the first write data written to the first NVM die. Processing logic generates second RAIN data corresponding to second write data. Processing logic temporarily stores the second RAIN data in the hierarchical buffer component. Processing logic transmits the second RAIN data from the hierarchical buffer component to the host buffer component together with the second write data written to the second die as a second programming unit. If there is still room, the RAIN data may remain in the hierarchical buffer component; otherwise, the RAIN data is to be placed back in the host buffer component if the host buffer component is not used to leave room for another stream of RAIN data. Similarly, the second RAIN data may be transmitted simultaneously or sequentially with the second write data written to the second NVM die.

[0029] In another embodiment, the processing logic stores first discarded item collection (GC) data corresponding to any stream in a host buffer component. Not all streams require GC, so if a first stream requires GC, then the first GC data may correspond to the first stream. Alternatively, the first GC data may correspond to a stream different from the first stream. As described herein, the order in which data is moved from the staging buffer component and the host buffer component depends on the host access through the host. The processing logic determines that the first GC data in the host buffer component meets a threshold for programming a third programming unit. The processing logic transfers the first GC data from the host buffer component to the staging buffer component. The processing logic writes the first GC data from the staging buffer component as a third programming unit to a third NVM die.

[0030] In another embodiment, processing logic causes the first write data to be encoded when transferred between the host buffer component and the staging buffer component. In another embodiment, processing logic stores the GC read data in the staging buffer component. The GC read data may be received from an NVM controller associated with one or more NVM dies. Processing logic transfers the GC read data from the staging buffer component to the host buffer component and decodes the GC read data when the GC read data is transferred from the staging buffer component to the host buffer component.

[0031] In some embodiments, the write data received from the host system is sequential write data. In other embodiments, the write data received from the host system is random write data.

[0032] Figure 3 1 is a flow chart of an example method 300 for buffering write data and RAIN data in a two-level memory buffer according to some embodiments of the present invention. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The memory two-stage buffer controller component 113 is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the processes can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0033] At box 310, processing logic determines that the first write data of the first stream stored in the host buffer component meets the threshold value of the first programming unit for programming the NVM die. The size of the first programming unit corresponds to the size of the NVM die. At box 320, processing logic transmits the first write data from the host buffer component to the hierarchical buffer component. At box 330, processing logic writes the first write data from the hierarchical buffer component to the first NVM die as the first programming unit. At box 340, processing logic generates first RAIN data corresponding to the first write data. At box 350, processing logic temporarily stores the first RAIN data in the hierarchical buffer component. It should be noted that the first RAIN data is transmitted to the hierarchical buffer component before or simultaneously with the first write data. At box 360, processing logic transmits the first RAIN data from the hierarchical buffer component to the host buffer component.

[0034] In another embodiment, processing logic determines that second write data of the second stream stored in the host buffer component satisfies a threshold for programming a second programming unit. Processing logic transmits the write data to the staging buffer component, generates second RAIN data corresponding to the second write data, and writes the second write data from the staging buffer component to the second NVM die as a second programming unit. Processing logic also temporarily stores the second RAIN data in the staging buffer component, and then transmits the second RAIN data from the staging buffer component to the host buffer component.

[0035] Figure 4 1 is a flow chart of a data flow of write data, obsolete collection data, and RAIN data from multiple streams using a two-level memory buffer according to some embodiments of the present invention. In the following description of the data flow, the host system 120 communicates with the SSD 400 via an electrical interface, and the SSD 400 includes an SSD controller 402 having a hierarchical buffer SRAM 406, an external DRAM component 404 (also referred to herein as a primary buffer component), and a flash device 408. The SSD controller 402 may be the same as described above with respect to Figure 1 The controller 115 described above may include firmware for controlling the interaction of these components for the data flows described below. The SSD controller 402 includes a RAIN exclusive OR (XOR) engine 410, a low density parity check (LDPC) encoder 412, an LDPC decoder 414, and a NAND controller 416. In other embodiments, the various components of the SSD controller 402 may be integrated into separate integrated circuits, such as a separate integrated circuit for the NAND controller 416. The hierarchical buffer SRAM may include multiple logical partitions, such as Figure 4In other embodiments, SSD 400 may be other types of memory subsystems and may have different types of memory for the primary buffer component and the staging buffer component. Also, the LDPC encoder and decoder may be other types of data protection encoders and data protection decoders. Furthermore, NAND controller 416 and flash device 408 may be other types of NVM controllers and NVM storage media.

[0036] In a first data stream 401, the host system 120 performs a sequential write operation 403 to store write data at the SSD 400. The write data may correspond to one or more streams. For example, the SSD 400 receives first write data 405 of the first stream, second write data 407 of the second stream, and the SSD controller 402 stores the first write data 405 and the second write data 407 separately in the DRAM component 404. The DRAM component 404 may be organized to store the first write data 405 in a programming unit (PU) buffer, where the size of the PU buffer corresponds to the die size of the flash device 408. Data from more than two streams may be received and stored in separate PU buffers in the DRAM component 404. When the SSD controller 402 determines that the first write data 405 of the first stream stored in the first PU buffer of the DRAM component 404 meets the threshold for programming the first programming unit (PU) (i.e., the PU buffer is filled with the first write data), the SSD controller 402 transfers the first write data 405 to the staging buffer SRAM 406. It should be noted that the first stream is the first one in the PU buffer that becomes full at this time, which can be any of the PU buffers, depending on the host. LDPC 412 encodes the first write data 405 before storing it in the staging buffer SRAM 406. That is, the first write data 405 flows to the LDPC encoder 412 and flows from the LDPC encoder 412 to the staging buffer SRAM 406. Since the first write data 405 is already one PU size, the SSD controller 402 can start programming one of the flash devices 408 using the PU corresponding to the first write data 405 stored in the staging buffer SRAM 406. The SSD controller 402 can send the first write data 405 to the NAND controller 416, or the NAND controller 416 can retrieve the first write data 405 from the staging buffer SRAM 406 to write the first write data 405 to the first device of the multiple flash devices 408.

[0037] As part of the first data stream 401, the SSD controller 402 may determine that the second write data 407 of the second stream stored in the second PU buffer in the DRAM component 404 meets the threshold for programming the second PU and transmit the second write data 407 to the staging buffer SRAM 406 via the LDPC encoder 412. The NAND controller 416 may write the second write data 407 from the staging buffer SRAM 406 as the second PU to a second flash device in the plurality of flash devices 408. The staging buffer SRAM 406 may be used as a pipeline for staging programming units for programming by the NAND controller 416. For example, once the first write data 405 is written to the flash device 408, the second write data 407 may be transmitted to the staging buffer SRAM 406 in a staggered manner. Data from more than two sequential write data streams may be received and stored in the staging buffer SRAM 406.

[0038] In some cases, parity information may be generated for sequentially writing data to the flash device 408. Figure 4 4, RAIN XOR engine 410 may receive first write data 407 from NAND controller 416 and may XOR first RAIN data 409 corresponding to first write data 405 with existing RAIN data. RAIN data is typically stored in DRAM and moved to staging buffer SRAM 406 with associated write data. First RAIN data 409 may be temporarily stored in staging buffer SRAM 406 before being transferred to DRAM component 404. This may be performed in conjunction with first write data 405 being written to a first flash device as a first programming unit. RAIN XOR engine 410 may receive second write data 407 from NAND controller 416 and generate second RAIN data 411 corresponding to second write data 407. Second RAIN data 411 may be temporarily stored in staging buffer SRAM 406 before being transferred to DRAM component 404. This may be performed in conjunction with second write data 407 being written to a second flash device as a second programming unit. Parity data from more than two streams may be generated and stored in staging buffer SRAM 406 and DRAM component 404 .

[0039] As described above with respect to first data stream 401, two levels of memory buffers may be used for sequential write data from sequential write data operation 403. In other embodiments, two levels of memory buffers may be used for random write data received from host system 120 in conjunction with random write operations, as illustrated as second data stream 421.

[0040] In the second data stream 421, the host system 120 performs a random write operation 423 to store the write data at the SSD 400. The random write data may correspond to one or more streams. For example, the SSD 400 receives the third write data 425 of the third stream, the fourth write data 427 of the fourth stream, and the SSD controller 402 stores the third write data 425 and the fourth write data 427 separately in the DRAM component 404. As described above, the DRAM component 404 may be organized to store data in a PU buffer, wherein the size of the PU buffer corresponds to the die size of the flash device 408. Data from more than two streams may be received and stored in separate PU buffers in the DRAM component 404. When the SSD controller 402 determines that the third write data 425 of the third stream stored in the third PU buffer of the DRAM component 404 meets the threshold for programming the third PU (i.e., the PU buffer is filled with the third write data), the SSD controller 402 transfers the third write data 425 to the staging buffer SRAM 406. Before storing the third write data 425 in the staging buffer SRAM 406, the LDPC encoder 412 encodes the third write data 425. That is, the third write data 425 flows to the LDPC encoder 412 and flows from the LDPC encoder 412 to the staging buffer SRAM 406. Since the third write data 425 is already one PU size, the SSD controller 402 can start programming one of the flash devices 408 using the PU corresponding to the third write data 425 stored in the staging buffer SRAM 406. The SSD controller 402 can send the third write data 425 to the NAND controller 416, or the NAND controller 416 can retrieve the third write data 425 from the staging buffer SRAM 406 to write the third write data 425 to a third device among the plurality of flash devices 408.

[0041] As part of the second data stream 421, the SSD controller 402 may determine that the fourth write data 427 of the second stream stored in the fourth PU buffer in the DRAM component 404 meets the threshold for programming the fourth PU and transmit the fourth write data 427 to the staging buffer SRAM 406 via the LDPC encoder 412. The NAND controller 416 may write the fourth write data 427 from the staging buffer SRAM 406 as the fourth PU to a fourth flash device in the plurality of flash devices 408. The staging buffer SRAM 406 may be used as a pipeline for staging programming units for programming by the NAND controller 416. For example, once the third write data 425 is written to the flash device 408, the fourth write data 427 may be transmitted to the staging buffer SRAM 406 in a staggered manner. Data from more than two random write data streams may be received and stored in the staging buffer SRAM 406.

[0042] In some cases, parity information may be generated for random write data written to the flash device 408. Figure 4 4, RAIN XOR engine 410 may receive third write data 427 from NAND controller 416 and generate third RAIN data 429 corresponding to third write data 425. Third RAIN data 429 may be temporarily stored in staging buffer SRAM 406 before being transferred to DRAM component 404. This may be performed in conjunction with third write data 425 being written to first flash device as a third programming unit. RAIN XOR engine 410 may receive fourth write data 427 from NAND controller 416 (or other NVM controller) and generate fourth RAIN data 431 corresponding to fourth write data 427. Fourth RAIN data 431 may be temporarily stored in staging buffer SRAM 406 before being transferred to DRAM component 404. This may be performed in conjunction with fourth write data 427 being written to fourth flash device as a fourth programming unit. Parity data from more than two streams may be generated and stored in staging buffer SRAM 406 and DRAM component 404.

[0043] As described above with respect to the first data stream 401 and the second data stream 421, the two-level memory buffer may be used for sequential write data from the sequential write data operation 403 and random write data from the random write data operation 423. In other embodiments, the two-level memory buffer may be used for read data received from the plurality of flash devices 408 before being sent to the host system 120, as illustrated as the third data stream 433.

[0044] In the third data stream 433, the NAND controller 416 transmits read data from one of the flash devices 408 to the staging buffer SRAM 406 in response to a read operation to be temporarily stored. The read data from the staging buffer SRAM 406 is decoded by the LDPC decoder 414 and sent to the host system 120. In other words, the read data is transferred from the NAND controller 416 to the staging buffer SRAM 406, from the staging buffer SRAM 406 to the LDPC decoder 414, and from the LDPC decoder 414 to the host system 120.

[0045] As described above with respect to the third data stream 433 , two levels of memory buffers may be used for read data from a read data operation. In other embodiments, two levels of memory buffers may be used for garbage collection (GC) read data from a GC read operation, as illustrated as the fourth data stream 441 .

[0046] In the fourth data stream 441, the NAND controller 416 transmits the first GC data 443 to the staging buffer SRAM 406 in response to the GC read operation on the first stream (the first write data 405) to be temporarily stored. The first GC data 443 from the staging buffer SRAM 406 is decoded by the LDPC decoder 414 and sent to the DRAM component 404. The GC data may also correspond to one or more streams. As described above, the DRAM component 404 may be organized to store the GC data in a PU buffer, where the size of the PU buffer corresponds to the die size of the flash device 408. GC data from more than two streams may be received and stored in separate PU buffers in the DRAM component 404, such as illustrated as the first GC data 443 and the second GC data 445. When the SSD controller 402 determines that the first GC data 425 of the first stream stored in the fifth PU buffer of the DRAM component 404 satisfies the threshold for programming the fifth PU (i.e., the PU buffer is filled with the first GC data), the SSD controller 402 transfers the first GC data 443 to the staging buffer SRAM 406. The LDPC encoder 412 encodes the first GC data 443 before storing the first GC data 443 in the staging buffer SRAM 406. That is, the first GC data 443 flows to the LDPC encoder 412 and flows from the LDPC encoder 412 to the staging buffer SRAM 406. Since the first GC data 443 is already one PU size, the SSD controller 402 can start programming one of the flash devices 408 using the PU corresponding to the first GC data 443 stored in the staging buffer SRAM 406. The SSD controller 402 may send the first GC data 443 to the NAND controller 416 , or the NAND controller 416 may retrieve the first GC data 443 from the staging buffer SRAM 406 to write the first GC data 443 to a third device among the plurality of flash devices 408 .

[0047] It should be noted that for the discarded item collection flow, GC reads can run at the same bandwidth as write operations and only valid transfer units (TUs) are read from the NAND controller 416. TU is the basic granularity (e.g., 4096B) at which data management is performed. Once the GC data is aggregated into the new PU buffer, the back-end write bandwidth is shared by write operations (e.g., 403, 423). The write amplification ratio can determine the ratio of GC data to host write data. In some embodiments, GC data from the NAND controller 416 is transmitted to the staging buffer SRAM 406 via multiple channels. Multiple channels can share the same buffer, depending on the percentage of valid data. The LDPC decoder 414 reads, processes the decoded data, and then writes the decoded data to the DRAM component 404. The GC data is aggregated into the new PU buffer. The GC write data stream is the same as the write data from the host system 120. In particular, the GC write data can be sent to the staging buffer SRAM 406 under the same rules as the write data. As Figure 4 4, staging buffer SRAM 406 stores GC read data until it is transferred to DRAM, and also stores GC write data. In one embodiment, staging buffer SRAM 406 has two logical partitions: a first logical partition in which write data and / or GC write data are temporarily stored before being written to flash device 408; and a second logical partition in which host read data and / or GC read data are temporarily stored before being transferred to host system 120 or DRAM component 404, respectively. Therefore, in addition to write data capacity, staging buffer SRAM 406 should also allocate capacity for GC read.

[0048] In order to scale from one stream to many streams (e.g., up to 1024 streams), the DRAM component 404 is the only option for expansion, and the staging buffer SRAM 406 operates as a pipeline in which all host write data and all GC read data are accumulated in the DRAM component 404 until the threshold for the die in the programming stream is met. In one embodiment, the die of the flash device 408 may have a programming unit (PU) size of 330KB per NAND die. In one embodiment, the write amplification (WA) is 2.1. RAIN storage is also allocated between the DRAM component 404 and the staging buffer SRAM 406. A certain number of RAIN contexts may reside in the staging buffer SRAM 406. As the stream count increases, the exchange of RAIN contexts between the DRAM component 404 and the staging buffer SRAM 406 may occur. In one embodiment, one or more DMA engines may be used to exchange RAIN contexts between the DRAM component 404 and the staging buffer SRAM 406.

[0049] In one embodiment based on the previously mentioned WA, the bandwidth for sequential write operations 403 is 4600MB / s, the bandwidth for random write operations 423 is 1250MB / s, and the bandwidth for host read data is 6600MB / s. The sequential write data is transferred from the DRAM component 404 to the staging buffer SRAM 406 with a bandwidth of 4600MB / s for sequential write data and 1250MB / s for random write data. The GC write data is transferred from the DRAM component 404 to the staging buffer SRAM 406 with a bandwidth of 2625MB / s for GC write data. This can be determined by multiplying 1250 by a write amplification factor of 2.1. The random write data and the GC write data can operate together using a bandwidth of 4000MB / s at a 31 / 32 bit rate. The LDPC encoder may operate with a bandwidth of 4600*0.92 for sequential write data, 1250*0.92 for random write data, and 2625*0.92 for GC write data, where 0.92 is the LDPC code rate. Data is transferred from the staging buffer SRAM 406 to the NAND controller 416 with an average bandwidth of 5150MB / s (e.g., 4600 / 0.92*32 / 31). This may be responsible for writing the RAIN data to the flash device 408 at a 31 / 32 code rate. One or more DMA engines may exchange RAIN data between the DRAM component 404 and the staging buffer SRAM 406 at a bandwidth of 4000MB / s. The staging buffer SRAM 406 and the RAIN XOR engine 410 may transfer the RAIN data using a bandwidth of 9600MB / s, since the RAIN XOR engine 410 may have a peak rate of 8*1200MB / s. For read operations, the staging buffer SRAM 406 and the NAND controller 416 may have an average bandwidth of 7174MB / s (6600 / 0.92) for the transmission of host read data and GC read data. The LDPC decoder 414 and the staging buffer SRAM 406 may have a bandwidth of 2853Mb / s for the GC read data transmitted between the staging buffer SRAM 406 and the DRAM component 404. The bandwidth between the NAND controller 416 and the host system 120 via the staging buffer is 6600MB / s. The bandwidth between the NAND controller 416 and the DRAM component 404 via the staging buffer is 2625MB / s. The above various bandwidths are demonstrated based on the programming unit size, DRAM and SRAM technology used. In other embodiments, the various bandwidths may be different. The Pu size may also be 220KB, 660KB, 440KB, 293KB or the like. The PU size may be facilitated by the page size and the number of planes. For example, a PU size of 330KB may be derived from a page size of 18344 bytes / page*3 pages*6 planes.The bandwidth may depend on the program time, ONFI transfer time, DRAM transfer time, and programming algorithm, such as 1-pass programming or 2-pass programming (8 to 16 programming levels).

[0050] In one embodiment, the design requirements for the two-level memory buffer architecture include 33 streams, 16 groups, 4.6GB / s host sequential writes, 5.15GB / s encoding rate (calculated as 4600MB / s sequential host writes / 0.92*32 / 31 LDPC code rate (31 / 32 RAIN code rate)), Rand write FOG=1M KIOPs-4.1GB / s (for WA=1) and Rand WrSS of 2.1, 3200MT / x 64b DDR interface with 15 / 16 ECC consumption and 1200MT / s ONFI 4.1 interface burst rate. The write amplification of 2.1 is estimated as 4600MB / s in the back end is adjusted down to 4000MB / s to account for the additional FW consumption (4000MB / s / 4096=977 KIOPs back end). The write amplification effect seen by the host is 3.2(2*WA)-1). 977 KIOPs / 3.2 = 305 KIOPs (estimated at 312 KIOPs), so 305 KIOPs*4096 = 1250 host write bandwidth. The GC bandwidth after the LDPC decoder is 1250MB / s*2.1 = 2625Mb / s (plus background scan overhead). The main basis for this flow is to build programming cells in DRAM and maintain RAIN background in DRAM to expand write data storage as the number of flows is expected to increase over time. As mentioned above, the bandwidth value can change based on different design requirements of the two-level memory buffer architecture.

[0051] In order to minimize the on-chip SRAM and provide scalability above the above requirements, host data and RAIN data are stored in DRAM. For this case, the host write data is accumulated in DRAM until there is threshold data that satisfies the die for programming flow. SRAM can be used as a hierarchical buffer for host data, GC data, and RAIN background. When the XOR is completed, the RAIN background needs to be written back to DRAM. Alternatively, the XOR operation can be completed using the RAIN background in DRAM. But when all 8 channels are sending data out, the XOR bandwidth can burst up to 9.6GB / s, which will require 19.2GB / s access to DRAM to read and write the RAIN background. If DRAM cannot keep up, the ONFI bus can be adjusted, which will not affect performance until the ONFI average bandwidth drops below 800MT / s.

[0052] Figure 55 is a diagram 500 illustrating eight streams 502 to 516 striped across eight channels to idle die according to some embodiments of the present invention. Continuing with the example of a PU size of 330KB above, the programming bandwidth is 115MB / s (330,192B / 2862μs). The minimum average throughput per channel is 644MB / s (5.15GB / 8). At least 45 die must be opened to meet the system write bandwidth of 5.15GB / s or about 6 die per channel. Figure 5 , there are 8 channels, each channel is used to accommodate one of the eight streams. The delay 501 between each stream is determined by the time it takes to move the data from DRAM to SRAM (plus any firmware overhead).

[0053] In one embodiment describing the staging buffer concept, by storing host write data in DRAM, the on-chip SRAM becomes a staging buffer component that can support a very high bandwidth interface to the ONFI backend. The ONFI maximum bandwidth (9.6 Gb / s) is much higher than the host bandwidth (5.15 GB / s - encoded), so the staging buffer component typically becomes empty faster than it fills.

[0054] Figure 6 600 is a diagram illustrating a staging buffer for programming four streams on a single channel according to some embodiments of the present invention. For a common data stream, the firmware can evaluate the current channel / die activity and available PUs. The firmware then selects the next PU for programming. The firmware starts data encoding and programs the NAND controller using NAND operations. The encoder begins filling the staging buffer component 602 with stream 0, as shown in FIG. Figure 6601 in the figure. After filling the staging buffer component 602 with stream 0 host data (and optionally associated RAIN data) at 601, NAND data transfer 603 begins to XOR the first die 604 (die 0) on the first channel (Ch0 NAND). When data transfer 603 is completed, the stream 0 host buffer can be released. If there are no other stream 0 host writes pending and the RAIN background is in the staging buffer component 602, the stream 0 RAIN data should be transferred (via the DMA engine) back to the DRAM. After filling the staging buffer component 602 with stream 1 host data (and optionally associated RAIN data) at 603, NAND data transfer 607 begins to XOR the second die 606 (die 1) on the same channel (Ch0 NAND). When data transfer 607 is completed, the same stream defined above for die 0 is completed for die 1. After filling the staging buffer component 602 with stream 2 host data (and optionally associated RAIN data) at 609, NAND data transfer 609 begins XORing the third die 608 (die 2). When data transfer 609 is complete, the same stream defined above for die 0 is completed for die 2. After filling the staging buffer component 602 with stream 3 host data (and optionally associated RAIN data) at 611, NAND data transfer 612 begins XORing the fourth die 610 (die 3). When data transfer 612 is complete, the same stream defined above for die 0 is completed for die 3. This can be done in parallel for all remaining die, such as Figure 6 As shown, data may always move through staging buffer component 602, but the retention period of data in staging buffer component 602 is short.

[0055] Since data is organized as programming units in DRAM, the firmware can have PU selection rules and can prevent or reduce channel conflicts or die conflicts. When the host system writes to various streams targeting the same channel / die, performance will be degraded regardless of the data stream. To minimize conflicts, the firmware can stagger and randomly order stream stripes across channels and dies. If the staging buffer component supports writing to the same channel / die, performance may be significantly affected, thereby preventing other operations from using the staging buffer component because the stream data will be stored in the staging buffer component for the duration of the ONFI transmission and its previous operation program. If multiple PUs target the same channel / die, the staging buffer component can be filled. To avoid filling the staging buffer component when the host is overloaded writing to one channel or die, the firmware can follow these rules: 1) limit the number of program operations per channel to 2; 2) if the PU is for a busy die, use cached program operations or save in DRAM until the die becomes idle; or similar. Figure 6A sequence is shown where four back-to-back programs to different dies may be transferred to the staging buffer component 602 at 619 with lane conflicts for the next stream data while the current NAND data transfer is in progress. In one embodiment, about six PUs fill the staging buffer component 602 during the time it takes to transfer 1 PU to the NAND, so a maximum of 3 lanes may appear similar, as shown in FIG. Figure 6 Alternatively, staging buffer component 602 can be sized to match more or fewer than six PUs.

[0056] Figure 7 704 is a diagram illustrating a sequence of program operations with simultaneous completion across all eight channels (which is impossible) according to some embodiments of the present invention. The delay 706 labeled E is the time to transfer data to the staging buffer component and configure the NAND controller for the program operation. In this worst case scenario, all existing channel programs 704 complete at the same time and all pending program operations 704 are not in the staging buffer component.

[0057] In one embodiment, cache programming can be performed to reduce this problem by performing the encoding operation and preparation during the previous program operation. It should be noted that cache programming increases the write cache size by effectively adding another data buffer. Program operations cached in this way should only be used when targeting a die that has been used by another programming operation. When this case occurs, channel program 704 is staggered so that it is not repeated as the write continues (but will eventually become randomly aligned), as shown in FIG. Figure 7 The write bandwidth may require six active dies per channel. It takes 1.8 ms to transfer data to six dies at 300 μs per transfer, leaving about 1 ms of idle channel time for every 6 data transfers. Some pending program operations 704 may already be in the staging buffer component.

[0058] In one embodiment for sequential write data, the two-level memory buffer may include 18 programming units with a PU size of 330KB, and the staging buffer SRAM may be 5804KB. For example, host data may have eight PUs and will require 2580KB in SRAM, and RAIN data may have ten PUs and will require 3225KB in SRAM. For an effective ONFI rate of 1 GB / s, at least six programming units (rounded to 8) may be buffered at a time. For RAIN data, two additional programming units may be used than for host data because the XOR operation keeps the RAIN data in the buffer longer.

[0059] In another embodiment for random write data, the two-level memory buffer may have 24 programming units, including seven for host data, nine for RAIN data, and eight for GC data. For this embodiment, the SRAM may be 7739KB, including 2257 for host data, 2902 for RAIN data, and 2580 for GC data. For an effective ONFI rate of 1 GB / s, at least five programming units (rounded to 7) may be buffered at a time. For RAIN data, two additional programming units may be used than for host data because the XOR operation keeps the RAIN data in the buffer longer. For 50% validity in GC data, the read data from 8 channels uses 4 buffers times 2 depth, is decoded, and sent to the DRAM.

[0060] Since random write data uses more PUs, if 8MB SRAM and 24 PUs are used, there are six or more PUs for sequential write data. These extra PUs can be used to permanently store 6 RAIN PUs. This can reduce the RAIN background switching BW by about 18%, depending on the host workload. If there is block-level RAIN protection for the flow, then 2MB can be saved, bringing the SRAM down to 6MB, or an extra 2MB can be used to save RAIN background or for other purposes that the firmware sees fit.

[0061] Figure 8 An example machine illustrating a computer system 800 may execute within the computer system 800 a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 800 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110) or can be used to perform operations of the controller (e.g., execute an operating system to execute corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0062] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0063] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0064] The processing device 802 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. The processing device 802 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. The computer system 800 may further include a network interface device 808 to communicate over a network 820.

[0065] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a non-transitory computer-readable storage medium) on which one or more sets of instructions 826 or software are stored to embody any one or more of the methodologies or functions described herein. The instructions 826 may also reside completely or at least partially within the main memory 804 and / or within the processing device 802 during execution thereof by the computer system 800, the main memory 804 and the processing device 802 also constituting machine-readable storage media. The machine-readable storage medium 824, the data storage system 818, and / or the main memory 804 may correspond to Figure 1 Memory subsystem 110.

[0066] In one embodiment, instructions 826 include implementing a component corresponding to a two-stage buffer controller (eg, Figure 1The two-stage buffer controller component 113 of the present invention is a two-stage buffer controller component 113 of the present invention. Although the machine-readable storage medium 824 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be deemed to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be deemed to include any medium capable of storing or encoding a set of instructions executed by a machine and causing the machine to perform any one or more of the methodologies of the present invention. The term "machine-readable storage medium" should accordingly be deemed to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0067] Some portions of the above detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is generally conceived here to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It proves convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0068] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present invention may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0069] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0070] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with the program according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the method. The structures of various these systems will appear as set forth in the description below. In addition, the present invention is not described with reference to any particular programming language. It should be appreciated that various programming languages ​​may be used to implement the teachings of the present invention described herein.

[0071] The present invention may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present invention. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0072] In the foregoing description, embodiments of the invention have been described with reference to specific example embodiments thereof. Obviously, various modifications may be made to the invention without departing from the broader spirit and scope of the embodiments of the invention as set forth in the appended claims. The description and drawings should accordingly be regarded as intended to be illustrative rather than restrictive.

Claims

1. A system for memory operation, comprising: A two-level memory buffer of the memory subsystem, comprising: a host buffer component of the two-level memory buffer, comprising a dynamic random access memory DRAM, wherein the host buffer component is used to store first write data of a first stream and second write data of a second stream, the first write data and the second write data being received from a host system, wherein the first write data of the first stream is to be stored in a first programming unit buffer among a plurality of programming unit buffers of the host buffer component, and wherein the second write data of the second stream is to be stored in a second programming unit buffer among the plurality of programming unit buffers of the host buffer component, the first programming unit buffer being dedicated to storing the write data of the first stream, and the second programming unit buffer being dedicated to storing the write data of the second stream; a hierarchical buffer component of the two-level memory buffer operatively coupled to the host buffer component, wherein the hierarchical buffer component includes a static random access memory (SRAM); a non-volatile memory NVM controller operably coupled to the staging buffer component, the NVM controller managing the host buffer component and the staging buffer component of the two-level memory buffer; a plurality of NVM dies coupled to the NVM controller and the staging buffer component, the plurality of NVM dies comprising NVMs; and a processing device operably coupled to the host buffer component, the staging buffer component, and the NVM controller to: determining that the first write data of the first stream stored in the host buffer component satisfies a threshold for programming a first programming unit, wherein a size of the first programming unit corresponds to a size of one of the plurality of NVM dies; transferring the first write data from the first programming unit buffer in the host buffer component to the staging buffer component; writing the first write data from the staging buffer component as the first programming unit to a first die among the plurality of NVM dies; determining that the second write data of the second stream stored in the host buffer component satisfies a threshold for programming a second programming unit; transferring the second write data from the second programming unit buffer in the host buffer component to the staging buffer component; and The second write data from the staging buffer component is written as the second programming unit to a second die of the plurality of NVM dies.

2. The system according to claim 1, further comprising: An independent redundant array of NAND RAIN XOR engine is coupled to the staging buffer component and the NVM controller, the RAIN XOR engine is used to: receiving the first write data from the NVM controller; generating first RAIN data corresponding to the first write data; and The first RAIN data is stored in the staging buffer component, wherein the processing device is further configured to transmit the first RAIN data corresponding to the first write data from the staging buffer component to the host buffer component in conjunction with writing the first write data as the first programming unit to the first die.

3. The system of claim 2, wherein the RAIN XOR engine is further configured to: receiving the second write data from the NVM controller; generating second RAIN data corresponding to the second write data; and The second RAIN data is stored in the staging buffer component, wherein the processing device is further configured to transmit the second RAIN data corresponding to the second write data from the staging buffer component to the host buffer component in conjunction with writing the second write data as the second programming unit to the second die.

4. The system of claim 1, wherein the first write data is sequential write data received from a host system. 5 . The system of claim 1 , wherein the first write data is random write data received from a host system.

6. The system of claim 1, wherein the host buffer component is further configured to store first garbage collection (GC) data corresponding to the first flow in the host buffer component, wherein the processing device is further configured to: determining that the first GC data in the host buffer component satisfies a threshold for programming a third programming unit; transferring the first GC data from the host buffer component to the staging buffer component; and The first GC data from the staging buffer component is written as the third programming unit to a third die of the plurality of NVM dies.

7. The system of claim 1, further comprising: A data protection encoder is coupled between the staging buffer component and the host buffer component, and is used to encode the first write data when transmitting between the host buffer component and the staging buffer component.

8. The system of claim 7, further comprising: A data protection decoder is coupled between the staging buffer component and the host buffer component, the data protection decoder being used to decode GC read data received from one or more of the plurality of NVM dies as the GC read data is transferred from the staging buffer component to the host buffer component.

9. The system of claim 8, wherein the data protection encoder is a low-density parity check (LDPC) encoder and the data protection decoder is an LDPC decoder.

10. The system of claim 8, wherein the staging buffer assembly comprises: a first logical partition in which the first write data before being written to the first die is temporarily stored and the second write data before being written to the second die is temporarily stored; and A second logical partition wherein the GC read data is temporarily stored prior to transmission to the host buffer component.

11. A system for memory operation, comprising: A host interface for receiving first write data of a first stream and second write data of a second stream from a host system; a dynamic random access memory DRAM interface for coupling to one or more external DRAM devices, wherein the first write data of the first stream is to be stored in a first programming unit buffer of a plurality of programming unit buffers of the one or more external DRAM devices, and wherein the second write data of the second stream is to be stored in a second programming unit buffer of the plurality of programming unit buffers of the one or more external DRAM devices, the first programming unit buffer being dedicated to storing the write data of the first stream, and the second programming unit buffer being dedicated to storing the write data of the second stream; an internal static RAM SRAM device, wherein the one or more external DRAM devices and the internal SRAM device are included in a memory subsystem; one or more non-volatile memory (NVM) devices; an NVM controller that manages the internal SRAM device and the one or more external DRAM devices; and A processing device, which interfaces with the host interface, the DRAM interface, the internal SRAM device, the The NVM controller and the one or more NVM devices are operably coupled to: transferring the first write data from the first programming unit buffer in the one or more external DRAM devices to the internal SRAM device when the first write data satisfies a programming unit PU threshold, the PU threshold corresponding to a PU size of the one or more NVM devices; writing the first write data from the internal SRAM device to the one or more NVM devices as a first programming unit; transferring the second write data from the second programming unit buffer in the one or more external DRAM devices to the internal SRAM device when the second write data satisfies the PU threshold; and The second write data from the internal SRAM device is written to the one or more NVM devices as a second programming unit.

12. The system of claim 11, further comprising: a low density parity check (LDPC) encoder coupled between the internal SRAM device and the DRAM interface; and An LDPC decoder is coupled between the internal SRAM device and the NVM controller.

13. The system of claim 11, further comprising: An independent redundant array of NAND RAIN XOR engine is coupled between the internal SRAM device and the NVM controller, and the RAIN XOR engine is used to: generating first RAIN data corresponding to the first write data; causing the first RAIN data to be stored in the internal SRAM element before being transmitted to the one or more external DRAM devices via the DRAM interface; generating second RAIN data corresponding to the second write data; and The second RAIN data is caused to be stored in the internal SRAM component before being transmitted to the one or more external DRAM devices via the DRAM interface.

14. The system of claim 11, further comprising: a low density parity check (LDPC) encoder coupled between the internal SRAM device and the DRAM interface, wherein the LDPC encoder is configured to receive the first write data via the host interface, encode the first write data, and store the first write data in a first logical partition of the internal SRAM device; and an LDPC decoder coupled between the internal SRAM device and the NVM controller, wherein the NVM controller stores obsolete collection (GC) data in a second logical partition of the internal SRAM device, wherein the LDPC decoder is used to receive the GC data from the internal SRAM device, decode the GC data, and send the GC data to the one or more external DRAM components via the DRAM interface.

15. The system of claim 11, wherein the first write data is first sequential write data received from the host system, wherein the second write data is second sequential write data received from the host system.

16. The system of claim 11, wherein the first write data is sequential write data received from the host system, wherein the second write data is random write data received from the host system.

17. A method for memory operation, comprising: determining that first write data of a first stream stored in a host buffer component of a two-level memory buffer of a memory subsystem satisfies a threshold for programming a first programming unit, wherein a size of the first programming unit corresponds to a size of one of a plurality of non-volatile memory (NVM) dies, wherein the first write data of the first stream is stored in a first programming unit buffer of a plurality of programming unit buffers of the host buffer component, the first programming unit buffer being dedicated to storing the write data of the first stream; transferring the first write data from the first programming unit buffer in the host buffer component to a staging buffer component of the two-level memory buffer of the memory subsystem, wherein the host buffer component and the staging buffer component of the two-level memory buffer are managed by an NVM controller associated with the plurality of NVM dies; writing the first write data from the staging buffer component as the first programming unit to a first die among the plurality of NVM dies; determining that second write data of a second stream stored in the host buffer component satisfies a threshold for programming a second programming unit, wherein the second write data of the second stream is to be stored in a second programming unit buffer of the plurality of programming unit buffers of the host buffer component, the second programming unit buffer being dedicated to storing the write data of the second stream; transferring the second write data from the second programming unit buffer in the host buffer component to the staging buffer component; and The second write data from the staging buffer component is written as the second programming unit to a second die of the plurality of NVM dies.

18. The method according to claim 17, further comprising: generating first independent NAND redundant array RAIN data corresponding to the first write data; temporarily storing the first RAIN data in the staging buffer component; and transferring the first RAIN data from the staging buffer component to the host buffer component in conjunction with writing the first write data as the first programming unit to the first die; generating second RAIN data corresponding to the second write data; temporarily storing the second RAIN data in the staging buffer component; and The second RAIN data from the staging buffer component is transferred to the host buffer component in conjunction with writing the second write data as the second programming unit to the second die.

19. The method of claim 17, further comprising: storing first garbage collection (GC) data corresponding to the first stream in the host buffer component; determining that the first GC data in the host buffer component satisfies a threshold for programming a third programming unit; transferring the first GC data from the host buffer component to the staging buffer component; and The first GC data from the staging buffer component is written as the third programming unit to a third die of the plurality of NVM dies.

20. The method of claim 17, further comprising: causing the first write data to be encoded when being transmitted between the host buffer component and the staging buffer component; storing obsolete collection (GC) read data in the staging buffer component, the GC read data being received from the NVM controller associated with the plurality of NVM dies; transferring the GC read data from the staging buffer component to the host buffer component; and The GC read data is decoded as the GC read data is transferred from the staging buffer component to the host buffer component.

Images