Memory array

Abstract

A memory array includes vertically alternating layers of insulating material and memory cells. The memory cells individually include transistors, the transistors including first and second source / drain regions with a channel region therebetween, and gates operatively proximate to the channel region. The individual memory cells include capacitors, the capacitors including first and second electrodes with a capacitor insulator therebetween. The first electrode is electrically coupled to the first source / drain region. A word line structure extends vertically through the insulating material of the vertically alternating layers and the memory cells. Individuals of the gates of different ones of the memory cell layers are directly electrically coupled to individuals of the word line structure. Sense lines are electrically coupled to a plurality of the second source / drain regions of the individual ones of the transistors.

Description

Technical Field

[0001] Embodiments disclosed herein relate to memory arrays. Background Art

[0002] Memory is a type of integrated circuit system and is used in computer systems to store data. Memory can be manufactured in one or more arrays of individual memory cells. Memory cells can be written or read using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). Digit lines can interconnect memory cells in a conductive manner along the columns of the array, and access lines can interconnect memory cells in a conductive manner along the rows of the array. Each memory cell can be uniquely addressed by a combination of digit lines and access lines.

[0003] Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is typically specified as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. In any case, the memory cell is configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered "0" or "1". In other systems, at least some individual memory cells may be configured to store information at more than two levels or states.

[0004] Capacitors are a type of electronic component that can be used in memory cells. A capacitor has two electrical conductors separated by an electrically insulating material. Energy as an electric field can be stored in this material in an electrostatic manner. Depending on the composition of the insulator material, the stored field will be volatile or non-volatile. For example, a capacitor insulator material containing only SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor, which has a ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarization states and thus can include programmable materials for capacitors and / or memory cells. The polarization state of a ferroelectric material can be changed by applying a suitable programming voltage and maintained (at least for a certain period of time) after the programming voltage is removed. Each polarization state has a different charge storage capacitance from each other, and the charge storage capacitance is ideally usable for writing (i.e., storing) and reading memory states without reversing the polarization state until such reversal is desired. Less desirable, in a memory having a ferroelectric capacitor, the act of reading the memory state may reverse the polarization. Thus, after the polarization state is determined, the memory cell is rewritten to place the memory cell in the pre-read state immediately after the polarization state is determined. In any case, memory cells incorporating ferroelectric capacitors are ideally non-volatile due to the bistable nature of the ferroelectric material that forms part of the capacitor. Other programmable materials can be used as capacitor insulators to make the capacitor non-volatile.

[0005] Field effect transistors are another type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductive channel region between them. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate. In any case, the gate insulator may be programmable, such as ferroelectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagrammatic cross-sectional view of a substrate fragment including a memory array according to an embodiment of the present invention, and is a cross-sectional view through Figures 2 to 5 Intercepted by line 1-1 in.

[0007] Figure 2 It passes through Figure 1 A cross-sectional view taken along line 2-2 in FIG.

[0008] Figure 3 It passes through Figure 1 The cross-sectional view is taken along the line 2-2 in FIG. 1 and is proportional to Figure 1 and 2 The proportion is small.

[0009] Figure 4 It passes through Figure 1 A cross-sectional view taken along line 4-4 in FIG.

[0010] Figure 5 It passes through Figure 1 A cross-sectional view taken along line 5-5 in FIG.

[0011] Figure 6 yes Figure 1 An enlarged view of a portion of.

[0012] Figure 7 yes Figure 1 An enlarged side-by-side exploded perspective view and an enlarged assembled perspective view of certain components of a substrate segment.

[0013] Figure 8 is a diagrammatic cross-sectional view of an alternative embodiment substrate fragment including a memory array according to an embodiment of the present invention, and as will be referred to in Figures 1 to 7 The embodiment passes through the corresponding Figure 1 The line 2-2 in the line intercept.

[0014] Fig. 9 If you refer to Figures 1 to 7 The embodiment passes through the corresponding Figure 1 The line 4-4 in the Figure 8 Diagrammatic cross-sectional view of an embodiment.

[0015] Fig.10 If you refer to Figures 1 to 7 The embodiment passes through the corresponding Figure 1 The line 5-5 in the Figure 8 Diagrammatic cross-sectional view of an embodiment.

[0016] Fig.11 yes Fig.10 Diagrammatic cross-sectional view of the construction, with a ratio of Fig.10 The proportion is small.

[0017] Fig.12 yes Figure 1 A diagrammatic cross-sectional view of another (different) portion of a substrate fragment.

[0018] Fig.13 yes Fig.12 Substrate fragments in Fig.12 A view at a processing step subsequent to the illustrated processing step. DETAILED DESCRIPTION

[0019] Embodiments of the present invention encompass memory arrays. A first exemplary embodiment is Figures 1 to 7 1 and described with reference to the figures. This shows a construction 8 having a memory array 10 above a base substrate 11, which may include any one or more of conductive / conductive, semiconductive / semiconductive, and insulating / insulator / insulating (i.e., electrically herein) materials. Various materials have been formed vertically above the base substrate 11. The materials may be Figures 1 to 7 The depicted material may be adjacent to, vertically inside, or vertically outside of the depicted material. For example, other partially or completely manufactured components of the integrated circuit system may be disposed somewhere above, around, or within the base substrate 11. Control and / or other peripheral circuitry for operating components within the memory array may also be manufactured and may or may not be completely or partially within the memory array or sub-array. In addition, multiple sub-arrays may also be manufactured and operated independently of each other, sequentially, or in other ways. As used in this document, a "sub-array" may also be considered an array.

[0020] Construction 8 includes vertically alternating layers 12 and 14 of insulating material 16 (e.g., carbon-doped silicon nitride [2 to 10 atomic percent carbon], silicon nitride, and / or doped or undoped silicon dioxide deposited to a thickness of 200 to 500 angstroms) and memory cells 19, respectively. Memory cell layer 14 may have the same or a different thickness than insulating material layer 12, with different and larger thicknesses (e.g., 500 to 1,500 angstroms) being shown. Construction 8 is shown with seven vertically alternating layers 12 and 14, but it is possible to form more (e.g., tens, hundreds, etc.). Thus, more layers 12 and 14 may be below the depicted layers and above base substrate 11, and / or more layers 12 and 14 may be above the depicted layers.

[0021] The memory cells 19 individually include a transistor 25 and a capacitor 34. The transistor 25 includes a first source / drain region 20 ( Figure 6 and 7 ) and a second source / drain region 22. The channel region may include any appropriately doped semiconductor material, such as polysilicon, but not intrinsically conductive. Additional examples are GaP and one or more semiconductor oxides. For example, the semiconductor oxide may include any suitable composition, and in some embodiments, may include one or more of indium, zinc, tin, and gallium. For example, the semiconductor oxide may have a combination of oxygen and any of indium, zinc, and gallium. Indium, zinc, and gallium are metals within such compositions (e.g., semiconductor metal oxides), and alternative and / or additional metals may be used, and the composition need not be or need not include one or more stoichiometric compounds. Regardless, and by way of example only, some examples include ZnO x 、InOx 、In2O3、SnO2、TiO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、In x Ga y Si z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a , Ga x Zn y Sn z O a and Zr x Zn y Sn z O a A semiconductive region (eg, an LDD and / or halogen region, and not shown) and / or a conductively doped semiconductive material region (not shown) may be between the channel region 24 and one or both of the source / drain regions 20 and 22 .

[0022] In one embodiment and as shown, one (e.g., 22) of the first source / drain region 20 and the second source / drain region 22 is above the other, in one embodiment directly above the other. In another embodiment, the first source / drain region 20 is above the second source / drain region 22, in one embodiment directly above the second source / drain region (e.g., as would occur or appear if the plane of the page [became inverted], on the plane Figure 1 , 6 7 are each rotated 180°). In one embodiment and as shown, the channel region 24 includes a straight vertical cross section (e.g., Figure 1 and 6 The opposite C-shaped shapes 21 ( Figure 6 and 7 ).

[0023] The conductive gate 26 is operatively proximate to the channel region 24. Specifically, in the depicted example, a gate insulator material 28 (e.g., silicon dioxide, silicon nitride, hafnium dioxide, other high-k insulator materials, and / or ferroelectric materials) is between the gate 26 and the channel region 24. In one embodiment, at least a portion of the channel region 24 is horizontally oriented for horizontal current flow in a portion between the first source / drain region 20 and the second source / drain region 22. In the depicted example embodiment, only a portion of the channel region 24 is horizontally oriented for horizontal current flow therethrough. Regardless, when a suitable voltage is applied to the gate 26, a conductive channel may be formed within the channel region 24 proximate to the gate insulator material 28, enabling current to flow between the source / drain regions 20 and 22.

[0024] The capacitor 34 includes a pair of conductive electrodes, such as a first electrode 46 and a second electrode 48 with a capacitor insulator 50 (e.g., silicon dioxide, silicon nitride, hafnium dioxide, other high-k insulator materials, and / or ferroelectric materials) therebetween. The first electrode 46 is electrically coupled to, and in one embodiment is directly electrically coupled to, the first source / drain region 20. Individual first source / drain regions 20 may include a portion of an individual first electrode 46 as shown. In one embodiment and as shown, the second capacitor electrodes 48 of a plurality of capacitors 34 in the array 10 are electrically coupled to, and in one embodiment are directly electrically coupled to, each other. In one embodiment, all such second electrodes of all capacitors in the array 10 are electrically coupled to each other, and in one embodiment are directly electrically coupled to each other.

[0025] In one embodiment, a capacitor-electrode structure 52 (e.g., a solid or hollow pillar, a solid or hollow wall, etc.) extends vertically through the vertical alternating layers 12 and 14, wherein individual ones of the second electrodes 48 of individual capacitors 34 in different memory cell layers 14 are electrically coupled, in one embodiment directly electrically coupled, to the vertically extending capacitor-electrode structure 52. Example materials for the capacitor-electrode structure 52 are metallic materials and conductively doped semiconductor materials, and this may have the same composition as that of the second electrode 48 as shown. In one embodiment, the capacitor-electrode structure 52 is directly electrically coupled to a horizontally extended capacitor-electrode construction 29 ( FIG. 2 ) above or below (shown as above) the vertical alternating layers 12 and 14. Figure 1 ; such as wires or plates). In one embodiment, the structure 29 can directly electrically couple all second electrodes 48 within the array together. In one embodiment and as reduced in scale Figure 3 As shown, a plurality of capacitor-electrode structures 52 extend vertically through the vertically alternating layers 12 and 14 , with individual second electrodes 48 of individual capacitors 34 in different memory cell layers 14 electrically coupled to individual ones of the capacitor-electrode structures 52 .

[0026] Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used with respect to the above-described embodiments.

[0027] In one embodiment and as shown, capacitor-electrode structure 52 includes vertically extending walls 53 that are horizontally elongated longitudinally (e.g., along Figures 2 to 5 In one embodiment, by way of example only, this is one example of how second capacitor electrodes 48 of multiple capacitors 34 in different memory cell layers 14 in array 10 may be electrically coupled to each other. Alternatively, and by way of example only, the capacitor-electrode structure may include multiple pillars that electrically couple the second capacitor electrodes of the multiple capacitors to each other, e.g., as described above. Figures 8 to 10 10a in the configuration 8a. The same reference numerals of the embodiments described above have been used where appropriate, with certain construction differences indicated by the suffix "a" or by different reference numerals. The capacitor-electrode structure 52a includes a plurality of pillars 55 that electrically couple the second capacitor electrodes of the plurality of capacitors directly to each other. The pillars 55 may be electrically coupled to, and in one embodiment are electrically coupled directly to, the horizontally elongated capacitor-electrode structures 29 ( Figures 8 to 10 Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0028] The word line electrically couples together, in one embodiment directly, a plurality of the gates of the individual ones of the transistors. The sense line is electrically coupled to, in one embodiment directly to, a plurality of the second source / drain regions of the individual ones of the transistors.

[0029] In one embodiment, construction 10 includes word line structures 56 extending vertically through insulating material 16 and memory cells 19 of vertical alternating layers 12 and 14. Individual gates 26 in different memory cell layers 14 are directly electrically coupled to individual word line structures 56 (e.g., include a portion of the individual word line structures). In one embodiment and as shown, word line structures 56 individually include vertical or within 10° of vertical pillar portions 58 (e.g., solid or hollow, and not shown for clarity of other components). Figure 7 ), and in one embodiment, gate 26 includes an annular region 60 that protrudes radially circumferentially around pillar portion 58. Thus, and in some embodiments, gate 26 may be considered to include an annular region portion, and the annular region portion may be considered to include a portion of a word line structure. In one embodiment and as shown, individual word line structures 56 are directly electrically coupled to individual horizontal longitudinally extending lines 62 (shown as below) above or below (shown as below) vertical alternating layers 12 and 14. Figure 1 Only one is shown).

[0030] Example insulating material 57 (eg, silicon dioxide or silicon nitride) is shown above and below radially protruding annular region 60 of gate 26. Example insulating material 59 (eg, silicon dioxide or silicon nitride) is shown between word line structure 56 and first electrode 46 of capacitor 34.

[0031] In one embodiment, the horizontally extending sense lines 64 are in individual memory cell layers 14. Individual second source / drain regions 22 in individual memory cell layers 14 are electrically coupled, in one embodiment directly electrically coupled, to individual horizontally extending sense lines 64 in respective individual memory cell layers 14. Individual second source / drain regions 22 may include a portion of individual sense lines 64 as shown. In one embodiment and as shown, individual horizontally extending sense lines 64 include end-to-end overlapping interconnected ring structures 66. Ring structures 66 individually circumferentially surround one of word line structures 56, with example insulating material 61 (e.g., silicon dioxide or silicon nitride) laterally / radially located between sense lines 64 and word line structures 56. In one embodiment, sense lines 64 may be considered to include respective central longitudinal axes 68, which in one embodiment are straight.

[0032] The above example structures may be fabricated by any existing or future developed technology. For example, and by way of example only, the insulating material 16 of the insulating layer 12 may include silicon nitride doped with carbon. The memory cell layer 14 may initially be fabricated as a stack of an undoped silicon nitride layer on top of an undoped silicon dioxide layer on top of an amorphous silicon layer. In any case, Figures 1 to 11 The components shown in can be manufactured in any order. In one example, a hole will be formed through the entire stack that will correspond to the size and shape of the pillar portion 58 of the word line structure. The undoped silicon nitride layer will then be selectively isotropically etched relative to the other exposed materials (e.g., by a timed wet etch using H3PO4) to form the outline of the overlapping annular portion 66, which includes the outline of what will be the sense line 64. The conductive material of the digit line is then deposited within the opening to fill the space radially outside of the opening, and then the conductive material is removed from the center of the opening, and such conductive material is laterally / radially recessed to make room for the insulating material 61. Next, the insulating material 61 (e.g., undoped silicon nitride) is deposited within the opening and above the recessed metal, and then such insulating material is removed from the center of the vertical opening.

[0033] The amorphous silicon layer will then be similarly selectively wet etched isotropically relative to the other materials (e.g., by a timed wet etch using tetramethylammonium hydroxide, hereinafter referred to as TMAH). A thin layer of conductive material that will be the first capacitor electrode 46 will then be deposited, followed by the sacrificial polysilicon. The polysilicon will then be isotropically etched (e.g., by a timed wet etch using TMAH) to be recessed relative to the vertically extending opening to mask the remaining radially outermost portion of the conductive material. Thereafter, such conductive material will be removed from the sidewalls of the vertical opening and from the unshielded portions within the amorphous silicon layer (e.g., in the case where the conductive material is titanium nitride, by a timed wet etch using a suitable mixture of NH4OH and H2O2). An insulating material (e.g., silicon nitride) is then deposited to fill the recess in the amorphous silicon layer, and the insulating material is then removed from the vertical opening.

[0034] Next, the silicon dioxide will be selectively isotropically etched relative to the other exposed materials (e.g., by a timed wet etch using HF), followed by the deposition of a thin layer of channel material 24, followed by gate insulator 28, and followed by the conductive material of gate 26. The conductive material will then be removed from the vertical opening (e.g., by etching), and the gate insulator will then be selectively wet etched (e.g., using HF if gate insulator 28 is silicon dioxide) to make room for insulating material 57. Insulating material 57 is then deposited within the vertical opening and fills the recess, and such insulating material is then removed from the center of the vertical opening. Conductive material is then deposited within the vertical opening for forming the remainder of wordline structure 56.

[0035] The capacitor-electrode structure 52 may then be formed in a similar manner, for example, by starting with a vertical opening formed corresponding to the contour of the wall 53 or pillar 55. The amorphous silicon will then be subjected to a timed isotropic selective etch (e.g., using TMAH) to expose only one side of the conductive material that will be the first capacitor electrode 46. Then, those exposed portions may be subjected to a short timed wet etch thereof (e.g., using a suitable mixture of NH4OH and H2O2 in the case where the conductive material is titanium nitride), thereby forming the isolated first capacitor electrode 46 (and individual portions thereof including the first source / drain region 20). After this, the conductive material of the capacitor insulator 50 and the common second capacitor electrode 48 is deposited.

[0036] The structures described above may be formed within a vertical recess of the structure, whereby the various materials may inherently be routed upward along the sidewalls. For example, and by way of example only, Fig.12 and 13 An example of such a technique is shown whereby a stack of sense lines in a vertical column in the stack can be routed upward for electrical coupling with a sense amplifier.

[0037] Fig.12 The various materials of array 10 of construction 8 are shown as having been fabricated within recess 75 (e.g., a bathtub shape) above base substrate 11. Insulating material 16 (not shown) in the sense line layer of memory cell layer 19 is shown as insulating material 80 (e.g., undoped silicon nitride), and will have a composition that is different in etchability than the composition of insulating material 16 (e.g., doped silicon nitride and / or silicon dioxide).

[0038] Fig.13 Insulating material 80 (not shown) is shown as having been removed (e.g., by selective wet etching with H3PO4) and replaced with conductive material 82, which is thereby essentially routed to be available over alternating layers 12 and 14. This may have been patterned and / or otherwise connected with example conductive lines 84 that may be routed to a sense amplifier (not shown) or other circuitry (not shown).

[0039] The above processing or construction may be viewed as an array with respect to components that are formed as a single stack or a single stack of such components, or within the single stack or a single stack that is above or as part of the underlying base substrate (although a single stack / stack may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed at any location as part of the finished construction, and in some embodiments may be located below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / stacks may be provided or fabricated above and / or below the stacks / stacks shown in the figures or described above. In addition, the arrays of components may be the same or different relative to each other in different stacks / stacks. Intervening structures may be provided between vertically adjacent stacks / stacks (e.g., additional circuitry and / or dielectric layers). Also, different stacks / stacks may be electrically coupled relative to each other. Multiple stacks / stacks may be fabricated individually and sequentially (e.g., one on top of another), or two or more stacks / stacks may be fabricated substantially simultaneously.

[0040] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0041] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "top", "bottom", "above", "below", "below", "under", "upward", and "downward" generally refer to the vertical direction. "Horizontal" refers to the general direction along the surface of the main substrate and can be referred to when processing the substrate during manufacturing (i.e., within 10 degrees), and vertical is a direction generally orthogonal to it. Reference to "just horizontal" refers to the direction along the surface of the main substrate (i.e., not at a degree to the surface) and can be referred to when processing the substrate during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally perpendicular directions relative to each other and have nothing to do with the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction inclined at least 45° from just horizontal. In addition, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", etc. with respect to a field effect transistor refer to the orientation of the channel length of the transistor, and the current flows along the orientation between the source / drain regions in operation. For bipolar junction transistors, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", etc. refer to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature and / or region extending vertically extends vertically or within 10° of vertical.

[0042] Furthermore, "directly above," "directly below," and "directly beneath" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components relative to each other. And, the use of "above" without a preceding "directly" requires only that some portion of the stated region / material / component that is above another stated region / material / component is located vertically outside of the other stated region / material / component (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" requires only that some portion of the stated region / material / component that is below / beneath another stated region / material / component is located vertically inside of the other stated region / material / component (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components).

[0043] Any of the materials, regions, and structures described herein may be homogeneous or inhomogeneous, and in any case may be continuous or discontinuous over any material overlying it. When one or more example compositions are provided for any material, the material may comprise, consist essentially of, or consist of the one or more compositions. Furthermore, unless otherwise indicated, each material may be formed using any suitable existing or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0044] In addition, "thickness" (without directional adjectives in front) used alone is defined as the average straight-line distance perpendicularly passing through a given material or region from the closest surface of the adjacent material or adjacent region with different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different compositions" only require that those parts of the two stated materials or regions that can directly abut against each other are chemically and / or physically different, such as when such materials or regions are not homogeneous. If the two stated materials or regions are not directly against each other, then in the case of such materials or regions being non-homogeneous, "different compositions" only require that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when the stated materials, regions or structures are in at least some physical contact relative to each other, the material, region or structure "directly abuts" another material, region or structure. In contrast, "over," "on," "adjacent," "along," and "against" without being preceded by "directly" encompass "directly against" as well as configurations in which intervening materials, regions, or structures are such that the stated materials, regions, or structures are not in physical contact with each other.

[0045] As used herein, region-material-components are "electrically coupled" relative to one another if, in normal operation, electrical current is able to flow continuously from one region-material-component to another region-material-component, and the flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between the region-material-components and electrically coupled thereto. In contrast, when region-material-components are referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0046] The composition of any of the conductive / conductor / conductive materials herein may be a metallic material and / or a conductively doped semiconductive / semiconductor / semiconductive material. "Metallic material" is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0047] As used herein, "selective" with respect to etching / etching, removing / removal, depositing, and / or forming / formation is such action performed on one stated material relative to another stated material acted upon at a ratio of at least 2:1 by volume. Additionally, selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another stated material or materials at a ratio of at least 2:1 by volume for at least the first 75 angstroms.

[0048] Unless otherwise indicated, the use of "or" herein includes either and both.

[0049] in conclusion

[0050] In some embodiments, a memory array includes vertically alternating layers of insulating material and memory cells. The memory cells individually include transistors, the transistors including first and second source / drain regions with a channel region therebetween, and gates operatively proximate to the channel region. The individual memory cells include capacitors, the capacitors including first and second electrodes with a capacitor insulator therebetween. The first electrode is electrically coupled to the first source / drain region. A word line structure extends vertically through the insulating material and the memory cells of the vertically alternating layers. Individuals of the gates of different ones of the memory cell layers are directly electrically coupled to individual ones of the word line structures. A sense line is electrically coupled to a plurality of the second source / drain regions of the individual ones of the transistors.

[0051] In some embodiments, a memory array includes vertically alternating layers of insulating material and memory cells. The memory cells individually include transistors, the transistors including first and second source / drain regions with a channel region therebetween, and a gate operatively proximate to the channel region. The individual memory cells include capacitors, the capacitors including first and second electrodes with a capacitor insulator therebetween. The first electrode is electrically coupled to the first source / drain region. Horizontally extending sense lines are in individual ones of the memory cell layers. Individual ones of the second source / drain regions in individual memory cell layers are electrically coupled to individual ones of the horizontally extending sense lines in corresponding individual memory cell layers. Word lines electrically couple together a plurality of the gates of the individual ones of the transistors.

[0052] In some embodiments, a memory array includes vertically alternating layers of insulating material and memory cells. The memory cells individually include transistors, the transistors including first and second source / drain regions with a channel region therebetween, and a gate operatively proximate to the channel region. The individual memory cells include capacitors, the capacitors including first and second electrodes with a capacitor insulator therebetween. The first electrode is electrically coupled to the first source / drain region. A word line structure extends vertically through the insulating material and the memory cells of the vertically alternating layers. Individuals of the gates of different ones of the memory cell layers are directly electrically coupled to individuals of the word line structure. Horizontally extending sense lines are in individual ones of the memory cell layers. Individuals of the second source / drain regions in individual memory cell layers are electrically coupled to individual ones of the horizontally extending sense lines in corresponding individual memory cell layers.

[0053] In some embodiments, a memory array includes vertically alternating layers of insulating material and memory cells. The memory cells individually include transistors, the transistors including first and second source / drain regions with a channel region therebetween, and gates operatively proximate to the channel region. The individual memory cells include capacitors, the capacitors including first and second electrodes with a capacitor insulator therebetween. The first electrode is electrically coupled to the first source / drain region. The second capacitor electrodes of a plurality of the capacitors in the array are electrically coupled to each other. A word line structure extends vertically through the insulating material and the memory cells of the vertically alternating layers. Individuals of the gates of different ones of the memory cell layers are directly electrically coupled to individual ones of the word line structure. A capacitor-electrode structure extends vertically through the vertically alternating layers. Individuals of the second electrodes of individual ones of the capacitors in different memory cell layers are electrically coupled to the vertically extending capacitor-electrode structure. A sense line is electrically coupled to a plurality of the second source / drain regions of the individual ones of the transistors.

[0054] In some embodiments, a memory array includes vertically alternating layers of insulating material and memory cells. The memory cells individually include transistors, the transistors including first and second source / drain regions with a channel region therebetween, and gates operatively proximate to the channel regions. The individual memory cells include capacitors, the capacitors including first and second electrodes with a capacitor insulator therebetween. The first electrode is electrically coupled to the first source / drain region. The second capacitor electrodes of a plurality of the capacitors in the array are electrically coupled to each other. Horizontally extending sense lines are in individual ones of the memory cell layers. Individual ones of the second source / drain regions in individual memory cell layers are electrically coupled to individual ones of the horizontally extending sense lines in corresponding individual memory cell layers. A capacitor-electrode structure extends vertically through the vertically alternating layers. Individual ones of the second electrodes in individual ones of the capacitors of different ones of the memory cell layers are electrically coupled to the vertically extending capacitor-electrode structure. A word line electrically couples together a plurality of the gates of the individual ones of the transistors.

[0055] In some embodiments, a memory array includes vertically alternating layers of insulating material and memory cells. The memory cells individually include transistors, the transistors including first and second source / drain regions with a channel region therebetween, and gates operatively proximate to the channel regions. The individual memory cells include capacitors, the capacitors including first and second electrodes with a capacitor insulator therebetween. The first electrode is electrically coupled to the first source / drain region. The second capacitor electrodes of a plurality of the capacitors in the array are electrically coupled to each other. Horizontally extending sense lines are in individual ones of the memory cell layers. Individual ones of the second source / drain regions in individual memory cell layers are electrically coupled to individual ones of the horizontally extending sense lines in corresponding individual memory cell layers. A capacitor-electrode structure extends vertically through the vertically alternating layers. Individual ones of the second electrodes in individual ones of the capacitors of different ones of the memory cell layers are electrically coupled to the vertically extending capacitor-electrode structure. A word line electrically couples together a plurality of the gates of the individual ones of the transistors.

Claims

1. A memory structure comprising: A memory cell hierarchical stack, wherein individual memory cells of the stack include: a transistor comprising first and second source / drain regions having a channel region therebetween and comprising a gate operatively proximate to the channel region; and a capacitor comprising first and second electrodes, the first electrode being electrically coupled to the first source / drain region; a conductive pillar extending vertically through a plurality of said memory cell levels, said gates of a plurality of said memory cells included in said stack being directly electrically coupled to said conductive pillar; and A conductive line structure extends horizontally within each memory cell level, the conductive line structure electrically coupling the second source / drain regions of a plurality of the transistors within the memory cell level stack.

2. The memory structure of claim 1 wherein at least a portion of the channel region is horizontally oriented for horizontal current flow in a portion between the first and second source / drain regions.

3. The memory structure of claim 2 wherein only a portion of the channel region is horizontally oriented for horizontal current flow in the portion between the first and second source / drain regions.

4. The memory structure according to claim 1, wherein: The first electrode is electrically coupled directly to the first source / drain region; and The conductive line structure is directly electrically coupled to the second source / drain regions of the plurality of the transistors.

5. The memory structure of claim 1, wherein the second electrodes of a plurality of the capacitors in the memory structure are electrically coupled to each other.

6. The memory structure of claim 5, comprising vertically extending walls that are horizontally elongated and electrically couple the second electrodes of the plurality of capacitors directly to one another.

7. The memory structure of claim 5, comprising a plurality of pillar structures electrically coupling the second electrodes of the plurality of the capacitors directly to each other.

8. The memory structure of claim 1, wherein the gate comprises an annular region circumferentially surrounding the pillar and protruding radially.

9. The memory structure of claim 1 wherein the channel region comprises opposing C-shapes facing each other in a straight vertical cross-section.

10. The memory structure of claim 1, wherein the pillar structure is electrically coupled directly to a horizontal longitudinally extending line above or below the stack.

11. The memory structure of claim 1 wherein one of the first and second source / drain regions is above the other.

12. The memory structure of claim 11, wherein the one is directly above the other.

13. The memory structure of claim 11, wherein the second source / drain region is above the first source / drain region.

14. The memory structure of claim 11, wherein the first source / drain region is above the second source / drain region.

15. A memory structure comprising: a first conductive structure extending vertically above the substrate, the first conductive structure including transistor gate regions of a plurality of memory cells; a second conductive structure extending vertically above the substrate, the second conductive structure electrically coupling electrodes of a capacitor of each of the plurality of memory cells to each other; A plurality of horizontally extending conductive structures, the horizontally extending conductive structures comprising the plurality of horizontally extending conductive structures being vertically stacked, each of the horizontally extending conductive structures being electrically associated with a single memory cell comprising the plurality of memory cells.

16. The memory structure of claim 15, wherein the capacitor electrode is a first capacitor electrode, wherein the capacitor further comprises a second electrode electrically coupled to a first source / drain region; and A second source / drain region is electrically coupled directly to one of the horizontally extending conductive structures.

17. The memory structure of claim 15, wherein the first conductive structure comprises a vertical pillar and comprises a plurality of horizontal protrusions stacked vertically along the vertical pillar, each of the protrusions constituting the gate region of an individual transistor. The memory structure of claim 17 , wherein each protrusion completely surrounds the pillar.

19. The memory structure of claim 18 wherein each of the individual transistors comprises a channel region between first and second source / drain regions, wherein the channel region extends above and below the gate region.

20. The memory structure of claim 15 wherein the horizontally extending conductive structures include end-to-end overlapping interconnected ring structures.

21. A memory structure comprising: a plurality of memory cells stacked vertically above a substrate, each of the memory cells comprising; a transistor comprising first and second source / drain regions having a channel region therebetween and a gate operatively proximate to the channel region; as well as a capacitor comprising first and second electrodes with a capacitor insulator therebetween, the first electrode being electrically coupled to the first source / drain region; a conductive structure extending vertically above the substrate, all of the gates included in the plurality of memory cells being directly electrically coupled to the conductive structure; as well as A plurality of horizontally extending line structures are stacked vertically above the substrate, each of the plurality of horizontally extending line structures being associated with a single memory cell included in the plurality of memory cells and electrically coupled to the second source / drain region of the single memory cell.

22. The memory structure of claim 21, wherein the conductive structure comprises a conductive pillar, and wherein all of the gates surround the conductive pillar.

23. The memory structure of claim 21, wherein the transistor is disposed directly above the capacitor in each of the memory cells.

24. The memory structure of claim 23, wherein the plurality of horizontally-extending line structures comprises each horizontally-extending line structure disposed directly above the capacitor of an associated memory cell.

25. A memory array comprising a plurality of the memory structure of claim 21.

26. The memory array of claim 25 including a vertically extending electrode structure electrically coupling second electrodes of a plurality of memory cells within the array.

27. The memory array of claim 26 wherein the vertically extending electrode structures are electrically coupled directly to horizontally elongated conductive structures above or below the plurality of the memory structures.

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