Manufacturing of Memory Cells for 3D NAND Applications

Abstract

Embodiments of the present disclosure provide an apparatus and method for forming a stepped structure with precise profile and dimension control for manufacturing a three-dimensional (3D) stacked memory cell semiconductor device. In one embodiment, a memory cell device includes: a film stack including an alternating pair of dielectric layers and conductive structures formed horizontally on a substrate; and an opening formed in the film stack, wherein the opening is filled with a metal dielectric layer, a multi-layer structure, and a central fill layer, and wherein the metal dielectric layer in the opening is interfacially connected to the conductive structure.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to methods for fabricating vertical memory cell semiconductor devices, and more particularly to methods for fabricating vertical memory cell semiconductor devices having a stair-like structure for semiconductor manufacturing applications. Background Art

[0002] For next-generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices, reliably producing sub-halfmicron and smaller features is one of the key technical challenges. However, as the limits of circuit technology continue to advance, the shrinking of VLSI and ULSI interconnect technologies places additional requirements on processing capabilities. Reliably forming a gate structure on a substrate is crucial for the success of VLSI and ULSI and for the ongoing efforts to increase circuit density and the quality of individual substrates and dies.

[0003] Patterning masks (such as photoresist layers) are typically used to form structures (such as gate structures, shallow trench isolation (STI), bite lines, and the like) on a substrate by an etching process. Patterning masks are conventionally fabricated by optically transferring a pattern having a desired critical dimension to a photoresist layer using a lithography process. The photoresist layer is then developed to remove the undesired portions of the photoresist, thereby creating openings in the remaining photoresist.

[0004] To enable the fabrication of next-generation devices and structures, three-dimensional (3D) stacking of semiconductor memory chips is generally utilized to improve transistor performance. By arranging transistors in three-dimensional dimensions instead of traditional two-dimensional dimensions, multiple transistors can be placed very close to each other in an integrated circuit (IC). Three-dimensional (3D) stacking of semiconductor chips can reduce wire lengths and maintain a low wiring delay. In fabricating three-dimensional (3D) stacks of semiconductor chips, a stair-like structure is generally utilized to allow multiple interconnect structures to be disposed thereon, thereby forming a high-density vertical transistor device.

[0005] When forming a stepped structure in a film stack disposed on a substrate, an etching process and a photoresist trimming process are repeatedly performed to etch the film stack using a sequentially trimmed photoresist layer as an etching mask. In the exemplary embodiment depicted in FIG. 1A, a trimmed photoresist layer (not shown) can be used as an etching mask layer to transfer a structure onto a film stack 120 disposed on a substrate 104 to form a stepped structure 110 on the substrate 104 for forming a semiconductor device 100. The film stack 120 generally includes alternating layers of layers 120a, 120b (shown as 120a1, 120b1, 120a2, 120b2, ……, 120a5, 120b5), whether conductive or insulating layers, as shown in FIG. 1B. During etching, the photoresist layer is sequentially trimmed to different sizes while serving as an etching mask to form a stepped structure 110 having different widths.

[0006] During the fabrication of the stepped structure 110 on the substrate 104, each step formed in the stepped structure 110 has its intended width to allow a channel (e.g., an opening) 125 to be formed thereon, as shown in FIGS. 1A and 1B. In some embodiments where higher device performance is required, alternating layers 120a, 120b of different materials can be utilized. For example, when higher electromigration performance of the device is required, a metal conductive material is typically used in the stepped structure 110. In one example, the second layer 120b of the alternating layers 120a, 120b (shown as 120b1, ……, 120b5 in FIG. 1B) can be removed from the stepped structure 110 and replaced with a metal-containing layer 150, as depicted in FIG. 1C, to improve the electrical performance of the device 100. However, when the original second layer 120b (shown as 120b1, ……, 120b5 in FIG. 1B) is removed from the stepped structure 110 to replace or insert a metal-containing layer 150 as depicted in FIG. 1C, residues and / or surface roughness 152 are often found at the interface 130 between the metal-containing layers 150 due to the etching selectivity at the interface, resulting in poor electrical contact at the interface 130 and ultimately leading to device failure or a decrease in electrical performance.

[0007] Accordingly, there is a need for improved methods and apparatuses for forming stepped structures with precise profile and dimension control for three-dimensional (3D) stacking of semiconductor devices. SUMMARY OF THE INVENTION

[0008] Embodiments of the present disclosure provide an apparatus and method for forming a stepped structure with precise profile and dimensional control for manufacturing a three-dimensional (3D) stacked memory cell semiconductor device. In one embodiment, a memory cell device includes: a film stack including an alternating pair of dielectric layers and conductive structures horizontally formed on a substrate; and an opening formed in the film stack, wherein the opening is filled with a metal dielectric layer, a multi-layer structure, and a central fill layer, and wherein the metal dielectric layer in the opening is interfaced with the conductive structure.

[0009] In another embodiment, a method of forming a memory device on a substrate includes the steps of: forming an opening in a film stack including a first layer and a second layer; selectively oxidizing the first layer to form an oxide layer on sidewalls of the first layer; filling the opening with one or more layers including a metal dielectric layer; selectively removing the first layer from the film stack to expose the oxide layer; selectively removing the oxide layer from the film stack to define a space in the film stack; and filling the space with a conductive structure.

[0010] In yet another embodiment, a method of forming a stepped structure on a substrate includes the steps of: selectively oxidizing a first layer in a film stack including a first layer and a second layer; forming a metal dielectric layer in contact with the oxide layer; selectively removing the first layer to expose the oxide layer; removing the oxide layer from the film stack; and forming a conductive structure in contact with the metal dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to understand in detail the manner in which the above-recited features of the present disclosure can be obtained, a more particular description of the disclosure briefly summarized above may be had by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

[0012] FIG. 1A depicts a schematic cross-sectional view of a conventional stepped structure formed on a substrate;

[0013] FIGS. 1B and 1C depict partial schematic cross-sectional views of the conventional stepped structure formed on the substrate of FIG. 1A;

[0014] Figure 2 Depicts an apparatus for forming a metal-containing layer on a substrate in a stepped structure according to one embodiment of the present disclosure;

[0015] Figure 3 Depicts an apparatus for forming a stepped structure on a substrate according to one embodiment of the present disclosure;

[0016] Figure 4depicts a schematic diagram of a cluster processing system for a device including Figure 2 and Figure 3 ; a flowchart of a method for forming a memory cell structure on a substrate in accordance with an embodiment of the present disclosure; and

[0017] Figure 5 depicts a flowchart of a method for forming a memory cell structure on a substrate in accordance with an embodiment of the present disclosure; and

[0018] Figures 6A - 6B , Figure 7 , Figures 8A - 8B , Figures 9A - 9B , Figures 10A - 10B , Figures 11A - 11B , Figures 12A - 12B , Figures 13A - 13C and Figures 14A - 14C depicts the sequence for fabricating a memory cell structure formed on a substrate in accordance with the embodiment depicted by Figure 5 .

[0019] For ease of understanding, the same reference numerals are used, where possible, to denote the same elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0020] However, it should be noted that only exemplary embodiments of the present disclosure are shown in the figures and thus should not be taken as limiting its scope, as the present disclosure may admit other equivalent embodiments. DETAILED DESCRIPTION

[0021] The present disclosure provides a method for forming a stepped structure on a substrate for three-dimensional (3D) memory cells of a semiconductor device. In one example, good interface management, excellent electrical properties, and good process control during fabrication can be obtained by utilizing a protective oxide layer (e.g., a sacrificial oxide layer) at an interface, as well as selective deposition and selective patterning / etching processes. In one example, a method for forming a memory cell for a three-dimensional (3D) stacked semiconductor device can utilize a protective / sacrificial oxide layer when removing a certain type of material from a film stack to form a stepped structure. Thus, during the removal process, the interface can remain protected and intact, providing good control of the interface profile and topography. As a result, when a conductive structure is subsequently formed therein, good electrical contact can be obtained at the interface, thereby providing the desired electrical properties for the memory cell.

[0022] Figure 2is a cross-sectional view of a plasma processing chamber 232 suitable for performing plasma deposition processes (e.g., plasma-enhanced CVD or metal-organic CVD), which can be used as a semiconductor interconnect structure in semiconductor device manufacturing. The processing chamber 232 can be a suitable SE or GT or XP processing system. It is expected that other processing systems (including those produced by other manufacturers) can benefit from the embodiments described herein.

[0023] The processing chamber 232 includes a chamber body 251. The chamber body 251 includes a lid 225, a sidewall 201, and a bottom wall 222 that define an internal volume 226.

[0024] A substrate support pedestal 250 is provided in the internal volume 226 of the chamber body 251. The pedestal 250 can be made of aluminum, ceramic, aluminum nitride, and other suitable materials. In one embodiment, the pedestal 250 is made of a ceramic material (such as aluminum nitride), which is a material suitable for use in high-temperature environments (such as plasma processing environments) without causing thermal damage to the pedestal 250. A lifting mechanism (not shown) can be used to move the pedestal 250 vertically inside the chamber body 251.

[0025] The pedestal 250 can include an embedded heater element 270 adapted to control the temperature of the substrate 290 supported on the pedestal 250. In one embodiment, the pedestal 250 can be resistively heated by applying current from a power supply 206 to the heater element 270. In one embodiment, the heater element 270 can be made of nickel-chromium wire encapsulated in a nickel-iron-chromium alloy (such as ). The current supplied from the power supply 206 is regulated by a controller 210 to control the heat generated by the heater element 270, so as to maintain the substrate 290 and the pedestal 250 at a substantially constant temperature within any suitable temperature range during film deposition. In another embodiment, the pedestal can be maintained at room temperature as needed. In yet another embodiment, the pedestal 250 can also include a cooler (not shown) as needed to cool the pedestal 250 to a range lower than room temperature as needed. The supplied current can be adjusted to selectively control the temperature of the pedestal 250 between about 100 degrees Celsius and about 700 degrees Celsius.

[0026] A temperature sensor 272 (such as a thermocouple) can be embedded in the substrate support pedestal 250 to monitor the temperature of the pedestal 250 in a conventional manner. The controller 210 uses the measured temperature to control the power supplied to the heater element 270 to maintain the substrate at the desired temperature.

[0027] The susceptor 250 generally includes a plurality of lift pins (not shown) disposed therethrough, which are configured to lift and lower the substrate 290 from the susceptor 250 and facilitate the exchange of the substrate 290 with a robot (not shown) in a conventional manner.

[0028] The susceptor 250 includes at least one electrode 292 for holding the substrate 290 on the susceptor 250. The electrode 292 is driven by a chucking power source 208 to generate an electrostatic force that holds the substrate 290 to the susceptor surface, as is well known. Alternatively, the substrate 290 can be held to the susceptor 250 by clamping, vacuum, or gravity.

[0029] In one embodiment, the susceptor 250 is configured to have a cathode with an electrode 292 embedded therein, and the electrode 292 is coupled to at least one RF bias power source, shown as two RF bias power sources 284, 286 in Figure 2 . Although the example depicted in Figure 2 shows two RF bias power sources 284, 286, it should be noted that the number of RF bias power sources can be any number as needed. The RF bias power sources 284, 286 are coupled between the electrode 292 disposed in the susceptor 250 and another electrode, such as the gas distribution plate 242 or the lid 225 of the processing chamber 232. The RF bias power sources 284, 286 excite and sustain a plasma discharge formed by the gas in the processing region of the processing chamber 232.

[0030] In Figure 2 the depicted embodiment, the dual RF bias power sources 284, 286 are coupled to the electrode 292 disposed in the susceptor 250 through a matching circuit 204. The signals generated by the RF bias power sources 284, 286 are fed through the matching circuit 204 to the susceptor 250 by a single feed to ionize the gas mixture provided in the plasma processing chamber 232, thereby providing the ion energy required to perform deposition or other plasma-enhanced processes. The RF bias power sources 284, 286 are generally capable of generating RF signals having a frequency ranging from about 50 kHz to about 200 MHz and a power between about 0 watts and about 5000 watts.

[0031] A vacuum pump 202 is coupled to a port formed in the bottom 222 of the chamber body 251. The vacuum pump 202 is used to maintain a desired gas pressure in the chamber body 251. The vacuum pump 202 also evacuates post-treatment gases and processing by-products from the chamber body 251.

[0032] The processing chamber 232 includes one or more gas delivery channels 244 coupled through a lid 225 of the processing chamber 232. The gas delivery channels 244 and the vacuum pump 202 are located at opposite ends of the processing chamber 232 to induce laminar flow within the internal volume 226 to minimize particle contamination.

[0033] The gas delivery channels 244 are coupled to a gas panel 293 through a remote plasma source (RPS) 248 to supply a gas mixture into the internal volume 226. In one embodiment, the gas mixture supplied through the gas delivery channels 244 may be further delivered through a gas distribution plate 242 disposed below the gas delivery channels 244. In one example, the gas distribution plate 242 having a plurality of holes 243 is coupled to the lid 225 of the chamber body 251 above the susceptor 250. The holes 243 of the gas distribution plate 242 are used to introduce the processing gas from the gas panel 293 into the chamber body 251. The holes 243 may have different sizes, numbers, distributions, shapes, designs, and diameters to facilitate the flow of various processing gases for different processing requirements. Plasma is formed from the processing gas mixture exiting the gas distribution plate 242 to enhance the thermal decomposition of the processing gas, resulting in material deposition on the surface 291 of the substrate 290.

[0034] The gas distribution plate 242 and the substrate support susceptor 250 may form a pair of spaced-apart electrodes within the internal volume 226. One or more RF sources 247 provide a biasing potential to the gas distribution plate 242 through a matching network 245 to facilitate the generation of plasma between the gas distribution plate 242 and the susceptor 250. Alternatively, the RF source 247 and the matching network 245 may be coupled to the gas distribution plate 242, the substrate support susceptor 250, or both the gas distribution plate 242 and the substrate support susceptor 250, or to an antenna (not shown) disposed outside the chamber body 251. In one embodiment, the RF source 247 may provide between about 10 watts and about 3000 watts at a frequency of about 30 kHz to about 13.6 MHz. Alternatively, the RF source 247 may be a microwave generator that provides microwave power to the gas distribution plate 242, and the microwave power helps to generate plasma within the internal volume 226.

[0035] Examples of gases that may be supplied from the gas panel 293 may include silicon-containing gases, fluorine-containing gases, oxygen-containing gases, hydrogen-containing gases, inert gases, and carrier gases. Suitable examples of reactive gases include silicon-containing gases (such as SiH4, Si2H6, SiF4, SiH2Cl2, Si4H 10 、Si5H 12 、TEOS, and the like). Suitable carrier gases include nitrogen (N2), argon (Ar), hydrogen (H2), alkanes, alkenes, helium (He), oxygen (O2), ozone (O3), water vapor (H2O), and the like.

[0036] In one embodiment, a remote plasma source (RPS) 248 may alternatively be coupled to the gas delivery channel 244 to assist in forming a plasma from the gas supplied from the gas panel 293 into the internal volume 226. The remote plasma source 248 supplies the plasma formed from the gas mixture provided by the gas panel 293 to the processing chamber 232.

[0037] The controller 210 includes a central processing unit (CPU) 212, a memory 216, and support circuitry 214 for controlling the processing sequence and regulating the gas flow from the gas panel 293. The CPU 212 may be any form of general-purpose computer processor that can be used in an industrial environment. Software programs may be stored in the memory 216 (such as random access memory, read-only memory), a floppy disk, or a hard disk drive, or other forms of digital memory. The support circuitry 214 is coupled to the CPU 212 in a conventional manner and may include a cache, a clock circuit, an input / output system, a power supply, and the like. Bidirectional communication between the controller 210 and the various components of the processing chamber 232 is handled by a number of signal cables collectively referred to as a signal bus 218, some of which are as Figure 2 shown.

[0038] Figure 3 is a simplified cross-sectional view of an exemplary processing chamber 300 for etching a metal layer. The exemplary processing chamber 300 is adapted to remove one or more film layers from a substrate 290. An example of a processing chamber that may be adapted to benefit from the present invention is the AdvantEdge Mesa Etch processing chamber available from Applied Materials, Inc. of Santa Clara, California. It is contemplated that other processing chambers (including those from other manufacturers) may be adapted to practice the embodiments of the present invention.

[0039] The processing chamber 300 includes a chamber body 305, within which a chamber volume 301 is defined. The chamber body 305 has a sidewall 312 and a bottom 318 that are coupled to ground 326. The sidewall 312 has a liner 315 to protect the sidewall 312 and extend the time between maintenance cycles of the processing chamber 300. The dimensions of the chamber body 305 and the associated components of the processing chamber 300 are not limited and are generally proportionally larger than the size of the substrate 290 to be processed therein. Examples of substrate sizes include a diameter of 200 mm, a diameter of 250 mm, a diameter of 300 mm, a diameter of 450 mm, and others.

[0040] The chamber body 305 supports the chamber lid assembly 310 to enclose the chamber volume 301. The chamber body 305 can be made of aluminum or other suitable materials. The substrate entry port 313 is formed through the sidewall 312 of the chamber body 105 to facilitate the transfer of the substrate 290 in and out of the processing chamber 300. The entry port 313 can be coupled to a transfer chamber and / or other chambers of the substrate processing system (not shown).

[0041] The pumping port 345 is formed through the sidewall 312 of the chamber body 305 and is connected to the chamber volume 301. A pumping device (not shown) is coupled to the chamber volume 301 through the pumping port 345 to evacuate and control the pressure therein. The pumping device can include one or more pumps and throttle valves.

[0042] The gas panel 360 is coupled to the chamber body 305 via a gas line 367 to supply process gases into the chamber volume 301. The gas panel 360 can include one or more process gas sources 361, 362, 363, 364, and, if needed, can also include inert gases, non-reactive gases, and reactive gases. Examples of process gases that the gas panel 360 can supply include (but are not limited to) hydrocarbon-containing gases (including methane (CH4)), sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), hydrogen bromide (HBr), hydrocarbon-containing gases, argon (Ar), chlorine (Cl2), nitrogen (N2), and oxygen (O2). In addition, the process gases can include chlorine-containing gases, fluorine-containing gases, oxygen-containing gases, and hydrogen-containing gases, such as BCl3, C4F8, C4F6, CHF3, CH2F2, CH3F, NF3, CO2, SO2, CO, and H2, etc.

[0043] The valve 366 controls the flow rate of the process gases from the sources 361, 362, 363, 364 of the gas panel 360 and is managed by the controller 365. The flow rate of the gases supplied from the gas panel 360 to the chamber body 305 can include a combination of gases.

[0044] The lid assembly 310 may include a nozzle 314. The nozzle 314 has one or more ports for introducing process gases from sources 361, 362, 364, 363 of a gas panel 360 into the chamber volume 301. After the process gases are introduced into the processing chamber 300, the gases are energized to form a plasma. An antenna 348, such as one or more induction coils, may be provided near the processing chamber 300. The antenna power supply 342 may power the antenna 348 through a matching circuit 341 to inductively couple energy, such as RF energy, to the process gases to maintain the plasma formed by the process gases in the chamber volume 301 of the processing chamber 300. Alternatively, or in addition to the antenna power supply 342, processing electrodes below and / or above the substrate 290 may be used to capacitively couple RF power to the process gases to maintain the plasma within the chamber volume 301. The operation of the antenna power supply 342 may be controlled by a controller, such as controller 365, which also controls the operation of other components in the processing chamber 300.

[0045] The substrate support base 335 is disposed in the chamber volume 301 to support the substrate 290 during processing. The substrate support base 335 may include an electrostatic chuck 322 for holding the substrate 290 during processing. The electrostatic chuck (ESC) 322 holds the substrate 290 to the substrate support base 335 using electrostatic attraction. The ESC 322 is powered by an RF power supply 325 integrated with a matching circuit 324. The ESC 322 includes an electrode 321 embedded within a dielectric body. The RF power supply 325 may provide an RF chucking voltage of from about 200 volts to about 2000 volts to the electrode 321. The RF power supply 325 may also include a system controller for controlling the operation of the electrode 321 by directing a DC current to the electrode 321 for chucking and de-chucking the substrate 290.

[0046] The ESC 322 may also include an electrode 351 disposed therein. The electrode 351 is coupled to a power source 350 and provides a bias voltage that attracts plasma ions formed by the process gases in the chamber volume 301 to the ESC 322 and the substrate 290 located thereon. The power source 350 may be cycled on and off, or pulsed, during processing of the substrate 290. The ESC 322 has an isolator 328, the purpose of which is to make the sidewalls of the ESC 322 less attractive to the plasma, thereby extending the maintenance life cycle of the ESC 322. Additionally, the substrate support base 335 may have a cathode lining 336 to protect the sidewalls of the substrate support base 335 from the plasma gases and extend the time between maintenance of the processing chamber 300.

[0047] The ESC 322 may include a heater disposed therein, and the heater is connected to a power source (not shown) for heating the substrate. The cooling base 329 that supports the ESC 322 may include conduits for circulating a heat transfer fluid to maintain the temperature of the ESC 322 and the substrate 290 disposed thereon. The ESC 322 is configured to operate within a temperature range required by the thermal budget of the device fabricated on the substrate 290. For example, for some embodiments, the ESC 322 may be configured to maintain the substrate 290 at a temperature of from about minus 25 degrees Celsius to about 500 degrees Celsius.

[0048] The cooling base 329 is provided to assist in controlling the temperature of the substrate 290. To mitigate process drift and time, the temperature of the substrate 290 may be held substantially constant by the cooling base 329 throughout the time the substrate 290 is in the processing chamber 300. In one embodiment, the temperature of the substrate 290 is held at from about 70 to 90 degrees Celsius throughout a subsequent etching process.

[0049] The cover ring 330 is disposed on the ESC 322 and along the periphery of the substrate support base 335. The cover ring 330 is configured to confine the etch gas to a desired portion of the exposed top surface of the substrate 290 while shielding the top surface of the substrate support base 335 from the plasma environment inside the processing chamber 300. Lift pins (not shown) selectively move through the substrate support base 335 to lift the substrate 290 above the substrate support base 335 to facilitate access to the substrate 290 by a transfer robot (not shown) or other suitable transfer mechanism.

[0050] The controller 365 may be used to control the processing sequence, regulate the gas flow rate into the processing chamber 300 from the gas panel 360, and other processing parameters. The software program (when executed by the CPU) converts the CPU into a dedicated computer (controller) for controlling the processing chamber 300 such that processing is performed in accordance with the present invention. The software program may also be stored and / or executed by a second controller (not shown) juxtaposed to the processing chamber 300.

[0051] The substrate 290 has various film layers disposed thereon, and the various film layers may include at least one metal layer. The various film layers may require an etching recipe that is unique for the different compositions of the other film layers in the substrate 290. Multilevel interconnects, which are at the core of VLSI and ULSI technologies, may require the fabrication of high aspect ratio features such as vias and other interconnects. Fabricating the multilevel interconnects may require one or more etching recipes to form patterns in the various film layers. These recipes may be executed in a single etching processing chamber or via a number of etching processing chambers. Each etching processing chamber may be configured to perform etching using one or more etching recipes. In one embodiment, the processing chamber 300 is configured to etch at least the metal layer to form a conductive structure. For the processing parameters provided herein, the processing chamber 300 is configured to process a substrate having a diameter of 300, i.e., a substrate having a planar area of approximately 0.0707 m 2 The planar area of the substrate. Processing parameters such as flow rate and power can generally be scaled proportionally with changes in chamber volume or substrate planar area.

[0052] Figure 4 A plan view of a semiconductor processing system 400 that can practice the methods described herein is depicted. One processing system that can benefit from the present invention is a 300 mm or 450 mm processing system, which can be purchased from Applied Materials, Inc. of Santa Clara, California. The processing system 400 generally includes a front end platform 402 where a substrate cassette 418 included in a FOUP 414 is supported and substrates are loaded into and unloaded from a load lock chamber 409; a transfer chamber 411 that houses a substrate handler 413 and a series of tandem processing chambers 406 mounted on the transfer chamber 411.

[0053] Each of the tandem processing chambers 406 includes two processing regions for processing substrates. The two processing regions share a common gas supply, a common pressure control, and a common process gas exhaust / pumping system. The modular design of the system enables rapid conversion from one configuration to any other configuration. To perform a specific processing step, the arrangement and combination of the chambers can be changed. Any of the tandem processing chambers 406 can include a lid according to aspects of the present invention as described below, the lid including one or more chamber configurations described above with reference to Figure 2 and / or Figure 3 The processing chambers 232, 300 depicted in. It should be noted that the processing system 400 can be configured to perform deposition processing, etching processing, curing processing, or heating / annealing processing as needed. In one embodiment, the processing chambers 232, 300 (shown as Figure 2and Figure 3 is incorporated into semiconductor processing system 400 in combination with the single chamber designed therein.

[0054] In one embodiment, processing system 400 may be adapted to one or more tandem processing chambers having support chamber hardware known to be adaptable to a variety of other known processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, curing, or heating / annealing, and the like. For example, system 400 may be configured with Figure 2 one of the processing chambers 232 in as a plasma deposition chamber for depositing (such as a metal film), or Figure 3 one of the processing chambers 300 depicted in as a plasma etching chamber for etching a material layer formed on a substrate. Such a configuration can maximize the utilization of research and development manufacturing and, if needed, eliminate exposure to the atmosphere when the film is etched.

[0055] Controller 440 (including central processing unit (CPU) 444, memory 442, and support circuitry 446) is coupled to the various components of semiconductor processing system 400 to facilitate control of the processes of the present invention. Memory 442 can be any computer-readable medium (such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of digital memory) local or remote to semiconductor processing system 400 or CPU 444. Support circuitry 446 is coupled to CPU 444 to support the CPU in a conventional manner. These circuits include cache memory, power supplies, clock circuits, input / output circuits and subsystems, and the like. When executed by CPU 444, the software programs or series of program instructions stored in memory 442 execute the tandem processing chamber 406.

[0056] Figure 5 is a flowchart of one embodiment of method 500 for forming a memory cell structure in a film stack disposed on a substrate. The method can be performed in a processing chamber (such as the processing chambers 232 depicted in incorporated into system 400 and Figure 2 the processing chamber 300 depicted in and Figure 3 other suitable processing chambers and systems as needed). Figures 6A - 6B , Figure 7 , Figures 8A - 8B , Figures 9A - 9B , Figures 10A - 10B , Figures 11A - 11B , Figures 12A - 12B , Figures 13A - 13B and Figures 14A - 14Bis a schematic cross-sectional view showing the sequence for forming a memory cell structure in a film stack disposed on a substrate according to method 500. Although method 500 will be described below with reference to a substrate for manufacturing a memory cell structure in a film stack of a three-dimensional semiconductor device, method 500 can also be used profitably in other device manufacturing applications.

[0057] Method 500 begins at operation 502 by providing a substrate (such as substrate 602 on which a film stack 604 is formed), as Figure 6A shown. Substrate 602 can be a silicon-based material or any suitable insulating or conductive material as needed, with a film stack 604 disposed on substrate 602, and film stack 604 can be used to form a memory cell structure in film stack 604.

[0058] As Figure 6A shown in the exemplary embodiment depicted, substrate 602 can have a substantially flat surface, an uneven surface, or a substantially flat surface with structures formed thereon. Film stack 604 is formed on substrate 602. In one embodiment, film stack 604 can be used in front-end or back-end processing to form gate structures, contact structures, or interconnect structures. Method 500 can be formed on film stack 604 to form a stepped structure in it for a memory cell structure (such as, a VNAND structure). In one embodiment, substrate 602 can be a material such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned silicon-on-insulator wafers (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire. Substrate 602 can have various sizes, such as wafers with diameters of 200mm, 300mm, 450mm, or other diameters, as well as rectangular or square panels. Unless otherwise stated, the embodiments and examples described herein are carried out on substrates with substrates having diameters of 200mm, 300mm, 450mm. In embodiments where an SOI structure is used for substrate 602, substrate 602 can include a buried dielectric layer disposed on a silicon crystal substrate. In the embodiments described herein, substrate 602 can be a crystalline silicon substrate.

[0059] In one embodiment, the film stack 604 disposed on substrate 600 can have a film stack 604 with multiple vertically stacked layers. Film stack 604 can include pairs, and the pairs include a first layer 604a and a second layer 604b that are repeatedly formed in film stack 604. The pairs include repeatedly formed alternating first layer 604a and second layer 604b until a desired number of pairs of the first and second layers is reached.

[0060] The membrane stack 604 is part of a memory cell device, such as a three-dimensional (3D) memory device. Although eleven repeating layers of the first layer 604a and the second layer 604b are shown in Figure 6A , it should be noted that any desired number of repeating pairs of the first and second layers can be used as needed.

[0061] In one embodiment, the membrane stack 604 can be used to form multiple gate structures of a three-dimensional (3D) memory device. The first layer 604a formed in the membrane stack 604 can be a first dielectric layer, and the second layer 604b can be a second dielectric layer. Suitable dielectric layers can be utilized to form the first layer 604a and the second layer 604b, including silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, titanium nitride, composites of oxides and nitrides, at least one or more oxide layers sandwiching a nitride layer, and combinations thereof, etc.

[0062] In a specific example, the first layer 604a is a silicon nitride layer, and the second layer 604b is a silicon oxide layer or a polysilicon layer. In one embodiment, the thickness of the first layer 604a can be controlled between about and about , such as about and the thickness of each second layer 604b can be controlled between about and about , such as about The total thickness of the membrane stack 604 is about 3 microns to 10 microns and will vary with the development of technology.

[0063] A membrane stack 604 of a first layer 604a of silicon nitride layer and a second layer 604b of silicon oxide layer is formed on the substrate 602. The membrane stack 604 is formed and patterned into a stepped structure surrounded by an insulating structure 610. A hard mask layer 608 can be formed on the membrane stack 604 to facilitate the formation of an opening 606 (e.g., also referred to as a trench, via, hole, or aperture) in the membrane stack 604. When the manufacturing process is completed, the opening 606 can be utilized to form a channel in the device structure. After forming the opening 606 in the membrane stack 604, an epitaxial deposition process is performed to grow silicon-containing pillars 612 (such as silicon material or SiGe material) in the bottom portion of the opening 606. It should be noted that for different device performance requirements, the device structure and configuration can be changed as needed.

[0064] Figure 6B An enlarged view of a part of the membrane stack 604 is depicted, as indicated by the circle, depicting the opening 606 surrounded by the first layer 604a and the second layer 606b. For ease of explanation, an enlarged view of the membrane stack 604 will be utilized in the following description instead of Figure 6AOverall cross-sectional view of the membrane stack 604 depicted therein.

[0065] At operation 503, a control layer or an etch stop layer 702 may optionally be formed in the opening 606, as Figure 7 shown. When removing the first layer 604a from the membrane stack 604, the control layer / etch stop layer 702 can assist in interface management during subsequent etching or removal processes. The control layer / etch stop layer 702 is in direct contact with the first layer 604a and the second layer 604b through the sidewalls 704a, 704b exposed by the opening 606. The control layer / etch stop layer 702 can prevent the aggressive etchant from sneaking into the opening 606 during subsequent etching processes, thereby undesirably attacking the structures or film layers formed in the opening 606 subsequently. In one embodiment, the control layer / etch stop layer 702 may be formed of an insulating material (such as SiN, SiON, or other suitable materials). The control layer 702 may have a thin thickness less than . In embodiments where there is no control layer 702, the following layers described in the following operations may be directly formed in the opening 606, being in direct contact with the sidewalls 704a, 704b of the first layer 604a and the second layer 604b respectively.

[0066] At operation 504, a selective oxidation process is performed to selectively oxidize the first layer 604a from the sidewall 704a in the opening 606, as Figure 8A and Figure 8B shown, thereby forming an oxide layer 802. Figure 8A The example depicted in Figure 8B shows the presence of the control layer 702 in the opening 606, while the example depicted in

[0067] shows the absence of the control layer 702 in the opening 606. The following figures marked with "A" at the end show cross-sectional views in various cases of the process with the control layer 702 present in the opening 606, and the following figures marked with "B" at the end show cross-sectional views in various cases of the process with the control layer 702 absent in the opening 606. In some figures, some element symbols of the components or features shown herein may be omitted to avoid confusing other components or features; this is for the convenience of depicting each figure.

[0067] It should be noted that then forming the control layer / etch stop layer 702 (especially when forming the etch stop layer), the oxide layer 802 can be removed, because the etch stop layer itself can be used as a barrier layer providing high etch selectivity to prevent the aggressive etchant from sneaking into the opening 606 to attack the layers in the opening 606.

[0068] Since the first layer 604a is a silicon-containing material (such as a SiN layer), the oxygen element supplied during the selective oxidation process reacts with the silicon element from the first layer 604a, thereby forming an oxide layer 802 at the sidewall 704a of the first layer 604a. It should be noted that due to the silicon source from the second layer 604b, a relatively small amount of oxide layer may be formed in the second layer 604b.

[0069] In one example, the selective oxidation process is a radical plasma oxidation process for oxidizing the sidewall 704a of the first layer 604a. The selective oxidation process forms an oxide layer 802 on the sidewall 704a of the first layer 604a. In one example, the selective oxidation (such as a radical plasma oxidation process) can be performed in respective oxidation chambers. In certain embodiments, the oxidation chambers can be coupled to an integrated processing tool (such as Figure 4 the cluster system 400 depicted in) or be part of an integrated processing tool. It is contemplated that the methods described herein can be practiced using other processing chambers and cluster tools having suitable processing chambers coupled thereto.

[0070] In one example, the selective oxidation process described herein can be performed in any suitable chamber configured for radical oxidation, also known as in-situ steam generation (ISSG) or the like. Suitable oxidation chambers can include (but are not limited to) those available from Applied Materials, Inc. of Santa Clara, California, Plasma Immersion Ion Implantation (P3I), RADOX TM 、 Plus、 RADOX TM chambers. Exemplary surface oxidation processes (or radical plasma oxidation processes) can be performed using various oxidative chemistries, which include varying reducing gas concentrations for reducing gases (such as one or more of hydrogen (H2), ammonia (NH3), or the like) in an oxidizing gas mixture that includes one or more oxidizing gases (such as oxygen (O2), nitric oxide (NO), nitrous oxide (N2O), or the like) and optionally includes one or more non-reactive gases (such as nitrogen (N2), helium (He), argon (Ar), neon (Ne), and xenon (Xe)). One form of radical plasma oxidation is performed using only H2 and O2.

[0071] The selective oxidation process at operation 504 is a radical plasma oxidation process or an "in-situ steam generation" (ISSG) process. The selective oxidation process can provide oxide growth on the thermally controlled first layer 604a in an oxidation environment. The in-situ steam generation (ISSG) process includes forming steam (H2O) in the same chamber in which the substrate to be oxidized is located (i.e., forming steam in-situ with the substrate). A reaction gas mixture including a hydrogen-containing gas (such as but not limited to H2 and NH3) and an oxygen-containing gas (such as but not limited to O2 and N2O) is fed into the reaction chamber in which the substrate is located. The oxygen-containing gas and the hydrogen-containing gas are reacted in the reaction chamber to form moisture or steam (H2O). The reaction of the hydrogen-containing gas and the oxygen-containing gas is ignited or catalyzed by heating the substrate 602 to a temperature sufficient to cause the steam reaction. Since the heated substrate 602 is used as an ignition source for the reaction, the steam generation reaction occurs in the vicinity of the exposed reaction surface of the substrate 602.

[0072] In one example, at a pressure between about 2 Torr and about 30 Torr (such as about 14 Torr), for a temperature greater than 900 degrees (such as a temperature between about 1000 degrees Celsius and about 1200 degrees Celsius, such as about 1050 °C), surface oxidation is performed for a period between about 30 seconds and about 300 seconds (such as about 130 seconds). During the selective oxidation process, a total gas flow having 33% hydrogen and 67% oxygen by volume flow is used. The selectively formed oxide layer 802 can have a thickness between about 2 nm and about 100 nm.

[0073] The formed oxide layer 802 can be used as a sacrificial layer and / or a protective layer during a subsequent etching process to protect the film layer formed in the opening 606, thereby improving and enhancing the etching selectivity during the etching process.

[0074] At operation 506, the metal dielectric layer 902 is vertically formed in the opening 606, thereby lining on the control layer / etch stop layer 702, as Figure 9A shown, or in direct contact with the oxide layer 802 and the second layer 604b, as Figure 9B shown. In Figure 9A the depicted example, the metal dielectric layer 902 is in direct contact with the control layer / etch stop layer 702. In Figure 9B the depicted example, the metal dielectric layer 902 is vertically formed in the opening 606, in contact with the sidewall 704b of the second layer 604b and the oxide layer 802.

[0075] The metal dielectric layer 902 can be a high-k material having a dielectric constant greater than 4. Suitable examples of high-k materials include hafnium dioxide (HfO2), zirconium dioxide (ZrO2), hafnium silicate (HfSiO2), hafnium aluminate (HfAlO), zirconium silicate (ZrSiO2), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), aluminum-doped hafnium dioxide, bismuth strontium titanate (BST), and platinum zirconium titanate (PZT), etc. In Figure 9A and Figure 9B In the depicted example, the metal dielectric layer 902 can be an aluminum oxide layer (Al2O3).

[0076] In one example, the metal dielectric layer 902 is formed by a suitable deposition process such as a CVD process, an ALD process, a sputtering process, or other suitable deposition processes. In a specific example, the metal dielectric layer 902 is formed by an ALD process. It is believed that when the metal dielectric layer 902 is used as a gate structure in a NAND or VNAND three-dimensional semiconductor memory device, the metal dielectric layer 902 vertically formed in the opening 606 in the film stack 604 can effectively improve electrical properties such as enhanced retention requirements and suppression of backtunneling current in the film stack 604. Different from the conventional structure with a first layer having a high-k material surrounding the adjacent second layer, repositioning the metal dielectric layer 902 into the opening 606 can allow additional space in each unit cell (e.g., allowing space to replace the first layer with a conductive structure between adjacent second layers), thus providing a wider process window for deposition processes, etching processes, or other related processes for the first layer to metal layer replacement process.

[0077] At operation 508, after forming the metal dielectric layer 902, the multilayer structure 904 can then be formed in the opening 606, thereby lining on the metal dielectric layer 902, as Figure 10A and Figure 10B depicted. The multilayer structure 904 can include one or more dielectric materials. In Figures 10A - 10B In one example depicted, the multilayer structure 904 includes a first oxide layer 904a, a first nitride layer 904b, a second oxide layer 904c, and a polysilicon layer 904d. The first oxide layer 904a and the second oxide layer 904c are silicon oxide layers, and the first nitride layer 904b is a silicon nitride layer or a silicon oxynitride (SiON) layer.

[0078] At operation 510, the center fill layer 906 is formed in the opening 606, thereby filling the remaining space left by the multilayer structure 904, as Figures 11A - 11BAs shown. The central fill layer 906 can also be a dielectric layer (such as SiO2, SiN, SiON, or other suitable dielectric materials). It should be noted that the multi-layer structure 904 and the central fill layer 906 can be formed by suitable deposition processes, such as CVD processes, ALD processes, sputtering processes, coating processes, or other suitable processes. In one example, the central fill layer 906 and the multi-layer structure 904 can be formed in the Figure 2 processing chamber 232 depicted.

[0079] At operation 512, after filling the opening 606 with the metal dielectric layer 902, the multi-layer structure 904, and the central fill layer 906, a lateral selective etching process is performed to selectively remove the first layer 604a from the film stack 604, as Figure 12A and Figure 12B shown. Removing the first layer 604a from the film stack 604 creates a space 910a in the film stack 604 where the first layer 604a was located, thereby forming a suspended film stack on the substrate 602 with only the second layer 604b of silicon oxide layer remaining. The space 910a exposes the oxide layer 802. The oxide layer 802 located at the interface between the first layer 604a and the metal dielectric layer 902 can effectively protect the metal dielectric layer 902 during the lateral selective etching process. By the blocking of the oxide layer 802, the aggressive etchant from the lateral selective etching process can be effectively blocked and kept away from the metal dielectric layer 902 during the lateral selective etching process, so as to improve the etching selectivity and improve the interface control and management. In an example using the control layer / etch stop layer 702, the combination of the control layer / etch stop layer 702 and the oxide layer 802 can provide solid interface protection to prevent damage to the metal dielectric layer 902 formed in the opening 606. In some examples, when forming the etch stop layer 702, the oxide layer 802 can be eliminated because the etch stop layer itself can provide high etching selectivity to effectively provide etching control at the interface.

[0080] At operation 514, after defining the space 910a between the second layers 604b, the oxide layer 802 can then be removed from the substrate 602, as Figure 13A and Figure 13B shown. During the lateral selective etching process at operation 512, the oxide layer 802 serves as a protective and sacrificial layer to protect the metal dielectric layer 902. After removing the first layer 604a and effectively defining the space 910a, the function of the oxide layer 802 is completed, such that the oxide layer 802 is subsequently removed at operation 514. It should be noted that the oxide layer 802 can be removed in the Figure 3 processing chamber 300 depicted. It should be noted that the oxide layer 802 can be removed by appropriate etching processes as needed.

[0081] In one example, when the oxide layer 802 is removed, a portion of the control layer / etch stop layer 702 in contact with the oxide layer 802 may also be removed, as Figure 13C shown, thereby creating additional space 952a that exposes the sidewall surface 952a of the metal dielectric layer 902. When a portion of the control layer / etch stop layer 702 is removed, another portion of the control layer / etch stop layer 702 remains in the opening and contacts the sidewall 704b of the second layer 604b.

[0082] At operation 516, after the oxide layer 802 is removed, a conductive structure 912 is then formed and filled in the space 910a in the film stack 604, as Figure 14A 、 Figure 14B and Figure 14C shown. The conductive structure 912 fills the space 910a defined between adjacent second layers 604b and has a relatively large contact area and a large amount. In conventional practice, the space 910a is not only filled with the conductive structure 912 but also filled with a metal dielectric layer (e.g., the metal dielectric layer 902 is now relocated into the opening 606 in the present disclosure). The occupation of the metal dielectric layer in the space 910a typically results in poor etch selectivity at the interface, as well as a reduced contact area and the amount of the conductive structure 912 that can be formed in the space 910a. Thus, by relocating the metal dielectric layer 902 into the opening 606 instead of the space 910a between the second layers 604b, a larger-sized space 910a can be obtained to allow a larger amount of the conductive structure 912 to be formed therein. In addition, when the first layer 604a is replaced with the conductive structure 912 into the space 910a, the larger size of the space 910a can also reduce manufacturing limitations and complexities. In addition, the larger size of the space 910a allows a larger amount of the conductive structure 912 to be replaced therein, such that increased metal conductivity and reduced resistivity can be obtained, thereby providing enhanced electrical performance of the device structure upon its completion.

[0083] It is believed that the metal material in the conductive structure 912 utilized in the film stack 604 can effectively improve the electrical properties (such as conductivity, mobility, and the like) in the film stack 604 when later used as a gate structure in a NAND or VNAND three-dimensional semiconductor memory device. The deposition process can be a metal-organic chemical vapor deposition (MOCVD) process or a sputter physical vapor deposition process, or other suitable processes as required. The deposition process can be performed in the Figure 2 depiction processing chamber 232. At Figure 14A 、 Figure 14B and Figure 14CIn the illustrated example, the conductive structure 912 includes a metal material 914 formed on a barrier layer 916. The barrier layer 916 is made of a material different from the metal dielectric layer 902. Since the oxide layer 802 and / or a portion of the control layer / etch stop layer 702 (if any) is removed, the barrier layer 916 can be in direct contact or interfacial connection with the metal dielectric layer 902 to enhance electrical properties as needed.

[0084] Suitable examples of the metal material 914 can be selected from the group consisting of tungsten (W), tungsten silicide (WSi), tungsten polysilicon (W / poly), tungsten alloys, tantalum (Ta), titanium (Ti), copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), aluminum (A1), hafnium (Hf), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Au), platinum (Pt), their alloys, or combinations thereof. Suitable examples of the barrier layer 916 can be a metal nitride layer or a metal silicon nitride layer, such as titanium nitride (TiN), tantalum nitride (TaN), TaSiN, TiSiN, and combinations thereof.

[0085] In a specific example, the metal material 914 can be a tungsten (W)-containing layer, and the barrier layer 916 can be titanium nitride (TiN), tantalum nitride (TaN), TaSiN, or TiSiN. It should be noted that the conductive structure 912 can have only the metal material 914 without the barrier layer 916 as needed.

[0086] Therefore, a method and apparatus for forming a stepped structure for a three-dimensional (3D) stack for manufacturing a memory cell of a semiconductor device are provided. A protective oxide layer (e.g., a sacrificial oxide layer) at the interface and selective deposition and selective etching processes are used to replace a dielectric layer in a film stack with a conductive structure. A metal dielectric material is formed in an opening (e.g., a channel) in a film stack for a three-dimensional (3D) stack of a memory cell of a semiconductor device. The protection / sacrifice oxide layer can protect the interface and the metal dielectric layer during the removal process, thereby providing good control over the interface profile and topography. As a result, when a conductive structure is subsequently formed therein, good electrical contact can be obtained at the interface, thereby providing desired electrical properties for the memory cell.

[0087] Although the foregoing relates to embodiments of the present disclosure, other and further embodiments of the present disclosure can be designed without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A memory cell device, comprising: a film stack including an alternating pair of dielectric layers and conductive structures horizontally formed on a substrate, wherein a first conductive structure of the conductive structures includes a metal material and a barrier layer covering the metal material; and an opening formed in the film stack, wherein the opening is filled with an etch stop layer, a metal dielectric layer, a multi-layer structure, and a center fill layer, the multi-layer structure including a first oxide layer, a second oxide layer, a nitride layer disposed between the first oxide layer and the second oxide layer, and a polysilicon layer, wherein the second oxide layer is disposed between the nitride layer and the polysilicon layer; wherein the etch stop layer, the metal dielectric layer, the multi-layer structure, and the center fill layer are vertically disposed in the opening, wherein the etch stop layer in the opening is interfacially connected to the first conductive structure, and wherein the barrier layer is disposed between the etch stop layer and the metal material.

2. The memory cell device according to claim 1, wherein the metal dielectric layer in the opening is a high-k material.

3. The memory cell device according to claim 1, wherein the metal material is selected from the group consisting of tungsten (W), tungsten silicide (WSi), tungsten polysilicon (W / poly), tungsten alloy, tantalum (Ta), titanium (Ti), copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), aluminum (A1), hafnium (Hf), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Ag), platinum (Pt), their alloys, or combinations thereof.

4. The memory cell device according to claim 1, wherein the barrier layer is titanium nitride (TiN), tantalum nitride (TaN), TaSiN, or TiSiN.

5. The memory cell device according to claim 2, wherein the high-k material is selected from the group consisting of hafnium dioxide (HfO2), zirconium dioxide (ZrO2), hafnium silicon oxide (HfSiO2), hafnium aluminum oxide (HfAlO), zirconium silicon oxide (ZrSiO2), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), aluminum-doped hafnium dioxide, bismuth strontium titanate (BST), and platinum zirconium titanate (PZT).

6. The memory cell device according to claim 1, wherein the dielectric layer is a silicon oxide layer.

7. The memory cell device according to claim 1, wherein the center fill layer is a silicon oxide material.

8. A method of forming a memory device on a substrate, comprising the steps of: forming an opening in a film stack including a first layer and a second layer; selectively oxidizing the first layer to form an oxide layer on a sidewall of the first layer; Fill the opening with a plurality of layers, the plurality of layers including an etch stop layer, a metal dielectric layer, a multi-layer structure, and a center fill layer, the multi-layer structure including a first oxide layer, a second oxide layer, a nitride layer disposed between the first oxide layer and the second oxide layer, and a polysilicon layer, wherein the second oxide layer is disposed between the nitride layer and the polysilicon layer; Selectively remove the first layer from the film stack to expose the oxide layer; Selectively remove the oxide layer from the film stack to define a space in the film stack; And Fill the space with a conductive structure.

9. The method of claim 8, wherein the first layer is a silicon nitride layer and the second layer is a silicon oxide layer.

10. The method of claim 8, wherein selectively oxidizing the first layer further comprises the steps of: Performing radical plasma oxidation to oxidize the first layer.

11. The method of claim 8, wherein the metal dielectric layer is a high dielectric constant material selected from the group consisting of hafnium dioxide (HfO2), zirconium dioxide (ZrO2), hafnium silicon oxide (HfSiO2), hafnium aluminum oxide (HfAlO), zirconium silicon oxide (ZrSiO2), tantalum pentoxide (Ta2O5), aluminum oxide (A12O3), aluminum-doped hafnium dioxide, bismuth strontium titanate (BST), and platinum zirconium titanate (PZT).

12. The method of claim 8, wherein the conductive structure includes a metal material and a barrier layer.

13. The method of claim 12, wherein the barrier layer is disposed between the etch stop layer and the metal material.

14. The method of claim 12, wherein the barrier layer is made of a material different from the metal dielectric layer.

15. The method of claim 12, wherein the barrier layer contacts the etch stop layer.

16. The method of claim 8, wherein the metal dielectric layer is a high dielectric constant material.

17. The method according to claim 8, further comprising the following steps: Form a center fill layer in the opening.

18. The method according to claim 8, wherein selectively removing the first layer from the membrane stack to expose the oxide layer comprises the steps of: Perform a lateral etch process to remove the first layer from the film stack.

19. The method according to claim 8, wherein selectively removing the oxide layer from the membrane stack to define a space in the membrane stack comprises the steps of: Laterally selectively remove the oxide layer from the film stack.

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