Display device

Abstract

A display device may include a display panel having a pixel area and an input sensing sensor, wherein the input sensing sensor includes: a first conductive layer arranged on the display panel, a first insulating layer arranged on the first conductive layer and having a first opening in a region overlapping the pixel area, a second conductive layer arranged on the first insulating layer, a second insulating layer arranged on the second conductive layer and having a second opening defined in a region overlapping the pixel area, and a third insulating layer arranged on the second insulating layer and filling the first opening and the second opening.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a display device with improved light efficiency. Background Art

[0002] The display device can be classified as a self-luminous display device, in which the light-emitting element itself emits light, or a light-receiving display device, in which the light-emitting element itself emits light, and a light-receiving display device that controls the transmission of the received light. The self-luminous display device may be, for example, an organic light-emitting display device. The light generated in the light-emitting layer of the organic light-emitting display device may be emitted not only in the front direction but also in the lateral direction. The light efficiency may be determined based on the light emitted in the front direction. That is, the light emitted in the lateral direction may result in a reduction in the light efficiency. Summary of the invention

[0003] Technical issues solved

[0004] The present invention provides a display device with improved light efficiency.

[0005] Workaround

[0006] A display device according to an embodiment of the present invention may include a display panel having a pixel area, and an input sensing sensor arranged on the display panel, wherein the input sensing sensor may include a first conductive layer arranged on the display panel, a first insulating layer arranged on the first conductive layer and having a first opening in a region overlapping with the pixel area, a second conductive layer arranged on the first insulating layer, a second insulating layer arranged on the second conductive layer and having a second opening defined in a region overlapping with the pixel area, and a third insulating layer arranged on the second insulating layer and filling the first opening and the second opening.

[0007] The first insulating layer may have a first refractive index, the second insulating layer may have a second refractive index, and the third insulating layer may have a third refractive index higher than the first and second refractive indices.

[0008] In a plane, an area of ​​the first opening may be smaller than an area of ​​the second opening.

[0009] In a plane, an area of ​​the first opening may be equal to or larger than an area of ​​the pixel region.

[0010] On a plane, a side surface of the first insulating layer defining the first opening may be surrounded by a side surface of the second insulating layer defining the second opening.

[0011] The first conductive layer may include a connection portion, and the second conductive layer may include a sensor portion.

[0012] Each of the sensor portions may have a grid shape, the sensor portion may have a sensor opening defined on a plane, and the sensor opening may overlap with the first opening and the second opening.

[0013] The first refractive index and the second refractive index may each be 1.45 to 1.55, and the third refractive index may be 1.60 to 1.70.

[0014] The display panel may include a base layer, a circuit layer disposed on the base layer, a light emitting layer disposed on the circuit layer, and an encapsulation layer disposed on the light emitting layer, and the input sensing sensor may be disposed to directly contact the encapsulation layer.

[0015] The input sensing sensor may further include a buffer layer directly contacting the encapsulation layer, and the buffer layer may be disposed between the encapsulation layer and the first conductive layer.

[0016] A display device according to an embodiment of the present invention may include: a display panel including a pixel area; a first insulating layer, disposed on the display panel, having a first refractive index, and having a first opening defined in an area overlapping the pixel area; a second insulating layer, disposed on the first insulating layer, having a second refractive index, and having a second opening larger than the first opening in an area corresponding to the first opening; and a third insulating layer, covering the display panel, the first insulating layer and the second insulating layer, and having a third refractive index higher than the first refractive index and the second refractive index, and in a plane, the third insulating layer may overlap with the pixel area.

[0017] The display panel may further include a first conductive layer disposed between the display panel and the first insulating layer, and a second conductive layer disposed between the first insulating layer and the second insulating layer.

[0018] A fourth insulating layer disposed between the first insulating layer and the second conductive layer and having a fourth refractive index lower than the third refractive index may be further included, wherein a third opening larger than the first opening and smaller than the second opening may be defined in the fourth insulating layer.

[0019] The first conductive layer may include a connection portion, and the second conductive layer may include a sensor portion.

[0020] Each of the sensor parts may have a grid shape, and the sensor part may not overlap with the pixel area on a plane.

[0021] Each of the sensor portions may have a grid shape, the sensor portion may have a sensor opening defined on a plane, and the sensor opening may overlap with the first opening and the second opening.

[0022] A fourth insulating layer disposed between the second insulating layer and the third insulating layer and having a fourth refractive index lower than the third refractive index may be further included, wherein a third opening larger than the second opening may be defined in the fourth insulating layer.

[0023] On a plane, a side surface of the first insulating layer defining the first opening may be surrounded by a side surface of the second insulating layer defining the second opening.

[0024] The first refractive index and the second refractive index may each be 1.45 to 1.55, and the third refractive index may be 1.60 to 1.70.

[0025] A third insulating layer may be filled in each of the first opening and the second opening.

[0026] Beneficial Effects

[0027] According to an embodiment of the present invention, a display device includes a first insulating layer having a first opening, a second insulating layer having a second opening, and a third insulating layer filled in the first opening and the second opening. The refractive index of the third insulating layer may be higher than the refractive index of the first insulating layer and the refractive index of the second insulating layer. Light emitted from a light-emitting element of the display device may be refracted or totally reflected at a boundary between a low refractive index layer and a high refractive index layer, and thus may have a changed optical path. By changing the optical path, the luminous efficiency of the display device may be improved. In addition, the first opening and the second opening are defined in different insulating layers. Therefore, even when the distance between the side wall portion defining each of the first opening and the second opening and the display area is reduced, the possibility of the following phenomenon occurring, that is, the phenomenon that the third insulating layer is not filled in each of the first opening and the second opening, may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0029] Figure 2a to Figure 2d is a cross-sectional view of a display device according to an embodiment of the present invention.

[0030] Figure 3 is a plan view of a display panel according to an embodiment of the present invention.

[0031] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0032] Figure 5 is a cross-sectional view showing some components of a display panel according to an embodiment of the present invention.

[0033] Figure 6 is a plan view of an input sensing layer according to an embodiment of the present invention.

[0034] Figure 7 It is enlarged to show Figure 6 The plan view of area AA.

[0035] Figure 8 is along Figure 6 A cross-sectional view taken along line II'.

[0036] Fig. 9 is along Figure 7 A cross-sectional view taken along line II-II'.

[0037] Fig.10a It is a cross-sectional view showing a portion of a display device according to a comparative example of the present invention.

[0038] Fig.10b Is magnification Fig.10a A cross-sectional view of region XX is shown.

[0039] Fig.11 is according to an embodiment of the present invention along the corresponding Figure 7 A cross-sectional view taken along line II-II'.

[0040] Fig.12 is according to an embodiment of the present invention along the corresponding Figure 7 A cross-sectional view taken along line II-II'.

[0041] Figures 13a to 13g is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In the present disclosure, when an element (or region, layer, part, etc.) is referred to as being "on," "connected to" or "coupled to" another element, it means that the element may be directly disposed on / directly connected to / directly coupled to the other element, or a third element may be disposed between them.

[0043] The same reference numerals denote the same elements. In addition, in the drawings, in order to effectively describe the technical contents, the thickness, ratio and size of the elements are exaggerated.

[0044] The term "and / or" includes all possible combinations of one or more associated components.

[0045] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of exemplary embodiments of the present invention. Terms in the singular may include plural forms unless the context clearly indicates otherwise.

[0046] In addition, terms such as "below", "lower", "above", "upper", etc. are used to describe the relationship of components shown in the drawings. These terms are used as relative concepts and are described with reference to the directions shown in the drawings.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. It should also be understood that terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology and are clearly defined herein unless they are interpreted in an ideal or overly formal sense.

[0048] It should be understood that the terms “including” or “having” are intended to specify the presence of the stated features, integers, steps, operations, elements, components, or combinations thereof in the present disclosure, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0049] Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

[0050] Figure 1 is a perspective view of a display device DD according to an embodiment of the present invention.

[0051] Reference Figure 1 The display device DD can be used in large electronic devices such as televisions, monitors or external advertising boards, and can also be used in small and medium-sized electronic devices such as personal computers, notebook computers, personal digital terminals, car navigation system units, game consoles, portable electronic devices and cameras. It should be understood that these are only exemplary embodiments, and the display device DD can be used in other electronic devices without departing from the present invention.

[0052] The display device DD may have a display area DA and a non-display area NDA.

[0053] The display area DA on which the image IM is displayed is parallel to the surface defined by the first direction DR1 and the second direction DR2. The normal direction of the display area DA, that is, the thickness direction of the display device DD, is represented by the third direction DR3. The front surface (or upper surface) and the rear surface (or lower surface) of each component are distinguished by the third direction DR3. However, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can be converted into different directions. In the following, the first direction, the second direction, and the third direction are directions represented by the first direction DR1, the second direction DR2, and the third direction DR3, respectively, and are given the same figure marks.

[0054] The non-display area NDA is an area adjacent to the display area DA, and is an area in which the image IM is not displayed. A bezel area of ​​the display device DD may be defined by the non-display area NDA.

[0055] The non-display area NDA may surround the display area DA. However, the embodiment of the present invention is not limited thereto. The shape of the display area DA and the shape of the non-display area NDA may be designed in association.

[0056] Figure 2a to Figure 2d is a cross-sectional view of a display device DD according to an embodiment of the present invention. Figure 2a to Figure 2d A cross section defined by the second direction DR2 and the third direction DR3 is shown. Figure 2a to Figure 2d It is simply shown to describe the stacking relationship of the functional components constituting the display device DD.

[0057] The display device DD according to an embodiment of the present invention may include a display panel, an input sensing sensor, an anti-reflector, and a window. At least some of the components of the display panel, the input sensing sensor, the anti-reflector, and the window may be provided in a continuous process, or at least some of the components may be bonded to each other by a bonding member. Figure 2a to Figure 2d In the embodiment of the present invention, the optically transparent adhesive member OCA is exemplarily shown as the bonding member. The bonding member described below may include a typical adhesive or a pressure-sensitive adhesive. In the embodiment of the present invention, the anti-reflector and the window may be replaced by other components, or may be omitted.

[0058] exist Figure 2a to Figure 2d , among the input sensing sensor, the anti-reflector, and the window, the corresponding component provided by a continuous process with another component is represented as a "layer". Among the input sensing sensor, the anti-reflector, and the window, the component bonded to another component by an adhesive member is represented as a "panel". The panel includes a base layer that provides a base surface, for example, a synthetic resin film, a composite film, a glass substrate, etc., but the "layer" may not include the base layer. In other words, a unit represented as a "layer" is provided on a base surface provided by another unit.

[0059] Hereinafter, the input sensing sensor, the anti-reflector and the window may be referred to as an input sensing panel ISP, an anti-reflection panel RPP and a window panel WP, or an input sensing layer ISL, an anti-reflection layer RPL and a window layer WL, depending on the presence of the base layer.

[0060] like Figure 2a As shown, the display device DD may include a display panel DP, an input sensing layer ISL, an anti-reflection panel RPP and a window panel WP. The input sensing layer ISL is directly disposed on the display panel DP. In the present disclosure, "component B is directly disposed on component A" means that no separate adhesive layer / adhesive member is disposed between component A and component B. After component A is disposed, component B may be disposed on a base surface provided by component A through a continuous process.

[0061] The display module DM may be defined by including a display panel DP and an input sensing layer ISL disposed directly on the display panel DP. An optically transparent adhesive member OCA is disposed between the display module DM and the anti-reflection panel RPP and between the anti-reflection panel RPP and the window panel WP.

[0062] The display panel DP generates an image IM, and the input sensing layer ISL obtains coordinate information of an external input (e.g., a touch event). Although not shown separately, the display module DM according to an embodiment of the present invention may further include a protective member disposed on the lower surface of the display panel DP. The protective member and the display panel DP may be bonded by an adhesive member. Figure 2b to Figure 2d The display device DD may further include a protection member.

[0063] The display panel DP according to an embodiment of the present invention may be a light-emitting display panel, but is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0064] The anti-reflection panel RPP reduces the reflectivity of external light incident from the upper side of the window panel WP. The anti-reflection panel RPP according to an embodiment of the present invention may include a phase retarder and a polarizer. The phase retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include a stretchable synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a predetermined arrangement. The phase retarder and the polarizer may also include a protective film. The phase retarder and the polarizer themselves or the protective film may be defined as a base layer of the anti-reflection panel RPP.

[0065] The anti-reflection panel RPP according to an embodiment of the present invention may include a color filter. The color filter has a predetermined arrangement. The arrangement of the color filter may be determined in consideration of the luminous color of the pixels included in the display panel DP. The anti-reflection panel RPP may further include a black matrix adjacent to the color filter.

[0066] The anti-reflection panel RPP according to an embodiment of the present invention may include a destructive interference structure. For example, the destructive interference structure may include a first reflection layer and a second reflection layer disposed on different layers. The first reflected light and the second reflected light reflected from the first reflection layer and the second reflection layer, respectively, may destructively interfere, and therefore, the reflectivity of the external light is reduced.

[0067] The window panel WP according to an embodiment of the present invention includes a base layer WP-BS and a light shielding pattern WP-BZ. The base layer WP-BS may include a glass substrate and / or a synthetic resin film, etc. The base layer WP-BS is not limited to a single layer. The base layer WP-BS may include two or more films bonded by an adhesive member.

[0068] The light shielding pattern WP-BZ partially overlaps with the base layer WP-BS. The light shielding pattern WP-BZ is disposed on the rear surface of the base layer WP-BS, and the light shielding pattern WP-BZ may substantially define a non-display area NDA of the display device DD. An area where the light shielding pattern WP-BZ is not disposed may define a display area DA of the display device DD. When limited to the window panel WP, an area where the light shielding pattern WP-BZ is disposed is defined as a light shielding area of ​​the window panel WP, and an area where the light shielding pattern WP-BZ is not disposed is defined as a transmission area of ​​the window panel WP.

[0069] The light shielding pattern WP-BZ may have a multi-layer structure. The multi-layer structure may include a colored color layer and a black light shielding layer. The colored color layer and the black light shielding layer may be provided by a deposition, printing, or coating process. Although not shown separately, the window panel WP may further include a functional coating disposed on the front surface of the base layer WP-BS. The functional coating may include an anti-fingerprint layer, an anti-reflection layer, a hard coating layer, and the like. Figure 2b to Figure 2d , the window panel WP and the window layer WL are simply shown without distinguishing between the base layer WP-BS and the light shielding pattern WP-BZ.

[0070] like Figure 2b and Figure 2c As shown, the display device DD may include a display panel DP, an input sensing panel ISP, an anti-reflection panel RPP, and a window panel WP. The stacking order of the input sensing panel ISP and the anti-reflection panel RPP is changed.

[0071] like Figure 2dAs shown, the display device DD may include a display panel DP, an input sensing layer ISL, an anti-reflection layer RPL, and a window layer WL. Figure 2a Compared with the display device DD shown in FIG. 1 , the optically transparent adhesive member OCA is omitted, and an input sensing layer ISL, an anti-reflection layer RPL, and a window layer WL are disposed in a continuous process on a base surface disposed on the display panel DP. The stacking order of the input sensing layer ISL and the anti-reflection layer RPL is changed.

[0072] Figure 3 is a plan view of a display panel DP according to an embodiment of the present invention.

[0073] Reference Figure 3 The display panel DP may include a driving circuit GDC, a plurality of signal lines SGL (hereinafter referred to as signal lines), a plurality of signal pads DP-PD (hereinafter referred to as signal pads), and a plurality of pixels PX (hereinafter referred to as pixels).

[0074] The display area DP-DA may be defined as an area in which pixels PX are disposed. Each of the pixels PX includes an organic light emitting diode and a pixel driving circuit connected thereto. The driving circuit GDC, the signal line SGL, the signal pad DP-PD, and the pixel driving circuit may be included in Figure 5 The circuit layer ML is shown.

[0075] The drive circuit GDC may include a scan drive circuit. The scan drive circuit generates a plurality of scan signals (hereinafter referred to as scan signals) and sequentially outputs the scan signals to a plurality of scan lines SL (hereinafter referred to as scan lines) described later. The scan drive circuit may also output another control signal to another drive circuit of the pixel PX.

[0076] The scan driving circuit may include a plurality of thin film transistors provided by the same process (eg, a low temperature polysilicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process) of the driving circuit GDC of the pixel PX.

[0077] The signal lines SGL include scan lines SL, data lines DL, power lines PL, emission control lines ECL, and control signal lines CSL.

[0078] Each of the scan lines SL is connected to a corresponding pixel PX among the pixels PX, and each of the data lines DL is connected to a corresponding pixel PX among the pixels PX. The power lines PL are connected to the pixels PX. Each of the emission control lines ECL is connected to a corresponding pixel PX among the pixels PX. The control signal line CSL may provide a control signal to the scan driving circuit.

[0079] The signal line SGL overlaps the display area DP-DA and the non-display area DP-NDA. The signal line SGL may include a pad unit and a line unit. The line unit overlaps the display area DP-DA and the non-display area DP-NDA. The pad unit is disposed at the end of the line unit. The pad unit is disposed in the non-display area DP-NDA and overlaps with a corresponding signal pad DP-PD in the signal pad DP-PD. In the non-display area DP-NDA, an area in which the signal pad DP-PD is disposed may be defined as a pad area DP-PA. A circuit substrate not shown may be connected to the pad area DP-PA.

[0080] Figure 4 is an equivalent circuit diagram of a pixel PX according to an embodiment of the present invention. Figure 4 The pixel PX connected to the i-th scan line SLi and the i-th emission control line ECLi is exemplarily shown.

[0081] The pixel PX may include an organic light emitting diode OLED and a pixel circuit CC. The pixel circuit CC may include a plurality of transistors T1 to T7 and a capacitor CP. The pixel circuit CC controls the amount of current flowing in the organic light emitting diode OLED according to a data signal.

[0082] The organic light emitting diode OLED may emit light at a predetermined brightness according to the amount of current supplied from the pixel circuit CC. To this end, the level of the first power source ELVDD may be set higher than the level of the second power source ELVSS.

[0083] Each of the plurality of transistors T1 to T7 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). In the present disclosure, for convenience, any one of the input electrode and the output electrode may be referred to as a first electrode, and the other one may be referred to as a second electrode.

[0084] A first electrode of the first transistor T1 is connected to the first power source ELVDD via the fifth transistor T5, and a second electrode of the first transistor T1 is connected to the anode electrode of the organic light emitting diode OLED via the sixth transistor T6. In the present disclosure, the first transistor T1 may be referred to as a driving transistor.

[0085] The first transistor T1 controls the amount of current flowing in the organic light emitting diode OLED according to a voltage applied to a control electrode of the first transistor T1 .

[0086] The second transistor T2 is connected between the data line DL and the first electrode of the first transistor T1. In addition, the control electrode of the second transistor T2 is connected to the i-th scan line SLi. When the i-th scan signal is supplied to the i-th scan line SLi, the second transistor T2 is turned on and electrically connects the data line DL and the first electrode of the first transistor T1.

[0087] The third transistor T3 is connected between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 is connected to the i-th scan line SLi. When the i-th scan signal is supplied to the i-th scan line SLi, the third transistor T3 is turned on and electrically connects the second electrode of the first transistor T1 and the control electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is connected in the form of a diode.

[0088] The fourth transistor T4 is connected between the node ND and the initialization power generation unit (not shown). In addition, the control electrode of the fourth transistor T4 is connected to the i-1th scan line SLi-1. When the i-1th scan signal is supplied to the i-1th scan line SLi-1, the fourth transistor T4 is turned on and supplies the initialization voltage Vint to the node ND.

[0089] The fifth transistor T5 is connected between the power line PL and the first electrode of the first transistor T1. A control electrode of the fifth transistor T5 is connected to the i-th light emission control line ECLi.

[0090] The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the anode electrode of the organic light emitting diode OLED. In addition, a control electrode of the sixth transistor T6 is connected to the i-th light emission control line ECLi.

[0091] The seventh transistor T7 is connected between the initialization power generation unit (not shown) and the anode electrode of the organic light emitting diode OLED. In addition, the control electrode of the seventh transistor T7 is connected to the i+1th scan line SLi+1. When the i+1th scan signal is supplied to the i+1th scan line SLi+1, the seventh transistor T7 such as described above is turned on and supplies the initialization voltage Vint to the anode electrode of the organic light emitting diode OLED.

[0092] The seventh transistor T7 can improve the ability of the pixel PX to express black. Specifically, when the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the organic light emitting diode OLED is discharged. Then, when black brightness is achieved, the organic light emitting diode OLED does not emit light due to the leakage current from the first transistor T1, and therefore, the ability to express black can be improved.

[0093] also, Figure 4The control electrode of the seventh transistor T7 is shown to be connected to the i+1th scan line SLi+1, but the embodiment of the present invention is not limited thereto. In the embodiment of the present invention, the control electrode of the seventh transistor T7 may be connected to the i-th scan line SLi or the i-1th scan line SLi-1.

[0094] although Figure 4 PMOS is shown as a reference, but the embodiments of the present invention are not limited thereto. In the embodiments of the present invention, the pixel circuit CC may be composed of NMOS. In the embodiments of the present invention, the pixel circuit CC may be composed of a combination of NMOS and PMOS.

[0095] The capacitor CP is provided between the power line PL and the node ND. The capacitor CP stores a voltage corresponding to the data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing in the first transistor T1 may be determined according to the voltage stored in the capacitor CP.

[0096] In the present invention, the equivalent circuit of the pixel PX is not limited to Figure 4 In the embodiment of the present invention, the pixel PX may be implemented in various forms for making the organic light emitting diode OLED emit light.

[0097] Figure 5 is a cross-sectional view showing some components of the display panel DP according to an embodiment of the present invention.

[0098] Reference Figure 5 , the display panel DP may include a base layer BL, a circuit layer ML, a light emitting element layer EL, and an encapsulation layer TFE. The circuit layer ML may include a transistor TR and a plurality of insulating layers BFL, L1, L2, L3, and L4.

[0099] An insulating layer BFL may be disposed on the base layer BL, and the transistor TR may be disposed on the insulating layer BFL. Figure 5 The transistor TR can be Figure 4 The transistor TR may include a semiconductor layer ACL, a control electrode GED, a first electrode ED1, and a second electrode ED2.

[0100] The semiconductor layer ACL may be disposed on the insulating layer BFL. The insulating layer BFL may be a buffer layer that provides a modified surface to the semiconductor layer ACL. In this case, the semiconductor layer ACL may have a higher adhesion to the insulating layer BFL than the base layer BL. In addition, the insulating layer BFL may be a barrier layer that protects the lower surface of the semiconductor layer ACL. In this case, the insulating layer BFL may block the penetration of pollutants or moisture introduced into the semiconductor layer ACL by the base layer BL itself or through the base layer BL. Alternatively, the insulating layer BFL may be a light shielding layer that blocks external light incident through the base layer BL from being incident on the semiconductor layer ACL. In this case, the insulating layer BFL may further include a light shielding material.

[0101] The semiconductor layer ACL may include polycrystalline silicon or amorphous silicon. In addition to the above, the semiconductor layer ACL may include a metal oxide semiconductor. The semiconductor layer ACL may include a channel region serving as a path through which electrons or holes may move, and a first ion doping region and a second ion doping region disposed with the channel region interposed therebetween.

[0102] The first insulating layer L1 is disposed on the insulating layer BFL and may cover the semiconductor layer ACL. The first insulating layer L1 may include an inorganic material. The inorganic material may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide.

[0103] On the first insulating layer L1, the control electrode GED may be disposed. The second insulating layer L2 is disposed on the first insulating layer L1 and may cover the control electrode GED. The second insulating layer L2 may include an inorganic material.

[0104] On the second insulating layer L2, a third insulating layer L3 may be disposed. On the third insulating layer L3, a first electrode ED1 and a second electrode ED2 may be disposed. The first electrode ED1 and the second electrode ED2 may be connected to the semiconductor layer ACL through a through hole passing through the first insulating layer L1, the second insulating layer L2, and the third insulating layer L3.

[0105] The fourth insulating layer L4 is disposed on the third insulating layer L3 and may cover the first electrode ED1 and the second electrode ED2. The fourth insulating layer L4 may be composed of a single layer or multiple layers. For example, a single layer may include an organic layer. Multiple layers may be provided by stacking an organic layer and an inorganic layer. The fourth insulating layer L4 may be a planarization layer that provides a flat surface to the upper portion.

[0106] On the fourth insulating layer L4, a light emitting element layer EL and a pixel defining film PDP may be disposed.

[0107] The light emitting element layer EL may include a first electrode E1, a light emitting layer EM, and a second electrode E2. The first electrode E1 is disposed on the fourth insulating layer L4 and may be electrically connected to the second electrode ED2 through a through hole defined in the fourth insulating layer L4. The light emitting element layer EL may correspond to the reference Figure 4 An organic light emitting diode OLED is described.

[0108] The pixel defining film PDP may be disposed on the circuit layer ML and define the pixel area PXA. The pixel defining film PDP may be disposed on the fourth insulating layer L4 while covering at least a portion of the first electrode E1. A portion of the first electrode E1 may not be covered by the pixel defining film PDP, and the portion may correspond to the pixel area PXA. Accordingly, an area other than the pixel area PXA may correspond to a non-pixel area NPXA.

[0109] The light emitting layer EM may be disposed between the first electrode E1 and the second electrode E2. The light emitting layer EM may have a single layer structure including a single layer formed of a single material, a single layer structure including a single layer formed of a plurality of different materials, or a multilayer structure including a plurality of layers formed of a plurality of different materials.

[0110] The light emitting layer EM may include an organic material. The organic material is not particularly limited as long as it is a commonly used material. For example, the light emitting layer EM may be composed of at least one material of a material emitting red, green, or blue, and may include a fluorescent material or a phosphorescent material.

[0111] The second electrode E2 may be disposed on the light emitting layer EM and the pixel defining film PDP. The second electrode E2 may receive a second power source ELVSS (see Figure 4 ).

[0112] On the second electrode E2, an encapsulation layer TFE is provided. The encapsulation layer TFE may directly cover the second electrode E2. In an embodiment of the present invention, a cover layer covering the second electrode E2 may be further provided between the encapsulation layer TFE and the second electrode E2. In this case, the encapsulation layer TFE may directly cover the cover layer. The cover layer may include an organic material. The cover layer protects the second electrode E2 from subsequent processes such as a sputtering process and improves the luminous efficiency of the light emitting element layer EL. The cover layer may have a greater refractive index than the first inorganic layer ECL1 to be described later.

[0113] The encapsulation layer TFE may include a first inorganic layer ECL1, an organic layer ECL2, and a second inorganic layer ECL3. The organic layer ECL2 may be disposed between the first inorganic layer ECL1 and the second inorganic layer ECL3. The first inorganic layer ECL1 and the second inorganic layer ECL3 may be provided by depositing an inorganic material, and the organic layer ECL2 may be provided by depositing, printing, or coating an organic material.

[0114] The first inorganic layer ECL1 and the second inorganic layer ECL3 protect the light emitting element layer EL from moisture and oxygen, and the organic layer ECL2 protects the light emitting element layer EL from foreign substances such as dust particles. The first inorganic layer ECL1 and the second inorganic layer ECL3 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide. The organic layer ECL2 may include a polymer, for example, an acrylic organic layer. However, this is merely exemplary, and embodiments of the present invention are not limited thereto.

[0115] Figure 5 The encapsulation layer TFE is exemplarily shown to include two inorganic layers and one organic layer, but the embodiments of the present invention are not limited thereto. For example, the encapsulation layer TFE may include three inorganic layers and two organic layers, and in this case, the inorganic layers and the organic layers may have an alternately stacked structure.

[0116] Figure 6 1 is a plan view of an input sensing layer ISL according to an embodiment of the present invention. The input sensing layer ISL described below may be equally applicable to an input sensing panel ISP (see Figure 2b ).

[0117] The input sensing layer ISL may include a Figure 3 The display panel DP is shown with a sensing area IS-DA of the display area DP-DA and a line area IS-NDA corresponding to the non-display area DP-NDA.

[0118] The input sensing layer ISL may include first sensing electrodes EG1, second sensing electrodes EG2, a first signal line group SG1 electrically connected to some corresponding electrodes of the first sensing electrodes EG1, a second signal line group SG2 electrically connected to other electrodes of the first sensing electrodes EG1, and a third signal line group SG3 electrically connected to the second sensing electrodes EG2.

[0119] Figure 6 The first signal line group SG1 and the second signal line group SG2 are exemplarily shown to be arranged with the sensing area IS-DA interposed therebetween. However, in an embodiment of the present invention, the first signal line group SG1 and the second signal line group SG2 may be arranged on the same side of the sensing area IS-DA. In addition, in an embodiment of the present invention, each of the first signal line group SG1 and the second signal line group SG2 may be connected to the first sensing electrode EG1 in a dual path structure.

[0120] The first sensing electrode EG1 and the second sensing electrode EG2 are disposed in the sensing area IS-DA. The first signal line group SG1, the second signal line group SG2, and the third signal line group SG3 are located in the line area IS-NDA.

[0121] In this embodiment, the input sensing layer ISL may be a capacitive touch sensor that senses external input in a mutual capacitance manner. Any one of the first sensing electrode EG1 and the second sensing electrode EG2 receives a detection signal, and the other one thereof outputs a change in capacitance between the first sensing electrode EG1 and the second sensing electrode EG2 as an output signal.

[0122] Each of the first sensing electrodes EG1 extends in the second direction DR2. A plurality of first sensing electrodes EG1 are disposed at intervals in the first direction DR1. Each of the second sensing electrodes EG2 extends in the first direction DR1. A plurality of second sensing electrodes EG2 are disposed at intervals in the second direction DR2.

[0123] The first sensing electrode EG1 may include first sensor parts SP1 and first connection parts CP1. A plurality of first sensor parts SP1 are arranged along the second direction DR2. Each of the first connection parts CP1 may connect two adjacent first sensor parts SP1 among the first sensor parts SP1.

[0124] The second sensing electrode EG2 may include second sensor parts SP2 and second connection parts CP2. A plurality of second sensor parts SP2 are arranged along the first direction DR1. Each of the second connection parts CP2 may connect two adjacent second sensor parts SP2 among the second sensor parts SP2.

[0125] The first signal line group SG1, the second signal line group SG2, and the third signal line group SG3 may be electrically connected to the corresponding signal pads IS-PD. In the line area IS-NDA, the area where the signal pads IS-PD are disposed may be defined as a pad area IS-PA. A circuit substrate not shown may be connected to the pad area IS-PA.

[0126] Figure 7 It is enlarged to show Figure 6 The plan view of area AA.

[0127] The display panel DP (see Figure 5 ) of the first pixel region PXA-R, the second pixel region PXA-B and the third pixel region PXA-G. The first pixel region PXA-R, the second pixel region PXA-B and the third pixel region PXA-G are defined as being aligned with the reference pixel region PXA-R, the second pixel region PXA-B and the third pixel region PXA-G. Figure 5 The pixel areas PXA are the same.

[0128] Reference Figure 6 and Figure 7In the present embodiment, the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G may have different areas. The first pixel region PXA-R may have a first area, the second pixel region PXA-B may have a second area, and the third pixel region PXA-G may have a third area. The second area may be greater than the first area, and the first area may be greater than the third area.

[0129] Reference Figure 3 The described plurality of pixels PX may include a red pixel generating red light, a blue pixel generating blue light, and a green pixel generating green light. In this embodiment, the first pixel region PXA-R may correspond to a red pixel, the second pixel region PXA-B may correspond to a blue pixel, and the third pixel region PXA-G may correspond to a green pixel.

[0130] The first pixel region PXA-R and the second pixel region PXA-B may be alternately arranged along the first direction DR1 and the second direction DR2. The third pixel region PXA-G provided in plurality may be arranged along the first direction DR1 and the second direction DR2. The first pixel region PXA-R and the third pixel region PXA-G may be alternately arranged along the fourth direction DR4. The second pixel region PXA-B and the third pixel region PXA-G may be alternately arranged along the fourth direction DR4. The fourth direction DR4 is a direction intersecting the first direction DR1 and the second direction DR2, and may be referred to as a diagonal direction.

[0131] Figure 7 An example is shown in which the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G are arranged in a PenTile shape, but the present invention is not limited thereto. For example, the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G may be arranged in a stripe shape. The stripe shape may mean that the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G are alternately arranged along the second direction DR2, and the same pixel region is arranged in the first direction DR1.

[0132] Each of the first sensor portion SP1 and the second sensor portion SP2 may have a grid shape. On each of the first sensor portion SP1 and the second sensor portion SP2, a plurality of sensor openings OP-MR, OP-MG, and OP-MB may be defined. Therefore, on a plane, the first sensor portion SP1 and the second sensor portion SP2 may not overlap with the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G. For example, in an area corresponding to the first pixel region PXA-R, a first sensor opening OP-MR may be defined, in an area corresponding to the second pixel region PXA-B, a second sensor opening OP-MB may be defined, and in an area corresponding to the third pixel region PXA-G, a third sensor opening OP-MG may be defined.

[0133] Figure 8 is along Figure 6 A cross-sectional view taken along line II'. Fig. 9 is along Figure 7 A cross-sectional view taken along line II-II'.

[0134] Reference Figure 7 , Figure 8 and Fig. 9 , the input sensing layer ISL may include a buffer layer BFL- 1 , a first conductive layer CL1 , a second conductive layer CL2 , a first insulating layer IL1 , a second insulating layer IL2 , and a third insulating layer IL3 .

[0135] The buffer layer BFL-1 may be disposed on the encapsulation layer TFE. The buffer layer BFL-1 may include an inorganic material. For example, the inorganic material may be silicon nitride. The thickness of the buffer layer BFL-1 may be 2000 angstroms. However, this is merely exemplary. The material and thickness of the buffer layer BFL-1 are not limited thereto. In addition, in an embodiment of the present invention, the buffer layer BFL-1 may be omitted.

[0136] On the buffer layer BFL-1, a first conductive layer CL1 may be disposed. The first conductive layer CL1 may include a first connection portion CP1.

[0137] On the first conductive layer CL1, a first insulating layer IL1 may be disposed The thickness of the first insulating layer IL1 may be 1.5 micrometers to 3 micrometers, but the embodiment of the present invention is not limited thereto.

[0138] The first insulating layer IL1 has a first refractive index and may include an organic material. The organic material may include at least any one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, or perylene resin. However, this is merely exemplary, and the organic material is not limited to the above examples.

[0139] A plurality of first openings OP1 -R may be defined in a region of the first insulating layer IL1 overlapping the first, second, and third pixel regions PXA-R, PXA-B, and PXA-G. Fig. 9 A first opening OP1-R is shown. The first opening OP1-R may be defined in an area corresponding to the first pixel region PXA-R. For example, in a plane, the first opening OP1-R may overlap with the first pixel region PXA-R. In a plane, the area of ​​the first opening OP1-R may be the same as the area of ​​the first pixel region PXA-R, or may be larger than the area of ​​the first pixel region PXA-R. In the present disclosure, some of the indicator lines of the reference numerals of the openings are shown as indicating the side surfaces of the components defining the openings.

[0140] On the first insulating layer IL1, a second conductive layer CL2 may be disposed The second conductive layer CL2 may include a first sensor part SP1, a second sensor part SP2, and a second connection part CP2.

[0141] In the first sensor part SP1, two first sensor parts SP1 adjacent to each other may be connected to one first connection part CP1. The two first sensor parts SP1 may be connected to the first connection part CP1 through a through hole HL-I defined on the first insulating layer IL1.

[0142] In the embodiment of the present invention, the first conductive layer CL1 may include the first sensor part SP1, the second sensor part SP2, and the second connection part CP2, and the second conductive layer CL2 may include the first connection part CP1.

[0143] On the second conductive layer CL2, a second insulating layer IL2 may be disposed. The second insulating layer IL2 may have a second refractive index. The second insulating layer IL2 may include an organic material.

[0144] In the second insulating layer IL2 , in regions corresponding to the plurality of first openings OP1 -R, a plurality of second openings OP2 -R may be defined. Fig. 9 One second opening OP2-R is shown. The second opening OP2-R may be defined in a region corresponding to the first pixel region PXA-R.

[0145] The minimum width WT1 of the first opening OP1-R may be smaller than the minimum width WT2 of the second opening OP2-R. On a plane, the area of ​​the first opening OP1-R may be smaller than the area of ​​the second opening OP2-R. Therefore, on a plane, the side surface of the first insulating layer IL1 defining the first opening OP1-R may be surrounded by the side surface of the second insulating layer IL2 defining the second opening OP2-R.

[0146] Reference Figure 7 , a first opening OP1-B, a second opening OP2-B, a first opening OP1-G, and a second opening OP2-G are shown. The first opening OP1-B and the first opening OP1-G are openings defined in the first insulating layer IL1, and the second opening OP2-B and the second opening OP2-G are openings defined in the second insulating layer IL2. The first opening OP1-B and the second opening OP2-B may be defined in a region corresponding to the second pixel region PXA-B, and the first opening OP1-G and the second opening OP2-G may be defined in a region corresponding to the third pixel region PXA-G.

[0147] The first opening OP1-B and the first opening OP1-G may correspond to the reference Fig. 9 The first opening OP1-R described above, and the second opening OP2-B and the second opening OP2-G may correspond to the reference Fig. 9 Therefore, the detailed description thereof will be omitted.

[0148] On the second insulating layer IL2, a third insulating layer IL3 may be provided. The third insulating layer IL3 may have a third refractive index. The third refractive index may be a value higher than the first refractive index and the second refractive index. For example, the first refractive index and the second refractive index may each be 1.45 to 1.55. The third refractive index may be 1.65 to 1.70. The difference between the third refractive index and the first refractive index, and the difference between the third refractive index and the second refractive index may be 0.1 or greater. The ranges of the first refractive index, the second refractive index, and the third refractive index are exemplarily proposed. Therefore, as long as the third refractive index is higher than the first refractive index and the second refractive index, the ranges of the first refractive index, the second refractive index, and the third refractive index are not limited to the above examples.

[0149] The third insulating layer IL3 may fill the first opening OP1-R and the second opening OP2-R. In addition, the third insulating layer IL3 may provide a flat upper surface.

[0150] The light provided from the light emitting element layer EL may be emitted not only in the front direction (e.g., the third direction DR3) but also in the lateral direction. The light efficiency may be determined based on the light emitted in the front direction. According to an embodiment of the present invention, the light LT1 and LT2 emitted in the lateral direction may be totally reflected at the boundary between the first insulating layer IL1 and the third insulating layer IL3 or at the boundary between the second insulating layer IL2 and the third insulating layer IL3. Therefore, the optical path of the light LT1 and LT2 may be changed to the third direction DR3 or a direction close to the third direction DR3. As a result, the display device DD (see Figure 1 )'s light efficiency.

[0151] Fig.10a 1 is a cross-sectional view showing a portion of a display device DD according to a comparative example of the present invention. Fig.10b Is magnification Fig.10a A cross-sectional view of region XX is shown.

[0152] Reference Fig.10a and Fig.10b According to the comparative example of the present invention, the input sensing layer ISLc may include a buffer layer BFL-1, a first conductive layer (not shown) disposed on the buffer layer BFL-1, a first insulating layer IL1c disposed on the first conductive layer, a second conductive layer (not shown) disposed on the first insulating layer IL1c, a second insulating layer IL2c disposed on the second conductive layer, and a third insulating layer IL3c disposed on the second insulating layer IL2c.

[0153] The first insulating layer IL1c may include an inorganic material. For example, the inorganic material may be silicon nitride. The thickness of the first insulating layer IL1c may be 3000 angstroms.

[0154] The second insulating layer IL2c and the third insulating layer IL3c include an organic material, and a refractive index of the third insulating layer IL3c may be higher than a refractive index of the second insulating layer IL2c.

[0155] The second insulating layer IL2c may have a first opening OP1-C and a second opening OP2-C surrounding the first opening OP1-C. The second opening OP2-C may be defined by a first sidewall SWa and a second sidewall SWb. The first sidewall SWa may be a sidewall closer to the first opening OP1-C than the second sidewall SWb.

[0156] Some of the light provided from the display panel DP may be totally reflected at the second side wall SWb, and thus may have a changed light path, thereby improving light efficiency. The closer the second side wall SWb is to the first pixel region PXA-R, the better the light emitting efficiency. That is, in order to improve the light emitting efficiency, the first side wall SWa and the second side wall SWb should have a short distance WTDc therebetween, which may cause process failure. Fig.10b A cross-sectional view showing the location where process failure occurs is shown in FIG.

[0157] refer to Fig.10b Since the first side wall SWa and the second side wall SWb are not properly provided, a failure area EAR in which the third insulating layer IL3c is not filled may be generated in the area corresponding to the second opening OP2-C. In the failure area EAR, there is no difference in refractive index. Therefore, the optical path of light emitted in the lateral direction is not controlled, thereby possibly reducing light efficiency.

[0158] However, according to Fig. 9 In the embodiment of the present invention shown, the first opening OP1-R and the second opening OP2-R are defined in different insulating layers, for example, in the first insulating layer IL1 and the second insulating layer IL2. Therefore, even when the distance WTD between the first side wall SW1 defining the first opening OP1-R and the second side wall SW2 defining the second opening OP2-R is reduced, the phenomenon that the second side wall SW2 is not properly disposed may not occur.

[0159] Fig.11 is according to an embodiment of the present invention along the corresponding Figure 7 A cross-sectional view taken along the line II-II'. Fig.11 When Fig. 9 Components that are substantially the same are denoted by the same reference numerals, and description thereof is omitted.

[0160] Reference Fig.11 The input sensing layer ISLa may further include a fourth insulating layer IL4. The fourth insulating layer IL4 may be disposed between the first insulating layer IL1 and the second insulating layer IL2. For example, the fourth insulating layer IL4 may be disposed between the first insulating layer IL1 and the second conductive layer CL2 (see Fig. 9 ). In this case, the through hole HL-I (see Figure 8 ) may be defined on the first insulating layer IL1 and the fourth insulating layer IL4. In the embodiment of the present invention, the fourth insulating layer IL4 may be disposed between the second conductive layer CL2 and the second insulating layer IL2. That is, the fourth insulating layer IL4 may cover the second conductive layer CL2.

[0161] On the fourth insulating layer IL4, a third opening OP3 may be defined. In a plane, the third opening OP3 may overlap with the first pixel region PXA-R. The third opening OP3 may be larger than the first opening OP1-R and may be smaller than the second opening OP2-R. Therefore, in a cross section, the sidewalls of the first insulating layer IL1 defining the first opening OP1-R, the third opening OP3, and the second opening OP2-R, the sidewalls of the fourth insulating layer IL4, and the sidewalls of the second insulating layer IL2, and some upper surfaces adjacent to the above-mentioned sidewalls may have a step shape.

[0162] The third insulating layer IL3 may be filled in the third opening OP3. The fourth insulating layer IL4 may have a fourth refractive index lower than the third refractive index of the third insulating layer IL3. Light emitted from the display panel DP in the lateral direction may be totally reflected at a boundary between the third insulating layer IL3 and the fourth insulating layer IL4. Therefore, the optical path of the totally reflected light may be changed to a third direction DR3 or a direction close to the third direction DR3. As a result, the display device DD (see Figure 1 )'s light efficiency.

[0163] Fig.12 is according to an embodiment of the present invention along the corresponding Figure 7 A cross-sectional view taken along the line II-II'. Fig.12 In the description of Fig. 9 Components that are substantially the same are denoted by the same reference numerals, and description thereof is omitted.

[0164] Reference Fig.12 The input sensing layer ISLb may further include a fourth insulating layer IL4-1. The fourth insulating layer IL4-1 may be disposed on the second insulating layer IL2. In addition, the fourth insulating layer IL4-1 may be covered by the third insulating layer IL3.

[0165] On the fourth insulating layer IL4-1, a third opening OP3-1 may be defined. On a plane, the third opening OP3-1 may overlap with the first pixel region PXA-R. The third opening OP3-1 may be larger than the first opening OP1-R and the second opening OP2-R.

[0166] The third insulating layer IL3 may be filled in the third opening OP3-1. The fourth insulating layer IL4-1 may have a fourth refractive index lower than the third refractive index of the third insulating layer IL3. Light emitted from the display panel DP in the lateral direction may be totally reflected at a boundary between the third insulating layer IL3 and the fourth insulating layer IL4-1. Therefore, the optical path of the totally reflected light may be changed to a third direction DR3 or a direction close to the third direction DR3. As a result, the display device DD (see Figure 1 )'s light efficiency.

[0167] Figures 13a to 13g is a cross-sectional view illustrating a method for manufacturing a display device DD according to an embodiment of the present invention.

[0168] refer to Fig.13a , a display panel DP including a plurality of pixel areas PXA1 , PXA2 , and PXA3 is provided.

[0169] The step of providing the display panel DP may include the steps of: providing a base layer BL; providing a circuit layer ML on the base layer BL; providing a light emitting element layer EL on the circuit layer ML; and providing an encapsulation layer TFE on the light emitting element layer EL.

[0170] Each of the plurality of pixel areas PXA1, PXA2, and PXA3 may correspond to a reference Figure 7 Each of the first pixel area PXA-R, the second pixel area PXA-B, and the third pixel area PXA-G is described.

[0171] Reference Fig.13b A buffer layer BFL-1 is provided on the display panel DP. A first conductive layer CL1 is provided on the buffer layer BFL-1.

[0172] On the first conductive layer CL1, a first preliminary layer PRL1 is provided. The first preliminary layer PRL1 may be a photoresist layer. The first preliminary layer PRL1 may be a negative photoresist layer or a positive photoresist layer. Fig.13b , an example in which the first preliminary layer PRL1 is a negative photoresist layer will be described.

[0173] On the first preliminary layer PRL1, a mask MK is set. The mask MK may be a binary mask including a transmission portion and a light shielding portion. After the mask MK is set, light is irradiated. When the photosensitized first preliminary layer PRL1 is developed, a portion of the first preliminary layer PRL1 not irradiated with light may be removed.

[0174] Reference Fig.13c , the first preliminary layer PRL1 may be patterned to provide a first insulating layer IL1. On the first insulating layer IL1, a first opening OP1 and a through hole HL-I may be provided. The first opening OP1 may correspond to Figure 7 The first openings OP1-R, OP1-G and OP1-B are shown.

[0175] Reference Fig.13d , a second conductive layer CL2 is provided on the first insulating layer IL1.

[0176] refer to Fig.13e , on the second conductive layer CL2, a second preliminary layer PRL2 is provided. The second preliminary layer PRL2 may be a photoresist layer.

[0177] refer to Fig.13f , the second preliminary layer PRL2 may be patterned to provide a second insulating layer IL2. On the second insulating layer IL2, a second opening OP2 may be provided. The second opening OP2 may correspond to Figure 7 The second openings OP2-R, OP2-G and OP2-B are shown.

[0178] Reference Figure 13g A third insulating layer IL3 is provided on the second insulating layer IL2. The refractive index of the third insulating layer IL3 may be higher than the refractive indexes of the first insulating layer IL1 and the second insulating layer IL2. The third insulating layer IL3 may be filled in the first opening OP1 and the second opening OP2.

[0179] Although the present invention has been described with reference to the preferred embodiments of the present invention, it will be understood by those skilled in the art that various modifications and changes may be made in form and detail without departing from the spirit and scope of the present invention as set forth in the appended claims. Therefore, the technical scope of the present invention is not intended to be limited to the contents set forth in the detailed description of the present disclosure, but is intended to be defined by the appended claims.

[0180] Industrial Applicability

[0181] The present invention, which improves the light efficiency of a display device, is highly applicable industrially.

Claims

1. A display device, comprising: A display panel including a pixel region; as well as An input sensing sensor is disposed on the display panel, wherein the input sensing sensor comprises: A first conductive layer, disposed on the display panel; a first insulating layer disposed on the first conductive layer and having a first opening defined in a region overlapping the pixel region; a second conductive layer, disposed on the first insulating layer; a second insulating layer disposed on the second conductive layer and having a second opening defined in a region overlapping the pixel region; and a third insulating layer, disposed on the second insulating layer and filling the first opening and the second opening, In the cross section, the sidewalls of the first insulating layer and the second insulating layer defining the first opening and the second opening and the upper surface of the first insulating layer adjacent to the sidewalls have a step shape.

2. The display device according to claim 1, wherein: The first insulating layer has a first refractive index, the second insulating layer has a second refractive index, and the third insulating layer has a third refractive index higher than the first and second refractive indices.

3. The display device according to claim 1, wherein: In a plane, an area of ​​the first opening is smaller than an area of ​​the second opening.

4. The display device according to claim 1, wherein: In a plane, an area of ​​the first opening is equal to or larger than an area of ​​the pixel region.

5. The display device according to claim 1, wherein: On a plane, a side surface of the first insulating layer defining the first opening is surrounded by a side surface of the second insulating layer defining the second opening.

6. The display device according to claim 1, wherein: The first conductive layer includes a connection portion, and the second conductive layer includes a sensor portion.

7. The display device according to claim 6, wherein: Each of the sensor portions has a grid shape, the sensor portion has a sensor opening defined on a plane, and the sensor opening overlaps the first opening and the second opening.

8. The display device according to claim 2, wherein: The first refractive index and the second refractive index are each 1.45 to 1.55, and the third refractive index is 1.60 to 1.

70.

9. The display device according to claim 1, wherein: The display panel comprises: Base layer; A circuit layer, disposed on the base layer; a light-emitting layer, disposed on the circuit layer; and an encapsulation layer, disposed on the light-emitting layer, and The input sensing sensor is disposed in direct contact with the encapsulation layer.

10. The display device according to claim 9, wherein: The input sensing sensor further comprises: The buffer layer is in direct contact with the packaging layer, and the buffer layer is arranged between the packaging layer and the first conductive layer.

11. A display device, comprising: A display panel including a pixel region; a first insulating layer disposed on the display panel, having a first refractive index and having a first opening defined in a region overlapping the pixel region; a second insulating layer, disposed on the first insulating layer, having a second refractive index and having a second opening larger than the first opening in a region corresponding to the first opening; as well as a third insulating layer, covering the display panel, the first insulating layer and the second insulating layer, and having a third refractive index higher than the first refractive index and the second refractive index, and overlapping the third insulating layer with the pixel area in a plane, In the cross section, the sidewalls of the first insulating layer and the second insulating layer defining the first opening and the second opening and the upper surface of the first insulating layer adjacent to the sidewalls have a step shape.

12. The display device according to claim 11, further comprising: A first conductive layer, disposed between the display panel and the first insulating layer; as well as The second conductive layer is disposed between the first insulating layer and the second insulating layer.

13. The display device according to claim 12, further comprising: a fourth insulating layer, disposed between the first insulating layer and the second conductive layer, and having a fourth refractive index lower than the third refractive index, A third opening which is larger than the first opening and smaller than the second opening is defined in the fourth insulating layer.

14. The display device according to claim 12, wherein: The first conductive layer includes a connection portion, and the second conductive layer includes a sensor portion.

15. The display device according to claim 14, wherein: Each of the sensor portions has a grid shape, and in a plane, the sensor portions do not overlap with the pixel area.

16. The display device according to claim 14, wherein: Each of the sensor portions has a grid shape, the sensor portion has a sensor opening defined on a plane, and the sensor opening overlaps the first opening and the second opening.

17. The display device according to claim 11, further comprising: a fourth insulating layer, disposed between the second insulating layer and the third insulating layer, and having a fourth refractive index lower than the third refractive index, Wherein, a third opening larger than the second opening is defined in the fourth insulating layer.

18. The display device according to claim 11, wherein: On a plane, a side surface of the first insulating layer defining the first opening is surrounded by a side surface of the second insulating layer defining the second opening.

19. The display device according to claim 11, wherein: The first refractive index and the second refractive index are each 1.45 to 1.55, and the third refractive index is 1.60 to 1.

70.

20. The display device according to claim 11, wherein: The third insulating layer is filled in each of the first opening and the second opening.

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