Semiconductor device and method for forming the same

Abstract

In an embodiment, a device includes: a first interconnect structure including a metallization pattern; a second interconnect structure including a power rail; a device layer located between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source / drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization pattern, and the conductive via contacting the epitaxial source / drain region. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic devices, such as, for example, personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry is increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby enabling more components to be integrated into a specific area. However, as the minimum feature size decreases, other issues arise that should be addressed. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor device, comprising: a nanostructure; a gate structure surrounding the nanostructure; an epitaxial source / drain region adjacent to the gate structure; a first dielectric layer located above an upper portion of the epitaxial source / drain region; a second dielectric layer located below a lower portion of the epitaxial source / drain region; and a power rail via extending through the first dielectric layer and the second dielectric layer, the power rail via being physically and electrically coupled to the upper portion and the lower portion of the epitaxial source / drain region.

[0005] Other embodiments of the present application provide a semiconductor device, comprising: a first interconnect structure including a metallization pattern; a second interconnect structure including a power rail; a device layer located between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source / drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization pattern, the conductive via contacting the epitaxial source / drain region.

[0006] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a nanostructure above a fin; forming a gate structure around the nanostructure; growing an epitaxial source / drain region adjacent to the gate structure; depositing a first dielectric layer on the epitaxial source / drain region; forming a first contact through the first dielectric layer to contact the epitaxial source / drain region; and forming a second contact through the fin to contact the epitaxial source / drain region and the first contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various embodiments of the present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 An example of a simplified nanostructure field effect transistor (nanoFET) is shown in accordance with some embodiments.

[0009] Figures 2 to 14B are various views of intermediate stages in fabricating a nanoFET according to some embodiments.

[0010] Figures 15 to 22 are various views of intermediate stages in the fabrication of a semiconductor device according to some embodiments.

[0011] FIG. 23A to FIG. 31 are various views of intermediate stages in the fabrication of a semiconductor device according to some other embodiments.

[0012] FIG. 32A to FIG. 40 are various views of intermediate stages in the fabrication of a semiconductor device according to some other embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] According to various embodiments, a semiconductor device having a device layer disposed between two interconnect structures is formed. The device layer includes transistors, for example, nanostructured field effect transistors (nano FETs). One of the interconnect structures is located at the front side of the device layer and includes conductive components that interconnect the transistors of the device layer to form a functional circuit. The other interconnect structure is located on the back side of the device layer and includes conductive components for providing a power supply circuit for the device layer. Specifically, the backside interconnect structure includes a dedicated power rail for providing a reference voltage, a power supply voltage, etc. to the functional circuit. A conductive via is formed to pass through the device layer, connecting the conductive components of the backside interconnect structure to the conductive components of the frontside interconnect structure. Forming such a conductive via allows the interconnect structure to be connected through a conductive component rather than a semiconductor component, which can improve the performance of the resulting semiconductor device.

[0016] Figure 1 An example of a simplified nanoFET is shown in accordance with some embodiments. Figure 1 It is a three-dimensional cross-sectional view, and some components of the nano FET are omitted for clarity of illustration. The nano FET may be a nanosheet field effect transistor (NSFET), a nanowire field effect transistor (NWFET), a gate-all-around field effect transistor (GAAFET), etc.

[0017] The nanoFET includes a nanostructure 56 above a substrate 50, such as a fin 54 extending from the substrate 50. The nanostructure 56 is a semiconductor layer that serves as a channel region of the nanoFET. An isolation region 60, such as a shallow trench isolation (STI) region, is disposed above the substrate 50 and between adjacent fins 54, which may protrude above and between adjacent isolation regions 60. Although the isolation regions 60 are described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may refer to a separate substrate 50 or a combination of a substrate 50 and an isolation region 60. In addition, although the fin 54 is shown as a single continuous material with the substrate 50, the fin 54 and / or the substrate 50 may include a single material or multiple materials. In this document, the fin 54 refers to the portion that extends above and between adjacent isolation regions 60.

[0018] The gate structure 100 wraps around the nanostructure 56. The gate structure 100 includes a gate dielectric 102 and a gate electrode 104. The gate dielectric 102 is along the top surface, sidewalls, and bottom surface of the nanostructure 56, and may extend along the sidewalls and / or top surface of the fin 54. The gate electrode 104 is above the gate dielectric 102. Epitaxial source / drain regions 92 are disposed on opposite sides of the gate structure 100. In embodiments where multiple transistors are formed, the epitaxial source / drain regions 92 may be shared between the transistors. For example, adjacent epitaxial source / drain regions 92 may be electrically coupled, such as by agglomerating the epitaxial source / drain regions 92 through epitaxial growth, or by coupling the epitaxial source / drain regions 92 to the same source / drain contacts. Overlying the epitaxial source / drain regions 92 and / or the gate structure 100 are one or more interlayer dielectric (ILD) layers (discussed in more detail below), through which contacts are formed to the epitaxial source / drain regions 92 and the gate electrode 104 (discussed in more detail below).

[0019] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate use in planar devices such as planar FETs or fin field effect transistors (FinFETs).

[0020] Figure 1 A reference cross section used in subsequent figures is further shown. Section AA is along the longitudinal axis of the nanostructure 56 and in the direction of current flow between epitaxial source / drain regions 92 such as a nanoFET. For clarity of illustration, subsequent figures refer to this reference cross section.

[0021] Figures 2 to 14B are various views of intermediate stages in fabricating a nanoFET according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A and Fig.14A Shown with Figure 1 A 3D view similar to that of FIG. 1 , additionally showing a gate structure and two fins. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B It is along Figure 1 A cross-sectional view is shown in reference section AA. Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A and Fig.14A is a simplified three-dimensional view and does not show the corresponding Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B all parts of the.

[0022] exist Figure 2 In the invention, a substrate 50 for forming a nano FET is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0023] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device such as an NMOS transistor, for example, an n-type nano FET, and the p-type region 50P can be used to form a p-type device such as a PMOS transistor, for example, a p-type nano FET. The n-type region 50N can be physically separated from the p-type region 50P (not shown separately), and any number of device components (e.g., other active devices, doped channel regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P.

[0024] The substrate 50 may be lightly doped with p-type or n-type impurities. An anti-punch-through (APT) implant may be performed on the upper portion of the substrate 50 to form an APT region. During the APT implant, dopants may be implanted into the n-type region 50N and the p-type region 50P. The dopants may have a conductivity type opposite to the conductivity type of the source / drain region that will be subsequently formed in each of the n-type region 50N and the p-type region 50P. The APT region may extend below the source / drain region that will be subsequently formed in the nanoFET, which will be formed in a subsequent process. The APT region may be used to reduce leakage from the source / drain region to the substrate 50. In some embodiments, the doping concentration in the APT region may be about 10 18 cm -3 to about 10 19 cm -3 within the range.

[0025] A multilayer stack 52 is formed over the substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 52A and second semiconductor layers 52B. The first semiconductor layers 52A are formed of a first semiconductor material and the second semiconductor layers 52B are formed of a second semiconductor material. The semiconductor materials can each be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes four layers of each of the first semiconductor layers 52A and the second semiconductor layers 52B. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 52A and second semiconductor layers 52B.

[0026] In the illustrated embodiment, the second semiconductor layer 52B will be used to form the channel region of the nanoFET in both the n-type region 50N and the p-type region 50P. The first semiconductor layer 52A is a sacrificial layer (or dummy layer) that will be removed in subsequent processing to expose the top and bottom surfaces of the second semiconductor layer 52B in both regions. The second semiconductor material of the second semiconductor layer 52B is a material suitable for n-type and p-type nanoFETs, such as silicon; and the first semiconductor material of the first semiconductor layer 52A is a material having a high etching selectivity to the etching of the second semiconductor material, such as silicon germanium.

[0027] In another embodiment, the first semiconductor layer 52A will be used to form a channel region of a nanoFET in one region (e.g., the p-type region 50P), and the second semiconductor layer 52B will be used to form a channel region of a nanoFET in another region (e.g., the n-type channel region 50N). The first semiconductor material of the first semiconductor layer 52A can be suitable for a p-type nanoFET, such as silicon germanium (e.g., Si x Ge 1-x, where x may be in the range of 0 to 1), pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc.; the second semiconductor material of the second semiconductor layer 52B may be suitable for n-type nano FETs, such as silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, etc. The first semiconductor material and the second semiconductor material may have high etching selectivity in etching each other, so that the first semiconductor layer 52A may be removed without removing the second semiconductor layer 52B in the n-type region 50N, and the second semiconductor layer 52B may be removed without removing the first semiconductor layer 52A in the p-type region 50P.

[0028] Each layer of the multilayer stack 52 can be formed using processes such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Each layer can be formed to a smaller thickness, such as a thickness in the range of about 5nm to about 30nm. In some embodiments, one group of layers (e.g., the second semiconductor layer 52B) is formed to be thinner than another group of layers (e.g., the first semiconductor layer 52A). For example, in an embodiment where the second semiconductor layer 52B is used to form a channel region and the first semiconductor layer 52A is a sacrificial layer (or a dummy layer), the first semiconductor layer 52A can be formed to a first thickness T1, and the second semiconductor layer 52B can be formed to a second thickness T2, which is about 30% to about 60% less than the first thickness T1. Forming the second semiconductor layer 52B to a smaller thickness allows the channel region to be formed at a greater density.

[0029] exist Figure 3 , trenches are etched in the substrate 50 and the multilayer stack 52 to form fins 54 and nanostructures 56. The fins 54 are semiconductor strips patterned in the substrate 50. The nanostructures 56 include the remaining portion of the multilayer stack 52 located on the fins 54. Specifically, the nanostructures 56 include alternating first nanostructures 56A and second nanostructures 56B. The first nanostructures 56A and the second nanostructures 56B are formed by the remaining portions of the first semiconductor layer 52A and the second semiconductor layer 52B, respectively. After formation, the second nanostructures 56B at the middle level of the structure are respectively arranged between the two first nanostructures 56A. Etching can be any feasible etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof, and can be performed with a mask 58 having a pattern of the fins 54 and the nanostructures 56. Etching can be anisotropic.

[0030] The fins 54 and nanostructures 56 may be patterned by any suitable method. For example, one or more photolithography processes may be used to pattern the fins 54 and nanostructures 56, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes to form, for example, patterns with a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers are used as a mask 58 to pattern the fins 54 and nanostructures 56. In some embodiments, the mask 58 (or other layers) may remain on the nanostructure 56.

[0031] The width of the fin 54 and the nanostructure 56 may be in the range of about 8 nm to about 40 nm. For ease of illustration, the fins 54 and the nanostructures 56 in the n-type region 50N and the p-type region 50P are shown as having substantially equal widths. In some embodiments, the fins 54 and the nanostructures 56 of one region (e.g., the n-type region 50N) may be wider or narrower than the fins 54 and the nanostructures 56 of another region (e.g., the p-type region 50P).

[0032] Then, an STI region 60 is formed near the fin 54. The STI region 60 can be formed by depositing an insulating material over the substrate 50 and the nanostructure 56 and between adjacent fins 54. The insulating material can be an oxide such as silicon oxide, a nitride such as silicon nitride, or the like, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. Other insulating materials formed by any feasible process can also be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed so that excess insulating material covers the mask 58 (if present) or the nanostructure 56. Although the insulating material is shown as a single layer, some embodiments can use multiple layers. For example, in some embodiments, a liner can be first formed along the surface of the substrate 50, the fin 54, and the nanostructure 56. Thereafter, a filling material such as described above can be formed over the liner.

[0033] A removal process is then applied to the insulating material to remove excess insulating material on mask 58 (if present) or nanostructure 56. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof. The planarization process exposes mask 58 (if present) or nanostructure 56 so that after the planarization process is completed, the top surfaces of mask 58 (if present) or nanostructure 56 and the insulating material are coplanar (within process tolerances).

[0034] The insulating material is then recessed to form STI regions 60. The insulating material is recessed so that at least a portion of the nanostructure 56 protrudes from between adjacent STI regions 60. In the illustrated embodiment, the top surface of the STI region 60 is coplanar with the top surface of the fin 54 (within the process variation range). In some embodiments, the top surface of the STI region 60 is above or below the top surface of the fin 54. In addition, the top surface of the STI region 60 may have a plane, a convex surface, a concave surface (e.g., a depression), or a combination thereof as shown. By suitable etching, the top surface of the STI region 60 may be formed to be flat, convex, and / or concave. The STI region 60 may be recessed using a feasible etching process (e.g., an etching process that is selective to the material of the insulating material), for example, selectively etching the insulating material of the STI region 60 at a faster rate than etching the material of the fin 54 and the nanostructure 56. For example, an oxide such as dilute hydrofluoric acid (dHF) may be used to remove the oxide.

[0035] Mask 58 (or other layers) may be removed before, during, or after forming STI regions 60. For example, mask 58 may be removed by an etching process used to pattern fins 54 and nanostructures 56 or by an etching process used to recess STI regions 60. In another embodiment, mask 58 is removed by another etching process after recessing STI regions 60.

[0036] The above process is just one example of how to form the fin 54 and the nanostructure 56. In some embodiments, the fin 54 and the nanostructure 56 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer to expose the substrate 50 below. The epitaxial structure can be epitaxially grown in the groove, and the dielectric layer can be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 54 and the nanostructure 56. The epitaxial structure may include the above-described alternating semiconductor materials, such as a first semiconductor material and a second semiconductor material. In embodiments where the epitaxial structure is epitaxially grown, the epitaxially grown material can be in-situ doped during growth, which can avoid previous and / or subsequent implants, although in-situ doping and implant doping can be used together.

[0037] In addition, suitable wells may be formed inside substrate 50, fins 54, and / or nanostructures 56. In some embodiments, a p-type well may be formed in n-type region 50N, and an n-type well may be formed in p-type region 50P. In another embodiment, a p-type well or an n-type well may be formed in both n-type region 50N and p-type region 50P.

[0038] In embodiments with different well types, photoresist or other masks may be used to implement different implantation steps for n-type region 50N and p-type region 50P. For example, a photoresist may be formed over fin 54, nanostructure 56, and STI region 60 in n-type region 50N. The photoresist is patterned to expose p-type region 50P. The photoresist may be formed using a spin coating technique and may be patterned using a feasible photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in p-type region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region, with a concentration of about 10 13 cm -3 to about 10 14 cm -3 After implantation, the photoresist is removed by, for example, an ashing process where applicable.

[0039] After implanting the p-type region 50P, a photoresist is formed over the fin 54, nanostructure 56, and STI region 60 in the p-type region 50P. The photoresist is patterned to expose the p-type region 50N. The photoresist may be formed using a spin coating technique and may be patterned using a feasible photolithography technique. Once the photoresist is patterned, a p-type impurity implantation is performed in the n-type region 50P, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50N. The p-type impurity may be boron, boron fluoride, indium, etc., implanted into the region, and its concentration may be about 10 13 cm -3 to about 10 14 cm -3 After implantation, the photoresist may be removed by, for example, an ashing process where applicable.

[0040] After implanting n-type region 50N and p-type region 50P, annealing may be performed to repair implant damage and activate implanted p-type and / or n-type impurities. In some embodiments, the grown material of the epitaxial fin may be doped in situ during growth, which may eliminate implantation, although in situ doping and implantation doping may be used together.

[0041] exist Figure 4In the embodiment of the present invention, a pseudo dielectric layer 62 is formed on the fin 54 and the nanostructure 56. The pseudo dielectric layer 62 may be, for example, silicon oxide, silicon nitride, and combinations thereof, and may be deposited or thermally grown according to feasible techniques. A pseudo gate layer 64 is formed above the pseudo dielectric layer 62, and a mask layer 66 is formed above the pseudo gate layer 64. The pseudo gate layer 64 may be deposited above the pseudo dielectric layer 62 and then planarized, for example, by CMP. The mask layer 66 may be deposited above the pseudo gate layer 64. The pseudo gate layer 64 may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, metal nitride, metal silicide, metal oxide, and metal. The pseudo gate layer 64 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The pseudo gate layer 64 may be made of a material having a high etch selectivity to the etching of insulating materials, for example, the material of the STI region 60 and / or the pseudo dielectric layer 62. The mask layer 66 may include one or more layers, such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 64 and a single mask layer 66 are formed across the n-type region 50N and the p-type region 50P. Although the dummy dielectric layer 62 is shown as covering the STI region 60, it should be understood that the dummy dielectric layer 62 may be formed in other ways. In some embodiments, such as when the dummy dielectric layer 62 is thermally grown, the dummy dielectric layer 62 is formed to cover only the fin 54 and the nanostructure 56.

[0042] FIG. 5A to FIG. 14B Other intermediate stages in the fabrication of the nanoFET are shown. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B This may be applicable to both the n-type region 50N and the p-type region 50P. The differences in the structures of the n-type region 50N and the p-type region 50P, if any, are described in the text accompanying each drawing.

[0043] exist Figure 5A and Figure 5BIn the embodiment of the present invention, the mask layer 66 is patterned using feasible photolithography and etching techniques to form a mask 76. The pattern of the mask 76 is then transferred to the dummy gate layer 64 by a feasible etching technique to form a dummy gate 74. The pattern of the mask 76 can optionally be further transferred to the dummy dielectric layer 62 by a feasible etching technique to form a pseudo dielectric 72. The dummy gate 74 covers a portion of the nanostructure 56, which will be exposed in subsequent processing to form a channel region. Specifically, the dummy gate 74 extends along the portion of the nanostructure 56 that will be used to form the channel region 68. The pattern of the mask 76 can be used to physically separate adjacent dummy gates 74. The dummy gate 74 may also have a length direction substantially perpendicular to the length direction of the fin 54 (within the process variation range). The mask 76 can be optionally removed after patterning, such as by a feasible etching technique.

[0044] exist Fig. 6A and Figure 6B In the embodiment of the present invention, a gate spacer 80 is formed above the nanostructure 56 and the fin 54, on the exposed sidewalls of the mask 76, the pseudo gate 74 and the pseudo dielectric 72. The gate spacer 80 can be formed by conformally forming an insulating material and then etching the insulating material. The insulating material of the gate spacer 80 can be silicon nitride, silicon carbon nitride, silicon oxycarbide or a combination thereof, and formed by thermal oxidation, deposition or a combination thereof. The gate spacer 80 can be formed by a single layer of insulating material or a multilayer insulating material. In some embodiments, each gate spacer 80 includes a multilayer of silicon oxycarbide, wherein each layer may have a different silicon oxycarbide component. In some embodiments, each gate spacer 80 includes a silicon oxide layer disposed between two layers of silicon nitride. Other spacer structures can be formed. The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching such as RIE, NBE, etc. After etching, the gate spacer 80 can have a straight sidewall or a curved sidewall.

[0045] Prior to forming the gate spacer 80, an implantation of a lightly doped source / drain (LDD) region may be performed. In embodiments having different device types, similar to the implantation discussed above, a mask (e.g., photoresist) may be formed over the n-type region 50N while exposing the p-type region 50P, and impurities of a suitable type (e.g., p-type) may be implanted into the nanostructures 56 and fins 54 exposed in the p-type region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over the p-type region 50P while exposing the n-type region 50N, and impurities of a suitable type (e.g., n-type) may be implanted into the nanostructures 56 and fins 54 exposed in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The impurity concentration of the lightly doped source / drain region may be about 10 15 cm -3 to about 1019 cm -3 Annealing may be used to repair implant damage and activate the implanted impurities. During implantation, the channel region 68 remains covered by the dummy gate 74 so that substantially no impurities are implanted into the LDD region.

[0046] Note that the above disclosure generally describes the formation process of spacers and LDD regions. Other processes and sequences may be used. For example, fewer or more spacers may be used, different step sequences may be used (such as additional spacers may be formed and removed, etc.), etc. Moreover, different structures and steps may be used to form n-type and p-type devices.

[0047] After forming the gate spacers 80, source / drain recesses 82 are formed in the nanostructures 56. In the illustrated embodiment, the source / drain recesses 82 extend through the nanostructures 56 to expose the fins 54. The source / drain recesses 82 may also extend into the substrate 50 and / or the fins 54. In other words, the source / drain recesses 82 may be formed only in the nanostructures 56, such as Fig. 6A As shown, or it can be formed to extend into the fin 54, as shown Figure 6B As shown. In various embodiments, the source / drain recess 82 may extend to the top surface of the substrate 50 without etching the substrate 50; the substrate 50 may be etched so that the bottom surface of the source / drain recess 82 is disposed below the top surface of the STI region 60; and so on. The source / drain recess 82 may be formed by etching the nanostructure 56 through an anisotropic etching process (such as RIE, NBE, etc.). During the etching process for forming the source / drain recess 82, the gate spacer 80 and the mask 76 collectively mask the nanostructure 56, the fin 54, and portions of the substrate 50. A single etching process may be used to etch each nanostructure 56. In other embodiments, multiple etching processes may be used to etch the nanostructure 56. After the source / drain recess 82 reaches the desired depth D1, a timed etching process may be used to stop etching the source / drain recess 82. The depth D1 may be in the range of about 40 nm to about 140 nm.

[0048] The internal spacers 84 are optionally formed on the sidewalls of the remaining portions of the first nanostructure 56A, such as those sidewalls exposed by the source / drain recesses 82. As will be discussed in more detail below, source / drain regions will be subsequently formed in the source / drain recesses 82, and the first nanostructure 56A will be subsequently replaced by corresponding gate structures. The internal spacers 84 serve as isolation components between the subsequently formed source / drain regions and the subsequently formed gate structures. Moreover, the internal spacers 84 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes (such as etching processes for subsequently forming gate structures).

[0049] As an example of forming an internal spacer 84, the source / drain recess 82 may be extended. Specifically, the portion of the sidewall of the first nanostructure 56A exposed by the source / drain recess 82 may be recessed. Although the sidewall of the first nanostructure 56A is shown as straight, the sidewall may also be concave or convex. A feasible etching process may be used to recess the sidewall, such as an etching process that is selective to the material of the first nanostructure 56A (e.g., selectively etching the material of the first nanostructure 56A at a faster rate than etching the material of the second nanostructure 56B and the fin 54). The etching may be isotropic. For example, when the fin 54 and the second nanostructure 56B are formed of silicon and the first nanostructure 56A is formed of silicon germanium, the etching process may be wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In another embodiment, the etching process may be dry etching using a fluorine-based gas such as HF. In some embodiments, the same etching process may be performed continuously to form the source / drain recess 82 and recess the sidewall of the first nanostructure 56A. The inner spacer 84 can be formed by conformally forming an insulating material and then etching the insulating material. The insulating material can be a material such as silicon nitride or silicon oxynitride, although any suitable material can be used, such as a low dielectric constant (low-k) material with a k value of less than about 3.5. The insulating material can be deposited by a conformal deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic. For example, the etching process can be a dry etch such as RIE, NBE, etc. Although the outer sidewalls of the inner spacer 84 are shown to be flush with the sidewalls of the gate spacer 80, the outer sidewalls of the inner spacer 84 can extend beyond the sidewalls of the gate spacer 80 or be recessed from the sidewalls of the gate spacer 80. In other words, the inner spacer 84 can partially fill, completely fill, or overfill the sidewall groove. In addition, although the sidewalls of the inner spacer 84 are shown to be straight, the sidewalls of the inner spacer 84 can be concave or convex.

[0050] exist Fig. 7A and Figure 7B , epitaxial source / drain regions 92 are formed in source / drain recesses 82. Epitaxial source / drain regions 92 are formed in source / drain recesses 82 so that each dummy gate 74 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, gate spacers 80 are used to separate epitaxial source / drain regions 92 from dummy gates 74 and first nanostructures 56A by an appropriate lateral distance so that epitaxial source / drain regions 92 do not short-circuit the gate of a subsequently formed nanoFET. Epitaxial source / drain regions 92 may be formed to contact internal spacers 84 (if present) and may extend beyond the sidewalls of second nanostructure 56B. Epitaxial source / drain regions 92 may apply stress on second nanostructure 56B, thereby improving performance.

[0051] The epitaxial source / drain region 92 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the epitaxial source / drain region 92 is epitaxially grown in the source / drain recess 82 in the n-type region 50N. The epitaxial source / drain region 92 may include any feasible material suitable for an n-type nano FET. For example, the epitaxial source / drain region 92 in the n-type region 50N may include a material that applies tensile strain on the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 in the n-type region 50N may have a face that protrudes from the corresponding faces of the second nanostructure 56B and the fin 54, and may have a small face.

[0052] The epitaxial source / drain region 92 in the p-type region 50P can be formed by masking the n-type region 50N. Then, the epitaxial source / drain region 92 is epitaxially grown in the source / drain recess 82 in the p-type region 50P. The epitaxial source / drain region 92 may include any feasible material suitable for a p-type nano FET. For example, the epitaxial source / drain region 92 in the p-type region 50P may include a material that applies compressive strain on the channel region 68, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 92 in the p-type region 50P may have a surface protruding from the corresponding surface of the second nanostructure 56B and the fin 54, and may have a small facet.

[0053] The epitaxial source / drain regions 92, the second nanostructures 56B and / or the fins 54 may be implanted with dopants to form source / drain regions, similar to the formation process of lightly doped source / drain regions discussed above, followed by annealing. The impurity concentration of the source / drain regions may be about 10 19 cm -3 to about 10 21 cm -3 The n-type and / or p-type impurities of the source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 92 may be in-situ doped during growth.

[0054] Due to the epitaxial process used to form the epitaxial source / drain region 92, the upper surface of the epitaxial source / drain region 92 has a small facet that extends laterally outward beyond the surface of the second nanostructure 56B and the fin 54. Therefore, the height H1 of the epitaxial source / drain region 92 is greater than the depth D1 of the source / drain recess 82. For example, the height H1 can be in the range of about 30 nm to about 120 nm. In some embodiments, as shown in FIG. Fig. 7A As shown, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed. In other embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge. Fig. 7A and Figure 7BIn the illustrated embodiment, the spacer etch used to form the gate spacers 80 is tuned to remove the spacer material so that the epitaxial source / drain regions 92 extend to the top surface of the STI regions 60. In another embodiment, the gate spacers 80 are formed to cover the portion of the sidewalls of the nanostructures 56 extending over the STI regions 60, thereby preventing epitaxial growth on the top surface of the STI regions 60.

[0055] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer. The epitaxial source / drain region 92 may use any number of semiconductor material layers. Each of the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer may be formed of a different semiconductor material and / or may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer may have a dopant concentration that is less than the second semiconductor material layer and greater than the third semiconductor material layer. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer may be grown from the fin 54, the second semiconductor material layer may be grown from the first semiconductor material layer, and the third semiconductor material layer may be grown from the second semiconductor material layer.

[0056] exist Fig. 8A and Figure 8B In the embodiment of the present invention, the first ILD 96 is formed on the epitaxial source / drain regions 92 and the STI regions 60. The first ILD 96 may be formed of a dielectric material. The dielectric material may include an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.; a nitride such as silicon nitride; or the like. Other insulating materials may be used.

[0057] The first ILD 96 can be formed by depositing a dielectric material on the epitaxial source / drain regions 92, the gate spacer 80, the mask 76 (if present) or the dummy gate 74, and the STI region 60, and then planarizing the dielectric material. The deposition can be performed by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Other feasible processes can be used to form the dielectric material. Planarization can be performed by any suitable method, such as CMP, etch-back process, a combination thereof, etc. The planarization process makes the top surface of the first ILD 96 flush with the top surface of the mask 76 or the dummy gate 74. The planarization process can also remove the mask 76 on the dummy gate 74, and the portion of the gate spacer 80 along the sidewall of the mask 76. After the planarization process, the top surfaces of the first ILD 96, the gate spacer 80, and the mask 76 (if present) or the dummy gate 74 are coplanar (within the process deviation range). Thus, the top surface of the mask 76 (if present) or the dummy gate 74 is exposed through the first ILD 96. In the illustrated embodiment, the mask 76 is retained, and the planarization process makes the top surface of the first ILD 96 flush with the top surface of the mask 76.

[0058] In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the gate spacers 80, and the STI regions 60. The CESL 94 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has a high etch selectivity compared to the etching of the first ILD 96.

[0059] exist Fig.9A and Fig. 9B In the etching process, the mask 76 (if present) and the dummy gate 74 are removed, thereby forming a groove 98. The portion of the dummy dielectric 72 in the groove 98 may also be removed. In some embodiments, the dummy gate 74 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 74 at a faster rate than etching the first ILD 96 or the gate spacer 80. During the removal, when etching the dummy gate 74, the pseudo dielectric 72 may be used as an etch stop layer. Then, the pseudo dielectric 72 may be removed after removing the dummy gate 74. Each groove 98 exposes and / or covers a portion of the channel region 68 in the second nanostructure 56B. The portion of the second nanostructure 56B used as the channel region 68 is disposed between adjacent pairs of epitaxial source / drain regions 92.

[0060] The remaining portion of the first nanostructure 56A is then removed to expand the recess 98. The remaining portion of the first nanostructure 56A can be removed by a feasible etching process that selectively etches the material of the first nanostructure 56A at a faster rate than the material of the second nanostructure 56B, the fin 54, and the STI region 60. The etching can be isotropic. For example, when the fin 54 and the second nanostructure 56B are formed of silicon and the first nanostructure 56A is formed of silicon germanium, the etching process can be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0061] The exposed portion of the second nanostructure 56B and the fin 54 may be optionally trimmed. The trimming reduces the thickness of the exposed portion of the second nanostructure 56B from the second thickness T2 (described above with reference to Figure 2 The second nanostructure 56B and the exposed portion of the fin 54 may be trimmed by a feasible etching process that selectively etches the material of the second nanostructure 56B and the fin 54 at a faster rate than etching the material of the first nanostructure 56A, the internal spacer 84, and the gate spacer 80. The etching may be isotropic. For example, when the fin 54 and the second nanostructure 56B are formed of silicon and the first nanostructure 56A is formed of silicon germanium, the etching process may be a wet etching using a dilute ammonium hydroxide-hydrogen peroxide mixture (APM), a sulfuric acid-hydrogen peroxide mixture (SPM), or the like.

[0062] exist Fig. 10A and Fig. 10B, a gate dielectric 102 and a gate electrode 104 are formed to replace the gate. The gate dielectric 102 is conformally deposited in the recess 98, such as deposited on the top surface and sidewalls of the fin 54 and the top surface, sidewalls and bottom surface of the second nanostructure 56B. The gate dielectric 102 may also be deposited on the top surface of the first ILD 96, the gate spacer 80 and the STI region 60. The gate dielectric 102 includes one or more dielectric layers, such as oxides, metal oxides, metal silicates, etc. or combinations thereof. In some embodiments, the gate dielectric 102 includes silicon oxide, silicon nitride or multiple layers thereof. In some embodiments, the gate dielectric 102 includes a high-k dielectric material, and in these embodiments, the gate dielectric 102 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead and combinations thereof. The gate dielectric 102 may be multilayered. For example, in some embodiments, each gate dielectric 102 may include a silicon oxide interface layer formed by thermal oxidation or chemical oxidation and a metal oxide layer over the interface layer. The gate dielectric 102 may be formed by molecular beam deposition (MBD), ALD, PECVD, and the like.

[0063] The gate electrode 104 is deposited over the gate dielectric 102, respectively, and fills the remaining portion of the groove 98. The gate electrode 104 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination thereof, or a multilayer thereof. For example, although a single-layer gate electrode 104 is shown, the gate electrode 104 may include any number of liner layers, any number of work function modulation layers, and filling materials. Any combination of layers constituting the gate electrode 104 may be deposited in the region between the second nanostructure 56B and between the fin 54 and the second nanostructure 56B. The formation method of the gate electrode 104 may include ALD, PECVD, etc. After filling the groove 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric 102 and gate electrode 104 materials, which are located above the top surface of the first ILD 96 and the gate spacer 80. Therefore, the remaining portions of the gate dielectric 102 and gate electrode 104 materials form a replacement gate of the resulting nanoFET. The gate dielectric 102 and the gate electrode 104 may be collectively referred to as a gate structure 100 or a “gate stack”.

[0064] The formation of the gate dielectric 102 in the region 50N and the region 50P can be performed simultaneously, so that the gate dielectric 102 in each region is formed of the same material, and the formation of the gate electrode 104 can be performed simultaneously, so that the gate electrode 104 in each region is formed of the same material. In some embodiments, the gate dielectric 102 in each region can be formed by different processes, so that the gate dielectric 102 can be a different material, and / or the gate electrode 104 in each region can be formed by different processes, so that the gate electrode 104 can be a different material. When different processes are used, different masking steps can be used to cover and expose appropriate areas.

[0065] exist Fig.11A and Fig. 11B In the embodiment, source / drain contact openings 106 are formed through the first ILD 96 and the CESL 94. The source / drain contact openings 106 may be initially formed in the first ILD 96 using applicable photolithography and etching techniques, such as using an etching process that is selective to the first ILD 96 (e.g., etching the material of the first ILD 96 at a faster rate than etching the material of the CESL 94). For example, the source / drain contact openings 106 may be initially formed through the first ILD 96 by dry etching using ammonia (NH3) and hydrogen fluoride (HF) gases. The source / drain contact openings 106 are then extended through the CESL 94 using applicable photolithography and etching techniques, such as using an etching process that is selective to the CESL 94 (e.g., etching the material of the CESL 94 at a faster rate than etching the material of the epitaxial source / drain regions 92). For example, the source / drain contact openings 106 may be extended through the CESL 94 by dry etching using a fluorine-based gas (e.g., C4F6) and hydrogen (H2) or oxygen (O2). The source / drain contact openings 106 are then partially extended into the epitaxial source / drain regions 92, for example, to the upper portions of the epitaxial source / drain regions 92. For example, the source / drain contact openings 106 may be extended to the upper portions of the epitaxial source / drain regions 92 by dry etching using chlorine (Cl2) gas, hydrogen bromide (HBr) gas, and oxygen (O2) gas.

[0066] After formation, the source / drain contact openings 106 extend a distance D2 into the upper portion of the epitaxial source / drain regions 92. In some embodiments, the distance D2 is approximately half the height H1 of the epitaxial source / drain regions 92. After the source / drain contact openings 106 extend a desired distance D2 into the upper portion of the epitaxial source / drain regions 92, a timed etching process may be used to stop the etching of the source / drain contact openings 106. For example, when the above-described etchant is used to etch the epitaxial source / drain regions 92, the etching may be performed for a duration in the range of about 50 seconds to about 200 seconds, which may result in the source / drain contact openings 136 extending into the upper portion of the epitaxial source / drain regions 92 by a distance in the range of about 15 nm to about 60 nm.

[0067] The metal-semiconductor alloy region 108 is formed in the source / drain contact opening 106, for example, on the portion of the epitaxial source / drain region 92 exposed by the source / drain contact opening 106. The metal-semiconductor alloy region 108 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon-germanium-silicon region formed of both a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 108 may be formed by depositing a metal in the source / drain contact opening 106 and then performing a thermal annealing process. The metal may be any metal that can react with the semiconductor material (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source / drain region 92 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be deposited by a deposition process such as ALD, CVD, PVD, etc. In an embodiment, the metal-semiconductor alloy region 108 is a silicide region formed of titanium-silicon. After the thermal annealing process, a cleaning process such as a wet clean may be performed to remove any residual metal from the source / drain contact openings 106 (e.g., from the top surface of the first ILD 96).

[0068] In the illustrated embodiment, the source / drain contact openings 106 are formed by a self-aligned patterning method such that Fig. 11B In another embodiment, other patterning methods may be used so that some of the first ILD 96 remains in the cross section. Fig. 11B in the cross section.

[0069] exist Fig. 12A and Fig. 12BIn the embodiment of the present invention, a first source / drain contact 112A is formed in the source / drain contact opening 106. A liner such as a diffusion barrier layer, an adhesion layer, and a conductive material liner are formed in the source / drain contact opening 106 and may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The liner may be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some embodiments, the liner may include an adhesion layer, and at least a portion of the adhesion layer may be processed to form a diffusion barrier layer. The conductive material may be tungsten, cobalt, ruthenium, aluminum, nickel, copper, copper alloy, silver, gold, etc. The conductive material may be deposited by ALD, CVD, PVD, etc. A planarization process such as CMP may be performed to remove excess material from the top surface of the first ILD 96. The remaining liner and conductive material in the source / drain contact opening 106 form the first source / drain contact 112A. The first source / drain contact 112A is physically and electrically coupled to the metal-semiconductor alloy region 108. Top surfaces of the first source / drain contact 112A, the gate electrode 104, and the gate spacers 80 are coplanar (within process variations).

[0070] After formation, the first source / drain contact 112A has similar dimensions to the source / drain contact opening 106. The first source / drain contact 112A extends into the upper portion of the epitaxial source / drain region 92 by a distance D2 (see FIG. Fig. 11B ), and has a height H2. The height H2 may be in the range of about 30 nm to about 90 nm. In an embodiment where the distance D2 is about half the height H1 (see Figure 7B ), the height H2 is greater than approximately half of the height H1.

[0071] exist Fig.13A and Fig. 13B In the embodiment of the present invention, the second ILD 114 is deposited on the first ILD 96, the gate electrode 104 and the first source / drain contact 112A. The second ILD 114 can be formed of a material selected from the same group of candidate materials as the first ILD 96, and can be deposited using a method selected from the same group of candidate methods used to deposit the first ILD 96. The first ILD 96 and the second ILD 114 can be formed of the same material, or can include materials that do not contain. After formation, the second ILD 114 can be planarized, such as by CMP. In some embodiments, an etch stop layer is formed between the first ILD 96 and the second ILD 114. The etch stop layer can include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., whose etching rate is different from the etching rate of the material of the second ILD 114.

[0072] Contact openings 116 are then formed in the second ILD 114. A first subset of the contact openings 116A exposes the first source / drain contacts 112A, and a second subset of the contact openings 116B exposes the gate electrode 104. The contact openings 116 may be formed using available photolithography and etching techniques.

[0073] exist Fig.14A and Fig. 14B In the embodiment of the present invention, a second source / drain contact 112B and a gate contact 118 extending through the second ILD 114 are formed. A liner, such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the contact opening 116. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The liner may be deposited by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some embodiments, the liner may include an adhesion layer, and at least a portion of the adhesion layer may be processed to form a diffusion barrier layer. The conductive material may be tungsten, cobalt, ruthenium, aluminum, nickel, copper, copper alloy, silver, gold, etc. The conductive material may be deposited by ALD, CVD, PVD, etc. A planarization process such as CMP may be performed to remove excess material from the top surface of the second ILD 114. The remaining liner and conductive material in the contact opening 116A form the second source / drain contact 112B. The remaining liner and conductive material in the contact opening 116B form a gate contact 118. The second source / drain contact 112B is physically and electrically coupled to the first source / drain contact 112A, and the gate contact 118 is physically and electrically coupled to the gate electrode 104.

[0074] The second source / drain contact 112B and the gate contact 118 may be formed by different processes, or may be formed by the same process. In addition, the second source / drain contact 112B and the gate contact 118 may be formed in the same cross section, such as Fig. 13B and Fig. 14B As shown, or can be formed in different cross-sections, such as Fig.13A and Fig.14A As shown, this can avoid short-circuiting the contacts.

[0075] As will be discussed in more detail below, a first interconnect structure (e.g., a front-side interconnect structure) is formed over substrate 50. Substrate 50 is then removed and replaced with a second interconnect structure (e.g., a back-side interconnect structure). Thus, a device layer 120 of active devices is formed between the front-side interconnect structure and the back-side interconnect structure. Both the front-side and back-side interconnect structures include conductive features that are electrically connected to the nanoFETs of device layer 120. The conductive features of the front-side interconnect structure (e.g., a metallization pattern, also referred to as an interconnect line) will be electrically connected to the front side of one or more epitaxial source / drain regions 92 and gate electrodes 104 to form functional circuits, such as logic circuits, memory circuits, image sensor circuits, etc. The conductive features of the back-side interconnect structure (e.g., a power rail) will be electrically connected to the back side of one or more epitaxial source / drain regions 92 to provide a reference voltage, a power supply voltage, etc. to the functional circuits. In addition, conductive vias will be formed through device layer 120 to connect some conductive features of the front-side interconnect structure to some conductive features of the back-side interconnect structure. Specifically, the conductive features of the backside interconnect structure (e.g., power rails) are connected to the conductive features of the frontside interconnect structure (e.g., metallization patterns), and are also connected to one or more epitaxial source / drain regions 92 of the device layer 120. Although the device layer 120 is described as having nanoFETs, other embodiments may include a device layer 120 having different types of transistors (e.g., planar FETs, FinFETs, TFTs, etc.).

[0076] although Fig. 14B A second source / drain contact 112B is shown extending to each epitaxial source / drain region 92, but the second source / drain contact 112B may be omitted from certain epitaxial source / drain regions 92. For example, as explained in more detail below, a subset of the epitaxial source / drain regions 92P are connected to a conductive feature (e.g., a power rail) of the backside interconnect structure. In the illustrated embodiment, for these particular epitaxial source / drain regions 92P, a second source / drain contact 112B is also formed so that the power rail can be connected to the upper conductive feature of the frontside interconnect structure. In other embodiments, for these particular epitaxial source / drain regions 92P, the second source / drain contact 112B may be omitted or may be a dummy contact that is not electrically connected to the upper conductive feature of the frontside interconnect structure.

[0077] Figures 15 to 22 are various views of intermediate stages in the fabrication of a semiconductor device according to some embodiments. Specifically, the fabrication of front-side and back-side interconnect structures for a nano-FET is shown. Fig.15 , Fig.16 , Fig.17 , Fig.18B , Fig.19B , Fig. 20 , Fig.21 and Fig. 22 It is along Figure 1 A cross-sectional view is shown in reference section AA. Fig.18A and Fig.19A is shown with Figure 1 A 3D view similar to that of FIG. 1 , additionally showing a gate structure and two fins. Fig.18A and Fig.19A is a simplified three-dimensional view and does not show the corresponding Fig.18B and Fig.19B all parts of the. Fig.15 , Fig.16 , Fig.17 , Fig.18B , Fig.19B , Fig. 20 , Fig.21 and Fig. 22 This may be applicable to both the n-type region 50N and the p-type region 50P. The differences in the structures of the n-type region 50N and the p-type region 50P, if any, are described in the text accompanying each drawing.

[0078] exist Fig.15 , interconnect structure 122 is formed on device layer 120, for example, on second ILD 114. Interconnect structure 122 may also be referred to as a front-side interconnect structure because it is formed on the front side of substrate 50 / device layer 120 (eg, the side of substrate 50 where device layer 120 is located).

[0079] The interconnect structure 122 may include one or more layers of conductive features 124 formed in one or more stacked dielectric layers 126. Each dielectric layer 126 may include a dielectric material, such as a low-k dielectric material, an ultra-low-k dielectric (ELK) material, etc. The dielectric layers 126 may be deposited using a suitable process, such as CVD, ALD, PVD, PECVD, etc.

[0080] Conductive component 124 may include conductive wires and conductive vias interconnecting conductive wire layers. Conductive vias may extend through corresponding dielectric layers in dielectric layer 126 to provide vertical connections between conductive wire layers. Conductive component 124 may be formed by any feasible process. For example, conductive component 124 may be formed by a damascene process (such as a single damascene process, a dual damascene process, etc.). In the damascene process, a combination of photolithography and etching techniques is used to pattern respective dielectric layers 126 to form grooves corresponding to the desired pattern of conductive component 124. An optional diffusion barrier layer and / or an optional adhesion layer may be deposited, and then the grooves may be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or other alternatives, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, or a combination thereof. In an embodiment, conductive component 124 may be formed by depositing a seed layer of copper or a copper alloy and filling the grooves by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to respectively remove excess conductive material from the surface of the dielectric layer 126 and planarize the surface for subsequent processing.

[0081] In the illustrated example, five layers of conductive features 124 and dielectric layers 126 are shown. However, it should be understood that the interconnect structure 122 may include any number of conductive features disposed in any number of dielectric layers. The conductive features 124 of the interconnect structure 122 are electrically connected to the gate contact 118 and the second source / drain contact 112B to form a functional circuit. In some embodiments, the functional circuit formed by the interconnect structure 122 may include a logic circuit, a memory circuit, an image sensor circuit, etc. The second ILD 114, the second source / drain contact 112B, and the gate contact 118 may also be considered as part of the interconnect structure 122, such as part of the first level conductive features of the interconnect structure 122.

[0082] exist Fig.16 In the embodiment, the carrier substrate 130 is bonded to the top surface of the interconnect structure 122 by bonding layers 132A, 132B (collectively referred to as bonding layers 132). The carrier substrate 130 can be a glass carrier substrate, a ceramic carrier substrate, a semiconductor substrate (e.g., a silicon substrate), a wafer (e.g., a silicon wafer), etc. The carrier substrate 130 can provide structural support in the subsequent processing steps and in the completed device. The carrier substrate 130 is substantially free of any active or passive devices.

[0083] In various embodiments, the carrier substrate 130 may be bonded to the interconnect structure 122 by a suitable technique (e.g., dielectric bonding, etc.). The dielectric bonding may include depositing bonding layers 132A, 132B on the interconnect structure 122 and the carrier substrate 130, respectively. In some embodiments, the bonding layer 132A includes silicon oxide (e.g., high density plasma (HDP) oxide, etc.) deposited by CVD, ALD, PVD, etc. The bonding layer 132B may also be an oxide layer formed prior to bonding using, for example, CVD, ALD, PVD, thermal oxidation, etc. Other suitable materials may also be used for the bonding layers 132A, 132B.

[0084] The dielectric to dielectric bonding process also includes surface treatment of one or more bonding layers 132. The surface treatment may include plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to one or more bonding layers 132. The carrier substrate 130 is then aligned with the interconnect structure 122 and pressed against each other to initiate pre-bonding of the carrier substrate 130 with the interconnect structure 122. The pre-bonding may be performed at room temperature (e.g., in the range of about 20°C to about 25°C). After the pre-bonding, an annealing process may be applied by, for example, heating the interconnect structure 122 and the carrier substrate 130 to a temperature of about 170°C.

[0085] exist Fig.17 In the embodiment of the present invention, the intermediate structure is flipped so that the back side of the substrate 50 faces upward. The back side of the substrate 50 refers to the side opposite to the front side of the substrate 50 on which the device layer 120 is formed. The substrate 50 is then thinned to remove the back side portion of the substrate 50. The thinning process may include a planarization process (e.g., mechanical grinding, chemical mechanical polishing (CMP)), an etch back process, or a combination thereof. The thinning process exposes the surface of the STI region 60 and the fin 54 on the back side of the device layer 120.

[0086] A dielectric layer 128 is then deposited over the backside of the device layer 120, such as over the fins 54 and the STI regions 60. The dielectric layer 128 is part of an interconnect structure formed on the device layer 120. The dielectric layer 128 may physically contact the surfaces of the remaining portions of the fins 54 and the STI regions 60. The dielectric layer 128 may be formed of a material selected from the same set of candidate materials as the first ILD 96, and may be deposited using a method selected from the same set of candidate methods used to deposit the first ILD 96. The first ILD 96 and the dielectric layer 128 may be formed of the same material, or may include different materials.

[0087] exist Fig.18A and Fig.18BIn the embodiment of the present invention, a mask 134 is formed on the dielectric layer 128. The mask 134 can be formed of a photoresist, such as a single-layer photoresist, a double-layer photoresist, a triple-layer photoresist, etc. In some embodiments, the mask 134 is a triple-layer mask, including a bottom layer (e.g., a bottom anti-reflective coating (BARC) layer), an intermediate layer (e.g., a nitride, an oxide, an oxynitride, etc.), and a top layer (e.g., a photoresist). The type of mask used (e.g., a single-layer mask, a double-layer mask, a triple-layer mask, etc.) can depend on the photolithography process subsequently used to pattern the mask 134. For example, in an extreme ultraviolet (EUV) photolithography process, the mask 134 can be a single-layer mask or a double-layer mask. The mask 134 can be formed by spin coating, a deposition process such as CVD, a combination thereof, and the like. The mask 134 can be patterned using a feasible photolithography technique to form an opening having a source / drain contact pattern subsequently formed.

[0088] Source / drain contact openings 136 are formed through dielectric layer 128, fin 54, epitaxial source / drain regions 92P, and metal-semiconductor alloy regions 108. Source / drain contact openings 136 may be initially formed in dielectric layer 128 using available photolithography and etching techniques, such as using mask 134 as an etching mask, utilizing an etching process that is selective to dielectric layer 128 (e.g., etches the material of dielectric layer 128 at a faster rate than etches the material of fin 54). For example, source / drain contact openings 136 may be initially formed through dielectric layer 128 by dry etching using ammonia (NH3) and hydrogen fluoride (HF) gases. Source / drain contact openings 136 are then extended through fin 54 using available photolithography and etching techniques, such as utilizing an etching process that is selective to fin 54 (e.g., etches the material of fin 54 at a faster rate than etches the material of epitaxial source / drain regions 92). For example, the source / drain contact opening 136 may be extended through the fin 54 by dry etching using a fluorine-based gas such as hydrogen fluoride (HF). The source / drain contact opening 136 is then extended through the epitaxial source / drain region 92P and the metal-semiconductor alloy region 108 so that the source / drain contact opening 136 extends into the lower portion of the epitaxial source / drain region 92P and exposes the first source / drain contact 112A. For example, the source / drain contact opening 136 may be extended through the epitaxial source / drain region 92P and the metal-semiconductor alloy region 108 by dry etching using chlorine (Cl2) gas, hydrogen bromide (HBr) gas, and oxygen (O2) gas. In the illustrated embodiment, when the source / drain contact opening 136 is patterned, etching of the first source / drain contact 112A does not substantially occur. In another embodiment, the source / drain contact opening 136 may also extend into the first source / drain contact 112A.

[0089] The mask 134 may be removed during or after patterning the source / drain contact openings 136. For example, the mask 134 may be removed by an etching process used to pattern the dielectric layer 128, the fins 54, the epitaxial source / drain regions 92P, or the metal-semiconductor alloy regions 108. In another embodiment, the mask 134 is removed after patterning the source / drain contact openings 136, such as by a possible ashing process.

[0090] After formation, the source / drain contact opening 136 extends into the lower portion of the epitaxial source / drain region 92P by a distance D3. In some embodiments, the distance D3 is approximately the height H1 of the epitaxial source / drain region 92P (see FIG. Figure 7B ). Distance D2 (see Fig. 11B ) and D3 are equal to height H1. In other words, distances D2 and D3 can be equal. In another embodiment, distances D2 and D3 are different; for example, distance D2 can be greater than or less than distance D3. After the source / drain contact opening 136 extends into the lower portion of the epitaxial source / drain region 92P by a desired distance D3, a timed etching process can be used to stop the etching of the source / drain contact opening 136. For example, when the above-mentioned etchant is used to etch the epitaxial source / drain region 92P, the etching can be continued for about 50 seconds to about 200 seconds, which can result in the source / drain contact opening 136 extending into the lower portion of the epitaxial source / drain region 92P by a distance D3 in the range of about 15nm to about 60nm.

[0091] exist Fig.19A and Fig.19BIn the embodiment of the present invention, a metal-semiconductor alloy region 138 is formed in the source / drain contact opening 136, for example, on the portion of the epitaxial source / drain region 92P exposed by the source / drain contact opening 136. The metal-semiconductor alloy region 138 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon-germanium-silicon region formed of both a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 138 may be formed by depositing a metal in the source / drain contact opening 136 and then performing a thermal annealing process. The metal may be any metal that can react with the semiconductor material (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source / drain region 92P to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be deposited by a deposition process such as ALD, CVD, PVD, etc. In an embodiment, the metal-semiconductor alloy region 138 is a silicide region formed of titanium-silicon. After the thermal annealing process, a cleaning process such as a wet clean may be performed to remove any residual metal from the source / drain contact opening 136 (e.g., from the surface of the first source / drain contact 112A and the STI region 60). Although the metal-semiconductor alloy regions 108, 138 are shown as separate regions, it should be understood that in some embodiments, the metal-semiconductor alloy regions 108, 138 may be merged during formation so that there is no distinguishable interface between them.

[0092] The third source / drain contact 112C is formed in the source / drain contact opening 136. A liner such as a diffusion barrier layer, an adhesive layer, and a conductive material liner formed in the source / drain contact opening 136 may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The liner may be deposited by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some embodiments, the liner may include an adhesive layer, and at least a portion of the adhesive layer may be processed to form a diffusion barrier layer. The conductive material may be tungsten, cobalt, ruthenium, aluminum, nickel, copper, copper alloy, silver, gold, etc. The conductive material may be deposited by ALD, CVD, PVD, etc. A planarization process such as CMP may be performed to remove excess material from the top surface of the dielectric layer 128. The remaining liner and conductive material in the source / drain contact opening 136 form the third source / drain contact 112C. The third source / drain contact 112C is physically and electrically coupled to the first source / drain contact 112 A. The top surfaces of the third source / drain contact 112C and the dielectric layer 128 are coplanar (within process tolerances).

[0093] After formation, the third source / drain contact 112C has a size similar to the source / drain contact opening 136. The third source / drain contact 112C extends into the lower portion of the epitaxial source / drain region 92 by a distance D3 (see FIG. Fig.18B ), and has a height H3. The height H2 may be in the range of about 25 nm to about 70 nm. In an embodiment where the distance D2 is about half the height H1 (see Figure 7B ), the height H2 is greater than approximately half of the height H1.

[0094] exist Fig. 20 , a dielectric layer 142 and a conductive feature 144 are formed on the dielectric layer 128 and the third source / drain contact 112C. The dielectric layer 142 and the conductive feature 144 are also part of an interconnect structure formed on the device layer 120. The dielectric layer 142 can be formed of a material selected from the same group of candidate materials as the first ILD 96, and can be deposited using a method selected from the same group of candidate methods used to deposit the first ILD 96. The first ILD 96 and the dielectric layer 142 can be formed of the same material, or can include different materials.

[0095] Conductive component 144 is formed in dielectric layer 142 and may be a conductive line. Forming conductive component 144 may include, for example, patterning a groove in dielectric layer 142 using a combination of photolithography and etching processes. The pattern of the groove in dielectric layer 142 may correspond to the pattern of conductive component 144. Conductive component 144 is then formed by depositing a conductive material in the groove. In some embodiments, conductive component 144 includes a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, conductive component 144 includes copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, etc. Before filling the groove with conductive material, an optional diffusion barrier layer and / or an optional adhesion layer may be deposited. Suitable materials for barrier / adhesion layers include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, etc. Conductive component 144 may be formed using materials such as CVD, ALD, PVD, plating, etc. Conductive feature 144 is electrically connected to epitaxial source / drain region 92P through third source / drain contact 112C and metal-semiconductor alloy region 138. A planarization process (eg, CMP, grinding, etch back, etc.) may be performed to remove excess portions of conductive feature 144 formed over dielectric layer 142.

[0096] Some or all of the conductive features 144 are power rails 144P, which are conductive lines that electrically connect the epitaxial source / drain regions 92P to a reference voltage, a power supply voltage, etc. Advantages may be gained by placing the power rails 144P on the back side of the device layer 120 rather than the front side of the device layer 120. For example, the gate density of the nanoFETs and / or the interconnect density of the interconnect structure 122 may be increased. Additionally, the back side of the device layer 120 may accommodate wider power rails, thereby reducing resistance and improving the efficiency of power transfer to the nanoFETs. For example, the width of the conductive features 144 may be the width of the first level conductive lines (e.g., Fig.15 At least twice the width of the conductive line 124A).

[0097] The first source / drain contact 112A and the third source / drain contact 112C form a conductive via 148, which may be referred to as a power rail via. Each power rail via includes a first source / drain contact 112A and a third source / drain contact 112C. The total height of the conductive via 148 is equal to the height H2 (see FIG. Fig. 12B ) and H3 (see Fig.19B ). The conductive via 148 extends through the device layer 120 and connects the conductive features (e.g., metallization patterns) of the interconnect structure 122 to the conductive features (e.g., power rails 144) of the interconnect structure 150. A reference voltage, a power supply voltage, etc. can thus be electrically connected to the epitaxial source / drain regions 92P and the interconnect structure 122 through the conductive via 148. Advantages can be obtained by connecting the power rail 144P to the interconnect structure 122 through a conductive feature (e.g., conductive via 148) rather than a semiconductor feature (e.g., epitaxial source / drain region 92P). For example, the resistance of the conductive feature is lower than that of the semiconductor feature, thereby improving the performance of the local interconnect between the interconnect structures 122, 150. In addition, the conductive via 148 is also physically and electrically coupled to the epitaxial source / drain region 92P to which the power rail connection is desired. In this embodiment, the metal-semiconductor alloy regions 108, 138 surround and couple to the portion of the conductive via 148 that extends through the epitaxial source / drain region 92P. Because conductive vias 148 extend through epitaxial source / drain regions 92P, voltage drops across the epitaxial material of epitaxial source / drain regions 92P can be avoided during operation, thereby reducing the parasitic capacitance of the nanoFET. Finally, the same conductive features can be used to connect epitaxial source / drain regions 92P to power rails 144P and provide local interconnects between interconnect structures 122, 150, thereby reducing the number of conductive features in interconnect structure 150.

[0098] exist Fig.21, the remainder of the interconnect structure 150 is formed on the back side of the device layer 120, such as above the dielectric layer 142 and the conductive component 144. The interconnect structure 150 may also be referred to as a backside interconnect structure because it is formed on the back side of the device layer 120. The remainder of the interconnect structure 150 may be similar to the interconnect structure 122. For example, the interconnect structure 150 may include similar materials and be formed using a similar process as the interconnect structure 122. In particular, the interconnect structure 150 may include a stacked layer of conductive components 154 formed in the stacked dielectric layer 152. The conductive component 154 may include a wiring line (e.g., for wiring between a contact pad and an external connector formed subsequently). The conductive component 154 may also include a conductive via extending in the dielectric layer 152 to provide vertical interconnection between the stacked layers of conductive lines. The interconnect structure 150 therefore includes dielectric layers 128, 142, 152 and conductive components 144, 154.

[0099] In some embodiments, the conductive features of the interconnect structure 150 may be further patterned to include one or more embedded passive devices, such as resistors, capacitors, inductors, etc., in the interconnect structure 150. The embedded passive devices may be integrated with the conductive features 144, 154 (e.g., power rails 144P) to provide a circuit (e.g., a power circuit) on the back side of the device layer 120.

[0100] exist Fig. 22 , a passivation layer 160, a UBM 162, and an external connector 164 are formed on the interconnect structure 150. The passivation layer 160 may include a polymer, such as PBO, polyimide, BCB, etc. Alternatively, the passivation layer 160 may include a non-organic dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc. The passivation layer 160 may be deposited by, for example, CVD, PVD, ALD, etc.

[0101] UBM 162 is formed as a conductive component 154 that passes through passivation layer 160 and interconnect structure 150, and external connector 164 is formed on UBM 162. UBM 162 may include one or more layers of copper, nickel, gold, etc. formed by a plating process, etc. External connector 164 (e.g., solder ball) is formed on UBM 162. The formation of external connector 164 may include placing solder ball on the exposed portion of UBM 162 and then reflowing the solder ball. In an optional embodiment, the formation of external connector 164 includes performing a plating step to form a solder area above the uppermost conductive component 154 and then reflowing the solder area. In another embodiment, external connector 164 is a metal connector with substantially vertical sidewalls, such as a microbump. UBM 162 and external connector 164 can be used to provide input / output connections for other electronic components (e.g., other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, etc.). UBM 162 and external connections 164 , which may also be referred to as backside input / output pads, may provide signal, reference voltage, supply voltage, and / or ground connections for the nanoFETs of device layer 120 .

[0102] FIG. 23A to FIG. 31 are various views of intermediate stages in the fabrication of a semiconductor device according to some other embodiments. Specifically, the fabrication of front-side and back-side interconnect structures for a nano-FET is shown. Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Fig.28A , Fig.29A and Fig. 30A Shown with Figure 1 A 3D view of FIG. 1 is a similar 3D view, additionally showing two gate structures and two fins. Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B , Fig.28B , Fig.29B , Fig. 30B and Fig.31 It is along Figure 1 A cross-sectional view is shown in reference section AA. Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Fig.28A , Fig.29A and Fig. 30A is a simplified three-dimensional view and does not show the corresponding Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B , Fig.28B , Fig.29B and Fig. 30B all parts of the. Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B , Fig.28B , Fig.29B , Fig. 30B and Fig.31 This may be applicable to both the n-type region 50N and the p-type region 50P. The differences in the structures of the n-type region 50N and the p-type region 50P, if any, are described in the text accompanying each drawing.

[0103] exist Fig.23A and Fig. 23B In the reference Fig. 10A and Fig. 10B The structure of the description.

[0104] exist Fig.24A and Fig. 24B In one embodiment, one or more gate structures 100 are removed and replaced with dielectric features 172. In some embodiments, the replaced gate structures 100 are those located at the ends of the memory cell, such as the gate structures 100 located at the ends of the fins 54. The replaced gate structures 100 are adjacent to the epitaxial source / drain regions 92P to be connected to the power rail. The desired gate structures 100 can be removed using feasible photolithography and etching techniques to form openings. Dielectric features 172 are then formed in the openings. Dielectric features 172 can be formed of dielectric materials such as silicon oxide, silicon nitride, etc. Dielectric features 172 can be formed by depositing a dielectric material on the remaining gate structures 100, and then planarizing the dielectric material so that the top surfaces of the dielectric features 172 and the remaining gate structures 100 are coplanar (within process tolerances). Dielectric features 172 thus surround the nanostructures 56B surrounded by the replaced gate structures 100.

[0105] exist Fig.25A and Fig.25B , source / drain contact openings 106 are formed through the first ILD 96 and the CESL 94. In this embodiment, a first subset of source / drain contact openings 106P (e.g., those to be used to form power rail vias) are also formed through the dielectric features 172, the inner spacers 84, the gate spacers 80, and the second nanostructures 56B to expose the sidewalls of the epitaxial source / drain regions 92P. A second subset of source / drain contact openings 106R (e.g., those not used to form power rail vias) do not extend through the dielectric features 172, the inner spacers 84, the gate spacers 80, or the second nanostructures 56B.

[0106] The source / drain contact openings 106R, 106P may be formed by a variety of photolithography and etching techniques. The source / drain contact openings 106R, 106P may be initially formed in the first ILD 96 using a feasible photolithography and etching technique, such as using an etching process that is selective to the first ILD 96 (e.g., etching the material of the first ILD 96 at a faster rate than etching the material of the CESL 94). For example, the source / drain contact openings 106R, 106P may be initially formed through the first ILD 96 by dry etching using ammonia (NH3) and hydrogen fluoride (HF) gases. The source / drain contact openings 106R, 106P are then extended through the CESL 94 using a feasible photolithography and etching technique, such as using an etching process that is selective to the CESL 94 (e.g., etching the material of the CESL 94 at a faster rate than etching the material of the epitaxial source / drain regions 92). For example, the source / drain contact openings 106R, 106P may be extended through the CESL 94 by dry etching using a fluorine-based gas (e.g., C4F6) and a hydrogen (H2) or oxygen (O2) gas. The source / drain contact openings 106R are then masked, for example, by forming a photoresist over the source / drain contact openings 106R. The source / drain contact openings 106 are then extended through the dielectric features 172, the inner spacers 84, the gate spacers 80, and the second nanostructures 56B using feasible photolithography and etching techniques, for example, using an etching process that is selective to the dielectric features 172, the inner spacers 84, the gate spacers 80, and the second nanostructures 56B (e.g., etching the material of the dielectric features 172, the inner spacers 84, the gate spacers 80, and the second nanostructures 56B at a faster rate than etching the material of the epitaxial source / drain regions 92). For example, the source / drain contact opening 106P may be extended through the dielectric member 172, the inner spacer 84, the gate spacer 80, and the second nanostructure 56B by dry etching using a fluorine-based gas (e.g., C4F6) and a hydrogen (H2) or oxygen (O2) gas. The source / drain contact opening 106P may not extend into the fin 54, as shown in FIG. Fig.25A or it may be formed to extend into the fin 54, as Fig.25B shown.

[0107] After formation, the source / drain contact openings 106R, 106P partially extend into the epitaxial source / drain region 92, for example, to the upper portion of the epitaxial source / drain region 92, and the extension distance D4. In some embodiments, the distance D4 is less than the height H1 of the epitaxial source / drain region 92 (see Figure 7B). After the source / drain contact openings 106R, 106P extend into the upper portion of the epitaxial source / drain region 92 by the desired distance D4, a timed etching process may be used to stop etching the source / drain contact openings 106R, 106P. For example, when the above-mentioned etchant is used to etch the epitaxial source / drain region 92, the etching may be continued for about 10 seconds to about 40 seconds, which may result in the source / drain contact opening 136 extending into the upper portion of the epitaxial source / drain region 92P by a distance D4 in the range of about 2 nm to about 10 nm. The width W1 of the formed source / drain contact opening 106R may be in the range of about 10 nm to about 30 nm.

[0108] After these openings are extended, the source / drain contact openings 106P extend into the intermediate structure by a distance D5. In some embodiments, the distance D5 is greater than the height H1 of the epitaxial source / drain region 92. After the source / drain contact openings 106P extend into the intermediate structure by a desired distance D5, a timed etching process may be used to stop etching the source / drain contact openings 106P. For example, when the above-described etchant is used to etch the dielectric features 172, the internal spacers 84, the gate spacers 80, and the second nanostructure 56B, the etching may be continued for about 140 seconds to about 400 seconds, which may cause the source / drain contact openings 136P to extend into the intermediate structure by a distance D5 in the range of about 40 nm to about 120 nm. The upper portions of the source / drain contact openings 106R (e.g., those portions on the epitaxial source / drain region 92P) may also extend to a width W2, which may be in the range of about 10 nm to about 50 nm and greater than the width W1. Lower portions of the source / drain contact openings 106R (eg, those adjacent to the epitaxial source / drain regions 92P) may be formed to have a width W3 , which may be in a range of about 10 nm to about 30 nm and is smaller than the width W2 .

[0109] Then, a metal-semiconductor alloy region 108 is formed in the source / drain contact opening 106, for example, on the portion of the epitaxial source / drain region 92 exposed by the source / drain contact opening 106. In this embodiment, the metal-semiconductor alloy region 108 extends along the exposed sidewalls of the epitaxial source / drain region 92P. The metal-semiconductor alloy region 108 may be similar to that described in reference to Fig.11A and Fig. 11B The method described is formed.

[0110] exist Fig.26A and Fig.26B , a first source / drain contact 112A is formed in the source / drain contact opening 106. The first source / drain contact 112A may be similar to that described in reference to Fig. 12A and Fig. 12BIn this embodiment, a subset of the first source / drain contacts 112AP (eg, those formed in the source / drain contact openings 106P) extend along and contact the sidewalls and top surfaces of the epitaxial source / drain regions 92P.

[0111] After formation, the first source / drain contact 112A has similar dimensions to the source / drain contact opening 106. The first source / drain contact 112A extends into the upper portion of the epitaxial source / drain region 92 by a distance D4 (see FIG. Fig.25B ), and the portion of the first source / drain contact 112A on the epitaxial source / drain region 92 has a height of about 2 nm to about 10 nm.

[0112] exist Fig.27A and Fig.27B In the embodiment, the second ILD 114 is deposited on the first ILD 96, the gate electrode 104 and the first source / drain contact 112A. Then, a contact opening 116 is formed in the second ILD 114. The second ILD 114 and the contact opening 116 may be similar to the embodiment of the reference Fig.13A and Fig. 13B The method described is formed.

[0113] exist Fig.28A and Fig.28B In the embodiment of the present invention, a second source / drain contact 112B and a gate contact 118 are formed to extend through the second ILD 114. The second source / drain contact 112B and the gate contact 118 may be similar to those described in reference to FIG. Fig.14A and Fig. 14B As described above, the second source / drain contact 112B and the gate contact 118 may be formed in the same cross section, such as Fig.27B and Fig.28B As shown, or can be formed in different cross-sections, such as Fig.27A and Fig.28A shown.

[0114] exist Fig.29A and Fig.29B In the example, the intermediate structure can be similar to Figures 15 to 17 For example, the interconnect structure 122 may be formed, the structure may be flipped, and the substrate 50 may be replaced with the dielectric layer 128. A source / drain contact opening 136 is then formed through the dielectric layer 128 and the fin 54. The source / drain contact opening 136 may also extend into the lower portion of the epitaxial source / drain region 92P. The source / drain contact opening 136 may be similar to that described with reference to Fig.18A and Fig.18BThe source / drain contact openings 136 are formed in the manner described, for example, by using the mask 134 as an etching mask. In this embodiment, the source / drain contact openings 136 are not formed through the epitaxial source / drain regions 92P, but only partially extend to the lower portion of the epitaxial source / drain regions 92P. After the source / drain contact openings 136 extend into the lower portion of the epitaxial source / drain regions 92P by the desired distance D6, a timed etching process can be used to stop etching the source / drain contact openings 136. For example, when referring to Fig.18A and Fig.18B When the described etchant is used to etch the source / drain contact opening 136, the etching may be continued for about 90 seconds to about 240 seconds, which may allow the source / drain contact opening 136 to extend into the lower portion of the epitaxial source / drain region 92P by a distance D6 in the range of about 2 nm to about 10 nm. The source / drain contact opening 136 may be formed to have a width W3, which may be in the range of about 10 nm to about 50 nm.

[0115] exist Fig. 30A and Fig. 30B In the embodiment, the metal-semiconductor alloy region 138 is formed in the source / drain contact opening 136, for example, on the portion of the epitaxial source / drain region 92P exposed by the source / drain contact opening 136. The metal-semiconductor alloy region 138 may be similar to the reference Fig.19A and Fig.19B In some embodiments, the metal-semiconductor alloy region 138 is a curved layer that is physically coupled to a portion of the metal-semiconductor alloy region 108 that extends along the sidewalls of the epitaxial source / drain region 92P. Although the metal-semiconductor alloy regions 108, 138 are shown as separate regions, it should be understood that in some embodiments, the metal-semiconductor alloy regions 108, 138 may be merged during formation so that there is no distinguishable interface between them.

[0116] Then, a third source / drain contact 112C is formed in the source / drain contact opening 136. The third source / drain contact 112C may be similar to that described with reference to FIG. Fig.19A and Fig.19BThe third source / drain contact 112C is formed in the manner described. In this embodiment, the third source / drain contact 112C has a portion on the first source / drain contact 112AP and a portion extending into the lower portion of the epitaxial source / drain region 92P. Therefore, the third source / drain contact 112C extends along the bottom surface of the epitaxial source / drain region 92P and contacts therewith. After formation, the third source / drain contact 112C has a size similar to the source / drain contact opening 136. The first source / drain contact 112AP and the third source / drain contact 112C form a conductive via 148, which can be referred to as a power rail via. In this embodiment, the metal-semiconductor alloy region 108, 138 is disposed between each conductive via 148 and each of the top surface, sidewalls, and bottom surface of the corresponding epitaxial source / drain region 92P.

[0117] exist Fig.31 In FIG. 1 , the remainder of the interconnect structure 150 is formed on the back side of the device layer 120. The remainder of the interconnect structure 150 may be similar to that of FIG. Fig. 20 and Fig.21 The interconnect structure 150 includes a power rail 144P connected to a conductive via 148 .

[0118] A passivation layer 160, UBM 162, and external connectors 164 are then formed over the interconnect structure 150. The passivation layer 160, UBM 162, and external connectors 164 may be similar to those described with reference to FIG. Fig. 22 The method described is formed.

[0119] FIG. 32A to FIG. 40 are various views of intermediate stages in the fabrication of a semiconductor device according to some other embodiments. Specifically, the fabrication of front-side and back-side interconnect structures for a nano-FET is shown. Fig.32A , Fig.33A , Fig.34A , Fig.35A , Fig.36A , Fig.37A , Fig.38A and Fig.39A Shown with Figure 1 A 3D view of FIG. 1 is a similar 3D view, additionally showing two gate structures and two fins. Fig.32B , Fig.33B , Fig.34B , Fig.35B , Fig.36B , Fig.37B , Fig.38B , Fig.39B and Fig.40 It is along Figure 1 A cross-sectional view is shown in reference section AA. Fig.32A , Fig.33A , Fig.34A , Fig.35A , Fig.36A , Fig.37A , Fig.38A and Fig.39A is a simplified three-dimensional view and does not show the corresponding Fig.32B , Fig.33B , Fig.34B , Fig.35B , Fig.36B , Fig.37B , Fig.38B ,and Fig.39B all parts of the. Fig.32B , Fig.33B , Fig.34B , Fig.35B , Fig.36B , Fig.37B , Fig.38B , Fig.39B and Fig.40 This may be applicable to both the n-type region 50N and the p-type region 50P. The differences in the structures of the n-type region 50N and the p-type region 50P, if any, are described in the text accompanying each drawing.

[0120] exist Fig.32A and Fig.32B In the reference Fig.24A and Fig. 24B The structure described above. Source / drain contact openings 106 are then formed through the first ILD 96 and the CESL 94. The source / drain contact openings 106 may be initially formed in the first ILD 96 using available photolithography and etching techniques, such as using an etching process that is selective to the first ILD 96 (e.g., etching the material of the first ILD 96 at a faster rate than etching the material of the CESL 94). For example, the source / drain contact openings 106 may be initially formed through the first ILD 96 by dry etching using ammonia (NH3) and hydrogen fluoride (HF) gases. The source / drain contact openings 106 are then extended through the CESL 94 using available photolithography and etching techniques, such as using an etching process that is selective to the CESL 94 (e.g., etching the material of the CESL 94 at a faster rate than etching the material of the epitaxial source / drain regions 92). For example, the source / drain contact openings 106 may be extended through the CESL 94 by dry etching using a fluorine-based gas (eg, C 4 F 6 ) and hydrogen (H 2 ) or oxygen (O 2 ).

[0121] A power rail via opening 174 is then formed through the dielectric feature 172 and the second nanostructure 56B. The power rail via opening 174 may be formed using available photolithography and etching techniques, such as using an etching process that is selective to the dielectric feature 172 and the second nanostructure 56B (e.g., etching the material of the dielectric feature 172 and the second nanostructure 56B at a faster rate than etching the material of the epitaxial source / drain region 92). For example, the power rail via opening 174 may be extended through the dielectric feature 172 and the second nanostructure 56B by dry etching using a fluorine-based gas (e.g., C4F6) and a hydrogen (H2) or oxygen (O2) gas. The power rail via opening 174 may not extend into the fin 54, such as Fig.32A or it may be formed to extend into the fin 54, as Fig.32B shown.

[0122] After they are formed, the power rail via openings 174 extend into the intermediate structure by a distance D7. In some embodiments, the distance D7 is greater than the height H1 of the epitaxial source / drain regions 92 (see FIG. Figure 7B ). After the power rail via opening 174 extends into the intermediate structure by a desired distance D7, a timed etching process may be used to stop etching the power rail via opening 174. For example, when the above-described etchant is used to etch the dielectric feature 172 and the second nanostructure 56B, etching may be continued for about 140 seconds to about 400 seconds, which may cause the source / drain contact opening 136 to extend into the intermediate structure by a distance D7 in the range of about 40 nm to about 120 nm. The power rail via opening 174 may be formed to a width W4, which may be in the range of about 10 nm to about 30 nm.

[0123] exist Fig.33A and Fig.33B , a first source / drain contact 112A is formed in the source / drain contact opening 106. The first source / drain contact 112A may be similar to that described in reference to Fig. 12A and Fig. 12B The power rail contact 176 is formed in the power rail by the power rail through hole opening 174. The power rail contact 176 can be formed in a similar manner to the first source / drain contact 112A. The first source / drain contact 112A and the power rail contact 176 can be formed in the same process or in different processes. The power rail contact 176 extends along the sidewalls of the epitaxial source / drain region 92P, but is physically separated from the sidewalls of the epitaxial source / drain region 92P. The power rail contact 176 extends through the dielectric component 172 and the second nanostructure 56B.

[0124] exist Fig.34A and Fig.34BIn the embodiment, the second ILD 114 is deposited over the first ILD 96, the gate electrode 104, the first source / drain contact 112A, and the power rail contact 176. Then, a contact opening 116 is formed in the second ILD 114. The second ILD 114 and the contact opening 116 may be similar to the embodiment of the reference Fig.13A and Fig. 13B In this embodiment, the third subset of contact openings 116C exposes the power rail contacts 176 and the corresponding adjacent first source / drain contacts 112A.

[0125] exist Fig.35A and Fig.35B , the second source / drain contact 112B, the gate contact 118, and the common contact 178 extend through the second ILD 114. The second source / drain contact 112B and the gate contact 118 may be similar to the reference 114. Fig.14A and Fig. 14B The shared contacts 178 may be formed in a similar manner to the second source / drain contacts 112B and the gate contacts 118. The shared contacts 178 are each connected to the power rail contact 176 and the corresponding adjacent first source / drain contact 112A.

[0126] exist Fig.36A and Fig.36B In the embodiment, the common contact 178 is recessed to form an opening 180 on the common contact 178. The remaining portion of the common contact 178 can therefore be regarded as a conductive line. The common contact 178 can be recessed using feasible photolithography and etching techniques, such as using an etch-back process that is selective to the common contact 178 (e.g., etching the material of the common contact 178 at a faster rate than etching the material of the second ILD 114).

[0127] exist Fig.37A and Fig.37B , a dielectric plug 182 is formed in the opening 180. The dielectric plug 182 can be formed of a material selected from the same group of candidate materials as the dielectric component 172, and can be deposited using a method selected from the same group of candidate methods used to deposit the dielectric component 172. The dielectric component 172 and the dielectric plug 182 can be formed of the same material, or can include different materials. Forming the dielectric plug 182 can electrically isolate and protect the common contact 178 during subsequent processing.

[0128] exist Fig.38A and Fig.38B In the example, the intermediate structure can be similar to Figures 15 to 17For example, the interconnect structure 122 may be formed, the structure may be flipped, and the substrate 50 may be replaced with the dielectric layer 128. A source / drain contact opening 136 is then formed through the dielectric layer 128 and the fin 54. The source / drain contact opening 136 may also extend into the lower portion of the epitaxial source / drain region 92P. The source / drain contact opening 136 may be similar to that described with reference to Fig.18A and Fig.18B The source / drain contact openings 136 are formed in the manner described, for example, by using mask 134 as an etching mask. In this embodiment, source / drain contact openings 136 are not formed through epitaxial source / drain regions 92P, but only partially extend to the lower portion of epitaxial source / drain regions 92P. After source / drain contact openings 136 extend into the lower portion of epitaxial source / drain regions 92P by a desired distance D6, a timed etching process can be used to stop etching of source / drain contact openings 136. For example, when reference is made to Fig.18A and Fig.18B When the described etchant is used to etch the source / drain contact opening 136, the etching may be continued for about 90 seconds to about 240 seconds, which may allow the source / drain contact opening 136 to extend into the lower portion of the epitaxial source / drain region 92P by a distance D6 in the range of about 2 nm to about 10 nm. The source / drain contact opening 136 may be formed to have a width W3, which may be in the range of about 10 nm to about 50 nm.

[0129] exist Fig.39A and Fig.39B In the embodiment, the metal-semiconductor alloy region 138 is formed in the source / drain contact opening 136, for example, on the portion of the epitaxial source / drain region 92P exposed by the source / drain contact opening 136. The metal-semiconductor alloy region 138 may be similar to the reference Fig.19A and Fig.19B In some embodiments, the metal-semiconductor alloy region 138 is a curved layer. Although the metal-semiconductor alloy regions 108, 138 are shown as separate regions, it should be understood that in some embodiments, the metal-semiconductor alloy regions 108, 138 can be merged during formation so that there is no distinguishable interface between them.

[0130] Then, a third source / drain contact 112C is formed in the source / drain contact opening 136. The third source / drain contact 112C may be similar to that described with reference to FIG. Fig.19A and Fig.19BThe third source / drain contact 112C is formed in the manner described. In this embodiment, the third source / drain contact 112C has a portion on the power rail contact 176 and a portion extending into the lower portion of the epitaxial source / drain region 92P. Therefore, the third source / drain contact 112C extends along the bottom surface of the epitaxial source / drain region 92P and contacts therewith. After formation, the third source / drain contact 112C has a size similar to the source / drain contact opening 136. The first source / drain contact 112A and the power rail contact 176 form a conductive via 148, which can be referred to as a power rail via.

[0131] exist Fig.40 In FIG. 1 , the remainder of the interconnect structure 150 is formed on the back side of the device layer 120. The remainder of the interconnect structure 150 may be similar to that of FIG. Fig. 20 and Fig.21 The interconnect structure 150 includes a power rail 144P connected to a conductive via 148 .

[0132] A passivation layer 160, UBM 162, and external connectors 164 are then formed over the interconnect structure 150. The passivation layer 160, UBM 162, and external connectors 164 may be similar to those described with reference to FIG. Fig. 22 The method described is formed.

[0133] Embodiments obtain advantages. Placing the power rail 144P at the back side of the device layer 120 rather than at the front side of the device layer 120 can increase the gate density and / or interconnect density of the resulting semiconductor device. In addition, the back side of the device layer 120 can accommodate a wider power rail, thereby reducing resistance and improving the power transmission efficiency of the semiconductor device. Advantages can also be obtained by connecting the power rail 144P to the interconnect structure 122 through a conductive component (e.g., a conductive via 148) rather than a semiconductor component (e.g., an epitaxial source / drain region 92P). Specifically, the performance of the local interconnect between the interconnect structures 122 and 150 can be improved. Finally, the same conductive component (e.g., a conductive via 148) can be used to connect the epitaxial source / drain region 92P to the power rail 144P and provide a local interconnect between the interconnect structures 122 and 150, thereby reducing the number of conductive components in the interconnect structure 150.

[0134] In one embodiment, a device includes: a nanostructure; a gate structure surrounding the nanostructure; an epitaxial source / drain region adjacent to the gate structure; a first dielectric layer above an upper portion of the epitaxial source / drain region; a second dielectric layer below a lower portion of the epitaxial source / drain region; and a power rail via extending through the first dielectric layer and the second dielectric layer, the power rail via being physically and electrically coupled to the upper and lower portions of the epitaxial source / drain region.

[0135] In some embodiments of the device, the power rail via extends through the epitaxial source / drain region. In some embodiments of the device, the power rail via includes: a first source / drain contact extending through the first dielectric layer and into an upper portion of the epitaxial source / drain region; and a second source / drain contact extending through the second dielectric layer and to a lower portion of the epitaxial source / drain region, the second source / drain contact being physically and electrically coupled to the first source / drain contact. In some embodiments, the device further includes: a metal-semiconductor alloy region surrounding a portion of the power rail via extending through the epitaxial source / drain region. In some embodiments of the device, the power rail via extends along a sidewall of the epitaxial source / drain region. In some embodiments of the device, the power rail via includes: a first source / drain contact extending through the first dielectric layer, the first source / drain contact extending along the sidewalls and top surface of the epitaxial source / drain region; and a second source / drain contact extending through the second dielectric layer, the second source / drain contact extending along the bottom surface of the epitaxial source / drain region. In some embodiments, the device further includes: a metal-semiconductor alloy region disposed between the power rail via and each of the top surface, the sidewalls, and the bottom surface of the epitaxial source / drain region.

[0136] In one embodiment, a device includes: a first interconnect structure having a metallization pattern; and a second interconnect structure including a power supply; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source / drain region; and a conductive via extending through the device layer, the conductive via connecting the power supply rail to the metallization pattern, and the conductive via contacting the epitaxial source / drain region.

[0137] In some embodiments of the device, the conductive via extends through the epitaxial source / drain region. In some embodiments of the device, the conductive via extends along and contacts the sidewalls, top surface, and bottom surface of the epitaxial source / drain region. In some embodiments of the device, the conductive via extends along and contacts the bottom surface of the epitaxial source / drain region and extends along and is physically separated from the sidewalls of the epitaxial source / drain region.

[0138] In an embodiment, a method includes: forming a nanostructure on a fin; forming a gate structure around the nanostructure; growing an epitaxial source / drain region adjacent to the gate structure; depositing a first dielectric layer on the epitaxial source / drain region; forming a first contact through the first dielectric layer to contact the epitaxial source / drain region; and forming a second contact through the fin to contact the epitaxial source / drain region and the first contact.

[0139] In some embodiments of the method, forming the first contact includes: forming a first opening extending through the first dielectric layer and into the upper portion of the epitaxial source / drain region; and forming the first contact in the first opening. In some embodiments of the method, forming the second contact includes: forming a second opening extending through the fin and into the lower portion of the epitaxial source / drain region, the second opening exposing the first contact; and forming the second contact in the second opening. In some embodiments of the method, forming the first opening includes: etching the first dielectric layer by dry etching using ammonia and hydrogen fluoride gases; and etching the epitaxial source / drain region by dry etching using chlorine gas, hydrogen bromide gas and oxygen. In some embodiments of the method, the first opening extends into the upper portion of the epitaxial source / drain region by a first distance, and the second opening extends into the lower portion of the epitaxial source / drain region by a second distance, the first distance and the second distance are respectively in the range of 15nm to 60nm. In some embodiments, the method further includes: replacing the gate structure with a second dielectric layer; forming a first opening extending through the first dielectric layer and the second dielectric layer, the first opening exposing the sidewalls of the epitaxial source / drain region; and forming the first contact in the first opening. In some embodiments of the method, forming the second contact includes: forming a second opening extending through the fin, the second opening exposing the first contact and the epitaxial source / drain region; and forming the second contact in the second opening. In some embodiments of the method, forming the first opening includes: etching the first dielectric layer by dry etching using ammonia and hydrogen fluoride gases; and etching the second dielectric layer by dry etching using fluorine-based gas and hydrogen or oxygen. In some embodiments of the method, the depth of the first opening is in the range of 40nm to 120nm.

[0140] The features of several embodiments are summarized above so that those skilled in the art can better understand the various embodiments of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: nanostructures, located above the fins; a gate structure surrounding the nanostructure; an epitaxial source / drain region adjacent to the gate structure and having an upper portion adjacent to the fin and a lower portion distal from the fin; a first dielectric layer located above the upper portion of the epitaxial source / drain region; a power rail disposed above the first dielectric layer; a second dielectric layer located below the lower portion of the epitaxial source / drain region; a metallization pattern disposed below the second dielectric layer; and A power rail via extends through the first dielectric layer and the second dielectric layer, is physically coupled to the power rail and the metallization pattern, and the power rail via is physically and electrically coupled to the upper portion and the lower portion of the epitaxial source / drain region.

2. The semiconductor device according to claim 1, wherein The power rail vias extend through the epitaxial source / drain regions.

3. The semiconductor device according to claim 2, wherein: The power rail vias include: a first source / drain contact extending through the first dielectric layer and into an upper portion of the epitaxial source / drain region; and A second source / drain contact extends through the second dielectric layer and into a lower portion of the epitaxial source / drain region, the second source / drain contact being physically and electrically coupled to the first source / drain contact.

4. The semiconductor device according to claim 2, further comprising: A metal-semiconductor alloy region surrounds a portion of the power rail via extending through the epitaxial source / drain region.

5. The semiconductor device according to claim 1, wherein The power rail vias extend along sidewalls of the epitaxial source / drain regions.

6. The semiconductor device according to claim 5, wherein: The power rail vias include: a first source / drain contact extending through the first dielectric layer, the first source / drain contact extending along the sidewalls and top surface of the epitaxial source / drain region; and A second source / drain contact extends through the second dielectric layer, and the second source / drain contact extends along a bottom surface of the epitaxial source / drain region.

7. The semiconductor device according to claim 6, further comprising: A metal-semiconductor alloy region is disposed between the power rail via and each of the top surface, the sidewalls, and the bottom surface of the epitaxial source / drain region.

8. A semiconductor device comprising: a first interconnect structure including a metallization pattern; a second interconnect structure including a power rail; a device layer located between the first interconnect structure and the second interconnect structure and having a front side and a back side, the power rail being located at the back side of the device layer, the device layer comprising a first transistor, the first transistor comprising a fin adjacent to the back side, and an epitaxial source / drain region located on a side of the fin opposite to the back side; as well as A conductive via extends through the device layer, the conductive via connecting the power rail to the metallization pattern and physically coupling the power rail and the metallization pattern, the conductive via contacting the epitaxial source / drain region.

9. The semiconductor device according to claim 8, wherein: The conductive via extends through the epitaxial source / drain region.

10. The semiconductor device according to claim 8, wherein The conductive via extends along and contacts the sidewalls, top surface and bottom surface of the epitaxial source / drain region.

11. The semiconductor device according to claim 8, wherein The conductive via extends along and contacts a bottom surface of the epitaxial source / drain region, and extends along and is physically separated from a sidewall of the epitaxial source / drain region.

12. A method of forming a semiconductor device, comprising: forming a nanostructure above the fin; forming a gate structure around the nanostructure; growing an epitaxial source / drain region adjacent to the gate structure; depositing a first dielectric layer on the epitaxial source / drain region; forming a first contact through the first dielectric layer to contact the epitaxial source / drain region; forming a metallization pattern physically coupled to the first contact on a side of the first contact opposite to the epitaxial source / drain region; forming a second contact through the fin to contact the epitaxial source / drain region and the first contact; as well as A power rail is formed on a side of the second contact opposite to the epitaxial source / drain region and is physically coupled thereto, and the first contact and the second contact connect the power rail to the metallization pattern.

13. The method according to claim 12, wherein: Forming the first contact comprises: forming a first opening extending through the first dielectric layer and into an upper portion of the epitaxial source / drain region; and The first contact is formed in the first opening.

14. The method according to claim 13, wherein: Forming the second contact comprises: forming a second opening extending through the fin and into a lower portion of the epitaxial source / drain region, the second opening exposing the first contact; and The second contact is formed in the second opening.

15. The method according to claim 13, wherein: Forming the first opening includes: etching the first dielectric layer by dry etching using ammonia and hydrogen fluoride gases; and The epitaxial source / drain regions are etched by dry etching using chlorine gas, hydrogen bromide gas, and oxygen gas.

16. The method according to claim 14, wherein: The first opening extends a first distance into the upper portion of the epitaxial source / drain region, and the second opening extends a second distance into the lower portion of the epitaxial source / drain region, the first distance and the second distance are respectively in a range of 15 nm to 60 nm.

17. The method according to claim 12, further comprising: replacing the gate structure with a second dielectric layer; forming a first opening extending through the first dielectric layer and the second dielectric layer, the first opening exposing a sidewall of the epitaxial source / drain region; as well as The first contact is formed in the first opening.

18. The method according to claim 17, wherein: Forming the second contact comprises: forming a second opening extending through the fin, the second opening exposing the first contact and the epitaxial source / drain region; and The second contact is formed in the second opening.

19. The method according to claim 17, wherein: Forming the first opening includes: etching the first dielectric layer by dry etching using ammonia and hydrogen fluoride gases; and The second dielectric layer is etched by dry etching using a fluorine-based gas and hydrogen or oxygen.

20. The method according to claim 17, wherein: The depth of the first opening is in the range of 40 nm to 120 nm.

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