PWM DAC with improved linearity and insensitivity to switching resistors

Abstract

The invention is entitled "PWM DAC with Improved Linearity and Switch Resistance Insensitivity". A pulse width modulation (PWM) digital-to-analog conversion circuit is disclosed that includes switches 102, 104, 114, 116 controlled by a first PWM signal and switches 106, 108, 110, 112 controlled by a second PWM signal. A first operational amplifier (op-amp) includes a first input coupled to an output of a filter and a second input coupled to an output of the first op-amp. During a first time period, an output of a second op-amp is coupled to an input of the filter via switches 102 and 104 and an output of a third op-amp is coupled to the output of the first op-amp. During a second time period, the output of the second op-amp is coupled to the output of the first op-amp via switches 106 and 108 and the output of the third op-amp is coupled to the input of the filter via switches 110 and 112.

Description

Technical Field

[0001] This application relates to digital-to-analog converter circuits, and more specifically to digital-to-analog converter circuits that output analog values ​​based on pulse width modulation signals input to the digital-to-analog converter circuit. Background Technology

[0002] The calibration device can generate extremely precise voltage levels for calibrating other devices. For example, it can be used to calibrate a voltmeter that measures an input voltage level and outputs a measured voltage value corresponding to that level. More specifically, the calibration device generates and outputs a signal with a predetermined voltage level, which is input to the voltmeter. If the voltmeter outputs a measured voltage value different from the predetermined level, the voltmeter can be adjusted so that the measured voltage value equals the predetermined level.

[0003] To generate an accurate voltage level output from the calibration device, the calibration device may include circuitry based on a pulse-width modulation (PWM) signal, which is input to a PWM digital-to-analog converter (DAC). The output of the PWM DAC may, for example, be input to an amplifier before being output from the calibration device. Therefore, it is desirable for the PWM DAC to output a relatively wide range of voltage levels. Additionally, it is desirable for the PWM DAC to output a voltage level that is linearly related to the duty cycle of the PWM input signal. Summary of the Invention

[0004] This application discloses a PWM DAC circuit capable of outputting a voltage level range wider than that of conventional PWM DAC circuits. Furthermore, the PWM DAC circuit according to this disclosure exhibits improved linearity compared to conventional PWM DAC circuits.

[0005] A pulse-width modulation (PWM) digital-to-analog converter (DAC) circuit can be summarized as follows: a first operational amplifier, the first operational amplifier including a first input terminal, a second input terminal, and an output terminal, wherein the voltage level at the output terminal is based on the voltage level at the second input terminal, and wherein the first input terminal is electrically coupled to a first reference voltage; a second operational amplifier, the second operational amplifier including a first input terminal, a second input terminal, and an output terminal, wherein the voltage level at the output terminal is based on the voltage level at the second input terminal, and wherein the first input terminal is electrically coupled to a second reference voltage; a third operational amplifier, the third operational amplifier... The operational amplifier includes a first input terminal, a second input terminal, and an output terminal, wherein the voltage level at the output terminal is based on the voltage levels at the first input terminal and the second input terminal, and the output terminal is electrically coupled to the second input terminal; a first switching network, in operation, when the first switching network is in a conducting state, electrically couples the output terminal of the first operational amplifier to the first input terminal of the third operational amplifier, and when the first switching network is in a non-conducting state, connects the output terminal of the first operational amplifier to the first input terminal of the third operational amplifier. Decoupling is performed in a first switching network, wherein a first input signal is provided to the first switching network, and the first switching network switches between an on state and a non-conducting state based on the first input signal; a second switching network, in operation, when the second switching network is in the on state, electrically couples the output terminal of the first operational amplifier to the output terminal of the third operational amplifier, and when the second switching network is in the non-conducting state, decouples the output terminal of the first operational amplifier from the output terminal of the third operational amplifier, wherein a second input signal is provided to the second switching network, and the second switching network... Based on the second input signal, the third switching network switches between the on state and the off state; in operation, when the third switching network is in the on state, the third switching network electrically couples the output terminal of the second operational amplifier to the first input terminal of the third operational amplifier, and when the third switching network is in the off state, the third switching network decouples the output terminal of the second operational amplifier from the first input terminal of the third operational amplifier, wherein the second input signal is provided to the third switching network, and the third switching network switches between the on state and the off state based on the second input signal;In operation, when the fourth switching network is in a conducting state, it electrically couples the output terminal of the second operational amplifier to the output terminal of the third operational amplifier, and when the fourth switching network is in a de-conducting state, it decouples the output terminal of the second operational amplifier from the output terminal of the third operational amplifier. The first input signal is provided to the fourth switching network, and the fourth switching network switches between the conducting and de-conducting states based on the first input signal.

[0006] The PWM DAC circuit may further include a filter circuit electrically coupled to the first input terminal of the third operational amplifier. In operation, when the first switching network is in the ON state, the first switching network can electrically couple the output terminal of the first operational amplifier to the input of the filter circuit, and when the first switching network is in the OFF state, the first switching network decouples the output terminal of the first operational amplifier from the input of the filter circuit. In operation, when the third switching network is in the ON state, the third switching network can electrically couple the output terminal of the second operational amplifier to the input of the filter circuit, and when the third switching network is in the OFF state, the third switching network decouples the output terminal of the second operational amplifier from the input of the filter circuit. The filter circuit may include: a first resistor, the first resistor including a first terminal electrically coupled to the input of the filter circuit and a second terminal electrically coupled to the first input terminal of the third operational amplifier; and a capacitor, the capacitor including a first terminal electrically coupled to the second terminal of the resistor and electrically coupled to the first input terminal of the third operational amplifier and a second terminal electrically coupled to a ground terminal.

[0007] When the second and third switch networks are in the non-conducting state, the first and fourth switch networks can be in the conducting state, and when the second and third switch networks are in the conducting state, the first and fourth switch networks can be in the non-conducting state.

[0008] The first input signal and the second input signal can be pulse wave modulated signals. The first input signal can have a first voltage level during a first time period and a second voltage level during a second time period. The first voltage level can be greater than the second voltage level. The first time period can be different from the second time period. The second input signal can have the first voltage level during the second time period and the second voltage level during the first time period.

[0009] A pulse width modulation (PWM) digital-to-analog converter (DAC) circuit can be summarized as including: a filter circuit; a first operational amplifier, the first operational amplifier including a first input terminal, a second input terminal, and an output terminal, wherein the voltage level at the output terminal is based on the voltage level at the first input terminal and the voltage level at the second input terminal, and wherein the first input terminal is electrically coupled to the output of the filter circuit, and the output terminal is electrically coupled to the second input terminal; a first switch, the first switch including a control terminal, a first terminal, and a second terminal, wherein the first switch electrically controls whether the first terminal is electrically coupled to the second input terminal based on the voltage level at the control terminal. A second terminal, wherein the control terminal is electrically coupled to a first input signal, and the second terminal is electrically coupled to the input of the filter circuit; a second switch, the second switch including a control terminal, a first terminal, and a second terminal, wherein the second switch electrically controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal, and wherein the control terminal is electrically coupled to the first input signal, and the second terminal is electrically coupled to the input of the filter circuit; a second operational amplifier, the second operational amplifier including a first input terminal, a second input terminal, and an output terminal, wherein the voltage level at the output terminal is based on the voltage level at the second input terminal, and The output terminal is electrically coupled to the first terminal of the first switch, and the first input terminal is electrically coupled to a first reference voltage; the third switch includes a control terminal, a first terminal, and a second terminal, wherein the third switch electrically controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal, and wherein the control terminal is electrically coupled to a second input signal, the first terminal is electrically coupled to the output terminal of the second operational amplifier, and the second terminal is electrically coupled to the first terminal of the second switch and to the second input terminal of the second operational amplifier; the fourth switch includes a control terminal, a first terminal, and a second input terminal. Two terminals, wherein the fourth switch controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal, and wherein the control terminal is electrically coupled to the second input signal, the first terminal is electrically coupled to the second terminal of the third switch, and the second terminal is electrically coupled to the output terminal of the first operational amplifier; a fifth switch, the fifth switch including a control terminal, a first terminal and a second terminal, wherein the fifth switch controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal, and wherein the control terminal is electrically coupled to the second input signal, and the second terminal is electrically coupled to the input of the filter circuit;A sixth switch, comprising a control terminal, a first terminal, and a second terminal, wherein the sixth switch electrically controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal, and wherein the control terminal is electrically coupled to the second input signal, and the second terminal is electrically coupled to the input of the filter circuit; a third operational amplifier, comprising a first input terminal, a second input terminal, and an output terminal, wherein the voltage level at the output terminal is based on the voltage level at the second input terminal, and wherein the output terminal is electrically coupled to the first terminal of the fifth switch, and the first input terminal is electrically coupled to a second reference voltage; a seventh switch, comprising a control terminal, a first terminal, and a second terminal, wherein the seventh switch is based on... The voltage level at the control terminal electrically controls whether the first terminal is electrically coupled to the second terminal, and wherein the control terminal is electrically coupled to the first input signal, the first terminal is electrically coupled to the output terminal of the third operational amplifier, and the second terminal is electrically coupled to the first terminal of the sixth switch and to the second input terminal of the third operational amplifier; and an eighth switch, the eighth switch including a control terminal, a first terminal and a second terminal, wherein the eighth switch electrically controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal, and wherein the control terminal is electrically coupled to the first input signal, the first terminal is electrically coupled to the second terminal of the seventh switch, and the second terminal is electrically coupled to the output terminal of the first operational amplifier.

[0010] The first input terminal of the first operational amplifier can be a non-inverting input terminal, the second input terminal of the first operational amplifier can be an inverting input terminal, the first input terminal of the second operational amplifier can be a non-inverting input terminal, the second input terminal of the second operational amplifier can be an inverting input terminal, the first input terminal of the third operational amplifier can be a non-inverting input terminal, and the second input terminal of the third operational amplifier is an inverting input terminal.

[0011] The filter circuit may include: a first resistor, the first resistor including a first terminal electrically coupled to the input of the filter circuit and a second terminal electrically coupled to the output of the filter circuit; and a capacitor, the capacitor including a first terminal electrically coupled to the second terminal of the resistor and electrically coupled to the output of the filter circuit and a second terminal electrically coupled to a ground terminal.

[0012] The PWM DAC circuit may further include: a second resistor, the second resistor including a first terminal electrically coupled to the second terminal of the fourth switch and a second terminal electrically coupled to the output terminal of the first operational amplifier; and a third resistor, the third resistor including a first terminal electrically coupled to the second terminal of the eighth switch and a second terminal electrically coupled to the output terminal of the first operational amplifier, wherein the resistance of the first resistor is equal to the resistance of the second resistor and equal to the resistance of the third resistor.

[0013] The DAC circuit may further include: a first resistor, the first resistor including a first terminal electrically coupled to the output terminal of the second operational amplifier and a second terminal electrically coupled to the first terminal of the first switch and the first terminal of the third switch; a first capacitor, the first capacitor including a first terminal electrically coupled to the output terminal of the second operational amplifier and a second terminal electrically coupled to the first terminal of the first switch and the first terminal of the third switch; a second resistor, the second resistor including a first terminal electrically coupled to the output terminal of the third operational amplifier and a second terminal electrically coupled to the first terminal of the fifth switch and the first terminal of the seventh switch; and a second capacitor, the second capacitor including a first terminal electrically coupled to the output terminal of the third operational amplifier and a second terminal electrically coupled to the first terminal of the fifth switch and the first terminal of the seventh switch.

[0014] The first input signal and the second input signal can be pulse wave modulated signals.

[0015] The first input signal may have a first voltage level during a first time period and a second voltage level during a second time period, the first voltage level may be greater than the second voltage level, the first time period may be different from the second time period, and the second input signal may have the first voltage level during the second time period and the second voltage level during the first time period.

[0016] The first reference voltage and the second reference voltage may have the same amplitude and opposite polarity.

[0017] A method can be summarized as follows: controlling a first switch based on a first input signal; controlling a second switch based on the first input signal; controlling a third switch based on a second input signal; controlling a fourth switch based on the second input signal; controlling a fifth switch based on the second input signal; controlling a sixth switch based on the second input signal; controlling a seventh switch based on the first input signal; controlling an eighth switch based on the first input signal; electrically coupling a first reference voltage to a first input of a first operational amplifier; electrically coupling a second reference voltage to a first input of a second operational amplifier; electrically coupling the output of a filter circuit to a first input of a third operational amplifier; electrically coupling the output of the third operational amplifier to a second input of the third operational amplifier; when the first switch is in a conducting state, electrically coupling the output of the first operational amplifier to the input of the filter circuit via the first switch; when the first switch and the second switch are in a conducting state, electrically coupling the output of the first operational amplifier to the second input of the first operational amplifier via the first switch and the second switch. When the seventh switch is on, the output of the second operational amplifier is electrically coupled to the second input of the second operational amplifier via the seventh switch; when the seventh and eighth switches are on, the output of the second operational amplifier is electrically coupled to the output of the third operational amplifier via the seventh and eighth switches; when the third switch is on, the output of the first operational amplifier is electrically coupled to the second input of the first operational amplifier via the third switch; when the third and fourth switches are on, the output of the first operational amplifier is electrically coupled to the output of the third operational amplifier via the third and fourth switches; when the fifth switch is on, the output of the second operational amplifier is electrically coupled to the input of the filter circuit via the fifth switch; and when the fifth and sixth switches are on, the output of the second operational amplifier is electrically coupled to the second input of the second operational amplifier via the fifth and sixth switches.

[0018] During a first time period, the output of the first operational amplifier can be electrically coupled to the input of the filter circuit via the first switch; during the first time period, the output of the first operational amplifier can be electrically coupled to the second input of the first operational amplifier via the first switch and the second switch; during the first time period, the output of the second operational amplifier can be electrically coupled to the second input of the second operational amplifier via the seventh switch; during the first time period, the output of the second operational amplifier can be electrically coupled to the output of the third operational amplifier via the seventh switch and the eighth switch; during a second time period... The first operational amplifier's output can be electrically coupled to its second input via the third switch during a second time period different from the first time period. During the second time period, the output of the first operational amplifier can be electrically coupled to its output via the third and fourth switches. During the second time period, the output of the second operational amplifier can be electrically coupled to its second input via the fifth and sixth switches. During the second time period, the output of the second operational amplifier can also be electrically coupled to its input via the seventh switch.

[0019] The first input signal and the second input signal can be pulse width modulation signals.

[0020] The first input signal may have a first voltage level during the first time period and a second voltage level during the second time period, the first voltage level being greater than the second voltage level, and the second input signal may have the first voltage level during the second time period and the second voltage level during the first time period.

[0021] The filter circuit may include a first resistor and a capacitor. The output of the first operational amplifier is electrically coupled to the output of the third operational amplifier via the third switch and the fourth switch. The output of the first operational amplifier is electrically coupled to the output of the third operational amplifier via the third switch, the fourth switch and the second resistor. The output of the second operational amplifier is electrically coupled to the output of the third operational amplifier via the seventh switch and the eighth switch. The output of the second operational amplifier is electrically coupled to the output of the third operational amplifier via the seventh switch, the eighth switch and the third resistor. The resistance of the first resistor may be equal to the resistance of the second resistor and may be equal to the resistance of the third resistor.

[0022] Connecting the output of the first operational amplifier to the input of the filter circuit via the first switch may include: connecting the output of the first operational amplifier to the first terminal of the first resistor; connecting the output of the first operational amplifier to the first terminal of the first capacitor; connecting the second terminal of the first resistor to the first switch; and connecting the second terminal of the first capacitor to the first switch. Connecting the output of the second operational amplifier to the input of the filter circuit via the fifth switch may include: connecting the output of the second operational amplifier to the first terminal of the second resistor; connecting the output of the second operational amplifier to the first terminal of the second capacitor; connecting the second terminal of the second resistor to the fifth switch; and connecting the second terminal of the second capacitor to the fifth switch.

[0023] The positive reference voltage and the negative reference voltage can have the same amplitude but opposite polarities. Attached Figure Description

[0024] Figure 1 This is a diagram of a PWM DAC circuit according to one or more embodiments of this disclosure;

[0025] Figure 2A and Figure 2B It is an input that can be made according to one or more embodiments of this disclosure. Figure 1 An example of the timing diagram of the PWM input signal of the PWM DAC circuit shown;

[0026] Figure 3A and Figure 3B A flowchart of a method according to one or more embodiments of the present disclosure is shown;

[0027] Figure 4 A flowchart of a method according to one or more embodiments of this disclosure is shown; and

[0028] Figure 5 A flowchart of a method according to one or more embodiments of this disclosure is shown. Detailed Implementation

[0029] Figure 1 This is a diagram of a pulse width modulation (PWM) digital-to-analog converter (DAC) circuit 100 according to one or more embodiments of the present disclosure. The PWM DAC circuit 100 includes eight analog switches 102, 104, 106, 108, 110, 112, 114, and 116. Each of the analog switches 102 through 116 includes a first terminal, a second terminal, and a control terminal. Each of the analog switches 102 through 116 electrically controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal.

[0030] In one or more embodiments, each of the analog switches 102 to 116 is typically "off". When the voltage level of the signal supplied to the control terminal of the switch is less than or equal to a predetermined value (e.g., zero volts), the switch is closed or "on" (i.e., in a conducting state), and the first terminal of the switch is electrically coupled to the second terminal of the switch. When the voltage level of the signal supplied to the control terminal of the switch is higher than the predetermined value, the switch is open or "off" (i.e., in a non-conducting state), and the first terminal of the switch is electrically decoupled from the second terminal of the switch. In one or more embodiments, each of the analog switches 102 to 116 includes two field-effect transistors (FETs) that provide switching functionality.

[0031] In addition to output terminal 126, the PWM DAC circuit 100 also includes four input terminals 118, 120, 122, and 124. A first PWM input signal PWM+ is input to the PWM DAC circuit 100 via input terminals 118 and 124. For example, the output terminal of the circuit generating the first PWM input signal PWM+ (not shown) is electrically coupled to wires that are electrically coupled to input terminals 118 and 124 of the PWM DAC circuit 100, respectively. A second PWM input signal PWM– is input to the PWMDAC circuit 100 via input terminals 120 and 122. For example, the output terminal (not shown) of the circuit generating the second PWM input signal PWM– is electrically coupled to wires that are electrically coupled to input terminals 120 and 122 of the PWMDAC circuit 100, respectively.

[0032] The first PWM input signal PWM+ and the second PWM input signal PWM– have the same peak-to-peak voltage level. In one or more embodiments, the second PWM input signal PWM– is 180 degrees out of phase with the first PWM input signal PWM+. See below for reference. Figure 2A and Figure 2B The first PWM input signal PWM+ and the second PWM input signal PWM– are described in more detail.

[0033] The PWM DAC circuit 100 also includes operational amplifiers 128, 130, and 132. Operational amplifiers 128 and 130 are configured to deliver a precise voltage at the output of switch 104 or switches 108 and 116. Therefore, the inverting and non-inverting terminals should not be different, and the output terminal should not be close to +V. Each operational amplifier in operational amplifiers 128 and 130 includes a non-inverting input terminal, an inverting input terminal, and an output terminal electrically coupled to a reference potential, wherein the voltage level at the output terminal is based on the voltage level at the non-inverting input terminal.

[0034] Operational amplifier 132 includes a non-inverting input terminal, an inverting input terminal, and an output terminal, wherein the voltage level at the output terminal is based on the voltage levels at the non-inverting input terminal and the voltage levels at the inverting input terminal. Operational amplifier 132 is configured to operate as a unity-gain buffer in its linear region.

[0035] In one or more embodiments, each of operational amplifiers 128, 130 and 132 is a chopper-stabilized operational amplifier with very low offset.

[0036] Operational amplifiers 128 and 130 are electrically coupled to filter circuit 134 via switches 102 to 116. In the depicted embodiment, filter circuit 134 includes resistor 136 and capacitor 138. A first terminal of resistor 136 is electrically coupled to the input of filter circuit 134. A second terminal of resistor 136 is electrically coupled to the first terminal of capacitor 138. A second terminal of capacitor 138 is electrically coupled to ground. The second terminal of resistor 136 and the first terminal of capacitor 138 are electrically coupled to the output of filter circuit 134, which is electrically coupled to the non-inverting input terminal of operational amplifier 132. The output terminal of operational amplifier 132 is electrically coupled to the inverting input terminal of operational amplifier 132 and to the output terminal 126 of PWM DAC circuit 100.

[0037] In one or more embodiments, the output terminal of operational amplifier 128 is electrically coupled to the first terminal of resistor 140 and to the first terminal of capacitor 142. Resistor 140 and capacitor 142 are connected in parallel and electrically coupled. More specifically, the second terminal of resistor 140 is electrically coupled to the second terminal of capacitor 142 and to node 144, which is electrically coupled to the first terminal of switch 102 and to the first terminal of switch 106. The inverting input terminal of operational amplifier 128 is electrically coupled to the first terminal of switch 104, the second terminal of switch 106, and the first terminal of switch 108. The non-inverting input terminal of operational amplifier 128 is electrically coupled to a positive reference voltage +VREF. For stability, resistor 140 and capacitor 142 may be added, wherein the resistance of resistor 140 and the capacitance of capacitor 142 are selected based on the characteristics of operational amplifier 128.

[0038] The control terminals of switch 102 and switch 104 are electrically coupled to input terminal 118, where a first PWM input signal PWM+ is provided. When the first PWM input signal PWM+ has a voltage level less than or equal to a predetermined value (e.g., zero volts), switches 102 and 104 are closed or "on," thus electrically coupling the first terminal of switch 102 to the second terminal of switch 102, and the first terminal of switch 104 to the second terminal of switch 104. When the first PWM input signal PWM+ has a voltage level higher than the predetermined value, switches 102 and 104 are open or "off," thus electrically decoupling the first terminal of switch 102 from the second terminal of switch 102, and the first terminal of switch 104 from the second terminal of switch 104.

[0039] The second terminals of switch 102 and switch 104 are electrically coupled to the first terminal of resistor 136 in filter circuit 134. As described above, node 144 is electrically coupled to the first terminal of switch 102 and to the first terminal of switch 106. More specifically, the second terminal of switch 106 is electrically coupled to the first terminal of switch 104, the first terminal of switch 108, and the inverting input terminal of operational amplifier 128. The second terminal of switch 108 is electrically coupled to the first terminal of resistor 146. The second terminal of resistor 146 is electrically coupled to the output terminal of operational amplifier 132, the inverting input terminal of operational amplifier 132, and the output terminal 126 of PWM DAC circuit 100.

[0040] The control terminals of switch 106 and switch 108 are electrically coupled to input node 120, where a second PWM input signal PWM- is provided. When the second PWM input signal PWM- has a voltage level less than or equal to a predetermined value (e.g., zero volts), switches 106 and 108 are closed or "on", thus electrically coupling the first terminal of switch 106 to the second terminal of switch 106, and the first terminal of switch 108 to the second terminal of switch 108. When the second PWM input signal PWM- has a voltage level higher than the predetermined value, switches 106 and 108 are open or "off", thus electrically decoupling the first terminal of switch 106 from the second terminal of switch 106, and the first terminal of switch 108 from the second terminal of switch 108.

[0041] In one or more embodiments, the output terminal of operational amplifier 130 is electrically coupled to the first terminal of resistor 148 and the first terminal of capacitor 150. Resistor 148 and capacitor 150 are connected in parallel and electrically coupled. More specifically, the second terminal of resistor 148 is electrically coupled to the second terminal of capacitor 150 and to node 152, which is electrically coupled to the first terminal of switch 110 and the first terminal of switch 114. The inverting input terminal of operational amplifier 130 is electrically coupled to the first terminal of switch 112, the second terminal of switch 114, and the first terminal of switch 116. The non-inverting input terminal of operational amplifier 130 is electrically coupled to the negative reference voltage -VREF. In one or more embodiments, the positive reference voltage +VREF and the negative reference voltage -VREF have the same magnitude but opposite polarities. For stability, resistor 148 and capacitor 150 may be added, wherein the resistance of resistor 148 and the capacitance of capacitor 150 are selected based on the characteristics of operational amplifier 130.

[0042] The control terminals of switch 110 and switch 112 are electrically coupled to input node 122, to which a second PWM input signal PWM- is provided. When the second PWM input signal PWM- has a voltage level less than or equal to a predetermined value (e.g., zero volts), switches 110 and 112 are closed or "on", thus electrically coupling the first terminal of switch 110 to the second terminal of switch 110, and the first terminal of switch 112 to the second terminal of switch 112. When the second PWM input signal PWM- has a voltage level higher than the predetermined value, switches 110 and 112 are open or "off", thus electrically decoupling the first terminal of switch 110 from the second terminal of switch 110, and the first terminal of switch 112 from the second terminal of switch 112. The second terminals of switches 110 and 112 are electrically coupled to the first terminal of resistor 136, which is electrically coupled to the input of filter circuit 134.

[0043] As described above, node 152 is electrically coupled to the first terminal of switch 110 and also electrically coupled to the first terminal of switch 114. The second terminal of switch 114 is electrically coupled to the first terminal of switch 112, the first terminal of switch 116, and the inverting input terminal of operational amplifier 130. The second terminal of switch 116 is electrically coupled to the first terminal of resistor 154. The second terminal of resistor 154 is electrically coupled to the output terminal of operational amplifier 132 and the output terminal of PWM DAC circuit 100.

[0044] The control terminals of switch 114 and switch 116 are electrically coupled to input node 124, where a first PWM input signal PWM+ is provided. When the first PWM input signal PWM+ has a voltage level less than or equal to a predetermined value (e.g., zero volts), switches 114 and 116 are closed or "on," thus electrically coupling the first terminal of switch 114 to the second terminal of switch 114, and the first terminal of switch 116 to the second terminal of switch 116. The second terminal of switch 114 is electrically coupled to the first terminal of switch 112 and to the first terminal of switch 116. When the first PWM input signal PWM+ has a voltage level higher than the predetermined value, switches 114 and 116 are open or "off," thus electrically decoupling the first terminal of switch 114 from the second terminal of switch 114, and the first terminal of switch 116 from the second terminal of switch 116.

[0045] In one or more embodiments, switches 102 and 104 form a first switching network that, in operation, when the first switching network is in a conducting state, electrically couples the output terminal of operational amplifier 128 to the input of filter circuit 134, the input of which is electrically coupled to the non-inverting input terminal of a third operational amplifier, and when the first switching network is in a non-conducting state, decouples the output terminal of operational amplifier 128 from the input of filter circuit 134, the input of which is electrically coupled to the non-inverting input terminal of the third operational amplifier, wherein a first PWM input signal PWM+ is provided to the first switching network, and the first switching network switches between a conducting state and a non-conducting state based on the first PWM input signal PWM+.

[0046] In one or more embodiments, switches 106 and 108 form a second switching network that, in operation, when the second switching network is in a conducting state, electrically couples the output terminal of operational amplifier 128 to the output terminal of a third operational amplifier, and when the second switching network is in a non-conducting state, decouples the output terminal of operational amplifier 128 from the output terminal of the third operational amplifier, wherein a second PWM input signal PWM- is provided to the second switching network, and the second switching network switches between a conducting state and a non-conducting state based on the second PWM input signal PWM-.

[0047] In one or more embodiments, switches 110 and 112 form a third switching network that, in operation, when the third switching network is in a conducting state, electrically couples the output terminal of operational amplifier 130 to the input of filter circuit 134, the input of which is electrically coupled to the non-inverting input terminal of the third operational amplifier; and when the third switching network is in a non-conducting state, decouples the output terminal of operational amplifier 130 from the input of filter circuit 134, the input of which is electrically coupled to the non-inverting input terminal of the third operational amplifier, wherein a second PWM input signal PWM- is provided to the third switching network, and the third switching network switches between a conducting state and a non-conducting state based on the second PWM input signal PWM-.

[0048] In one or more embodiments, switches 114 and 116 form a fourth switching network that, in operation, when the fourth switching network is in a conducting state, electrically couples the output terminal of operational amplifier 130 to the output terminal of a third operational amplifier, and when the fourth switching network is in a non-conducting state, decouples the output terminal of operational amplifier 130 from the output terminal of the third operational amplifier, wherein a first PWM input signal PWM+ is provided to the fourth switching network, and the fourth switching network switches between a conducting state and a non-conducting state based on the first PWM input signal PWM+.

[0049] The structure of the PWM DAC circuit 100 has already been described; now, refer to... Figure 1 , Figure 2A and Figure 2B Describe the operation of the PWM DAC circuit 100. Figure 2A and Figure 2B It is an input that can be made according to one or more embodiments of this disclosure. Figure 1 An example timing diagram of the first PWM input signal PWM+ and the second PWM input signal PWM– of the PWMDAC circuit 100 shown. More specifically, Figure 2A This is an example of the timing diagram for the first PWM input signal PWM+, and Figure 2B This is an example of a timing diagram for the second PWM input signal, PWM–.

[0050] The first PWM input signal PWM+ has a high voltage level during time period t1 and a low voltage level during time period t2, such as Figure 2A As shown. The duty cycle of the first PWM input signal PWM+ is equal to t1 / (t1+t2). The second PWM input signal PWM– has a low voltage level during time period t1 and a high voltage level during time period t2, as shown. Figure 2BAs shown. Therefore, the duty cycle of the second PWM input signal PWM+ is equal to t2 / (t1+t2). Each of the first PWM input signal PWM+ and the second PWM input signal PWM- has a constant frequency. In other words, the sum of time intervals t1 and t2 is a constant value. Figure 2A and Figure 2B The first PWM input signal PWM+ and the second PWM input signal PWM- shown each have a 50% duty cycle. However, during the operation of the PWM DAC circuit 100, PWM input signals with other duty cycles can be input to the PWM DAC circuit 100 according to the desired voltage level at the output terminal 126 of the PWM DAC circuit 100.

[0051] In one or more embodiments, the PWM DAC circuit 100 is configured to receive a first PWM input signal PWM+ and a second PWM input signal PWM– from an external circuit. In one or more embodiments, the PWM DAC circuit 100 is configured to generate the first PWM input signal PWM+ and the second PWM input signal PWM–. The PWM DAC circuit 100 may include one or more microprocessors or field-programmable gate arrays (FPGAs) that generate the first PWM input signal PWM+ and the second PWM input signal PWM– based on drive signals input to the microprocessor or FPGA. For example, a drive signal having a value corresponding to a 50% duty cycle causes the FPGA output to have a high value during the first half of a fixed number of clock cycles and a low value during the second half of a fixed number of clock cycles.

[0052] As will be described in more detail below, switches 102, 104, 114, and 116 are closed or "on" during time periods when the first PWM input signal PWM+ has a voltage level less than or equal to a predetermined value (e.g., zero volts), such as during time period t1. Switches 102, 104, 114, and 116 are open or "off" during time periods when the first PWM input signal PWM+ has a voltage level higher than the predetermined value, such as during time period t2. Additionally, switches 106, 108, 110, and 112 are closed or "on" during time periods when the second PWM input signal PWM- has a voltage level less than or equal to a predetermined value, such as during time period t2. Switches 106, 108, 110, and 112 are open or "off" during time periods when the second PWM input signal PWM- has a voltage level higher than the predetermined value, such as during time period t1.

[0053] The operation of the upper half of the PWM DAC circuit 100 will now be described. When +VREF is on, the output terminal of operational amplifier 128 provides charging current to the input of filter circuit 134. When switches 102 and 104 are on, switches 106 and 108 are off, and the output terminal of operational amplifier 128 provides charging current to the input of filter circuit 134. When switch 104 is on, only the input bias current and leakage current (which are relatively small currents) from switches 106 and 108 flow through switch 104. Therefore, those small currents multiplied by the resistance of switch 104 produce a negligible voltage and cause almost undetectable error in the output of switch 104. Because switch 102 is in the loop, the resistance of switch 102 does not affect the output of PWM DAC circuit 100. A voltage level very close to +VREF is seen at the input of filter circuit 134.

[0054] When switches 102 and 104 are off and switches 106 and 108 are on, the output terminal of operational amplifier 128 provides charging current to the output terminal of operational amplifier 132 through resistor 146. Because the resistance of resistor 136 is equal to the resistance of resistor 146, and because the voltage level at the output of filter circuit 134 is the same as the voltage level at the output of operational amplifier 132, operational amplifier 128 does not perceive load changes except for small switching transients when switches 102 and 104 are off and when switches 106 and 108 are on. This keeps the output of operational amplifier 128 stable and constant during PWM, minimizing conversion errors.

[0055] The operation of the lower half of the PWM DAC circuit 100 will now be described. When –VREF is turned on, operational amplifier 130 provides charging current to the input of filter circuit 134. When switches 110 and 112 are turned on, switches 114 and 116 are turned off, and operational amplifier 130 provides charging current to the input of filter circuit 134. When switch 112 is turned on, only the input bias current and leakage current (which are relatively small currents) from switches 114 and 116 flow through switch 112. Therefore, those small currents multiplied by the resistance of switch 112 produce a negligible voltage and cause almost undetectable error in the output of switch 112. Because switch 110 is in the loop, the resistance of switch 110 does not affect the output of PWM DAC circuit 100. A voltage level very close to –VREF is seen at the input of filter circuit 134.

[0056] When switches 110 and 112 are off and switches 114 and 116 are on, operational amplifier 130 provides charging current to the output terminal of operational amplifier 132 through resistor 154. Because the resistance of resistor 136 is equal to the resistance of resistor 154, and because the voltage level at the output of filter circuit 134 is the same as the voltage level at the output of operational amplifier 132, operational amplifier 130 does not perceive load changes except for small switching transients when switches 110 and 112 are off and when switches 114 and 116 are on. This keeps the output voltage level of operational amplifier 130 stable and constant during PWM, minimizing conversion errors.

[0057] The advantage of the PWM DAC circuit 100 is that almost no current is drawn from +VREF or –VREF, thus eliminating reference load errors and pulse interference.

[0058] The voltage level at the output terminal 126 of the PWM DAC circuit 100 is given by Equation 1 below.

[0059] VDAC = ((+ VREF – (–VREF)) × D) + (–VREF) (Formula 1)

[0060] In Equation 1, D is the duty cycle t1 / (t1+t2), where t1 is the time period during which switches 102, 104, 114 and 116 are turned on, and t2 is the time period during which switches 106, 108, 110 and 112 are turned on.

[0061] The placement of switches 102 to 116 within the PWM DAC circuit 100 is a key aspect of the PWM DAC circuit 100. Switch 102 connects the output of operational amplifier 128 to the input of filter circuit 134 via resistor 140, while switch 104 simultaneously connects the input of filter circuit 134 to the inverting input terminal of operational amplifier 128, with +VREF applied to filter circuit 134. Then, when switches 102 and 104 are turned off to apply the output of operational amplifier 128 to resistor 146 to maintain operational amplifier 128 in normal output mode, switches 106 and 108 are simultaneously turned on.

[0062] Similarly, during the time –VREF is applied to filter circuit 134, switch 110 connects the output terminal of operational amplifier 130 to the input of filter circuit 134 via resistor 148, while switch 112 connects the inverting input terminal of operational amplifier 130 to the input of filter circuit 134. PWM DAC circuit 100 uses operational amplifier 130 to “sensor” the input of filter circuit 134 to remove errors from the drop in IR (i.e., current multiplied by resistance) of the switched resistor. Then, during the time +VREF is applied to filter circuit 134, switches 114 and 116 connect the output of operational amplifier 130 to resistor 154. Thus, operational amplifiers 128 and 130 switch from the voltage level at the input of filter circuit 134 to the voltage level at the output terminal 126 of PWM DAC circuit 100, allowing them to see minimal disturbances and thus reducing conversion errors.

[0063] Figure 3A and Figure 3B A flowchart of method 300 according to one or more embodiments of the present disclosure is shown. Method 300 begins at 302.

[0064] At point 302, the first switch is controlled based on the first input signal. For example, at point 302, switch 102 is controlled based on the first PWM input signal PWM+, as described above.

[0065] At point 304, the second switch is controlled based on the first input signal. For example, at point 304, switch 104 is controlled based on the first PWM input signal PWM+, as described above.

[0066] At point 306, the third switch is controlled based on the second input signal. For example, at point 306, switch 106 is controlled based on the second PWM input signal PWM–, as described above.

[0067] At point 308, the fourth switch is controlled based on the second input signal. For example, at point 308, switch 108 is controlled based on the second PWM input signal PWM–, as described above.

[0068] At point 310, the fifth switch is controlled based on the second input signal. For example, at point 310, switch 110 is controlled based on the second PWM input signal PWM–, as described above.

[0069] At point 312, the sixth switch is controlled based on the second input signal. For example, at point 312, switch 112 is controlled based on the second PWM input signal PWM–, as described above.

[0070] At point 314, the seventh switch is controlled based on the first input signal. For example, at point 314, switch 114 is controlled based on the first PWM input signal PWM+, as described above.

[0071] At 316, the eighth switch is controlled based on the first input signal. For example, at 316, switch 116 is controlled based on the first PWM input signal PWM+, as described above. Although the control of the first to eighth switches is described in the sequence of blocks 302 to 316, it should be understood that all eight switches can be controlled simultaneously (i.e., there is not necessarily a sequence in which eight switches are controlled).

[0072] At point 318, a first reference voltage is electrically coupled to the first input of the first operational amplifier. For example, at point 318, a positive reference voltage +VREF is electrically coupled to the non-inverting input terminal of operational amplifier 128, as described above.

[0073] At 320, the second reference voltage is electrically coupled to the first input of the second operational amplifier. For example, at 320, the negative reference voltage –VREF is electrically coupled to the non-inverting input terminal of operational amplifier 130, as described above.

[0074] At point 322, the output of the filter circuit is electrically coupled to the first input of the third operational amplifier. For example, at point 322, the output of the filter circuit 134 is electrically coupled to the non-inverting input terminal of the operational amplifier 132, as described above.

[0075] At point 324, the output of the third operational amplifier is electrically coupled to the second input of the third amplifier circuit. For example, at point 324, the output terminal of operational amplifier 132 is electrically coupled to the inverting input terminal of amplifier circuit 132, as described above.

[0076] At point 326, the output of the first operational amplifier is electrically coupled to the input of the filter circuit via a first switch. For example, at point 326, when switch 102 is in the ON state, the output terminal of operational amplifier 128 is electrically coupled to the input of filter circuit 134 via switch 102, as described below. Figure 4 More details to follow.

[0077] At 328, the output of the first operational amplifier is electrically coupled to the second input of the first operational amplifier via a first switch and a second switch. For example, at 328, when switches 102 and 104 are in the ON state, the output of operational amplifier 128 is electrically coupled to the inverting input terminal of operational amplifier 128 via switches 102 and 104, as described above.

[0078] At 330, the output of the second operational amplifier is electrically coupled to the second input of the second operational amplifier via a seventh switch. For example, at 330, when switch 114 is in the ON state, the output terminal of operational amplifier 130 is electrically coupled to the inverting input terminal of operational amplifier 130 via switch 114, as described above.

[0079] At 332, the output of the second operational amplifier is electrically coupled to the output of the third operational amplifier via the seventh and eighth switches. For example, at 332, when switches 114 and 116 are in the ON state, the output of operational amplifier 130 is electrically coupled to the output terminal of operational amplifier 132 via switches 114 and 116, as described above.

[0080] At 334, the output of the first operational amplifier is electrically coupled to the second input of the first operational amplifier via a third switch. For example, at 334, when switch 106 is in the ON state, the output terminal of operational amplifier 128 is electrically coupled to the inverting input terminal of operational amplifier 128 via switch 106, as described above.

[0081] At 336, the output of the first operational amplifier is electrically coupled to the output of the third operational amplifier via the third and fourth switches. For example, at 336, when switches 106 and 108 are in the ON state, the output terminal of operational amplifier 128 is electrically coupled to the output terminal of operational amplifier 132 via switches 106 and 108, as described above.

[0082] At point 338, the output of the second operational amplifier is electrically coupled to the input of the filter circuit via a fifth switch. For example, at point 338, when switch 110 is in the ON state, the output terminal of operational amplifier 130 is electrically coupled to the input of filter circuit 134 via switch 110, as described below. Figure 5 More details to follow.

[0083] At 340, the output of the second operational amplifier is electrically coupled to the second input of the second operational amplifier via the fifth and sixth switches. For example, at 340, when switches 110 and 112 are in the ON state, the output of operational amplifier 130 is electrically coupled to the inverting input terminal of operational amplifier 130 via switches 110 and 112, as described above. In one or more embodiments, depending on the ON or OFF state of the respective switches at any given time, the above actions are performed at different times. The above actions are not necessarily performed according to... Figure 3A and Figure 3B Execute in the order shown.

[0084] Figure 4A flowchart of method 400 according to one or more embodiments of the present disclosure is shown. Method 400 corresponds to block 326 of method 300 described above. Method 400 begins at 402.

[0085] At 402, the output of the first operational amplifier is electrically coupled to the first terminal of the first resistor. For example, at 402, the output terminal of operational amplifier 128 is electrically coupled to the first terminal of resistor 140, as described above.

[0086] At 404, the output of the first operational amplifier is electrically coupled to the first terminal of the first capacitor. For example, at 404, the output terminal of operational amplifier 128 is electrically coupled to the first terminal of capacitor 142, as described above.

[0087] At 406, the second terminal of the first resistor is electrically coupled to the first switch. For example, at 406, the second terminal of resistor 140 is electrically coupled to the input terminal of switch 102, as described above.

[0088] At 408, the second terminal of the first capacitor is electrically coupled to the first switch. For example, at 408, the second terminal of capacitor 142 is electrically coupled to the input terminal of switch 102, as described above. The actions performed in blocks 402 to 408 can be performed simultaneously.

[0089] Figure 5 A flowchart of method 500 according to one or more embodiments of the present disclosure is shown. Method 500 corresponds to block 338 of method 300 described above.

[0090] At point 502, the output of the second operational amplifier is electrically coupled to the first terminal of the second resistor. For example, at point 502, the output terminal of operational amplifier 130 is electrically coupled to the first terminal of resistor 148, as described above.

[0091] At point 504, the output of the second operational amplifier is electrically coupled to the first terminal of the second capacitor. For example, at point 504, the output terminal of operational amplifier 130 is electrically coupled to the first terminal of capacitor 150, as described above.

[0092] At 506, the second terminal of the second resistor is electrically coupled to the fifth switch. For example, at 506, the second terminal of resistor 148 is electrically coupled to the input terminal of switch 110, as described above.

[0093] At 508, the second terminal of the second capacitor is electrically coupled to the fifth switch. For example, at 508, the second terminal of capacitor 152 is electrically coupled to the input terminal of switch 110, as described above. The actions performed in blocks 502 to 508 can be performed simultaneously.

[0094] The various implementation schemes described above can be combined to provide other implementation schemes.

[0095] In light of the detailed description above, these and other changes may be made to these embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in this specification and claims, but rather as encompassing all possible embodiments and the full scope of equivalents conferred by such claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A pulse width modulation (PWM) digital-to-analog converter circuit, the PWM PWM digital-to-analog converter circuit comprising: A first operational amplifier, comprising a first input terminal, a second input terminal, and an output terminal, wherein the voltage level at the output terminal is based on the voltage level at the second input terminal, and wherein the first input terminal is electrically coupled to a first reference voltage; A second operational amplifier, comprising a first input terminal, a second input terminal, and an output terminal, wherein the voltage level at the output terminal is based on the voltage level at the second input terminal, and wherein the first input terminal is electrically coupled to a second reference voltage; A third operational amplifier includes a first input terminal, a second input terminal, and an output terminal, wherein the voltage level at the output terminal is based on the voltage level at the first input terminal and the voltage level at the second input terminal, and wherein the output terminal is electrically coupled to the second input terminal; In operation, when the first switching network is in a conducting state, the first switching network electrically couples the output terminal of the first operational amplifier to the first input terminal of the third operational amplifier, and when the first switching network is in a non-conducting state, the first switching network decouples the output terminal of the first operational amplifier from the first input terminal of the third operational amplifier, wherein a first input signal is provided to the first switching network, and the first switching network switches between the conducting state and the non-conducting state based on the first input signal; In operation, when the second switching network is in a conducting state, the second switching network electrically couples the output terminal of the first operational amplifier to the output terminal of the third operational amplifier, and when the second switching network is in a non-conducting state, the second switching network decouples the output terminal of the first operational amplifier from the output terminal of the third operational amplifier, wherein a second input signal is provided to the second switching network, and the second switching network switches between the conducting state and the non-conducting state based on the second input signal; In operation, when the third switching network is in a conducting state, it electrically couples the output terminal of the second operational amplifier to the first input terminal of the third operational amplifier, and when the third switching network is in a non-conducting state, it decouples the output terminal of the second operational amplifier from the first input terminal of the third operational amplifier, wherein a second input signal is provided to the third switching network, and the third switching network switches between the conducting state and the non-conducting state based on the second input signal. and The fourth switching network, in operation, when in a conducting state, electrically couples the output terminal of the second operational amplifier to the output terminal of the third operational amplifier, and when in a de-conducting state, decouples the output terminal of the second operational amplifier from the output terminal of the third operational amplifier, wherein a first input signal is provided to the fourth switching network, and the fourth switching network switches between the conducting and de-conducting states based on the first input signal. The first input signal and the second input signal have the same peak-to-peak voltage level, and the first input signal and the second input signal are 180 degrees out of phase. The first reference voltage and the second reference voltage have the same amplitude and opposite polarities.

2. The pulse width modulation digital-to-analog converter circuit according to claim 1, wherein the pulse width modulation digital-to-analog converter circuit further comprises: A filter circuit, electrically coupled to the first input terminal of the third operational amplifier, In operation, when the first switching network is in the ON state, it electrically couples the output terminal of the first operational amplifier to the input of the filter circuit; and when the first switching network is in the OFF state, it decouples the output terminal of the first operational amplifier from the input of the filter circuit. In operation, when the third switching network is in the ON state, the third switching network electrically couples the output terminal of the second operational amplifier to the input of the filter circuit, and when the third switching network is in the OFF state, the third switching network decouples the output terminal of the second operational amplifier from the input of the filter circuit.

3. The pulse width modulation digital-to-analog converter circuit according to claim 2, wherein the filter circuit comprises: A first resistor, the first resistor including a first terminal electrically coupled to the input of the filter circuit and a second terminal electrically coupled to the first input terminal of the third operational amplifier; and The capacitor includes a first terminal electrically coupled to the second terminal of the first resistor and electrically coupled to the first input terminal of the third operational amplifier, and a second terminal electrically coupled to the ground terminal.

4. The pulse width modulation digital-to-analog converter circuit according to claim 1, wherein: When the second and third switch networks are in the non-conducting state, the first and fourth switch networks are in the conducting state, and When the second switch network and the third switch network are in the on state, the first switch network and the fourth switch network are in the off state.

5. The pulse width modulation digital-to-analog converter circuit according to claim 1, wherein: The first input signal and the second input signal are pulse wave modulated signals. The first input signal has a first voltage level during a first time period and a second voltage level during a second time period. The first voltage level is greater than the second voltage level. The first time period is different from the second time period, and The second input signal has the first voltage level during the second time period and the second voltage level during the first time period.

6. A pulse width modulation digital-to-analog converter circuit, the pulse width modulation digital-to-analog converter circuit comprising: Filter circuit; A first operational amplifier includes a first input terminal, a second input terminal, and an output terminal, wherein the voltage level at the output terminal is based on the voltage level at the first input terminal and the voltage level at the second input terminal, and wherein the first input terminal is electrically coupled to the output of the filter circuit, and the output terminal is electrically coupled to the second input terminal; A first switch, comprising a control terminal, a first terminal, and a second terminal, wherein the first switch electrically controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal, and wherein the control terminal is electrically coupled to a first input signal, and the second terminal is electrically coupled to the input of the filter circuit; The second switch includes a control terminal, a first terminal, and a second terminal, wherein the second switch electrically controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal, and wherein the control terminal is electrically coupled to the first input signal, and the second terminal is electrically coupled to the input of the filter circuit; The second operational amplifier includes a first input terminal, a second input terminal, and an output terminal, wherein the voltage level at the output terminal is based on the voltage level at the second input terminal, and wherein the output terminal is electrically coupled to the first terminal of the first switch, and the first input terminal is electrically coupled to a first reference voltage; A third switch, comprising a control terminal, a first terminal, and a second terminal, wherein the third switch electrically controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal, and wherein the control terminal is electrically coupled to a second input signal, the first terminal is electrically coupled to the output terminal of the second operational amplifier, and the second terminal is electrically coupled to the first terminal of the second switch and electrically coupled to the second input terminal of the second operational amplifier; The fourth switch includes a control terminal, a first terminal, and a second terminal. The fourth switch controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal. The control terminal is electrically coupled to the second input signal. The first terminal is electrically coupled to the second terminal of the third switch. The first terminal is also electrically coupled to the first terminal of the second switch. The second terminal is electrically coupled to the output terminal of the first operational amplifier. The fifth switch includes a control terminal, a first terminal, and a second terminal, wherein the fifth switch electrically controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal, and wherein the control terminal is electrically coupled to the second input signal, and the second terminal is electrically coupled to the input of the filter circuit; A sixth switch, comprising a control terminal, a first terminal, and a second terminal, wherein the sixth switch electrically controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal, and wherein the control terminal is electrically coupled to the second input signal, and the second terminal is electrically coupled to the input of the filter circuit; A third operational amplifier includes a first input terminal, a second input terminal, and an output terminal, wherein the voltage level at the output terminal is based on the voltage level at the second input terminal, and wherein the output terminal is electrically coupled to the first terminal of the fifth switch, and the first input terminal is electrically coupled to a second reference voltage; The seventh switch includes a control terminal, a first terminal, and a second terminal. The seventh switch controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal. The control terminal is electrically coupled to the first input signal, the first terminal is electrically coupled to the output terminal of the third operational amplifier, and the second terminal is electrically coupled to the first terminal of the sixth switch and to the second input terminal of the third operational amplifier. and The eighth switch includes a control terminal, a first terminal, and a second terminal. The eighth switch electrically controls whether the first terminal is electrically coupled to the second terminal based on the voltage level at the control terminal. The control terminal is electrically coupled to the first input signal. The first terminal is electrically coupled to the second terminal of the seventh switch, and also electrically coupled to the first terminal of the sixth switch. The second terminal is electrically coupled to the output terminal of the first operational amplifier. The first input signal and the second input signal have the same peak-to-peak voltage level, and the first input signal and the second input signal are 180 degrees out of phase. The first reference voltage and the second reference voltage have the same amplitude and opposite polarities.

7. The pulse width modulation digital-to-analog converter circuit according to claim 6, wherein: The first input terminal of the first operational amplifier is a non-inverting input terminal. The second input terminal of the first operational amplifier is an inverting input terminal. The first input terminal of the second operational amplifier is a non-inverting input terminal; The second input terminal of the second operational amplifier is an inverting input terminal. The first input terminal of the third operational amplifier is a non-inverting input terminal, and The second input terminal of the third operational amplifier is an inverting input terminal.

8. The pulse width modulation digital-to-analog converter circuit according to claim 6, wherein the filter circuit comprises: A first resistor, the first resistor including a first terminal electrically coupled to the input of the filter circuit and a second terminal electrically coupled to the output of the filter circuit; and The capacitor includes a first terminal electrically coupled to the second terminal of the first resistor and electrically coupled to the output of the filter circuit, and a second terminal electrically coupled to a ground terminal.

9. The pulse width modulation digital-to-analog converter circuit according to claim 8, wherein the pulse width modulation digital-to-analog converter circuit further comprises: The second resistor includes a first terminal electrically coupled to the second terminal of the fourth switch and a second terminal electrically coupled to the output terminal of the first operational amplifier. and The third resistor includes a first terminal electrically coupled to the second terminal of the eighth switch and a second terminal electrically coupled to the output terminal of the first operational amplifier. The resistance of the first resistor is equal to the resistance of the second resistor and the resistance of the third resistor.

10. The pulse width modulation digital-to-analog converter circuit according to claim 6, wherein the pulse width modulation digital-to-analog converter circuit further comprises: A first resistor, the first resistor including a first terminal electrically coupled to the output terminal of the second operational amplifier and a second terminal electrically coupled to the first terminal of the first switch and electrically coupled to the first terminal of the third switch; A first capacitor, the first capacitor including a first terminal electrically coupled to the output terminal of the second operational amplifier and a second terminal electrically coupled to the first terminal of the first switch and electrically coupled to the first terminal of the third switch; The second resistor includes a first terminal electrically coupled to the output terminal of the third operational amplifier and a second terminal electrically coupled to the first terminal of the fifth switch and the first terminal of the seventh switch. The second capacitor includes a first terminal electrically coupled to the output terminal of the third operational amplifier and a second terminal electrically coupled to the first terminal of the fifth switch and the first terminal of the seventh switch.

11. The pulse width modulation digital-to-analog converter circuit according to claim 6, wherein the first input signal and the second input signal are pulse wave modulation signals.

12. The pulse width modulation digital-to-analog converter circuit according to claim 11, wherein: The first input signal has a first voltage level during a first time period and a second voltage level during a second time period. The first voltage level is greater than the second voltage level. The first time period is different from the second time period, and The second input signal has the first voltage level during the second time period and the second voltage level during the first time period.

13. A method for operating a pulse width modulation digital-to-analog converter circuit according to any one of claims 6 to 12, the method comprising: The fifth switch is controlled based on the second input signal; The sixth switch is controlled based on the second input signal; The seventh switch is controlled based on the first input signal; Control the eighth switch based on the first input signal; Control the first switch based on the first input signal; The second switch is controlled based on the first input signal; The third switch is controlled based on the second input signal; The fourth switch is controlled based on the second input signal; The second reference voltage is electrically coupled to the first input of the third operational amplifier; The first reference voltage is electrically coupled to the first input of the second operational amplifier; The output of the filter circuit is electrically coupled to the first input of the first operational amplifier; The output of the first operational amplifier is electrically coupled to the second input of the first operational amplifier; When the fifth switch is in the ON state, the output of the third operational amplifier is electrically coupled to the input of the filter circuit via the fifth switch; When the fifth switch and the sixth switch are in the ON state, the output of the third operational amplifier is electrically coupled to the second input of the third operational amplifier via the fifth switch and the sixth switch; When the third switch is in the ON state, the output of the second operational amplifier is electrically coupled to the second input of the second operational amplifier via the third switch; When the third switch and the fourth switch are in the ON state, the output of the second operational amplifier is electrically coupled to the output of the first operational amplifier via the third switch and the fourth switch; When the seventh switch is in the ON state, the output of the third operational amplifier is electrically coupled to the second input of the third operational amplifier via the seventh switch; When the seventh switch and the eighth switch are in the ON state, the output of the third operational amplifier is electrically coupled to the output of the first operational amplifier via the seventh switch and the eighth switch; When the first switch is in the ON state, the output of the second operational amplifier is electrically coupled to the input of the filter circuit via the first switch; as well as When the first switch and the second switch are in the ON state, the output of the second operational amplifier is electrically coupled to the second input of the second operational amplifier via the first switch and the second switch.

14. The method of claim 13, wherein: During the first time period, the output of the third operational amplifier is electrically coupled to the input of the filter circuit via the fifth switch. During the first time period, the operation of electrically coupling the output of the third operational amplifier to the second input of the third operational amplifier via the fifth and sixth switches is performed. During the first time period, the operation of electrically coupling the output of the second operational amplifier to the second input of the second operational amplifier via the third switch is performed. During the first time period, the operation of electrically coupling the output of the second operational amplifier to the output of the first operational amplifier via the third and fourth switches is performed. The second time period is different from the first time period. The operation of electrically coupling the output of the third operational amplifier to the second input of the third operational amplifier via the seventh switch is performed during the second time period. During the second time period, the output of the third operational amplifier is electrically coupled to the output of the first operational amplifier via the seventh and eighth switches; During the second time period, the operation of electrically coupling the output of the second operational amplifier to the second input of the second operational amplifier via the first and second switches is performed, and During the second time period, the output of the second operational amplifier is electrically coupled to the input of the filter circuit via the first switch.

15. The method of claim 14, wherein the second input signal and the first input signal are pulse width modulation signals.

16. The method of claim 15, wherein: The second input signal has a first voltage level during the first time period and a second voltage level during the second time period. The first voltage level is greater than the second voltage level, and The first input signal has the first voltage level during the second time period and has the second voltage level during the first time period.

17. The method of claim 13, wherein: The filter circuit includes a first resistor and a capacitor. The step of electrically coupling the output of the third operational amplifier to the output of the first operational amplifier via the seventh switch and the eighth switch includes electrically coupling the output of the third operational amplifier to the output of the first operational amplifier via the seventh switch, the eighth switch, and the third resistor. The step of electrically coupling the output of the second operational amplifier to the output of the first operational amplifier via the third switch and the fourth switch includes electrically coupling the output of the second operational amplifier to the output of the first operational amplifier via the third switch, the fourth switch, and the second resistor. The resistance of the first resistor is equal to the resistance of the second resistor and equal to the resistance of the third resistor.

18. The method of claim 13, wherein: The step of electrically coupling the output of the third operational amplifier to the input of the filter circuit via the fifth switch includes: The output of the third operational amplifier is electrically coupled to the first terminal of the second resistor; The output of the third operational amplifier is electrically coupled to the first terminal of the second capacitor; The second terminal of the second resistor is electrically coupled to the fifth switch; The second terminal of the second capacitor is electrically coupled to the fifth switch, and The step of electrically coupling the output of the second operational amplifier to the input of the filter circuit via the first switch includes: The output of the second operational amplifier is electrically coupled to the first terminal of the first resistor; The output of the second operational amplifier is electrically coupled to the first terminal of the first capacitor; Electrically couple the second terminal of the first resistor to the first switch; and The second terminal of the first capacitor is electrically coupled to the first switch.

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