A method and system for detecting low voltage network circuit topology structure

Abstract

The present invention provides a method and system for detecting the circuit topology structure of a low-voltage network. The first data acquisition terminal corresponding to the first node in the data acquisition terminal set sends a distorted current signal and reports the sending completion information to a centralized processor; if the second data acquisition terminal corresponding to the second node receives the distorted current signal, the receiving information is reported to the centralized processor; the centralized processor marks the second data acquisition terminal as the superior of the first data acquisition terminal; the above steps are repeated until each data acquisition terminal in the data acquisition terminal set has sent a distorted current signal to obtain a marking result; the centralized processor generates a circuit topology diagram according to the marking result. In the present invention, when the data acquisition terminals on all nodes to be confirmed have sent distorted currents, the superior-subordinate relationship between each node and the remaining nodes can be obtained, and finally the superior-subordinate relationship between all nodes is obtained to generate a circuit topology diagram, thereby realizing automatic detection of the topology structure in the low-voltage network.

Description

Technical Field

[0001] The present invention relates to the field of electric power distribution, and in particular to a method and system for detecting a low-voltage network circuit topology structure. Background Art

[0002] The topological structure of the circuit in the existing low-voltage network is not clear, and the relationship between transformers, lines, boxes and households in many early-built low-voltage circuits is not clear, which affects the efficiency of daily maintenance and troubleshooting. In addition, the low-voltage distribution network directly serves end-users. If the low-voltage distribution network is to be included in the power dispatching system, it is even more necessary to obtain the circuit topological structure in the low-voltage distribution network. The relationship between transformers, lines, boxes and households in the existing low-voltage distribution network is basically checked manually, which is time-consuming, costly and labor-intensive, and the accuracy of the obtained circuit topological structure also depends on the precision of manual operation. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a method and system for detecting the circuit topology structure of a low-voltage network, so as to realize automatic generation of a circuit topology diagram of a low-voltage network.

[0004] In order to solve the above technical problems, a technical solution adopted by the present invention is:

[0005] A method for detecting a low voltage network circuit topology structure comprises the steps of:

[0006] S1, the first data acquisition terminal corresponding to the first node in the data acquisition terminal set sends a distorted current signal, and reports the sending completion information to the centralized processor;

[0007] S2. If the second data acquisition terminal corresponding to the second node receives the distorted current signal, the received information is reported to the centralized processor;

[0008] S3, the centralized processor marks the second data acquisition terminal as the superior data acquisition terminal of the first data acquisition terminal;

[0009] S4, repeatedly executing S1 to S3 until each data collection end in the data collection end set has executed S1 once, and a marking result is obtained;

[0010] S5. The centralized processor generates a circuit topology diagram according to the marking result.

[0011] In order to solve the above technical problems, another technical solution adopted by the present invention is:

[0012] A low-voltage network circuit topology detection system includes a data acquisition terminal set and a centralized processor, each of the data acquisition terminals in the data acquisition terminal set includes a first memory, a first processor, and a first computer program stored in the first memory and executable on the first processor, the centralized processor includes a second memory, a second processor, and a second computer program stored in the second memory and executable on the second processor, and the first processor implements the following steps when executing the first computer program:

[0013] S1, sending distorted current signal and reporting the sending completion information to the centralized processor;

[0014] S2. If the distorted current signal is received, the received information is reported to the centralized processor;

[0015] When the second processor executes the second computer program, S3 and S5 are implemented:

[0016] S3, marking the second data collection end as the superior data collection end of the first data collection end;

[0017] S4, repeatedly executing S1 to S3 until each data collection end in the data collection end set has executed S1 once, and a marking result is obtained;

[0018] S5. Generate a circuit topology diagram according to the marking result.

[0019] The beneficial effect of the present invention is that a data acquisition terminal is set on a node whose position in the topology structure needs to be confirmed, and the data acquisition terminal can send a distorted current. According to the principle of the upward flow of fault current, the distorted current can be detected by the upper node of the node that sends the distorted current, that is, the upper-lower relationship between the node and all other nodes can be obtained. After the corresponding data acquisition terminals on all nodes that need to be confirmed have sent the distorted current, the upper-lower relationship between each node and the remaining nodes can be obtained, and finally the upper-lower relationship between all nodes can be obtained, and a circuit topology diagram can be obtained, thereby realizing automatic detection of the topology structure in the low-voltage network. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A flowchart of a method for detecting a low-voltage network circuit topology structure according to an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of the structure of a low-voltage network circuit topology structure detection system according to an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of a circuit topology diagram of an embodiment of the present invention;

[0023] Description of labels:

[0024] 1. Data acquisition terminal; 11. First processor; 12. First memory; 2. Centralized processor; 21. Second processor; 22. Second memory; 3. A low-voltage network circuit topology structure detection system. DETAILED DESCRIPTION

[0025] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.

[0026] Please refer to Figure 1 and Figure 3 , a method for detecting a low voltage network circuit topology structure, comprising the steps of:

[0027] S1, the first data acquisition terminal corresponding to the first node in the data acquisition terminal set sends a distorted current signal, and reports the sending completion information to the centralized processor;

[0028] S2. If the second data acquisition terminal corresponding to the second node receives the distorted current signal, the received information is reported to the centralized processor;

[0029] S3, the centralized processor marks the second data acquisition terminal as the superior data acquisition terminal of the first data acquisition terminal;

[0030] S4, repeatedly executing S1 to S3 until each data collection end in the data collection end set has executed S1 once, and a marking result is obtained;

[0031] S5. The centralized processor generates a circuit topology diagram according to the marking result.

[0032] From the above description, it can be seen that the beneficial effects of the present invention are: a data acquisition terminal is set on the node whose position in the topology structure needs to be confirmed, and the data acquisition terminal can send a distorted current. According to the principle of the upward fault current, the distorted current can be detected by the upper node of the node that sends the distorted current, that is, the superior-subordinate relationship between the node and all other nodes can be obtained. When the corresponding data acquisition terminals on all nodes that need to be confirmed have completed sending the distorted current, the superior-subordinate relationship between each node and the remaining nodes can be obtained, and finally the superior-subordinate relationship between all nodes can be obtained, and the circuit topology diagram is obtained, thereby realizing automatic detection of the topological structure in the low-voltage network.

[0033] Furthermore, before S1, the step further includes:

[0034] The data collection terminal set receives a broadcast signal sent by the centralized processor, wherein the broadcast signal includes a reporting timing of each data collection terminal in the data collection terminal set;

[0035] Each of the data collection terminals stores its corresponding reporting timing;

[0036] The S1 is specifically:

[0037] The first data acquisition terminal in the data acquisition terminal set corresponding to the first node determines whether the reporting timing saved by itself is reached, and if so, sends the distorted current signal and reports the sending completion information to the centralized processor.

[0038] From the above description, it can be seen that the centralized processor sends a broadcast signal to the data acquisition end, and the data acquisition end sends the distorted current according to its corresponding reporting timing, avoiding the situation where two distorted currents exist in the circuit at the same time, resulting in the inability to determine the node and its corresponding upper-level node.

[0039] Furthermore, the S1 further includes:

[0040] The first data collection terminal collects the voltage of the first node corresponding to it, and reports the voltage to the centralized processor;

[0041] The S5 is specifically:

[0042] The centralized processor generates initial circuit topology diagrams corresponding to the three phases A, B and C respectively according to the marking results and the voltage quantity;

[0043] The initial circuit topology diagram is synthesized to obtain the circuit topology diagram.

[0044] From the above description, it can be seen that by determining which of the three phases A, B or C the node is in based on the voltage, the circuit topology corresponding to each phase can be obtained, which is convenient for later judgment such as whether the three phases are balanced based on the topology diagram.

[0045] Furthermore, each data collection terminal also includes a unique identifier;

[0046] The S3 is specifically:

[0047] The centralized processor marks the second data collection terminal as the superior data collection terminal of the first data collection terminal, and stores the corresponding relationship between the second unique identifier of the superior data collection terminal and the first unique identifier of the first data collection terminal;

[0048] If the second data collection terminal does not exist, the centralized processor marks the number of the upper-level data collection terminals of the first data collection terminal as 0;

[0049] The S5 is specifically:

[0050] S51, the centralized processor obtains the marking result, the marking result including the number of superior data collection terminals of each data collection terminal to be located and the third unique identifier of each superior data collection terminal;

[0051] S52, the centralized processor determines the level of a corresponding data collection terminal to be located according to the number of the upper-level data collection terminals, the larger the number of the upper-level data collection terminals, the lower the level;

[0052] S53, the centralized processor determines the corresponding relationship between the corresponding data collection terminal to be located and the data collection terminal to be located at an adjacent level according to the third unique identifier;

[0053] S54, the centralized processor executes S52 and S53 in a loop until each of the data collection terminals to be located obtains the level and the corresponding relationship;

[0054] S55. The centralized processor generates a tree-like circuit topology diagram according to the levels and the corresponding relationships.

[0055] From the above description, it can be seen that the number of upper-level data collection terminals corresponding to the data collection terminal and the unique identifier of the upper-level data collection terminal are obtained. The larger the number of upper-level data collection terminals corresponding to the data collection terminal is, the closer the data collection terminal is to the end of the tree diagram. After determining the level of the data collection terminal, the data collection terminal on the branch where the data collection terminal is located can be obtained according to the unique identifier of the upper-level data collection terminal corresponding to the data collection terminal, and then the position of the node corresponding to the data collection terminal in the branch can be obtained, thereby realizing the automatic generation of the circuit topology diagram.

[0056] Furthermore, the frequency of the distorted current is 100 Hz.

[0057] From the above description, it can be seen that using 100 Hz current as the distorted current is within the allowable range of normal circuit operation and can be distinguished from other distorted currents that may be generated in the circuit, thereby avoiding measurement errors to the greatest extent.

[0058] Please refer to Figure 2 A low-voltage network circuit topology structure detection system includes a data acquisition terminal set and a centralized processor, each of the data acquisition terminals in the data acquisition terminal set includes a first memory, a first processor, and a first computer program stored in the first memory and executable on the first processor, the centralized processor includes a second memory, a second processor, and a second computer program stored in the second memory and executable on the second processor, and the first processor implements the following steps when executing the first computer program:

[0059] S1, sending distorted current signal and reporting the sending completion information to the centralized processor;

[0060] S2. If the distorted current signal is received, the received information is reported to the centralized processor;

[0061] When the second processor executes the second computer program, S3 and S5 are implemented:

[0062] S3, marking the second data collection end as the superior data collection end of the first data collection end;

[0063] S4, repeatedly executing S1 to S3 until each data collection end in the data collection end set has executed S1 once, and a marking result is obtained;

[0064] S5. Generate a circuit topology diagram according to the marking result.

[0065] The beneficial effect of the present invention is that a data acquisition terminal is set on a node whose position in the topology structure needs to be confirmed, and the data acquisition terminal can send a distorted current. According to the principle of the upward flow of fault current, the distorted current can be detected by the upper node of the node that sends the distorted current, that is, the upper-lower relationship between the node and all other nodes can be obtained. After the corresponding data acquisition terminals on all nodes that need to be confirmed have sent the distorted current, the upper-lower relationship between each node and the remaining nodes can be obtained, and finally the upper-lower relationship between all nodes can be obtained, and a circuit topology diagram can be obtained, thereby realizing automatic detection of the topology structure in the low-voltage network.

[0066] Furthermore, before S1, the step further includes:

[0067] The first processor receives a broadcast signal sent by the centralized processor when executing the first computer program, wherein the broadcast signal includes a reporting timing of each data collection terminal in the data collection terminal set;

[0068] The first processor saves its corresponding reporting timing when executing the first computer program;

[0069] The S1 is specifically:

[0070] When executing the first computer program, the first processor determines whether the reporting timing saved by itself is reached. If so, the distorted current signal is sent, and the sending completion information is reported to the centralized processor.

[0071] From the above description, it can be seen that the centralized processor sends a broadcast signal to the data acquisition end, and the data acquisition end sends the distorted current according to its corresponding reporting timing, avoiding the situation where two distorted currents exist in the circuit at the same time, resulting in the inability to determine the node and its corresponding upper-level node.

[0072] Furthermore, the S1 further includes:

[0073] When the first processor executes the first computer program, the first processor collects the voltage of the first node corresponding to the first processor, and reports the voltage to the central processor;

[0074] The S5 is specifically:

[0075] When the second processor executes the second computer program, the second processor generates initial circuit topology diagrams corresponding to the three phases A, B and C respectively according to the marking results and the voltage amount;

[0076] The initial circuit topology diagram is synthesized to obtain the circuit topology diagram.

[0077] From the above description, it can be seen that by determining which of the three phases A, B or C the node is in based on the voltage, the circuit topology corresponding to each phase can be obtained, which is convenient for later judgment such as whether the three phases are balanced based on the topology diagram.

[0078] Furthermore, each data collection terminal also includes a unique identifier;

[0079] The S3 is specifically:

[0080] Marking the second data collection end as the superior data collection end of the first data collection end, and storing the corresponding relationship between the second unique identifier of the superior data collection end and the first unique identifier of the first data collection end;

[0081] If the second data collection terminal does not exist, the number of the upper-level data collection terminals marking the first data collection terminal is 0;

[0082] The S5 is specifically:

[0083] S51, obtaining the marking result, wherein the marking result includes the number of superior data collection terminals of each data collection terminal to be located and the third unique identifier of each superior data collection terminal;

[0084] S52, determining the level of a corresponding data collection terminal to be located according to the number of the upper-level data collection terminals, wherein the larger the number of the upper-level data collection terminals, the lower the level;

[0085] S53, determining a corresponding relationship between a corresponding data collection terminal to be located and a data collection terminal to be located at an adjacent level according to the third unique identifier;

[0086] S54, looping through S52 and S53 until each of the data collection terminals to be located obtains the level and the corresponding relationship;

[0087] S55: Generate a tree-like circuit topology diagram according to the levels and the corresponding relationships.

[0088] From the above description, it can be seen that the number of upper-level data collection terminals corresponding to the data collection terminal and the unique identifier of the upper-level data collection terminal are obtained. The larger the number of upper-level data collection terminals corresponding to the data collection terminal is, the closer the data collection terminal is to the end of the tree diagram. After determining the level of the data collection terminal, the data collection terminal on the branch where the data collection terminal is located can be obtained according to the unique identifier of the upper-level data collection terminal corresponding to the data collection terminal, and then the position of the node corresponding to the data collection terminal in the branch can be obtained, thereby realizing the automatic generation of the circuit topology diagram.

[0089] Furthermore, the frequency of the distorted current is 100 Hz.

[0090] From the above description, it can be seen that using 100 Hz current as the distorted current is within the allowable range of normal circuit operation and can be distinguished from other distorted currents that may be generated in the circuit, thereby avoiding measurement errors to the greatest extent.

[0091] Please refer to Figure 1 , Embodiment 1 of the present invention is:

[0092] A method for detecting a low voltage network circuit topology structure comprises the steps of:

[0093] S1, the data collection terminal set receives a broadcast signal sent by the centralized processor, the broadcast signal includes a reporting timing of each data collection terminal in the data collection terminal set;

[0094] Each of the data collection terminals stores its corresponding reporting timing;

[0095] S2. The first data acquisition terminal in the data acquisition terminal set corresponding to the first node sends a distorted current signal and reports the sending completion information to the centralized processor, specifically:

[0096] The first data acquisition terminal in the data acquisition terminal set corresponding to the first node determines whether the reporting timing saved by itself is reached, and if so, sends the distorted current signal and reports the sending completion information to the centralized processor;

[0097] In an optional embodiment, the frequency of the distorted current is 100 Hz;

[0098] S3. If the second data acquisition terminal corresponding to the second node receives the distorted current signal, the received information is reported to the centralized processor;

[0099] S4, the centralized processor marks the second data acquisition terminal as the superior data acquisition terminal of the first data acquisition terminal;

[0100] S5, repeatedly executing S1 to S3 until each data collection end in the data collection end set has executed S1 once, and a marking result is obtained;

[0101] S6, the centralized processor generates a circuit topology diagram according to the marking result;

[0102] In an optional implementation, the data collection end includes a node data collection end and a user data collection end. The user data collection end is located in the meter box on the user side, and can collect the voltage on the user side, and distinguish which phase of the three-phase line A, B and C the user is located in according to the voltage on the user side;

[0103] In an optional implementation, the data collection terminal set and the centralized processor perform data exchange via a self-organizing network, and implement clock synchronization via a self-organizing network, such as a self-organizing network via LPWAN;

[0104] In an optional implementation, the node data acquisition terminal uses a through-hole current transformer for data sampling.

[0105] Embodiment 2 of the present invention is:

[0106] A method for detecting a low voltage network circuit topology structure, which is different from the first embodiment in that:

[0107] S2 also includes:

[0108] The first data collection terminal collects the voltage of the first node corresponding to it, and reports the voltage to the centralized processor;

[0109] S6 is specifically:

[0110] The centralized processor generates initial circuit topology diagrams corresponding to the three phases A, B and C respectively according to the marking results and the voltage quantity;

[0111] The initial circuit topology diagram is synthesized to obtain the circuit topology diagram.

[0112] Embodiment 3 of the present invention is:

[0113] A method for detecting a low voltage network circuit topology structure, which is different from the first or second embodiment in that:

[0114] Each data collection terminal also includes a unique identifier;

[0115] S4 is specifically:

[0116] The centralized processor marks the second data collection terminal as the superior data collection terminal of the first data collection terminal, and stores the corresponding relationship between the second unique identifier of the superior data collection terminal and the first unique identifier of the first data collection terminal;

[0117] If the second data collection terminal does not exist, the centralized processor marks the number of the upper-level data collection terminals of the first data collection terminal as 0;

[0118] S6 is specifically:

[0119] S61, the centralized processor obtains the marking result, the marking result including the number of superior data collection terminals of each data collection terminal to be located and the third unique identifier of each superior data collection terminal;

[0120] S62, the centralized processor determines the level of a corresponding data collection terminal to be located according to the number of the upper-level data collection terminals, the larger the number of the upper-level data collection terminals, the lower the level;

[0121] S63, the centralized processor determines the branch corresponding to the data collection terminal to be located according to the third unique identifier and the level;

[0122] S64, the centralized processor executes S52 and S53 in a loop until each of the to-be-located data collection terminals obtains the branch;

[0123] S65, the centralized processor generates a tree-like circuit topology diagram according to the branches, wherein the node position in the circuit topology diagram is the node corresponding to the data collection terminal to be located at the position;

[0124] In an optional implementation, the node includes a substation, a distribution box and a user end.

[0125] Please refer to Figure 3 , Embodiment 4 of the present invention is:

[0126] The above-mentioned low-voltage network circuit topology structure detection method is applied to the actual scenario:

[0127] Please refer to Figure 3 , record the data collection terminal at node 1 as data collection terminal 1, and the same applies to the remaining nodes;

[0128] S1, the data collection terminal set (data collection terminal 1-data collection terminal 6) receives the broadcast signal sent by the centralized processor, and the broadcast signal includes the reporting timing of each data collection terminal in the data collection terminal set;

[0129] Each of the data collection terminals stores its corresponding reporting time sequence: data collection terminal 6: 1, data collection terminal 3: 2, data collection terminal 4: 3, data collection terminal 5: 4, data collection terminal 2: 5, data collection terminal 1: 6;

[0130] S2, the data acquisition terminal 6 corresponding to the node 6 determines whether it has reached the reporting timing saved by itself, and if so, sends the distorted current signal and reports the sending completion information to the centralized processor;

[0131] S3, the data acquisition terminal 4, the data acquisition terminal 2 and the data acquisition terminal 1 corresponding to the node 4, the node 2 and the node 1 respectively receive the distorted current signal and report the received information to the centralized processor;

[0132] S4, the centralized processor marks the data collection terminal 4, the data collection terminal 2 and the data collection terminal 1 as the superior data collection terminals of the data collection terminal 6, and records the number 3 of the superior data collection terminals of the data collection terminal 4;

[0133] S5, repeatedly execute S2-S4 until each data collection terminal in the data collection terminal set has executed S2 once, and obtain the marking result: the number of superior data collection terminals of data collection terminal 6 is 3, namely data collection terminal 4, data collection terminal 2 and data collection terminal 1; the number of superior data collection terminals of data collection terminal 3 is 2, namely data collection terminal 2 and data collection terminal 1; the number of superior data collection terminals of data collection terminal 4 is 2, namely data collection terminal 2 and data collection terminal 1, the number of superior data collection terminals of data collection terminal 5 is 1, namely data collection terminal 1; the number of superior data collection terminals of data collection terminal 2 is 1, namely data collection terminal 1, and the number of superior data collection terminals of data collection terminal 1 is 0;

[0134] S6. Generate a circuit topology diagram based on the marking results:

[0135] S61, determining the corresponding level according to the number of upper-level data collection terminals corresponding to the data collection terminals: first level: data collection terminal 1, second level: data collection terminal 2 and data collection terminal 5, third level: data collection terminal 3 and data collection terminal 4, fourth level: data collection terminal 6;

[0136] S62, determine the corresponding branch according to the upper data collection terminal and the layer corresponding to the data collection terminal, for example, data collection terminal 2 is located at the second layer, and its upper data collection terminal is data collection terminal 1, then the branch corresponding to data collection terminal 2 is data collection terminal 1→data collection terminal 2; for another example, data collection terminal 6 is located at the fourth layer, and its upper data collection terminals are data collection terminal 4, data collection terminal 2 and data collection terminal 1, data collection terminal 4 is located at the third layer, data collection terminal 2 is located at the second layer, and data collection terminal 1 is located at the first layer, then the branch corresponding to data collection terminal 6 is: data collection terminal 1→data collection terminal 2→data collection terminal 4→data collection terminal 6;

[0137] S63, looping through S61 and S62 until each data collection terminal acquires the branch;

[0138] S64. Generate a tree-like circuit topology diagram based on the branches.

[0139] Please refer to Figure 2 , Embodiment 5 of the present invention is:

[0140] A low-voltage network circuit topology detection system 3 includes a data acquisition terminal set and a centralized processor 2, wherein each data acquisition terminal 1 in the data acquisition terminal set includes a first memory 12, a first processor 11, and a first computer program stored in the first memory 12 and executable on the first processor 11, and the centralized processor 2 includes a second memory 22, a second processor 21, and a second computer program stored in the second memory 22 and executable on the second processor 21, and the first processor 11 implements the corresponding steps executed by the data acquisition terminal in Embodiments 1 to 4 when executing the first computer program, and the second processor 21 implements the corresponding steps executed by the centralized processor in Embodiments 1 to 4 when executing the second computer program;

[0141] In an optional implementation, the centralized processor includes a gateway for collecting reported data and an intelligent terminal for processing reported data.

[0142] In summary, the present invention provides a method and system for detecting the topological structure of a low-voltage network circuit. A data acquisition terminal is set on each node whose topological position needs to be confirmed. The data acquisition terminal sends the distorted current to the circuit according to the timing of the central processor broadcast received, and reports the sending completion information to the central processor. If the data acquisition terminal on a node receives the distorted current information at this time, the receiving information is reported. Since the distorted current is upstream in the circuit, the node that receives the distorted current is the upper node of the node that sends the distorted current; the central processor marks the corresponding relationship. After the data acquisition terminal on each node to be confirmed has sent the distorted current, the upper and lower relationships between the nodes in the area can be obtained, and the corresponding circuit topology map is generated; and a data acquisition terminal is also set in the user-side meter box, which can confirm which phase of the three-phase line the terminal user is specifically located in according to the voltage, so that the final topology map is more accurate, which is convenient for the subsequent statistics of the circuit data in the three phases. It only needs to set a data acquisition device on the node, and the automatic generation of the circuit topology map can be realized through the central processor, which saves labor costs and has high accuracy.

[0143] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for detecting a low voltage network circuit topology structure, characterized in that: Includes steps: S0. Setting a data acquisition terminal on a node whose position in the topology structure needs to be confirmed, wherein the data acquisition terminal is capable of sending distorted current; S1, the first data acquisition terminal corresponding to the first node in the data acquisition terminal set sends a distorted current signal, and reports the sending completion information to the centralized processor; S2. If the second data acquisition terminal corresponding to the second node receives the distorted current signal, the received information is reported to the centralized processor; S3, the centralized processor marks the second data acquisition terminal as the superior data acquisition terminal of the first data acquisition terminal; S4, repeatedly executing step S1 to step S3 until each data collection end in the data collection end set has executed step S1 once, and a marking result is obtained; S5, the centralized processor generates a circuit topology diagram according to the marking result; Each data collection terminal also includes a unique identifier; The step S3 is specifically as follows: The centralized processor marks the second data collection terminal as the superior data collection terminal of the first data collection terminal, and stores the corresponding relationship between the second unique identifier of the superior data collection terminal and the first unique identifier of the first data collection terminal; If the second data collection terminal does not exist, the centralized processor marks the number of the upper-level data collection terminals of the first data collection terminal as 0; The step S5 comprises the steps of: S51, the centralized processor obtains the marking result, the marking result including the number of superior data collection terminals of each data collection terminal to be located and the third unique identifier of each superior data collection terminal; S52, the centralized processor determines the level of a corresponding data collection terminal to be located according to the number of the upper-level data collection terminals, the larger the number of the upper-level data collection terminals, the lower the level; S53, the centralized processor determines the branch corresponding to the data collection terminal to be located according to the third unique identifier and the level; S54, the centralized processor executes the step S52 and the step S53 in a loop until each of the data collection terminals to be located obtains the branch; S55, the centralized processor generates a tree-shaped circuit topology diagram according to the branches; Before step S1, the following steps are also included: The data collection terminal set receives a broadcast signal sent by the centralized processor, wherein the broadcast signal includes a reporting timing of each data collection terminal in the data collection terminal set; Each of the data collection terminals stores its corresponding reporting timing; The step S1 is specifically as follows: The first data acquisition terminal in the data acquisition terminal set corresponding to the first node determines whether the reporting timing saved by itself is reached, and if so, sends the distorted current signal and reports the sending completion information to the centralized processor.

2. A low voltage network circuit topology detection method according to claim 1, characterized in that: The step S1 further comprises: The first data collection terminal collects the voltage of the first node corresponding to it, and reports the voltage to the centralized processor; The step S5 is specifically as follows: The centralized processor generates initial circuit topology diagrams corresponding to the three phases A, B and C respectively according to the marking results and the voltage quantity; The initial circuit topology diagram is synthesized to obtain the circuit topology diagram.

3. A low voltage network circuit topology detection method according to claim 1, characterized in that: The frequency of the distorted current is 100 Hz.

4. A low-voltage network circuit topology structure detection system, comprising a data acquisition terminal set and a centralized processor, wherein a data acquisition terminal is set at a node whose position in the topology structure needs to be confirmed, and the data acquisition terminal can send distorted current, each data acquisition terminal in the data acquisition terminal set comprises a first memory, a first processor, and a first computer program stored in the first memory and executable on the first processor, and the centralized processor comprises a second memory, a second processor, and a second computer program stored in the second memory and executable on the second processor, characterized in that: The first processor of the first data acquisition terminal implements the following steps when executing the first computer program: S1, sending distorted current signal and reporting the sending completion information to the centralized processor; S2. If the second data acquisition terminal corresponding to the second node receives the distorted current signal, the received information is reported to the centralized processor; When the second processor executes the second computer program, S3 and S5 are implemented: S3, marking the second data collection end as the superior data collection end of the first data collection end; S4, repeatedly executing step S1 to step S3 until each data collection end in the data collection end set has executed step S1 once, and a marking result is obtained; S5, generating a circuit topology diagram according to the marking result; Each data collection terminal also includes a unique identifier; The step S3 is specifically as follows: Marking the second data collection end as the superior data collection end of the first data collection end, and storing the corresponding relationship between the second unique identifier of the superior data collection end and the first unique identifier of the first data collection end; If the second data collection terminal does not exist, the number of the upper-level data collection terminals marking the first data collection terminal is 0; The step S5 comprises the steps of: S51, obtaining the marking result, wherein the marking result includes the number of superior data collection terminals of each data collection terminal to be located and the third unique identifier of each superior data collection terminal; S52, determining the level of a corresponding data collection terminal to be located according to the number of the upper-level data collection terminals, wherein the larger the number of the upper-level data collection terminals, the lower the level; S53, determining the branch corresponding to the data collection terminal to be located according to the third unique identifier and the level; S54, looping through step S52 and step S53 until each of the to-be-located data collection terminals acquires the branch; S55, generating a tree-shaped circuit topology diagram according to the branches; Before step S1, the following steps are also included: The first processor receives a broadcast signal sent by the centralized processor when executing the first computer program, wherein the broadcast signal includes a reporting timing of each data collection terminal in the data collection terminal set; The first processor saves its corresponding reporting timing when executing the first computer program; The step S1 is specifically as follows: When executing the first computer program, the first processor determines whether the reporting timing saved by itself is reached. If so, the distorted current signal is sent, and the sending completion information is reported to the centralized processor.

5. A low voltage network circuit topology structure detection system according to claim 4, characterized in that: The step S1 further comprises: When the first processor executes the first computer program, the first processor collects the voltage of the first node corresponding to the first processor, and reports the voltage to the central processor; The step S5 is specifically as follows: When the second processor executes the second computer program, the second processor generates initial circuit topology diagrams corresponding to the three phases A, B and C respectively according to the marking results and the voltage amount; The initial circuit topology diagram is synthesized to obtain the circuit topology diagram.

6. A low voltage network circuit topology structure detection system according to claim 4, characterized in that: The frequency of the distorted current is 100 Hz.

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