Machine learning sparse computing mechanism

Abstract

An apparatus for facilitating the processing of sparse matrices is disclosed. The apparatus includes a plurality of processing units, each including one or more processing elements, the one or more processing elements including logic for reading operands, a multiplication unit for multiplying two or more operands, and a scheduler for identifying operands having a zero value and preventing the scheduler of the multiplication unit from scheduling the operands having the zero value.

Description

Technical Field

[0001] Embodiments generally relate to data processing and, more particularly, to data processing via a general purpose graphics processing unit. Background Art

[0002] Current parallel graphics data processing includes systems and methods developed for performing specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors used fixed function computing units to process graphics data; however, recently, multiple parts of graphics processors have become programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques, such as pipelining, that attempt to process as much graphics data in parallel as possible throughout different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, multiple groups of parallel threads attempt to synchronously execute program instructions together as often as possible to improve processing efficiency. A general overview of the software and hardware for the SIMT architecture can be found in Shane Cook's CUDA Programming ( CUDA Programming ), Chapter 3, pages 37 - 51 (2013). Brief Description of the Drawings

[0004] In order to describe the above-recited features of the embodiments in a manner that enables a detailed understanding, the embodiments briefly summarized above may be described in more detail by reference to the embodiments, some of which are illustrated in the drawings. However, it should be noted that the drawings only illustrate typical embodiments and are therefore not to be considered as limiting their scope.

[0005] Figure 1 is a block diagram that illustrates a computer system configured to implement one or more aspects of the embodiments described herein;

[0006] Figures 2A - 2D illustrates a parallel processor component according to an embodiment;

[0007] Figures 3A - 3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0008] Figures 4A - 4F illustrates an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0009] Figure 5 illustrates a graphics processing pipeline according to an embodiment;

[0010] Figure 6 Shows a computing device employing a sparse computing mechanism according to an embodiment;

[0011] Figure 7A Shows an exemplary matrix multiplication;

[0012] Figure 7B Shows an embodiment of processing elements with a sparse scheduler;

[0013] Figure 7C Shows an embodiment of a sparse tracker;

[0014] Figure 7D &7E shows an embodiment of a graphics processor;

[0015] Figure 8 Shows a machine learning software stack according to an embodiment;

[0016] Figure 9 Shows a highly parallel general - purpose graphics processing unit according to an embodiment;

[0017] Figure 10 Shows a multi - GPU computing system according to an embodiment;

[0018] Figures 11A - 11B Shows a layer of an exemplary deep neural network;

[0019] Figure 12 Shows an exemplary recurrent neural network;

[0020] Figure 13 Shows the training and deployment of a deep neural network;

[0021] Figure 14 Is a block diagram showing distributed learning;

[0022] Figure 15 Shows an exemplary system - on - chip (SOC) for inference suitable for performing inference using a trained model;

[0023] Figure 16 Is a block diagram of a processing system according to an embodiment;

[0024] Figure 17 Is a block diagram of a processor according to an embodiment;

[0025] Figure 18 Is a block diagram of a graphics processor according to an embodiment;

[0026] Figure 19 Is a block diagram of a graphics processing engine of a graphics processor according to some embodiments;

[0027] Figure 20is a block diagram of a graphics processor provided by an additional embodiment;

[0028] Figure 21 shows thread execution logic, which includes an array of processing elements employed in some embodiments;

[0029] Figure 22 is a block diagram showing a graphics processor instruction format according to some embodiments;

[0030] Figure 23 is a block diagram of a graphics processor according to another embodiment;

[0031] Figures 24A - 24B shows a graphics processor command format and command sequence according to some embodiments;

[0032] Figure 25 shows an exemplary graphics software architecture of a data processing system according to some embodiments;

[0033] Figure 26 is a block diagram showing an IP core development system according to an embodiment;

[0034] Figure 27 is a block diagram showing an exemplary system-on-chip integrated circuit according to an embodiment;

[0035] Figure 28 is a block diagram showing an additional exemplary graphics processor; and

[0036] Figure 29 is a block diagram showing an additional exemplary graphics processor of a system-on-chip integrated circuit according to an embodiment. Detailed Description

[0037] In an embodiment, a mechanism for performing a sparse matrix processing mechanism is disclosed. In some embodiments, the processing mechanism includes processing elements, and the processing elements include a scheduler for identifying operands having a zero value and preventing the scheduling of operands having a zero value in a multiplication unit. In other embodiments, the processing mechanism includes pattern tracking logic for detecting one or more sparse data segments in a storage block of data and recording the address locations of each detected sparse data segment. In still other embodiments, for processing, the processing mechanism compresses a sparse matrix and stores one or more frequently used sparse matrices in a sparse compression buffer for execution. In further embodiments, the processing mechanism partitions a plurality of execution units (EUs) and assigns each partition of the EUs to execution threads associated with a neural network layer.

[0038] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one of ordinary skill in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of the embodiments.

[0039] System Overview

[0040] Figure 1 is a block diagram that illustrates a computing system configured to implement one or more aspects of the embodiments described herein. Computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, the one or more processors 102 communicating with the system memory 104 via an interconnect path that may include a memory hub 105. Memory hub 105 may be a separate component within a chipset component or may be integrated within the one or more processors 102. Memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. I / O subsystem 111 includes an I / O hub 107, which may enable computing system 100 to receive input from one or more input devices 108. Additionally, I / O hub 107 may enable a display controller to provide output to one or more display devices 110A, the display controller being included within the one or more processors 102. In one embodiment, the one or more display devices 110A coupled to I / O hub 107 may include a local, internal, or embedded display device.

[0041] In one embodiment, processing subsystem 101 includes one or more parallel processors 112, the parallel processors 112 being coupled to memory hub 105 via a bus or other communication link 113. Communication link 113 may be any one of a number of standard-based communication link technologies or protocols (such as, but not limited to, PCI Express), or may be a vendor-specific communication interface or communication fabric. In one embodiment, the one or more parallel processors 112 form a computationally concentrated parallel or vector processing system that includes a large number of processing cores and / or processing clusters (such as, an integrated many-core (MIC) processor). In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that may output pixels to one of the one or more display devices 110A coupled via I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 110B.

[0042] Within the I / O subsystem 111, the system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. The I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components, such as network adapter 118 and / or wireless network adapter 119 that can be integrated into the platform, and various other devices that can be added via one or more plug-in devices 120. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of the following: Wi-Fi, Bluetooth, Near Field Communication (NFC), or another network device that includes one or more wireless radios.

[0043] The computing system 100 can include other components not explicitly shown, including USB or other port connectors, optical storage drives, video capture devices, and the like, which can also be connected to the I / O hub 107. The communication paths interconnecting the various components in Figure 1 can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI Express) or any other bus or point-to-point communication interface and / or protocol (such as NV-Link high-speed interconnect, or interconnect protocols known in the art).

[0044] In one embodiment, the one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a Graphics Processing Unit (GPU). In another embodiment, the one or more parallel processors 112 incorporate circuitry optimized for general-purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 can be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processors 112, memory hub 105, processor 102, and I / O hub 107 can be integrated into a System-on-Chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a System-in-Package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 can be integrated into a Multi-Chip Module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0045] It will be appreciated that the computing system 100 shown herein is illustrative, and variations and modifications are possible. The connection topology can be modified as desired, including the number and arrangement of bridges, the number of processors 102, and the number of parallel processors 112. For example, in some embodiments, system memory 104 is connected directly to the processor(s) 102 rather than through a bridge, while other devices communicate with the processor(s) 102 and system memory 104 via memory hub 105. In other alternative topologies, the parallel processor(s) 112 are connected to I / O hub 107 or directly to one of the processor(s) 102, rather than to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 can be integrated into a single chip. Some embodiments can include two or more sets of processors 102 attached via multiple sockets, which can be coupled to two or more instances of the parallel processor(s) 112.

[0046] Some of the specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripheral devices can be supported, or some components can be eliminated. Additionally, some architectures may use different terms for components similar to those shown Figure 1 herein. For example, in some architectures, memory hub 105 may be referred to as the north bridge, while I / O hub 107 may be referred to as the south bridge.

[0047] Figure 2A A parallel processor 200 is shown in accordance with an embodiment. The various components of parallel processor 200 can be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). In accordance with an embodiment, the parallel processor 200 shown is Figure 1 a variant of one or more of the parallel processors 112 shown above.

[0048] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices, including other instances of the parallel processing unit 202. The I / O unit 204 can be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via the use of a hub or switch interface, such as the memory hub 105. The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, where the host interface 206 receives commands for performing processing operations and the memory crossbar 216 receives commands for performing memory operations.

[0049] When the host interface 206 receives a command buffer via the I / O unit 204, the host interface 206 can direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled to a scheduler 210 that is configured to distribute commands or other work items to an array of processing clusters 212. In one embodiment, the scheduler 210 ensures that the array of processing clusters 212 is properly configured and in an active state before tasks are distributed to the processing clusters of the array of processing clusters 212.

[0050] The array of processing clusters 212 can include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each cluster 214A - 214N of the array of processing clusters 212 can execute a large number of concurrent threads. The scheduler 210 can use various scheduling and / or work distribution algorithms to allocate work to the clusters 214A - 214N of the array of processing clusters 212, which can vary depending on the workload generated for each type of program or computation. Scheduling can be handled dynamically by the scheduler 210 or can be assisted in part by compiler logic during the compilation of the program logic configured to be executed by the array of processing clusters 212.

[0051] In one embodiment, different clusters 214A - 214N of the array of processing clusters 212 can be assigned to process different types of programs or to perform different types of computations.

[0052] The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, the processing cluster array 212 can include logic for performing processing tasks that include filtering video and / or audio data, and / or modeling operations (including physics operations), and performing data transformations.

[0053] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 can include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. Additionally, the processing cluster array 212 can be configured to execute graphics processing-related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 can transfer data from the system memory via the I / O unit 204 for processing. During processing, the transferred data can be stored in on-chip memory (e.g., the parallel processor memory 222) during processing and then written back to the system memory.

[0054] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to the multiple clusters 214A - 214N in the processing cluster array 212. In some embodiments, multiple portions of the processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A - 214N can be stored in a buffer to allow the transfer of the intermediate data between the clusters 214A - 214N for further processing.

[0055] During operation, the processing cluster array 212 can receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks can include commands and status parameters defining how the data is to be processed (e.g., what program is to be executed) and indices of the data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data). The scheduler 210 can be configured to obtain the indices corresponding to the tasks or can receive the indices from the front end 208. The front end 208 can be configured to ensure that the processing cluster array 212 is configured in an effective state before initiating the workload specified by the incoming command buffers (e.g., batch buffers, push buffers, etc.).

[0056] Each of one or more instances of the parallel processing units 202 can be coupled to the parallel processor memory 222. The parallel processor memory 222 can be accessed via the memory crossbar 216, which can receive memory requests from the processing cluster array 212 as well as the I / O unit 204. The memory crossbar 216 can access the parallel processor memory 222 via the memory interface 218. The memory interface 218 can include a plurality of partitioning units (e.g., partitioning unit 220A, partitioning unit 220B, up to partitioning unit 220N), which can each be coupled to a portion (e.g., a memory unit) of the parallel processor memory 222. In one implementation, the number of partitioning units 220A - 220N is configured to be equal to the number of memory units such that the first partitioning unit 220A has a corresponding first memory unit 224A, the second partitioning unit 220B has a corresponding memory unit 224B, and the Nth partitioning unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partitioning units 220A - 220N can be different from the number of memory devices.

[0057] In various embodiments, the memory units 224A - 224N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A - 224N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of the memory units 224A - 224N can vary and can be selected from one of various conventional designs. Render targets, such as frame buffers or texture maps, can be stored across the memory units 224A - 224N, allowing the partitioning units 220A - 220N to write multiple portions of each render target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 222. In some embodiments, a local instance of the parallel processor memory 222 can be excluded in favor of a unified memory design that utilizes system memory along with local cache memory.

[0058] In one embodiment, any one of the clusters 214A - 214N of the cluster array 212 of processing clusters can process data that is to be written to any one of the memory units 224A - 224N within the parallel processor memory 222. The memory crossbar 216 can be configured to transfer the output of each cluster 214A - 214N to any of the partitioning units 220A - 220N or to another cluster 214A - 214N, which can perform additional processing operations on the output. Each cluster 214A - 214N can communicate with the memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar 216 has connections to the memory interface 218 to communicate with the I / O unit 204 and to a local instance of the parallel processor memory 222, enabling processing units within different processing clusters 214A - 214N to communicate with system memory or other memory not local to the parallel processing unit 202. In one embodiment, the memory crossbar 216 can use virtual channels to separate the traffic flow between the clusters 214A - 214N and the partitioning units 220A - 220N.

[0059] Although a single instance of the parallel processing unit 202 is shown within the parallel processor 200, any number of instances of the parallel processing unit 202 may be included. For example, multiple instances of the parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of the parallel processing unit 202 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example and in one embodiment, some instances of the parallel processing unit 202 may include higher precision floating point units relative to other instances. Systems incorporating one or more instances of the parallel processing unit 202 or the parallel processor 200 may be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0060] Figure 2B is a block diagram of a partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is Figure 2A an instance of one of the partition units 220A - 220N. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. Read misses and urgent write-back requests are output from the L2 cache 221 to the frame buffer interface 225 for processing. Dirty updates may also be sent to the frame buffer via the frame buffer interface 225 for opportunistic processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory cells in the parallel processor memory (such as the memory cells 224A - 224N of FIG. 2 (e.g., within the parallel processor memory 222)).

[0061] In a graphics application, the ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, and the like. Subsequently, the ROP 226 outputs the processed graphics data stored in the graphics memory. In some embodiments, the ROP 226 includes compression logic for compressing z or color data written to the memory and decompressing z or color data read from the memory. In some embodiments, the ROP 226 is included within each processing cluster (e.g., clusters 214A - 214N of FIG. 2) rather than within the partition unit 220. In such embodiments, read and write requests for pixel data rather than pixel fragment data are transmitted through the memory crossbar 216.

[0062] The processed graphics data can be displayed on a display device (such as, Figure 1 one of the one or more display devices 110), routed for further processing by a processor 102 (one or more), or routed for further processing by Figure 2A one of the processing entities within the parallel processor 200.

[0063] Figure 2C is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A - 214N of FIG. 2. The processing cluster 214 can be configured to execute a number of threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific set of input data. In some embodiments, without providing multiple independent instruction units, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads. In other embodiments, a common instruction unit configured to issue instructions to a set of processing engines within each of the processing clusters is used, and single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads. Different from the SIMD execution regime (where all processing engines typically execute the same instruction), SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0064] The operation of the processing cluster 214 can be controlled via a pipeline manager 232, which distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within the processing cluster 214. The graphics multiprocessor 234 can process data, and a data crossbar 240 can be used to distribute the processed data to one of a number of possible destinations (including other shader units). The pipeline manager 232 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 240.

[0065] Each graphics multiprocessor 234 within processing cluster 214 can include the same set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). The functional execution logic can be configured in a pipelined manner, in which new instructions can be issued before previous instructions are completed. The functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, boolean operations, bit-shifting, and the calculation of various algebraic functions. In one embodiment, different operations can be performed using the same functional unit hardware, and any combination of functional units can exist.

[0066] Instructions transmitted to processing cluster 214 constitute a thread. A set of threads executed across a group of parallel processing engines is a thread group. The thread group executes the same program on different input data. Each thread within the thread group can be assigned to a different processing engine within graphics multiprocessor 234. The thread group can include fewer threads than the number of processing engines within graphics multiprocessor 234. When the thread group includes fewer threads than the number of processing engines, one or more of the processing engines can be idle during the cycle in which the thread group is being processed. The thread group can also include more threads than the number of processing engines within graphics multiprocessor 234. When the thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 234.

[0067] In one embodiment, graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, graphics multiprocessor 234 can forgo the internal cache and use the cache memory within processing cluster 214 (e.g., L1 cache 308). Each graphics multiprocessor 234 also has access to an L2 cache within a partition unit (e.g., partition units 220A - 220N of FIG. 2) that is shared among all processing clusters 214 and can be used to transfer data between threads. Graphics multiprocessor 234 also has access to off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 can be used as global memory. Embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share common instructions and data, which can be stored in L1 cache 308.

[0068] Each processing cluster 214 may include an MMU 245 (Memory Management Unit) configured to map virtual addresses into physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2. The MMU 245 includes: a set of page table entries (PTEs) for mapping virtual addresses of tiles (more discussion on tiling) into physical addresses; and optionally a cache line index. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. The physical addresses are processed to distribute surface data access locality, thereby allowing efficient request interleaving in the partitioning unit. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0069] In graphics and computing applications, the processing cluster 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. As needed, texture data is read from an internal texture L1 cache (not shown) or in some embodiments from the L1 cache within the graphics multiprocessor 234, and the texture data is fetched from the L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 234 outputs the processed tasks to the data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in the L2 cache, local parallel processor memory, or system memory via the memory crossbar 216. The preROP 242 (e.g., pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to the ROP unit, which may be co-located with a partitioning unit as described herein (e.g., the partitioning units 220A - 220N of FIG. 2). The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0070] It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within the processing cluster 214. Additionally, although only one processing cluster 214 is shown, the parallel processing unit as described herein may include any number of instances of the processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0071] Figure 2D FIG. 234 shows a graphics multiprocessor according to one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing units (GPGPUs) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to the cache memory 272 and the shared memory 270 via a memory and cache interconnect 268.

[0072] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched by the instruction unit 254 for execution. The instruction unit 254 may dispatch the instructions as thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions may access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 may be used to translate an address in the unified address space into a distinct memory address that can be accessed by the load / store unit 266.

[0073] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for the operands of the data paths of the functional units (e.g., GPGPU cores 262, load / store units 266) connected to the graphics multiprocessor 324. In one embodiment, the register file 258 is partitioned among each of the functional units such that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is partitioned among different warps executed by the graphics multiprocessor 324.

[0074] The GPGPU cores 262 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. According to an embodiment, the GPGPU cores 262 may be architecturally similar or may be architecturally different. For example and in one embodiment, a first portion of the GPGPU cores 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU cores includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or be capable of implementing variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units to perform specific functions (such as copy rectangle or pixel blend operations). In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0075] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU cores 262, whereby data transfers between the GPGPU cores 262 and the register file 258 are very low-latency. The shared memory 270 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a program-managed cache. Threads executing on the GPGPU cores 262 can programmatically store data in the shared memory other than the automatically cached data stored in the cache memory 272.

[0076] Figures 3A - 3B An additional graphics multiprocessor is shown according to an embodiment. The shown graphics multiprocessors 325, 350 are Figure 2C variants of the graphics multiprocessor 234. The shown graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of simultaneously executing a large number of execution threads.

[0077] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 is relative to Figure 2DThe graphics multiprocessor 234 includes multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A - 332B, register files 334A - 334B, and texture units 344A - 344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A - 336B, GPGPU cores 337A - 337B, GPGPU cores 338A - 338B) and multiple sets of load / store units 340A - 340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346. The various components may communicate via an interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbar switches to enable communication between the various components of the graphics multiprocessor 325.

[0078] Figure 3B FIG. shows a graphics multiprocessor 350 according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A - 356D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load / store units, as Figure 2D and Figure 3A shown. The execution resources 356A - 356D may work in concert with the texture units 360A - 360D for texture operations while sharing an instruction cache 354 and a shared memory 362. In one embodiment, the execution resources 356A - 356D may share the instruction cache 354 and the shared memory 362 as well as multiple instances of texture and / or data cache memories 358A - 358B. The various components may communicate via an interconnect structure 352 similar to Figure 3A the interconnect structure 327.

[0079] Those skilled in the art will understand that Figure 1 、 2A the architectures described in FIGS. - 2D and 3A - 3B are descriptive and not restrictive in the context of this embodiment. Thus, without departing from the scope of the embodiments described herein, the techniques described herein may be implemented on any properly configured processing unit, including but not limited to one or more mobile application processors, one or more desktop computer or server central processing units (CPUs) (including multi - core CPUs), one or more parallel processing units (such as the parallel processing unit 202 of FIG. 2), and one or more graphics processors or specialized processing units.

[0080] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0081] Techniques for GPU - to - Host Processor Interconnect

[0082] Figure 4A An exemplary architecture is shown where multiple GPUs 410 - 413 are communicatively coupled to multiple multi-core processors 405 - 406 via high-speed links 440 - 443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, depending on the implementation, the high-speed links 440 - 443 support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the fundamental principles of the present invention are not limited to any specific communication protocol or throughput.

[0083] Additionally, in one embodiment, two or more of the GPUs 410 - 413 are interconnected via high-speed links 444 - 445, which may be implemented using the same or a different protocol / link as that used for the high-speed links 440 - 443. Similarly, two or more of the multi-core processors 405 - 406 may be connected via a high-speed link 433, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A all communication between the various system components shown in may be achieved using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the fundamental principles of the present invention are not limited to any specific type of interconnect technology.

[0084] In one embodiment, each multi-core processor 405-406 is communicatively coupled to a processor memory 401-402 via a memory interconnect 430-431, respectively, and each GPU 410-413 is communicatively coupled to a GPU memory 420-423 via a GPU memory interconnect 450-453, respectively. The memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, the processor memories 401-402 and the GPU memories 420-423 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics double data rate SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0085] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to specific memories 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed across all of the individual physical memories. For example, each of the processor memories 401-402 may include 64GB of system memory address space, and each of the GPU memories 420-423 may include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0086] Figure 4B Additional details of the interconnect between a multi-core processor 407 and a graphics acceleration module 446 are shown in accordance with one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card that is coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or die as the processor 407.

[0087] The illustrated processor 407 includes multiple cores 460A - 460D, each having a translation lookaside buffer 461A - 461D and one or more caches 462A - 462D. The cores may include various other components for executing instructions and processing data (e.g., instruction fetch unit, branch prediction unit, decoder, execution unit, reorder buffer, etc.), and such other components are not shown to avoid obscuring the underlying principles of the present invention. The caches 462A - 462D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 426 may be included in the cache hierarchy and shared by multiple sets of cores 460A - 460D. For example, one embodiment of the processor 407 includes 24 cores, each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and the graphics accelerator integration module 446 are connected to the system memory 441, which may include processor memories 401 - 402.

[0088] Consistency of data and instructions stored in the various caches 462A - 462D, 456, and the system memory 441 is maintained through inter - core communication via the coherence bus 464. For example, each cache may have cache coherence logic / circuit associated therewith to communicate via the coherence bus 464 in response to a detected read or write to a specific cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 464 to snoop on cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the underlying principles of the present invention.

[0089] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the cores. Specifically, the interface 435 provides connectivity to the proxy circuit 425 via the high - speed link 440 (e.g., PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0090] In one implementation, the accelerator integrated circuit 436 represents multiple graphics processing engines 431, 432, N of the graphics acceleration module 446 to provide cache management, memory access, context management, and interrupt management services. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431 - 432, N, or the graphics processing engines 431 - 432, N may be individual GPUs integrated on a common package, line card, or chip.

[0091] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 to perform various memory management functions, such as virtual - to - physical memory translation (also known as effective - to - real memory translation) and a memory access protocol for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective - to - physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431 - 432, N. In one embodiment, the data stored in the cache 438 and the graphics memories 433 - 434, N is kept consistent with the core caches 462A - 462D, 456, and the system memory 411. As mentioned, this may be achieved via the proxy circuit 425, which represents the cache 438 and the memories 433 - 434, N to participate in the cache coherence mechanism (e.g., sending updates related to modifications / accesses of cache lines on the processor caches 462A - 462D, 456 to the cache 438, and receiving updates from the cache 438).

[0092] A set of registers 445 stores context data for threads to be executed by the graphics processing engines 431 - 432, N, and the context management circuit 448 manages thread contexts. For example, the context management circuit 448 may perform save and restore operations during context switching to save and restore the contexts of various threads (e.g., where the first thread is saved and the second thread is stored so that the second thread can be executed by the graphics processing engine). For example, during context switching, the context management circuit 448 may store the current register values into an area in memory (e.g., identified by a context pointer). Then, it may restore the register values when returning to the context. In one embodiment, the interrupt management circuit 447 receives and processes interrupts received from system devices.

[0093] In one implementation, the MMU 439 converts the virtual / valid addresses from the graphics processing engine 431 into real / physical addresses in the system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator modules 446 can be dedicated to a single application executing on the processor 407 or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented where the resources of the graphics processing engines 431 - 432, N are shared among multiple applications or virtual machines (VMs). The resources can be further divided into "slices" which are allocated to the VMs and / or applications based on the processing requirements and priorities associated with different VMs and / or applications.

[0094] Accordingly, the accelerator integrated circuit acts as a bridge to the system of the graphics accelerator modules 446 and provides address translation and system memory cache services. Additionally, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engine.

[0095] Since the hardware resources of the graphics processing engines 431 - 432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431 - 432, N such that they appear to the system as independent units.

[0096] As mentioned, in the illustrated embodiment, one or more graphics memories 433 - 434, M are coupled to each of the graphics processing engines 431 - 432, N respectively. The graphics memories 433 - 434, M store the instructions and data being processed by each of the graphics processing engines 431 - 432, N. The graphics memories 433 - 434, M can be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6) or HBM, and / or can be non-volatile memories such as 3D XPoint or Nano-Ram.

[0097] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that the data stored in graphics memories 433 - 434, M is the data that will be most frequently used by graphics processing engines 431 - 432, N and preferably not used (at least not frequently) by cores 460A - 460D. Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not by graphics processing engines 431 - 432, N) in system memory 411 and in caches 462A - 462D, 456 of the cores.

[0098] Figure 4C Another embodiment is shown where accelerator integrated circuit 436 is integrated within processor 407. In this embodiment, graphics processing engines 431 - 432, N communicate directly via interface 437 and interface 435 (again, which may utilize any form of bus or interface protocol) to accelerator integrated circuit 436 over high - speed link 440. Accelerator integrated circuit 436 may perform the same operations as those described with respect to Figure 4B but potentially at a higher throughput considering its close proximity to coherence bus 462 and caches 462A - 462D, 426.

[0099] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0100] In one embodiment of the dedicated process model, graphics processing engines 431 - 432, N are dedicated to a single application or process under a single operating system. A single application may funnel requests from another application to graphics engines 431 - 432, N, thereby providing virtualization within a VM / partition.

[0101] In the dedicated process programming model, graphics processing engines 431 - 432, N may be shared by multiple VM / application partitions. The shared model requires a hypervisor to virtualize graphics processing engines 431 - 432, N to allow access by each operating system. For a non - hypervisor single - partition system, graphics processing engines 431 - 432, N are owned by the operating system. In both cases, the operating system may virtualize graphics processing engines 431 - 432, N to provide access to each process or application.

[0102] For a shared programming model, the graphics acceleration module 446 or individual graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, the process element is stored in the system memory 411 and is addressable using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 431-432, N (i.e., calling system software to add the process element to a linked list of process elements). The lower 16 bits of the process handle can be the offset of the process element within the linked list of process elements.

[0103] Figure 4D An exemplary accelerator integration slice 490 is shown. As used herein, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process elements 483 are stored in response to a GPU call 481 from an application 480 executing on the processor 407. The process elements 483 contain the process state of the corresponding application 480. The work descriptor (WD) 484 contained within the process element 483 can be a single job requested by the application or can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to a job request queue within the address space 482 of the application.

[0104] The graphics acceleration module 446 and / or individual graphics processing engines 431-432, N can be shared by all processes or a subset of processes in the system. Embodiments of the present invention include infrastructure for setting the process state and sending the WD 484 to the graphics acceleration module 446 to start a job in a virtualized environment.

[0105] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 446 or an individual graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, when the graphics acceleration module 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition and the operating system initializes the accelerator integrated circuit 436 for the owning process.

[0106] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of work to be completed by one of the graphics processing engines of the graphics acceleration module 446. Data from the WD 484 can be stored in the register 445 and used by the MMU 439, interrupt management circuit 447, and / or context management circuit 446 as shown. For example, one embodiment of the MMU 439 includes a segment / page walk circuitry for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process the interrupt event 492 received from the graphics acceleration module 446. When performing a graphics operation, the MMU 439 converts the effective address 493 generated by the graphics processing engines 431 - 432, N into a real address.

[0107] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431 - 432, N and / or graphics acceleration module 446, and it can be initialized by the hypervisor or the operating system. Each of these replicated registers can be included in the accelerator integrated slice 490. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0108] Table 1 - Registers Initialized by the Hypervisor

[0109] 1 Slice Control Register 2 Real Address (RA) Scheduled Process Region Pointer 3 Permission Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0110] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0111] Table 2 - Registers Initialized by the Operating System

[0112] 1 Process and Thread Identification 2 Effective Address (EA) Context Save / Recovery Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Permission Mask 6 Work Descriptor

[0113] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431 - 432, N. It contains all the information required for the graphics processing engines 431 - 432, N to complete their work, or it can be a pointer to a memory location in a command queue where the application has set up work to be done.

[0114] Figure 4E Additional details of one embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 498 in which a list of process elements 499 is stored. The hypervisor real address space 498 can be accessed via the hypervisor 496, which virtualizes the graphics acceleration module engine for the operating system 495.

[0115] The shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time slice sharing and graphics directed shared.

[0116] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. To enable the graphics acceleration module 446 to support virtualization by the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) The job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 is guaranteed to complete the job requests of the application (including any translation faults) within a specified amount of time, or the graphics acceleration module 446 provides the ability to handle preempted jobs. 3) When operating in the directed sharing programming model, fairness of the graphics acceleration module 446 among processes must be guaranteed.

[0117] In one embodiment, for the shared model, the application 480 needs to make an operating system 495 system call with the graphics acceleration module 446 type, work descriptor (WD), permission mask register (AMR) value, and context save / restore area pointer (CSRP). The graphics acceleration module 446 type describes the acceleration function targeted for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can be in the form of a graphics acceleration module 446 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure used to describe the work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implementation do not support the user authority mask override register (UAMOR), then the operating system may apply the current UAMOR value to the AMR value and then pass the AMR in the hypervisor call. Optionally, the hypervisor 496 may apply the current authority mask override register (AMOR) value and then place the AMR in the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the valid address of a region in the application's address space 482 for the graphics acceleration module 446 to save and restore the context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore area can be pinned system memory.

[0118] Upon receiving a system call, the operating system 495 may verify that the application 480 is registered and has been granted permission to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 with the information shown in Table 3.

[0119] Table 3 – OS to hypervisor call parameters

[0120] 1 Work Descriptor (WD) 2 Permission Mask Register (AMR) Value (Potentially Masked) 3 Effective Address (EA) Context Save / Recovery Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0121] Upon receiving a hypervisor call, the hypervisor 496 verifies that the operating system 495 is registered and has been granted permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into the linked list of process elements of the corresponding graphics acceleration module 446 type. The process element may include the information shown in Table 4.

[0122] Table 4 - Process element information

[0123] 1 Work Descriptor (WD) 2 Permission Mask Register (AMR) Value (Potentially Masked) 3 Effective Address (EA) Context Save / Recovery Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table Derived from Hypervisor Call Parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0124] In one embodiment, the hypervisor initializes the registers 445 of the plurality of accelerator integrated slices 490.

[0125] As Figure 4F shown, one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing the physical processor memories 401 - 402 and the GPU memories 420 - 423. In such an implementation, operations executed on the GPUs 410 - 413 utilize the same virtual / effective memory address space to access the processor memories 401 - 402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 401, a second portion is allocated to the second processor memory 402, a third portion is allocated to the GPU memory 420, and so on. Thus, the entire virtual / effective memory space (sometimes referred to as the effective address space) is distributed across each of the processor memories 401 - 402 and the GPU memories 420 - 423, allowing any processor or GPU to access any physical memory (using the virtual address mapped to that memory).

[0126] In one embodiment, the bias / coherency management circuits 494A - 494E within one or more of the MMUs 439A - 439E ensure cache coherency between the host processor (e.g., 405) and the caches of the GPUs 410 - 413, as well as a bias technique for indicating the physical memory in which certain types of data should be stored. Although Figure 4FMultiple instances of bias / coherence management circuits 494A - 494E are shown, but the bias / coherence circuits may be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0127] One embodiment allows the use of shared virtual memory (SVM) technology to access GPU - attached memories 420 - 423 and map them as part of the system memory without suffering the typical performance penalties associated with full system cache coherence. The ability to access GPU - attached memories 420 - 423 as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access computed results without the overhead of traditional I / O DMA data copies. Such traditional copies involve driver calls, interrupts, and memory - mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access GPU - attached memories 420 - 423 without cache coherence overhead can be critical to the runtime of offloaded computations. In the case of substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410 - 413. The efficiency of operand setting, result access, and GPU computation all play a role in determining the effectiveness of GPU offloading.

[0128] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. A bias table may be used, for example, which can be a page - granularity structure (i.e., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU - attached memory page. The bias table may be implemented in the stolen memory ranges of one or more GPU - attached memories 420 - 423, with or without a bias cache in GPUs 410 - 413 (e.g., for caching frequently / most recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0129] In one implementation, the bias table entries associated with each access to the GPU-attached memories 420-423 are accessed before actually accessing the GPU memory, thus causing the following operations. First, local requests from the GPUs 410-413 to find their pages in the host bias are directly forwarded to the corresponding GPU memories 420-423. Local requests from the GPUs are forwarded to the processor 405 (e.g., via the high-speed link as discussed above). In one embodiment, a request from the processor 405 (which looks for the requested page in the host processor bias) completes a request similar to a normal memory read. Alternatively, a request for a page in the GPU bias can be forwarded to the GPUs 410-413. Then, if the GPU is not currently using the page, the GPU can transition the page to the host processor bias.

[0130] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or a purely hardware-based mechanism for a limited set of cases.

[0131] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the device driver of the GPU, which in turn sends a message (or enqueues a command descriptor) to the GPU, thereby instructing it to change the bias state and perform a cache dump flush operation in the host for some transitions. The cache dump flush operation is required for transitioning from the host processor 405 bias to the GPU bias, but not for the reverse transition.

[0132] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that are not cacheable by the host processor 405. To access these pages, the processor 405 can request access from the GPU 410, which may or may not immediately grant access depending on the implementation. Thus, to reduce communication between the processor 405 and the GPU 410, ensure that the GPU bias pages are those that are needed by the GPU but not by the host processor 405 and vice versa.

[0133] Graphics Processing Pipeline

[0134] Figure 5 Illustrates a graphics processing pipeline 500 according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included within a parallel processing subsystem as described herein (such as the parallel processor 200 of FIG. 2), which in one embodiment is Figure 1Variants of the (one or more) parallel processors 112. Various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., the parallel processing unit 202 of FIG. 2) as described herein. For example, shader units (e.g., the graphics multiprocessor 234 of FIG. 3) may be configured to perform the functions of one or more of the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines and corresponding partitioning units (e.g., the partitioning units 220A-220N of FIG. 2) within a processing cluster (e.g., the processing cluster 214 of FIG. 3). The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., the parallel processor memory 222 of FIG. 2) via a memory interface 528, which may be an instance of the memory interface 218 of FIG. 2.

[0135] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to light and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for use in processing the vertex data, and the vertex processing unit 504 may be programmed to transform the vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0136] A first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads stored vertex attributes as needed and constructs graphics primitives for processing by the tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0137] The tessellation control processing unit 508 treats the input vertices as control points for geometric patches. The control points are transformed from an input representation from a patch (e.g., the basis of the patch) to a representation suitable for use by the tessellation evaluation processing unit 512 in surface evaluation. The tessellation control processing unit 508 may also compute tessellation factors for the edges of the geometric patch. The tessellation factors are applied to individual edges and quantify the view-dependent level of detail associated with that edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and to tessellate the patch surface into a plurality of geometric primitives such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0138] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphics primitive into one or more new graphics primitives and to compute parameters for rasterizing the new graphics primitives.

[0139] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs the parameters and vertices specifying the new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scale, cull, and clip unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing geometric data. The viewport scale, cull, and clip unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522. The rasterizer 522 may perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on the new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The rasterizer 522 performs scan conversion on the new graphics primitives and outputs the fragments and coverage data to the fragment / pixel processing unit 524.

[0140] The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations such as, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels output to the raster operations unit 526. The fragment / pixel processing unit 524 can read data stored in the parallel processor memory or the system memory for use in processing fragment data. The fragment or pixel shader program can be configured to shade at the sample, pixel, tile, or other granularity depending on the sampling rate configured for the processing unit.

[0141] The raster operations unit 526 is a processing unit that performs raster operations including, but not limited to, stencil printing, z-testing, blending, and the like, and outputs pixel data as processed graphics data to be stored in a graphics memory (e.g., the parallel processor memory 222 as in Figure 1 ), for display on the one or more display devices 110, or for further processing by one of the (one or more) parallel processors 112 or the one or more processors 102. In some embodiments, the raster operations unit 526 is configured to compress z or color data written to the memory and decompress z or color data read from the memory.

[0142] Figure 6 An embodiment of a computing device 600 employing a sparse matrix processing mechanism is shown. The computing device 600 (e.g., a smart wearable device, a virtual reality (VR) device, a head-mounted display (HMD), a mobile computer, an Internet of Things (IoT) device, a laptop computer, a desktop computer, a server computer, etc.) can be the same as Figure 1 the data processing system 100, and thus, for the sake of brevity, clarity, and ease of understanding, many of the details described above with reference to Figures 1 - 5 are not further discussed or repeated below. As shown, in one embodiment, the computing device 600 is shown as a host sparse matrix processing mechanism 610.

[0143] As shown, in one embodiment, the sparse matrix processing mechanism 610 may be hosted by the GPU 614. However, in other embodiments, the sparse matrix processing mechanism 610 may be hosted in the graphics driver 616. In still other embodiments, the sparse matrix processing mechanism 610 may be hosted by, or be part of, the firmware of the central processing unit (“CPU” or “application processor”) 612. For simplicity, clarity, and ease of understanding, throughout the remainder of this document, the sparse matrix processing mechanism 610 may be discussed as part of the graphics driver 616; however, the embodiments are not limited thereto.

[0144] In yet another embodiment, the sparse matrix processing mechanism 610 may be hosted by the operating system 606 as software or firmware logic. In yet a further embodiment, the sparse matrix processing mechanism 610 may be hosted in part and simultaneously by multiple components of the computing device 600, such as one or more of the graphics driver 616, GPU 614, GPU firmware, CPU 612, CPU firmware, operating system 606, and / or the like. It is contemplated that the sparse matrix processing mechanism 610, or one or more of its components, may be implemented as hardware, software, and / or firmware.

[0145] Throughout this document, the term “user” may be referred to interchangeably as “viewer”, “observer”, “person”, “individual”, “end user”, and / or the like. Note that throughout this document, terms such as “graphics domain” may be referred to interchangeably with “graphics processing unit”, “graphics processor”, or simply “GPU” for short, and similarly, “CPU domain” or “host domain” may be referred to interchangeably with “computer processing unit”, “application processor”, or simply “CPU” for short.

[0146] The computing device 600 may include any number and type of communication devices, such as large computing systems (such as, server computers, desktop computers, etc.), and may further include set-top boxes (e.g., Internet-based cable TV set-top boxes, etc.), global positioning system (GPS)-based devices, etc. The computing device 600 may include mobile computing devices that serve as communication devices, such as cellular phones including smart phones, personal digital assistants (PDAs), tablet computers, laptop computers, e-readers, smart TVs, TV platforms, wearable devices (such as glasses, watches, bracelets, smart cards, jewelry, clothing items, etc.), media players, etc. For example, in one embodiment, the computing device 600 may include a mobile computing device that employs a computer platform that masters an integrated circuit (IC) such as a system on a chip (“SoC” or “SOC”), where the integrated circuit integrates various hardware and / or software components of the computing device 600 on a single chip.

[0147] As shown, in one embodiment, the computing device 600 may include any number and type of hardware and / or software components, such as (but not limited to) GPU 614, a graphics driver (also referred to as “GPU driver”, “graphics driver logic”, “driver logic”, user mode driver (UMD), UMD, user mode driver framework (UMDF), UMDF, or simply “driver”) 616, CPU 612, memory 608, network devices, drivers, etc., and input / output (I / O) sources 604 such as touchscreens, touch panels, touch pads, virtual or regular keyboards, virtual or regular mice, ports, connectors, etc.

[0148] The computing device 600 may include an operating system (OS) 606 that serves as an interface between the hardware and / or physical resources of the computing device 600 and the user. It is contemplated that the CPU 612 may include one or more processors, such as Figure 1 the (one or more) processors 102, and the GPU 614 may include one or more graphics processors (or multi-processors).

[0149] Note that throughout this document, terms such as “node”, “computing node”, “server”, “server device”, “cloud computer”, “cloud server”, “cloud server computer”, “machine”, “host machine”, “device”, “computing device”, “computer”, “computing system” and the like may be used interchangeably. Further note that throughout this document, terms such as “application”, “software application”, “program”, “software program”, “package”, “software package” and the like may be used interchangeably. Similarly, throughout this document, terms such as “job”, “input”, “request”, “message” and the like may be used interchangeably.

[0150] Contemplated and as described in reference Figures 1 - 5 As further described above, certain processes of the graphics pipeline described above are implemented in software, while the rest are implemented in hardware. The graphics pipeline can be implemented in a graphics co-processor design, where the CPU 612 is designed to work with a GPU 614 that can be included in or co-located with the CPU 612. In one embodiment, the GPU 614 can employ any number and type of conventional software and hardware logic for performing conventional functions related to graphics rendering, as well as novel software and hardware logic for performing any number and type of instructions.

[0151] As mentioned previously, the memory 608 can include a random access memory (RAM) containing an application database that has object information. A memory controller hub (such as, Figure 1 the memory hub 105) can access the data in the RAM and forward it to the GPU 614 for graphics pipeline processing. The RAM can include double data rate RAM (DDR RAM), extended data output RAM (EDO RAM), etc. The CPU 612 interacts with the hardware graphics pipeline to share graphics pipeline functionality.

[0152] The processed data is stored in a buffer in the hardware graphics pipeline, and the status information is stored in the memory 608. The resulting image is then transferred to an I / O source 604, such as a display component for displaying the image. It is contemplated that the display device can be of various types, such as a cathode ray tube (CRT), thin film transistor (TFT), liquid crystal display (LCD), organic light emitting diode (OLED) array, etc., to display information to the user.

[0153] The memory 608 includes a pre-allocated buffer (e.g., frame buffer) area; however, those of ordinary skill in the art should understand that the embodiments are not limited thereto, and any memory accessible to the lower graphics pipeline can be used. The computing device 600 can further include an input / output (I / O) control hub (ICH) 107 as cited in Figure 1 as one or more I / O sources 604, etc.

[0154] The CPU 612 may include one or more processors for executing instructions to perform whatever software routines are implemented by the computing system. The instructions frequently involve a certain class of operations performed on data. Both the data and the instructions may be stored in the system memory 608 and any associated caches. Caches are typically designed to have a shorter latency than the system memory 608; for example, a cache may be integrated onto the same (one or more) silicon chip(s) as the (one or more) processors, and / or constructed with faster static RAM (SRAM) cells, while the system memory 608 may be constructed with slower dynamic RAM (DRAM) cells. By tending to store more frequently used instructions and data in the cache rather than in the system memory 608, the overall performance efficiency of the computing device 600 is improved. It is contemplated that, in some embodiments, the GPU 614 may exist as part of the CPU 612 (such as, part of a physical CPU package), in which case the memory 608 may be shared by the CPU 612 and the GPU 614 or kept separate.

[0155] The system memory 608 may be made available to other components within the computing device 600. For example, in the implementation of a software program, any data (such as, input graphics data) received from various interfaces of the computing device 600 (e.g., keyboard and mouse, printer port, local area network (LAN) port, modem port, etc.) or retrieved from an internal storage element of the computing device 600 (e.g., hard drive) is often temporarily queued in the system memory 608 before being operated on by one or more processors. Similarly, data determined by a software program to be sent from the computing device 600 to an external entity via one of the computing system interfaces or to be stored in an internal storage element is often temporarily queued in the system memory 608 before it is sent or stored.

[0156] Further, for example, the ICH may be used to ensure proper transfer of such data between the system memory 608 and its appropriate corresponding computing system interfaces (and internal storage devices, if the computing system is so designed), and may have a bi-directional point-to-point link between itself and the observed I / O source / device 604. Similarly, the MCH may be used to manage various contention requests for access to the system memory 608 between the CPU 612 and the GPU 614, the interfaces, and the internal storage elements, which requests may occur closely in time to each other.

[0157] The I / O source 604 may include one or more I / O devices that are implemented to transfer data to / from the computing device 600 (e.g., a network adapter); or, for large-scale non-volatile storage devices, to transfer data within the computing device 600 (e.g., a hard disk drive). A user input device including alphanumeric and other keys may be used to pass information and command selections to the GPU 614. Another type of user input device is a cursor control (such as a mouse, trackball, touch screen, touchpad, or cursor direction keys) for passing direction information and command selections to the GPU 614 and for controlling the movement of the cursor on the display device. The camera and microphone array of the computer device 600 may be used to observe poses, record audio and video, and receive and transmit visual and audio commands.

[0158] The computing device 600 may further include one or more network interfaces for providing access to networks such as a LAN, a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN), Bluetooth, a cloud network, a mobile network (e.g., third generation (3G), fourth generation (4G), etc.), an intranet, the Internet, etc. The one or more network interfaces may include, for example, a wireless network interface having an antenna (which may represent one or more antennas). The one or more network interfaces may also include, for example, a wired network interface for communicating with a remote device via a network cable, which may be, for example, an Ethernet cable, a coaxial cable, an optical fiber cable, a serial cable, or a parallel cable.

[0159] The one or more network interfaces may provide access to a LAN, for example, by conforming to the IEEE 802.11b and / or IEEE 802.11g standards, and / or the wireless network interface may provide access to a personal area network, for example, by conforming to the Bluetooth standard. Other wireless network interfaces and / or protocols may also be supported, including previous and subsequent versions of the standards. In addition to, or instead of, communicating via the wireless LAN standard, the one or more network interfaces may also provide wireless communication using, for example, a time division multiple access (TDMA) protocol, a global system for mobile communications (GSM) protocol, a code division multiple access (CDMA) protocol, and / or any other type of wireless communication protocol.

[0160] The one or more network interfaces may include one or more communication interfaces, such as a modem, a network interface card, or other well-known interface devices, such as those for coupling to an Ethernet, a token ring network, or other types of physical wired or wireless attachments designed to provide, for example, a communication link supporting a LAN or a WAN. In this way, the computer system may also be coupled to multiple peripheral devices, clients, control surfaces, consoles, or servers via a conventional network architecture, including, for example, an intranet or the Internet.

[0161] It should be appreciated that for some implementations, systems with fewer or more components than the examples described above may be preferred. Thus, depending on numerous factors such as price constraints, performance requirements, technological improvements, or other circumstances, the configuration of computing device 600 may vary between implementations. Examples of electronic devices or computer systems 600 may include (but are not limited to), mobile devices, personal digital assistants, mobile computing devices, smart phones, cellular phones, handheld devices, one-way pagers, two-way pagers, messaging devices, computers, personal computers (PCs), desktop computers, laptop computers, notebook computers, handheld computers, tablet computers, servers, server arrays, or server farms, web servers, network servers, Internet servers, workstations, minicomputers, mainframe computers, supercomputers, network appliances, web appliances, distributed computing systems, multiprocessor systems, processor-based systems, consumer electronics, programmable consumer electronics, televisions, digital televisions, set-top boxes, wireless access points, base stations, subscriber stations, mobile subscriber centers, radio network controllers, routers, hubs, gateways, bridges, switches, machines, or combinations thereof.

[0162] Embodiments may be implemented as any one or combination of the following: one or more microchips or integrated circuits interconnected using a motherboard, hardwired logic, software stored in a memory device and executed by a microprocessor, firmware, application specific integrated circuits (ASICs), and / or field programmable gate arrays (FPGAs). The term "logic" may include, by way of example, software or hardware and / or a combination of software and hardware.

[0163] Embodiments may be provided, for example, as a computer program product that may include one or more machine-readable media having machine-executable instructions stored thereon. When these machine-executable instructions are executed by one or more machines such as a computer, a network of computers, or other electronic devices, these instructions may cause the one or more machines to perform operations in accordance with the embodiments described herein. Machine-readable media may include, but are not limited to, floppy disks, optical disks, CD-ROMs (compact disk - read only memory), and magneto-optical disks, ROMs, RAMs, EPROMs (erasable programmable read only memories), EEPROMs (electrically erasable programmable read only memories), magnetic or optical cards, flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions.

[0164] In addition, an embodiment can be downloaded as a computer program product, wherein the program can be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem and / or network connection) by one or more data signals embodied in and / or modulated by a carrier wave or other propagation medium.

[0165] Sparse matrix multiplication operations are important in various applications that include neural networks. A sparse matrix is a matrix in which most of the elements are zero (or some other mathematically irrelevant value). Sparse matrices are often the result of received image data that indicates that an image contains uninteresting information. Matrix multiplication typically uses a blocked approach to perform, as Figure 7A shown. Thus, traditional GPUs take two input matrix frames as input and produce an output matrix frame. However, when operating on a sparse matrix, most of these input frames contain zero values, which do not contribute to the cumulative result in the output matrix (e.g., multiplication by zero produces zero). According to one embodiment, the sparse matrix processing mechanism 610 includes a scheduler 613 that dynamically identifies operands having zero values in the matrix being processed.

[0166] Figure 7B An embodiment showing such a scheduler 613 included within a GPU processing element 700 is shown. As Figure 7B shown, the processing element 700 includes logic 701 for reading operands included in received instructions. A computing unit 702 and write result logic 703 are also included. In one embodiment, the scheduler 613 detects and identifies the memory locations of operands having zero values. In such embodiments, when an instruction is received by the GPU 614, the scheduler 613 retrieves the stored operand values from memory (or cache).

[0167] Once retrieved, a determination is made as to whether the operand value is zero. Once it is determined that the operand value is zero, the scheduler 613 blocks the multiplication scheduling of those operands in the multiplication unit 702. Thus, only non-zero operands are scheduled and processed in the computing unit 702, and zero values are written by the scheduler 703 to the write result logic 703 for zero operands. Although shown as resident within the logic 701, other embodiments may feature a scheduler 703 external to the logic 701.

[0168] In a further embodiment, the sparse matrix processing mechanism 610 further includes a sparse pattern tracker 615 that is used to detect one or more sparse data segments (e.g., sparsity patterns) within a stored data block and use the patterns to convert potential dense matrix computations into sparse computations. In one embodiment, the sparse pattern tracker 615 detects sparsity patterns in data (e.g., image data) stored in memory / cache.

[0169] Future deep learning systems are expected to store billions of images to be processed. Typically, an image can be broken down into segments depicting useful versus unimportant information. For example, if half of an image is empty, this information may be tracked at the memory level (e.g., via a memory controller), at the page level (in the OS), or at the cache hierarchy level. This information is useful during the execution of an application to eliminate performing computational operations on unimportant (or sparse) empty segments.

[0170] Figure 7C An embodiment of a sparse pattern tracker 615 is shown, which includes pattern recognition logic 708 and sparse segment (or segment logic) 709. According to one embodiment, the pattern recognition logic 708 performs a bounding box operation on data blocks by paging through image data stored in memory to determine the similarity of various segments within the data blocks. Data segments within a bounding box having the same value can be considered sparse data.

[0171] In one embodiment, the pattern recognition logic 708 coordinates with the memory controller to track data stored in the memory device. In other embodiments, the pattern recognition logic 708 tracks information at the cache hierarchy level. In still other embodiments, the pattern recognition logic 708 tracks information at the page table level via the OS 606. In a further embodiment, the pattern recognition logic 708 can be implemented to parse large amounts of dense data to determine segments that can be processed as sparse operations. As a result, the segment logic 709 records the address locations of the sparse segments identified by the pattern recognition logic 708. In one embodiment, the sparse segment 709 includes a pointer to the sparse segment component. As discussed above, matrix multiplication for sparse operations can be bypassed, thereby reducing the processing load on the GPU 614.

[0172] In still further embodiments, the sparse matrix processing mechanism 610 includes compression logic 617, which is used to compress a sparse matrix. In such embodiments, a compressed sparse matrix representation is dynamically generated based on a sparsity exponent (e.g., defined by the % of non - zero entries in the matrix). In this embodiment, a compressed format of the sparse matrix can be represented using non - zero values pointed to by row and column exponents.

[0173] According to one embodiment, the compression logic 617 receives the sparse segments defined by the pattern recognition logic 708 and determines whether the data meets a pre - determined threshold to be considered sparse. For example, when it is determined that Y number of entries within an MxN matrix are zero values, the matrix can be considered sparse. The compression logic 617 compresses the matrix determined to be sparse and stores the compressed matrix in a sparse compression buffer for execution on the GPU 614.

[0174] Figure 7D Shows an embodiment of a GPU 614 that includes a sparse compression buffer 712 and a plurality of execution units (EUs) 710. In one embodiment, the sparse compression buffer 712 includes compressed sparse matrix storage entries 712(0)-712(n) processed by the EUs 710. In such embodiments, the compression logic 717 stores frequently used sparse matrices. Prior to being processed by the EUs 710, the compression logic 617 decompresses the compressed matrix back into its original format. In one embodiment, the same compressed matrix can be used by all of the EUs 710 for the threads to be executed. However, in other embodiments, each EU 710 can use a unique sparse matrix for computation. Thus, frequently accessed sparse matrices are stored locally and read to avoid transferring data from the cache via a long interconnect.

[0175] The GPU 614 can be implemented to perform other deep learning operations. For example, the GPU 614 can perform layer processing of a neural network. A pattern frequently executed in almost all deep neural networks is that a convolutional (C) layer follows a bias (B) layer, followed by a rectified linear unit (ReLu (R)) layer, and then a pooling (P) layer. Most systems today execute these layers one after another (e.g., on a GPU, C, B, R, and P are mapped to individual kernels), or are mapped as two separate kernels as fused CBR followed by P.

[0176] In both scenarios, more than one kernel call is required; thus incurring additional data transfer overhead. According to one embodiment, the GPU 614 is configured such that the EUs are partitioned and assigned to perform certain functions, and intermediate results are forwarded between them to achieve high throughput. Figure 7E Shows an embodiment of a GPU 614 with partitioned EUs 720.

[0177] As Figure 7E shown, the EUs 720(1)-720(10) are assigned to execute convolutional layer threads, while the EUs 720(11)-720(13), EUs 720(14)-720(16), and EUs 720(17)-720(19) execute bias, ReLu, and pooling layer thread executions, respectively. Further, data is forwarded between the layer EUs 720. For example, by setting up a pipeline, data from C can be pushed into the cache hierarchy of B as soon as it is completed.

[0178] According to one embodiment, the partitioning and allocation of EU 720 can be established in advance based on domain knowledge. In such embodiments, the computing mechanism EU 720 can be statically partitioned such that the EU allocation remains the same during the lifetime of a particular application. In other embodiments, EU 720 can be optimally partitioned for each call executed by GPU 614. In still other embodiments, the configuration can be dynamic such that it changes by thread group during dispatch. In still further embodiments, by determining common patterns and setting up a pipeline, partitioning can be achieved to perform the processing of other types of neural network layers (other than C, B, R, and P layers) to execute them faster on the GPU rather than executing them individually.

[0179] Machine Learning Overview

[0180] A machine learning algorithm is an algorithm that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, an image recognition algorithm can be used to determine which of several categories a given input belongs to; a regression algorithm can output a numerical value given an input; and a pattern recognition algorithm can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0181] One example type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph where nodes are arranged in layers. Generally, a feedforward network topology includes an input layer and an output layer, which are separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating an output in the output layer. The network nodes are fully connected to the nodes in the adjacent layer via edges, but there are no edges between the nodes within each layer. The data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function that calculates the state of the nodes in each successive layer of the network based on coefficients ("weights"), which are respectively associated with each of the edges connecting the layers. Depending on the particular model represented by the algorithm being executed, the output from a neural network algorithm can take various forms.

[0182] Before a machine learning algorithm can be used to model a particular problem, a training data set is used to train the algorithm. Training a neural network involves selecting a network topology, using a set of training data that represents the problem being modeled by the network, and adjusting the weights until the network model exhibits minimal error for all instances of the training data set. For example, during the supervised learning training process for a neural network, the output produced by the network in response to an input representing an instance in the training data set is compared with the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is computed, and the weights associated with the connections are adjusted to minimize the error as the error signal is propagated backward through the layers of the network. When the error for each output generated from an instance of the training data set is minimized, the network is considered to be "trained".

[0183] The accuracy of machine learning algorithms can be significantly affected by the quality of the data sets used to train the algorithms. The training process can be computationally intensive and may require a large amount of time on a conventional general-purpose processor. Accordingly, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks because the computations performed when adjusting the coefficients in a neural network inherently lend themselves to parallel implementation. Specifically, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general-purpose graphics processing devices.

[0184] Figure 8 is a generalized diagram of a machine learning software stack 800. A machine learning application 802 can be configured to train a neural network using a training data set or to implement machine intelligence using a trained deep neural network. The machine learning application 802 can include specialized software that can be used to train a neural network before deployment and / or the training and inference capabilities of a neural network. The machine learning application 802 can implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0185] Hardware acceleration for machine learning applications 802 can be enabled via a machine learning framework 804. The machine learning framework 804 can provide a machine learning primitive library. Machine learning primitives are the basic operations that machine learning algorithms typically perform. In the absence of the machine learning framework 804, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithms and then re-optimize that computational logic when a new parallel processor is developed. In contrast, machine learning applications can be configured to perform the necessary computations using primitives provided by the machine learning framework 804. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed when training a convolutional neural network (CNN). The machine learning framework 804 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations.

[0186] The machine learning framework 804 can process input data received from the machine learning application 802 and generate appropriate inputs to a compute framework 806. The compute framework 806 can abstract the basic instructions provided to a GPGPU driver 808 such that the machine learning framework 804 can utilize hardware acceleration via the GPGPU hardware 810 without requiring the machine learning framework 804 to be very familiar with the architecture of the GPGPU hardware 810. Additionally, the compute framework 806 can enable hardware acceleration for the machine learning framework 804 across multiple types and generations of GPGPU hardware 810.

[0187] GPGPU Machine Learning Acceleration

[0188] Figure 9 A highly parallel general-purpose graphics processing unit 900 according to an embodiment is illustrated. In one embodiment, the general-purpose processing unit (GPGPU) 900 can be configured to be particularly efficient when processing computational workloads of the type associated with training deep neural networks. Additionally, the GPGPU 900 can be directly linked to other instances of GPGPUs to create a multi-GPU cluster to improve the training speed of particularly deep neural networks.

[0189] The GPGPU 900 includes a host interface 902 for enabling connection to a host processor. In one embodiment, the host interface 902 is a PCI Express interface. However, the host interface can also be a vendor-specific communication interface or communication fabric. The GPGPU 900 receives commands from the host processor and distributes execution threads associated with those commands to a group of compute clusters 906A-H using a global scheduler 904. The compute clusters 906A-H share a cache memory 908. The cache memory 908 can act as a cache within the cache memories in the compute clusters 906A-H.

[0190] The GPGPU 900 includes memories 914A-B that are coupled to the compute clusters 906A-H via a set of memory controllers 912A-B. In various embodiments, the memories 914A-B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory cells 224A-224N can further include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0191] In one embodiment, each compute cluster GPLAB06A-H includes a set of graphics multiprocessors, such as Figure 4A the graphics multiprocessor 400. The graphics multiprocessors of the compute clusters include multiple types of integer and floating-point logic units that can perform computational operations at a range of precisions, including precisions suitable for machine learning computations. For example and in one embodiment, at least one subset of the floating-point units in each of the compute clusters 906A-H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0192] Multiple instances of the GPGPU 900 can be configured to operate as compute clusters. The communication mechanisms used by the compute clusters for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of the GPGPU 900 communicate via the host interface 902. In one embodiment, the GPGPU 900 includes an I / O hub 909 that couples the GPGPU 900 to the GPU link 910, which enables a direct connection to other instances of the GPGPU. In one embodiment, the GPU link 910 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGPU 900. In one embodiment, the GPU link 910 is coupled to a high-speed interconnect to transfer data to and receive data from other GPGPUs or parallel processors. In one embodiment, multiple instances of the GPGPU 900 are located in separate data processing systems and communicate via a network device that can be accessed via the host interface 902. In one embodiment, in addition to or as an alternative to the host interface 902, the GPU link 910 can be configured to enable a connection to a host processor.

[0193] While the illustrated configuration of the GPGPU 900 can be configured to train neural networks, one embodiment provides an alternative configuration of the GPGPU 900 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, the GPGPU 900 includes fewer compute clusters 906A-H relative to the training configuration. Additionally, the memory technology associated with memories 914A-B may differ between the inference configuration and the training configuration. In one embodiment, the inference configuration of the GPGPU 900 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which are typically used during inference operations for deployed neural networks.

[0194] Figure 10 FIG. 1000 illustrates a multi-GPU computing system 1000 according to an embodiment. The multi-GPU computing system 1000 may include a processor 1002 that is coupled to a plurality of GPGPUs 1006A-D via a host interface switch 1004. In one embodiment, the host interface switch 1004 is a PCI express switch device that couples the processor 1002 to a PCI express bus through which the processor 1002 can communicate with the set of GPGPUs 1006A-D. Each of the plurality of GPGPUs 1006A-D can be an Figure 9 instance of the GPGPU 900. The GPGPUs 1006A-D can be interconnected via a set of high-speed point-to-point GPU-to-GPU links 1016. The high-speed GPU-to-GPU links can be connected to each of the GPGPUs 1006A-D via dedicated GPU links (such as the GPU link 910 as Figure 9 illustrated). The P2P GPU links 1016 enable direct communication between each of the GPGPUs 1006A-D without requiring communication through the host interface bus to which the processor 1002 is connected. In cases where GPU-to-GPU traffic involves the P2P GPU links, the host interface bus can still be used for system memory access or for communicating with other instances of the multi-GPU computing system 1000 via, for example, one or more network devices. While the GPGPUs 1006A-D are connected to the processor 1002 via the host interface switch 1004 in the illustrated embodiment, in one embodiment the processor 1002 includes direct support for the P2P GPU links 1016 and can be directly connected to the GPGPUs 1006A-D.

[0195] Machine Learning Neural Network Implementation

[0196] The computing architectures provided by the embodiments described herein can be configured to perform parallel processing of a type particularly suited for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions having graphical relationships. As is well known in the art, there are multiple types of neural network implementations used in machine learning. One exemplary type of neural network is the feedforward network described previously.

[0197] A second exemplary type of neural network is the convolutional neural network (CNN). A CNN is a specialized feedforward neural network for processing data having a known grid-like topology, such as image data. Thus, CNNs are commonly used in computational vision and image recognition applications, but they can also be used in other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by receptive fields found in the retina), and the output of each set of filters is propagated to the nodes in successive layers of the network. The computations for a CNN include applying convolutional mathematical operations to each filter to produce the output of that filter. Convolution is a specialized kind of mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function of the convolution can be referred to as the input, and the second function can be referred to as the convolution kernel. The output can be referred to as the feature map. For example, the input to a convolutional layer can be a multi-dimensional data array that defines the various color components of an input image. The convolution kernel can be a multi-dimensional parameter array, where the parameters are adapted through a training process for the neural network.

[0198] A recurrent neural network (RNN) is a class of feedforward neural network that includes feedback connections between layers. An RNN enables the modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes a loop. The loop represents the influence of the current value of a variable on its own value at a future time, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. Due to the variable nature that language data can include, this feature makes RNNs particularly useful for language processing.

[0199] The figures described below present exemplary feedforward, CNN, and RNN networks and describe the general processes for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any particular embodiment described herein, and in general, the concepts illustrated can be generally applied to deep neural networks and machine learning techniques.

[0200] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. In contrast to shallow neural networks that include only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Training deeper neural networks is generally more computationally intensive. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output error compared to shallow machine learning techniques.

[0201] The deep neural networks used in deep learning typically include a front-end network to perform feature recognition coupled to a back-end network representing a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning enables machine learning to be performed without requiring handcrafted feature engineering for the model. Instead, the deep neural network can learn features based on the statistical structure or correlations within the input data. The learned features can be provided to the mathematical model, which can map the detected features into an output. The mathematical model used by the network is generally specialized for the specific task to be performed, and different models will be used to perform different tasks.

[0202] Once the neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Backpropagation of error is a commonly used method for training neural networks. An input vector is presented to the network for processing. A loss function is used to compare the output of the network with the desired output, and an error value is calculated for each neuron in the output layer. The error value is then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm such as the stochastic gradient descent algorithm to update the weights of the neural network.

[0203] Figure 11A -Figure B illustrates an exemplary convolutional neural network. Figure 11A Illustrates the various layers within the CNN. As Figure 11AAs shown, an exemplary CNN for modeling image processing can receive an input 1102 that describes the red, green, and blue (RGB) components of an input image. The input 1102 can be processed by a plurality of convolutional layers (e.g., convolutional layer 1104, convolutional layer 1106). The output from the plurality of convolutional layers can optionally be processed by a set of fully connected layers 1108. Neurons in the fully connected layers have full connections to all activation functions in the previous layer, as previously described for feedforward networks. The output from the fully connected layer 1108 can be used to generate an output result from the network. Matrix multiplication can be used instead of convolution to compute the activations within the fully connected layer 1108. Not all CNN implementations use the fully connected layer 1108. For example, in some implementations, the convolutional layer 1106 can generate the output of the CNN.

[0204] Convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 1108. Traditional neural network layers are fully connected such that each output unit interacts with each input unit. However, convolutional layers are sparsely connected because the output of the convolution of the domain (rather than the corresponding state values of each node in the domain) is input to the nodes of the subsequent layer, as illustrated. The kernel associated with the convolutional layer performs a convolution operation, and the output of the convolution operation is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables the CNN to scale to handle large images.

[0205] Figure 11B An exemplary computational stage within the convolutional layer of a CNN is illustrated. The input 1112 to the convolutional layer of the CNN can be processed in three stages of the convolutional layer 1114. These three stages can include a convolution stage 1116, a detector stage 1118, and a pooling stage 1120. The convolutional layer 1114 can then output the data to a successive convolutional layer. The last convolutional layer of the network can generate output feature map data or provide an input to the fully connected layer, e.g., to generate classification values for the input to the CNN.

[0206] In the convolution stage 1116, a number of convolutions are performed in parallel to produce a set of linear activations. The convolution stage 1116 can include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage computes the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as the local region associated with the neuron. The neuron computes the dot product between the weights of the neuron and the region in the local input to which the neuron is connected. The output from the convolution stage 1116 defines a set of linear activations to be processed by successive stages of the convolutional layer 1114.

[0207] The linear activations can be processed by the detector stage 1118. In the detector stage 1118, each linear activation is processed by a non-linear activation function. The non-linear activation function increases the non-linearity of the overall network without affecting the receptive field of the convolutional layer. Several types of non-linear activation functions can be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max( 0 , x ) such that the activation is thresholded at zero.

[0208] The pooling stage 1120 uses a pooling function that replaces the output of the convolutional layer 1106 with a summary statistic of nearby outputs. The pooling function can be used to introduce translational invariance into the neural network so that small translations of the input do not change the pooled output. Invariance to local translations can be useful in scenarios where the presence of a feature in the input data is more important than the exact location of that feature. Various types of pooling functions can be used during the pooling stage 1120, including max pooling, average pooling, and l2-norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such implementations replace it with an additional convolutional stage that has an increased stride relative to the previous convolutional stage.

[0209] The output from the convolutional layer 1114 can then be processed by the next layer 1122. The next layer 1122 can be either an additional convolutional layer or one of the fully connected layers 1108. For example, Figure 11A the first convolutional layer 1104 can output to the second convolutional layer 1106, and the second convolutional layer can output to the first of the fully connected layers 1108.

[0210] Figure 12An exemplary recurrent neural network 1200 is illustrated. In a recurrent neural network (RNN), the previous state of the network affects the output of the current state of the network. The RNN can be built in a variety of ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous input sequences. For example, an RNN can be used to perform statistical language modeling to predict upcoming words given a previous sequence of words. The illustrated RNN 1200 can be described as having an input layer 1202 that receives an input vector, a hidden layer 1204 that implements a recurrent function, a feedback mechanism 1205 that enables a 'memory' of the previous state, and an output layer 1206 that outputs the result. The RNN 1200 operates based on time steps. The state of the RNN at a given time step is affected by the previous time step via the feedback mechanism 1205. For a given time step, the state of the hidden layer 1204 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1204. The second input (x2) can be processed by the hidden layer 1204 using the state information determined during the processing of the initial input (x1). A given state can be calculated as s t = f ( Ux t + Ws t-1 ), where U and W are parameter matrices. The function f is generally non-linear, such as the hyperbolic tangent function (Tanh) or a variant of the rectifier function f(x) = max( 0 , x ). However, the specific mathematical function used in the hidden layer 1204 can vary depending on the specific implementation details of the RNN 1200.

[0211] In addition to the basic CNN and RNN networks described, variations of those networks can also be enabled. One example of an RNN variant is the long short-term memory (LSTM) RNN. The LSTM RNN is capable of learning long-term dependencies that may be necessary for processing longer language sequences. A variant of the CNN is the convolutional deep belief network, which has a structure similar to the CNN and is trained in a manner similar to a deep belief network. A deep belief network (DBN) is a generative neural network consisting of multiple layers of stochastic (random) variables. The DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining a set of optimal initial weights for the neural network.

[0212] Figure 13Illustrated is the training and deployment of a deep neural network. Once a given network has been structured for a task, a training data set 1302 is used to train the neural network. A variety of training frameworks have been developed to enable hardware acceleration of the training process. For example, Figure 8 the machine learning framework 804 of Figure 8 can be configured as a training framework 1304. The training framework 1304 can be hooked up to an untrained neural network 1306 and enable the use of the parallel processing resources described herein to train the untrained neural network to generate a trained neural network 1308.

[0213] To start the training process, initial weights can be selected randomly or by pre-training using a deep belief network. Then, the training loop is performed in a supervised or unsupervised manner.

[0214] Supervised learning is a learning method in which training is performed as a mediation operation, such as when the training data set 1302 includes the input paired with the desired output of the input, or when the training data set includes an input with a known output and the output of the neural network is manually graded. The network processes the input and compares the resulting output with a set of expected or desired outputs. Then, the error is backpropagated through the system. The training framework 1304 can be adjusted to adjust the weights controlling the untrained neural network 1306. The training framework 1304 can provide tools to monitor how well the untrained neural network 1306 converges towards a model suitable for generating the correct answer based on the known input data. The training process occurs repeatedly as the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated with the trained neural network 1308. Then, the trained neural network 1308 can be deployed to perform any number of machine learning operations.

[0215] Unsupervised learning is a learning method in which the network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1302 will include input data without any associated output data. The untrained neural network 1306 can learn the groupings within the unlabeled input and can determine how individual inputs relate to the overall data set. Unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network 1307 that can perform operations useful in reducing data dimensionality. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from the normal data pattern.

[0216] Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training data set 1302 includes a mixture of labeled and unlabeled data of the same distribution. Incremental learning is a variant of supervised learning in which input data is continuously used to further train the model. Incremental learning enables the trained neural network 1308 to adapt to new data 1312 without forgetting the knowledge instilled within the network during initial training.

[0217] Regardless of whether it is supervised or unsupervised, the training process for a particularly deep neural network can be computationally intensive for a single computing node. A distributed network of computing nodes can be used instead of a single computing node to accelerate the training process.

[0218] Figure 14 FIG. is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. Each distributed computing node can include one or more host processors and one or more of general-purpose processing nodes, such as the highly parallel general-purpose graphics processing unit 900 in FIG. 900. As illustrated, distributed learning can perform model parallelism 1402, data parallelism 1404, or a combination of model and data parallelism 1404.

[0219] In model parallelism 1402, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes of a distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of a neural network enables the training of very large neural networks in which the weights of all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0220] In data parallelization 1404, different nodes of a distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. While different methods for data parallelization are possible, data parallelization training methods all require techniques for combining the results and synchronizing the model parameters across the nodes. Exemplary methods for combining data include parameter averaging and update-based data parallelization. Parameter averaging trains each node on a subset of the training data and sets the global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Update-based data parallelization is similar to parameter averaging, except that updates to the model are communicated rather than the parameters from the nodes to the parameter server. Additionally, update-based data parallelization can be performed in a decentralized manner, where the updates are compressed and communicated between the nodes.

[0221] For example, the combined model and data parallelization 1406 can be implemented in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, where individual GPUs within each node are used to train different parts of the model.

[0222] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques for reducing the overhead of distributed training, including techniques for enabling high-bandwidth GPU-to-GPU data transfer and accelerated remote data synchronization.

[0223] Exemplary Machine Learning Applications

[0224] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The applications of computer vision range from reproducing human vision capabilities such as face recognition to creating new classes of vision capabilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced by objects visible in a video. Machine learning accelerated by parallel processors enables the training of computer vision applications using training data sets that are significantly larger than previously feasible, and enables the deployment of inference systems using low-power parallel processors.

[0225] Machine learning accelerated by a parallel processor has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. The accelerated machine learning techniques can be used to train a driving model based on a data set that defines an appropriate response to a particular training input. The parallel processors described herein can enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0226] Parallel-processor-accelerated deep neural networks have enabled machine learning methods for automatic speech recognition (ASR). ASR includes creating a function that computes the most likely language sequence given an input sound sequence. Accelerated machine learning using deep neural networks has enabled replacement of the Hidden Markov Model (HMM) and Gaussian Mixture Model (GMM) previously used for ASR.

[0227] Parallel-processor-accelerated machine learning can also be used to accelerate natural language processing. An automated learning program can use statistical inference algorithms to produce a model that is robust to incorrect or unfamiliar inputs. Exemplary natural language processor applications include automated machine translation between human languages.

[0228] The parallel processing platforms for machine learning can be divided into a training platform and a deployment platform. The training platform is generally highly parallel and includes optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include the highly parallel general-purpose graphics processing unit 900 of FIG. 900 and the multi-GPU computing system 1000 of FIG. 1000. In contrast, the deployed machine learning platforms generally include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0229] Figure 15FIG. illustrates an exemplary inference system-on-a-chip (SOC) 1500 suitable for performing inference using a trained model. The SOC 1500 may integrate processing components, including a media processor 1502, a vision processor 1504, a GPGPU 1506, and a multi-core processor 1508. The SOC 1500 may additionally include on-chip memory 1505, which may enable a shared on-chip data pool accessible by each of the processing components. The processing components may be optimized for low-power operation to enable deployment to a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 1500 may be used as part of the main control system for an autonomous vehicle. When the SOC 1500 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards for the deployment jurisdiction.

[0230] During operation, the media processor 1502 and the vision processor 1504 may work in concert to accelerate computer vision operations. The media processor 1502 may enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams may be written to a buffer in the on-chip memory 1505. The vision processor 1504 may then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing the frames using a trained image recognition model. For example, the vision processor 1504 may accelerate the convolutional operations for a CNN used to perform image recognition on high-resolution video data, and the backend model calculations are performed by the GPGPU 1506.

[0231] The multi-core processor 1508 may include control logic to assist in the ordering and synchronization of shared memory operations and data transfers performed by the media processor 1502 and the vision processor 1504. The multi-core processor 1508 may also act as an application processor to execute software applications that may utilize the inference computing capabilities of the GPGPU 1506. For example, at least a portion of the navigation and driving logic may be implemented in software executed on the multi-core processor 1508. Such software may directly issue compute workloads to the GPGPU 1506, or may issue compute workloads to the multi-core processor 1508, which may offload at least a portion of those operations to the GPGPU 1506.

[0232] The GPGPU 1506 may include compute clusters, such as a low-power configuration of compute clusters 906A-906H within the highly parallel general-purpose graphics processing unit 900. The compute clusters within the GPGPU 1506 may support instructions that are specifically optimized to perform inference computations on trained neural networks. For example, the GPGPU 1506 may support instructions for performing low-precision computations, such as 8-bit and 4-bit integer vector operations.

[0233] Additional Exemplary Graphics Processing Systems

[0234] The details of the embodiments described above may be incorporated within the graphics processing systems and devices described below. Figures 16 - 29 The graphics processing systems and devices illustrate alternative systems and graphics processing hardware that may implement any and all of the techniques described above.

[0235] Additional Exemplary Graphics Processing System Overview

[0236] Figure 16 is a block diagram of a processing system 1600 according to an embodiment. In various embodiments, the system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and may be a server system, a single-processor desktop system, or a multi-processor workstation system having a large number of processors 1602 or processor cores 1607. In one embodiment, the system 1600 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0237] Embodiments of the system 1600 may include or may be incorporated within the following: server-based game platforms, game consoles (including game and media consoles, mobile game consoles, handheld game consoles, or online game consoles). In some embodiments, the system 1600 is a mobile phone, smartphone, tablet computing device, or mobile Internet device. The data processing system 1600 may also include, be coupled to, or be integrated within the following: wearable devices, such as smartwatch wearable devices, smart eyewear devices, augmented reality devices, or virtual reality devices. In some embodiments, the data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphical interface generated by one or more graphics processors 1608.

[0238] In some embodiments, each of the one or more processors 1602 includes one or more processor cores 1607 for processing instructions that, when executed, perform the operations of system and user software. In some embodiments, each of the one or more processor cores 1607 is configured to process a particular instruction set 1609. In some embodiments, the instruction set 1609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). The multiple processor cores 1607 can each process a different instruction set 1609, which can include instructions for facilitating the emulation of other instruction sets. The processor cores 1607 can also include other processing devices, such as a digital signal processor (DSP).

[0239] In some embodiments, the processor 1602 includes a cache memory 1604. Depending on the architecture, the processor 1602 can have a single internal cache or multiple levels of internal caches. In some embodiments, the cache memory is shared among the various components of the processor 1602. In some embodiments, the processor 1602 also uses an external cache (e.g., a level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among the processor cores 1607 using known cache coherence techniques. A register file 1606 is additionally included in the processor 1602, which can include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). Some registers can be general-purpose registers, while other registers can be specific to the design of the processor 1602.

[0240] In some embodiments, the processor 1602 is coupled to a processor bus 1610 component for conveying communication signals (such as address, data, or control signals) between the processor 1602 and other components in the system 1600. In one embodiment, the system 1600 uses an exemplary 'hub' system architecture that includes a memory controller hub 1616 and an input / output (I / O) controller hub 1630. The memory controller hub 1616 facilitates communication between the memory device and other components of the system 1600, while the I / O controller hub (ICH) 1630 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 1616 is integrated within the processor.

[0241] The memory device 1620 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable performance to serve as a process memory. In one embodiment, the memory device 1620 can operate as the system memory of the system 1600 to store data 1622 and instructions 1621 for use when the one or more processors 1602 execute an application or process. The memory controller hub 1616 is also coupled to an optional external graphics processor 1612, which can communicate with one or more graphics processors 1608 in the processor 1602 to perform graphics and media operations.

[0242] In some embodiments, the ICH 1630 enables peripheral devices to be connected to the memory device 1620 and the processor 1602 via a high-speed I / O bus. The I / O peripheral devices include but are not limited to: an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., a hard disk drive, a flash memory, etc.), and a legacy I / O controller 1640 for coupling legacy (e.g., personal system 2 (PS / 2)) devices to the system. One or more universal serial bus (USB) controllers 1642 connect input devices (such as a combination of a keyboard and a mouse 1644). A network controller 1634 can also be coupled to the ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 1610. It will be appreciated that the system 1600 shown is exemplary and not restrictive, as other types of data processing systems configured in different ways can also be used. For example, the I / O controller hub 1630 can be integrated within the one or more processors 1602, or the memory controller hub 1616 and the I / O controller hub 1630 can be integrated into a discreet external graphics processor (such as the external graphics processor 1612).

[0243] Figure 17 is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A - 1702N, an integrated memory controller 1714, and an integrated graphics processor 1708. Figure 17Those elements having the same reference numbers (or names) as elements in any other figure in this document can operate or function in any manner similar to the manner described elsewhere in this document, but are not limited thereto. The processor 1700 can include additional cores up to and including additional core 1702N represented by the dashed box. Each of the processor cores 1702A - 1702N includes one or more internal cache units 1704A - 1704N. In some embodiments, each processor core is also capable of accessing one or more shared cache units 1706.

[0244] The internal cache units 1704A - 1704N and the shared cache unit 1706 represent a cache memory hierarchy within the processor 1700. The cache memory hierarchy can include at least one level of instruction and data caches within each processor core and one or more levels of shared intermediate - level caches (such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache), where the highest - level cache in front of the external memory is classified as the LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 1706 and 1704A - 1704N.

[0245] In some embodiments, the processor 1700 can also include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 1710 provides management functionality for various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714 to manage access to various external memory devices (not shown).

[0246] In some embodiments, one or more of the processor cores 1702A - 1702N include support for simultaneous multithreading. In such embodiments, the system agent core 1710 includes components for coordinating and operating the cores 1702A - 1702N during multithreading. The system agent core 1710 can additionally include a power control unit (PCU), which includes logic and components for regulating the power states of the processor cores 1702A - 1702N and the graphics processor 1708.

[0247] In some embodiments, the processor 1700 further includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, the graphics processor 1708 is coupled to a set of shared cache units 1706 and a system agent core 1710 (including the one or more integrated memory controllers 1714). In some embodiments, a display controller 1711 is coupled to the graphics processor 1708 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 1711 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 1708 or the system agent core 1710.

[0248] In some embodiments, a ring-based interconnect unit 1712 is used to couple the internal components of the processor 1700. However, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other techniques, including techniques well known in the art, can be used. In some embodiments, the graphics processor 1708 is coupled to the ring interconnect 1712 via an I / O link 1713.

[0249] The exemplary I / O link 1713 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1718, such as an eDRAM module. In some embodiments, each of the processor cores 1702A - 1702N and the graphics processor 1708 uses the embedded memory module 1718 as a shared last-level cache.

[0250] In some embodiments, the processor cores 1702A - 1702N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 1702A - 1702N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the processor cores 1702A - 1702N execute a first instruction set, and at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 1702A - 1702N are heterogeneous in terms of microarchitecture, where one or more cores with relatively higher power consumption are coupled to one or more power cores with lower power consumption. Additionally, the processor 1700 can be implemented on one or more chips or as a SoC integrated circuit with the components shown in addition to other components.

[0251] Figure 18is a block diagram of a graphics processor 1800, which can be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and with commands placed in the processor memory. In some embodiments, the graphics processor 1800 includes a memory interface 1814 for accessing memory. The memory interface 1814 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0252] In some embodiments, the graphics processor 1800 also includes a display controller 1802 for driving display output data to a display device 1820. The display controller 1802 includes hardware for one or more overlapping planes of the display and components for multi-layer video or user interface elements. In some embodiments, the graphics processor 1800 includes a video codec engine 1806 for encoding, decoding, or transcoding media to, from, or between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG) formats).

[0253] In some embodiments, the graphics processor 1800 includes a block transfer (BLIT) engine 1804 for performing two-dimensional (2D) rasterizer operations, which include (for example) bit boundary block transfers. However, in one embodiment, one or more components of the Graphics Processing Engine (GPE) 1810 are used to perform 2D graphics operations. In some embodiments, the GPE 1810 is a computing engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0254] In some embodiments, the GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 1812 includes programmable and fixed-function elements that perform various tasks within the element and / or generate execution threads for the 3D / media subsystem 1815. Although the 3D pipeline 1812 can be used to perform media operations, embodiments of the GPE 1810 also include a media pipeline 1816 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0255] In some embodiments, the media pipeline 1816 includes fixed-function or programmable logic units for performing one or more specialized media operations (such as video decoding acceleration, video deinterlacing, and video encoding acceleration) in place of or on behalf of the video codec engine 1806. In some embodiments, the media pipeline 1816 additionally includes a thread generation unit to generate threads for execution on the 3D / media subsystem 1815. The generated threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 1815.

[0256] In some embodiments, the 3D / media subsystem 1815 includes logic for executing the threads generated by the 3D pipeline 1812 and the media pipeline 1816. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 1815, which includes thread dispatch logic for arbitrating and dispatching various requests for available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and store output data.

[0257] Graphics Processing Engine

[0258] Figure 19 is a block diagram of a graphics processing engine 1910 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 1910 is Figure 18 a version of the GPE 1810 shown in Figure 19 Elements having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto. For example, illustratedFigure 18 3D pipeline 1812 and media pipeline 1816. Media pipeline 1816 is optional in some embodiments of GPE 1910 and may not be explicitly included within GPE 1910. For example and in at least one embodiment, a separate media and / or image processor is coupled to GPE 1910.

[0259] In some embodiments, GPE 1910 is coupled to or includes command stream transmitter 1903, which provides a command stream to 3D pipeline 1812 and / or media pipeline 1816. In some embodiments, command stream transmitter 1903 is coupled to a memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command stream transmitter 1903 receives commands from the memory and sends the commands to 3D pipeline 1812 and / or media pipeline 1816. The commands are instructions fetched from a ring buffer storing commands for 3D pipeline 1812 and media pipeline 1816. In one embodiment, the ring buffer may additionally include a batch command buffer storing batches of multiple commands. Commands for 3D pipeline 1812 may also include references to data stored in the memory, such as but not limited to vertex and geometry data for 3D pipeline 1812 and / or image data and memory objects for media pipeline 1816. 3D pipeline 1812 and media pipeline 1816 process commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to graphics core array 1914.

[0260] In various embodiments, 3D pipeline 1812 may execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to graphics core array 1914. Graphics core array 1914 provides a unified execution resource block. The multi-purpose execution logic (e.g., execution units) within graphics core array 1914 includes support for various 3D API shader languages and may execute multiple simultaneous execution threads associated with multiple shaders.

[0261] In some embodiments, graphics core array 1914 also includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution units additionally include general-purpose logic programmable to perform parallel general-purpose computing operations. The general-purpose logic may be associated with Figure 16 one or more of the processor cores 1607 or as Figure 17The general logic within the processor cores 1702A - 1702N performs processing operations either in parallel or in combination.

[0262] Output data generated by threads executing on the graphics core array 1914 can output the data to memory in the unified return buffer (URB) 1918. The URB 1918 can store data for multiple threads. In some embodiments, the URB 1918 can be used to send data between different threads executing on the graphics core array 1914. In some embodiments, the URB 1918 can additionally be used for synchronization between fixed - function logic within the shared - function logic 1920 and threads on the graphics core array.

[0263] In some embodiments, the graphics core array 1914 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance levels of the GPE 1910. In one embodiment, the execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0264] The graphics core array 1914 is coupled to the shared - function logic 1920, which includes multiple resources shared among the graphics cores within the graphics core array. The shared functions within the shared - function logic 1920 are hardware logic units that provide specialized supplementary functions to the graphics core array 1914. In various embodiments, the shared - function logic 1920 includes, but is not limited to, sampler 1921, math 1922, and inter - thread communication (ITC) 1923 logic. Additionally, some embodiments implement one or more caches 1925 within the shared - function logic 1920. The shared function is implemented when the demand for a given specialized function is not sufficient to be included within the graphics core array 1914. Alternatively, a single instantiation of the specialized function is implemented as a separate entity within the shared - function logic 1920 and shared among the execution resources within the graphics core array 1914. A set of exact functions that are shared among and included within the graphics core array 1914 vary between embodiments.

[0265] Execution Unit

[0266] Figure 20 is a block diagram of another embodiment of the graphics processor 2000. Figure 20 Elements in having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0267] In some embodiments, the graphics processor 2000 includes a ring interconnect 2002, a pipeline front end 2004, a media engine 2037, and graphics cores 2080A - 2080N. In some embodiments, the ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general - purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi - core processing system.

[0268] In some embodiments, the graphics processor 2000 receives multiple batches of commands via the ring interconnect 2002. The incoming commands are interpreted by a command stream fetcher 2003 in the pipeline front end 2004. In some embodiments, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via the graphics cores 2080A - 2080N. For 3D geometry processing commands, the command stream fetcher 2003 supplies the commands to a geometry pipeline 2036. For at least some media processing commands, the command stream fetcher 2003 supplies the commands to a video front end 2034, which is coupled to the media engine 2037. In some embodiments, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post - processing and a multi - format encoding / decoding (MFX) 2033 engine for providing hardware - accelerated encoding and decoding of media data. In some embodiments, both the geometry pipeline 2036 and the media engine 2037 generate execution threads for the thread execution resources provided by at least one of the graphics cores 2080A.

[0269] In some embodiments, the graphics processor 2000 includes scalable thread execution resources characterized by modular cores 2080A - 2080N (sometimes referred to as core slices), each modular core having a plurality of sub - cores 2050A - 550N, 2060A - 2060N (sometimes referred to as core sub - slices). In some embodiments, the graphics processor 2000 can have any number of graphics cores 2080A through 2080N. In some embodiments, the graphics processor 2000 includes a graphics core 2080A that has at least a first sub - core 2050A and a second sub - core 2060A. In other embodiments, the graphics processor is a low - power processor having a single sub - core (e.g., 2050A). In some embodiments, the graphics processor 2000 includes a plurality of graphics cores 2080A - 2080N, each graphics core including a set of first sub - cores 2050A - 2050N and a set of second sub - cores 2060A - 2060N. Each sub - core in the set of first sub - cores 2050A - 2050N includes at least a first set of execution units 2052A - 2052N and media / texture samplers 2054A - 2054N. Each sub - core in the set of second sub - cores 2060A - 2060N includes at least a second set of execution units 2062A - 2062N and samplers 2064A - 2064N. In some embodiments, each sub - core 2050A - 2050N, 2060A - 2060N shares a set of shared resources 2070A - 2070N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0270] Figure 21 Thread execution logic 2100 is shown, including an array of processing elements employed in some embodiments of the GPE. Figure 21 Those elements having the same reference numerals (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0271] In some embodiments, the thread execution logic 2100 includes a shader processor 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable execution unit array (including multiple execution units 2108A - 2108N), a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 2108A, 2108B, 2108C, 2108D, up to 2108N - 1 and 2108N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, via the instruction cache 2106, the data port 2114, the sampler 2110, and one or more of the execution units 2108A - 2108N, the thread execution logic 2100 includes one or more connections to memory (such as system memory or cache memory). In some embodiments, each execution unit (e.g., 2108A) is an independently programmable general - purpose computing unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the execution unit array 2108A - 2108N is scalable to include any number of individual execution units.

[0272] In some embodiments, the execution units 2108A - 2108N are primarily used to execute shader programs. The shader processor 2102 can process various shader programs and dispatch execution threads associated with the shader programs via the thread dispatcher 2104. In one embodiment, the thread dispatcher includes logic for arbitrating requests for threads initiated from the graphics and media pipelines and instantiating the requested threads on one or more of the execution units 2108A - 2108N. For example, a geometry pipeline (e.g., Figure 20 2036) can dispatch vertex, tessellation, or geometry shaders to the thread execution logic 2100 ( Figure 21 ) for processing. In some embodiments, the thread dispatcher 2104 can also handle runtime thread spawning requests from executing shader programs.

[0273] In some embodiments, execution units 2108A - 2108N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling shader programs from graphics libraries (e.g., Direct 3D and OpenGL) to be executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general - purpose processing (e.g., compute and media shaders). Each of the execution units 2108A - 2108N has the ability for multi - issue single - instruction multiple - data (SIMD) execution, and multi - threaded operation enables an efficient execution environment in the face of higher - latency memory accesses. Each hardware thread within each execution unit has a dedicated high - bandwidth register file and associated independent thread state. For pipelines with integer, single - and double - precision floating - point arithmetic, SIMD branch capabilities, logical operations, transcendental operations, and other miscellaneous arithmetic capabilities, execution is multi - issue per clock. When waiting for data from either memory or one of the shared functions, the dependency logic within the execution units 2108A - 2108N puts the waiting threads to sleep until the requested data has returned. While the waiting threads are sleeping, the hardware resources may be dedicated to processing other threads. For example, during the latency associated with vertex shader operations, the execution units can perform operations on pixel shaders, fragment shaders, or another type of shader program including a different vertex shader.

[0274] Each of the execution units 2108A - 2108N operates on an array of data elements. The number of data elements is the "execution size" or the number of lanes for the instruction. Execution lanes are the logical units for flow control, data - element access, and masking execution within an instruction. The number of lanes can be independent of the number of physical arithmetic - logic units (ALUs) or floating - point units (FPUs) of a particular graphics processor. In some embodiments, the execution units 2108A - 2108N support integer and floating - point data types.

[0275] The execution - unit instruction set includes SIMD instructions. Various data elements can be stored in registers as packed data types, and the execution units will process the various elements based on the element's data size. For example, when operating on a 256 - bit - wide vector, the 256 - bit vector is stored in a register, and the execution unit operates on the vector as four separate 64 - bit packed data elements (quad - word (QW) - sized data elements), eight separate 32 - bit packed data elements (double - word (DW) - sized data elements), sixteen separate 16 - bit packed data elements (word (W) - sized data elements), or thirty - two separate 8 - bit data elements (byte (B) - sized data elements). However, different vector widths and register sizes are possible.

[0276] One or more internal instruction caches (e.g., 2106) are included in the thread execution logic 2100 to cache the thread instructions of the execution units. In some embodiments, one or more data caches (e.g., 2112) are included to cache the thread data during thread execution. In some embodiments, a sampler 2110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2110 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution units.

[0277] During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2100 via the thread generation and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2102 is invoked to further compute the output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader operations interpolate the values of various vertex attributes across the rasterized objects. In some embodiments, the pixel processor logic within the shader processor 2102 then executes the pixel or fragment shader program supplied by the application programming interface (API). To execute the shader program, the shader processor 2102 dispatches threads to the execution units (e.g., 2108A) via the thread dispatcher 2104. In some embodiments, the pixel shader 2102 uses the texture sampling logic in the sampler 2110 to access the texture data in the texture map stored in memory. Arithmetic operations performed on the texture data and the input geometric data compute the pixel color data for each geometric fragment, or discard one or more pixels from further processing.

[0278] In some embodiments, the data port 2114 provides a memory access mechanism for the thread execution logic 2100 to output the processed data to memory for processing on the graphics processor output pipeline. In some embodiments, the data port 2114 includes or is coupled to one or more cache memories (e.g., the data cache 2112) to cache the data for memory access via the data port. Figure 22FIG. 2200 is a block diagram illustrating a graphics processor instruction format according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid boxes show components that are typically included in execution unit instructions, while the dashed boxes include optional or components only included in a subset of the instructions. In some embodiments, the described and illustrated instruction formats 2200 are macro-instructions as they are the instructions supplied to the execution unit, as opposed to micro-operations decoded from the instructions (once the instructions are processed).

[0279] In some embodiments, a graphics processor execution unit natively supports instructions in a 128-bit instruction format 2210. A 64-bit compact instruction format 2230 is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted to the 64-bit format 2230. The native instructions available in the 64-bit format 2230 vary by embodiment. In some embodiments, a set of index values in an index field 2213 partially compacts the instruction. The execution unit hardware references a set of compact tables based on the index values and uses the compact table outputs to reconstruct the native instruction in the 128-bit instruction format 2210.

[0280] For each format, an instruction opcode 2212 defines the operation the execution unit is to perform. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, an instruction control field 2214 enables control of certain execution options such as channel selection (e.g., predication) and data channel ordering (e.g., swizzling). For instructions in the 128-bit instruction format 2210, an execution size field 2216 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 2216 is not available for use in the 64-bit compact instruction format 2230.

[0281] Some execution unit instructions have up to three operands, including two source operands src0 2220, src1 2222, and one destination 2218. In some embodiments, the execution unit supports dual destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed by the instruction.

[0282] In some embodiments, the 128-bit instruction format 2210 includes an access / addressing mode field 2226 that specifies, for example, whether to use direct register addressing mode or indirect register addressing mode. When using direct register addressing mode, the register addresses of one or more operands are provided directly by bits in the instruction.

[0283] In some embodiments, the 128-bit instruction format 2210 includes an access / addressing mode field 2226 that specifies the addressing mode and / or access mode for the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte alignment access mode and a 1-byte alignment access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands, and when in a second mode, the instruction may use 16-byte-aligned addressing for all source and destination operands.

[0284] In one embodiment, the addressing mode portion of the access / addressing mode field 2226 determines whether the instruction will use direct or indirect addressing. When using direct register addressing mode, bits in the instruction directly provide the register addresses of one or more operands. When using indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address immediate field and the address register value in the instruction.

[0285] In some embodiments, instructions are grouped based on the 2212-bit opcode fields to simplify opcode decoding 2240. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The exact opcode grouping shown is merely an example. In some embodiments, the move and logic opcode group 2242 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2242 shares the five most significant bits (MSB), where the move (mov) instruction takes the form 0000xxxxb, and the logic instruction takes the form 0001xxxxb. The flow control instruction group 2244 (e.g., call, jump (jmp)) includes instructions that take the form 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2246 includes a mix of instructions, which includes synchronization instructions (e.g., wait, send) that take the form 0011xxxxb (e.g., 0x30). The parallel math instruction group 2248 includes component arithmetic instructions (e.g., add, multiply (mul)) that take the form 0100xxxxb (e.g., 0x40). The parallel math group 2248 executes arithmetic operations in parallel across data channels. The vector math group 2250 includes arithmetic instructions (e.g., dp4) that take the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as a dot product operation on vector operands.

[0286] Graphics Pipeline

[0287] Figure 23 is a block diagram of another embodiment of the graphics processor 2300. Figure 23 Elements having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0288] In some embodiments, the graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, thread execution logic 2350, and a render output pipeline 2370. In some embodiments, the graphics processor 2300 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to the graphics processor 2300 via the ring interconnect 2302. In some embodiments, the ring interconnect 2302 couples the graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2302 are interpreted by a command streamer 2303, which supplies instructions to individual components of the graphics pipeline 2320 or the media pipeline 2330.

[0289] In some embodiments, the command stream fetcher 2303 directs the operation of the vertex fetcher 2305, which reads vertex data from memory and executes vertex processing commands provided by the command stream fetcher 2303. In some embodiments, the vertex fetcher 2305 provides vertex data to the vertex shader 2307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 2305 and the vertex shader 2307 execute vertex processing instructions by dispatching execution threads to execution units 2352A - 2352B via a thread dispatcher 2331.

[0290] In some embodiments, the execution units 2352A - 2352B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, the execution units 2352A - 2352B have attached L1 caches 2351 that are specific to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0291] In some embodiments, the graphics pipeline 2320 includes a tessellation component for performing hardware - accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 configures the tessellation operation. A programmable domain shader 817 provides a backend evaluation of the tessellation output. The tessellator 2313 operates in the direction of the hull shader 2311 and includes dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 2320. In some embodiments, if tessellation is not used, the tessellation components (e.g., hull shader 2311, tessellator 2313, and domain shader 2317) can be bypassed.

[0292] In some embodiments, a complete geometric object can be processed by the geometry shader 2319 via one or more threads dispatched to execution units 2352A - 2352B, or can proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on an entire geometric object (as opposed to a patch of vertices or vertices as in the previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, if the tessellation unit is disabled, the geometry shader 2319 can be programmed by a geometry shader program to perform geometric tessellation.

[0293] Before rasterization, clipper 2329 processes vertex data. The clipper 2329 can be a programmable clipper with clipping and geometry shader capabilities or a fixed-function clipper. In some embodiments, the rasterizer and depth test component 2373 in the render output pipeline 2370 dispatches pixel shaders to transform geometric objects into their per-pixel representations. In some embodiments, the pixel shader logic is included in the thread execution logic 2350. In some embodiments, an application can bypass the rasterizer and depth test component 2373 and access the un-rasterized vertex data via the stream out unit 2323.

[0294] The graphics processor 2300 has an interconnect bus, an interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed among the major components of the processor. In some embodiments, the execution units 2352A - 2352B and the associated cache(s) 2351, the texture and media sampler 2354, and the texture / sampler cache 2358 are interconnected via the data port 2356 to perform memory accesses and communicate with the render output pipeline components of the processor. In some embodiments, the sampler 2354, the caches 2351, 2358, and the execution units 2352A - 2352B each have separate memory access paths.

[0295] In some embodiments, the render output pipeline 2370 includes a rasterizer and depth test component 2373 that transforms vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. Associated render cache 2378 and depth cache 2379 are also available in some embodiments. The pixel operation component 2377 performs pixel-based operations on the data, although in some examples, pixel operations associated with 2D operations (e.g., bitblt with blending for transfer) are performed by the 2D engine 2341 or, at display time, by the display controller 2343 using an overlay display plane instead. In some embodiments, a shared L3 cache 2375 is available for all graphics components, allowing data to be shared without using the main system memory.

[0296] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front end 2334. In some embodiments, the video front end 2334 receives pipeline commands from the command streamer 2303. In some embodiments, the media pipeline 2330 includes a separate command streamer. In some embodiments, the video front end 2334 processes the commands before sending the media commands to the media engine 2337. In some embodiments, the media engine 2337 includes thread generation functionality for generating threads for dispatch to thread execution logic 2350 via a thread dispatcher 2331.

[0297] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and is coupled to the graphics processor via a ring interconnect 2302, or some other interconnect bus or fabric. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 contains dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 2343 is coupled to a display device (not shown), which may be a system integrated display device (such as in a laptop computer), or may be an external display device attached via a display device connector.

[0298] In some embodiments, the graphics pipeline 2320 and the media pipeline 2330 can be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor converts API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulkan graphics and compute APIs, all from the Khronos Group. In some embodiments, support can also be provided for the Direct3D library from Microsoft Corporation. In some embodiments, combinations of these libraries can be supported. Support can also be provided for the Open Source Computer Vision Library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a mapping can be made from the pipelines of the future APIs to the pipelines of the graphics processor.

[0299] Graphics Pipeline Programming

[0300] Figure 24A is a block diagram of a graphics processor command format 2400 according to some embodiments. Figure 24BIt is a block diagram of a graphics processor command sequence 2410 according to an embodiment. Figure 24A The solid boxes in [the figure] show components that are generally included in a graphics command, while the dashed boxes include optional components or components that are only included in a subset of graphics commands. Figure 24A An exemplary graphics processor command format 2400 includes data fields for identifying a target client 2402 of the command, a command operation code (opcode) 2404, and associated data 2406 for the command. A sub-opcode 2405 and a command size 2408 are also included in some commands.

[0301] In some embodiments, the client 2402 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and route the command data to an appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads the opcode 2404 and (if present) the sub-opcode 2405 to determine the operation to perform. The client unit uses the information in the data field 2406 to execute the command. For some commands, an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands in the command based on the command opcode. In some embodiments, the commands are aligned by a multiple of a double word length.

[0302] Figure 24B The flowchart in [the figure] shows an exemplary graphics processor command sequence 2410. In some embodiments, software or firmware of a data processing system characterized by an embodiment of a graphics processor uses a version of the shown command sequence to initiate, execute, and terminate a set of graphics operations. The sample command sequence is shown and described only for illustrative purposes, as embodiments are not limited to these specific commands or this command sequence. Additionally, the commands may be issued in a batch in the command sequence such that the graphics processor processes at least a portion of the sequence of commands simultaneously.

[0303] In some embodiments, the graphics processor command sequence 2410 may begin with a pipeline dump flush command 2412 to cause any active graphics pipeline to complete the current outstanding commands of the pipeline. In some embodiments, the 3D pipeline 2422 and the media pipeline 2424 do not operate simultaneously. Execution of the pipeline dump flush is to cause the active graphics pipeline to complete any outstanding commands. In response to the pipeline dump flush, the command parser for the graphics processor will pause command processing until the active drawing engine has completed the outstanding operations and the associated read caches are invalidated. Optionally, any data marked 'dirty' in the render cache may be dumped to memory. In some embodiments, the pipeline dump flush command 2412 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0304] In some embodiments, a pipeline select command 2413 is used when the command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline select command 2413 is only required once within an execution context before issuing pipeline commands, unless the context is to issue commands for both pipelines. In some embodiments, the pipeline dump flush command 2412 is required immediately before a pipeline switch via the pipeline select command 2413.

[0305] In some embodiments, the pipeline control command 2414 configures the graphics pipeline for operation and is used to program the 3D pipeline 2422 and the media pipeline 2424. In some embodiments, the pipeline control command 2414 configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command 2414 is used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0306] In some embodiments, a return buffer status command 2416 is used to configure a set of return buffers for the corresponding pipeline to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers, which write intermediate data to the one or more return buffers during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer status 2416 includes selecting the size and number of return buffers for a set of pipeline operations.

[0307] The remaining commands in the command sequence differ based on the active pipeline for the operation. Based on pipeline determination 2420, the command sequence is customized for the 3D pipeline 2422 or the media pipeline 2424, where the 3D pipeline 2422 starts with the 3D pipeline state 2430 and the media pipeline 2424 starts with the media pipeline state 2440.

[0308] Commands for configuring the 3D pipeline state 2430 include 3D state setting commands for the following: vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured prior to processing 3D primitive commands. The values of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 2430 commands are also capable of selectively disabling or bypassing certain pipeline elements if those elements will not be used.

[0309] In some embodiments, the 3D primitive commands 2432 are used to submit 3D primitive commands to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive commands 2432 are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive command 2432 data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive commands 2432 are used to perform vertex operations on the 3D primitive commands via the vertex shader. To process the vertex shader, the 3D pipeline 2422 dispatches shader execution threads to the graphics processor execution units.

[0310] In some embodiments, the 3D pipeline 2422 is triggered via an execute 2434 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in the command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution to dump a clear command sequence through the graphics pipeline. The 3D pipeline will perform geometric processing on the 3D primitive commands. Once the operation is complete, the resulting geometric object is rasterized, and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0311] In some embodiments, when performing media operations, the graphics processor command sequence 2410 follows the media pipeline 2424 path. Generally, the specific use and manner of programming for the media pipeline 2424 depends on the media or compute operations to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed and media decoding can be performed in whole or in part (using the resources provided by one or more general-purpose processing cores). In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using a compute shader program that does not explicitly involve the rendering of graphics primitives.

[0312] In some embodiments, the media pipeline 2424 is configured in a manner similar to the 3D pipeline 2422. A set of commands for configuring the media pipeline state 2440 is dispatched or placed into the command queue before the media object command 2442. In some embodiments, the media pipeline state commands 2440 include data for configuring the media pipeline elements that will be used to process the media object. This includes data for configuring the video decoding and video encoding logic within the media pipeline (such as the encoding or decoding format). In some embodiments, the media pipeline state commands 2440 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0313] In some embodiments, the media object command 2442 supplies pointers to the media objects to be processed by the media pipeline. The media objects include memory buffers containing the video data to be processed. In some embodiments, all media pipeline states must be valid before the media object command 2442 is issued. Once the pipeline state is configured and the media object command 2442 is queued, the media pipeline 2424 is triggered via an execute command 2444 or an equivalent execution event (e.g., a register write). Then the output from the media pipeline 2424 can be post-processed by operations provided by the 3D pipeline 2422 or the media pipeline 2424. In some embodiments, the GPGPU operations are configured and executed in a manner similar to the media operations.

[0314] Graphic software architecture

[0315] Figure 25Shows an exemplary graphics software architecture for a data processing system 2500 according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, the processor 2530 includes a graphics processor 2532 and one or more general-purpose processor cores 2534. The graphics application 2510 and the operating system 2520 each execute in the system memory 2550 of the data processing system.

[0316] In some embodiments, the 3D graphics application 2510 includes one or more shader programs, which include shader instructions 2512. The shader language instructions may be in a high-level shader language, such as High-Level Shading Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 2514 in machine language suitable for execution by the general-purpose processor cores 2534. The application also includes graphics objects 2516 defined by vertex data.

[0317] In some embodiments, the operating system 2520 is the Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open-source UNIX-like operating system (using a variant of the Linux kernel). The operating system 2520 may support a graphics API 2522, such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 in HLSL into a lower-level shader language. The compilation may be just-in-time (JIT) compilation, or the application may perform shader pre-compilation. In some embodiments, during the compilation of the 3D graphics application 2510, high-level shaders are compiled into low-level shaders. In some embodiments, the shader instructions 2512 are provided in an intermediate form, such as the standard portable intermediate representation version used by the Vulkan API.

[0318] In some embodiments, the user-mode graphics driver 2526 includes a backend shader compiler 2527 that is used to convert shader instructions 2512 into a hardware-specific representation. When the OpenGL API is in use, shader instructions 2512 in the GLSL high-level language are passed to the user-mode graphics driver 2526 for compilation. In some embodiments, the user-mode graphics driver 2526 uses operating system kernel-mode functions 2528 to communicate with the kernel-mode graphics driver 2529. In some embodiments, the kernel-mode graphics driver 2529 communicates with the graphics processor 2532 to dispatch commands and instructions.

[0319] IP core implementation

[0320] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium can include instructions that represent various logics within the processor. When read by the machine, the instructions can cause the machine to fabricate the logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit that can be stored on a tangible machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model can be supplied to various consumers or manufacturing facilities that load the hardware model on a fabrication machine for manufacturing the integrated circuit. The integrated circuit can be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

[0321] Figure 26FIG. 0 is a block diagram illustrating an IP core development system 2600 according to an embodiment, which can be used to fabricate integrated circuits to perform operations. The IP core development system 2600 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build an entire integrated circuit (e.g., a SOC integrated circuit). A design facility 2630 can generate a software simulation 2610 of an IP core design using a high-level programming language (e.g., C / C++). The software simulation 2610 can be used to design, test, and verify the behavior of the IP core using a simulation model 2612. The simulation model 2612 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 2615 can then be created or synthesized from the simulation model 2612. The RTL design 2615 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers (including the associated logic performed using the modeled digital signals). In addition to the RTL design 2615, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can vary.

[0322] The RTL design 2615 or equivalent can be further synthesized by the design facility into a hardware model 2620, which can be in a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. A non-volatile memory 2640 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party fabrication facility 2665. Alternatively, the IP core design can be transmitted (e.g., via the Internet) through a wired connection 2650 or a wireless connection 2660. The fabrication facility 2665 can then fabricate an integrated circuit based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

[0323] Exemplary system-on-chip integrated circuit

[0324] Figures 27 - 29 Exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein are shown. In addition to those shown, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0325] Figure 27is a block diagram showing an exemplary system - on - chip integrated circuit 2700 according to an embodiment. The system - on - chip integrated circuit 2700 can be fabricated using one or more IP cores. The exemplary integrated circuit 2700 includes one or more application processors 2705 (e.g., CPUs), at least one graphics processor 2710, and may additionally include an image processor 2715 and / or a video processor 2720, any of which can be a modular IP core from the same or multiple different design facilities. The integrated circuit 2700 includes peripheral or bus logic, which includes a USB controller 2725, a UART controller 2730, an SPI / SDIO controller 2735, I 2 S / I 2 C controller 2740. Additionally, the integrated circuit may include a display device 2745, which is coupled to one or more of a high - definition multimedia interface (HDMI) controller 2750 and a mobile industry processor interface (MIPI) display interface 2755. Storage can be provided by a flash memory subsystem 2760 (including flash memory and a flash memory controller). A memory interface can be provided via a memory controller 2765 for accessing SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2770.

[0326] Figure 28 is a block diagram showing an exemplary graphics processor 2810 of a system - on - chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 2810 can be Figure 27 a variant of the graphics processor 2710. The graphics processor 2810 includes a vertex processor 2805 and one or more fragment processors 2815A - 2815N (e.g., 2815A, 2815B, 2815C, 2815D to 2815N - 1 and 2815N). The graphics processor 2810 can execute different shader programs via separate logic, such that the vertex processor 2805 is optimized to perform operations for vertex shader programs, while the one or more fragment processors 2815A - 2815N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 2805 executes the vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. The (multiple) fragment processors 2815A - 2815N use the primitives and vertex data generated by the vertex processor 2805 to produce a frame buffer that is displayed on a display device. In one embodiment, the (multiple) fragment processors 2815A - 2815N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs as provided in the Direct 3D API.

[0327] The graphics processor 2810 further includes one or more memory management units (MMUs) 2820A-2820B, caches 2825A-2825B, and circuit interconnects 2830A-2830B. The one or more MMUs 2820A-2820B provide virtual-to-physical address mapping for the image processor 2810, including the vertex processor 2805 and / or fragment processors 2815A-2815N, and the virtual-to-physical address mapping can reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in the one or more caches 2825A-2825B. In one embodiment, the one or more MMUs 2820A-2820B can be synchronized with other MMUs within the system, and the other MMUs include one or more MMUs associated with Figure 27 one or more of the application processors 2705, image processors 2715, and / or video processors 2720 such that each processor 2705-2720 can participate in a shared or unified virtual memory system. According to an embodiment, the one or more circuit interconnects 2830A-2830B enable the graphics processor 2810 to interface with other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0328] Figure 29 FIG. is a block diagram illustrating an additional exemplary graphics processor 2910 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 2910 can be Figure 27 a variant of the graphics processor 2710. The graphics processor 2910 includes Figure 28 the one or more MMUs 2820A-2820B, caches 2825A-2825B, and circuit interconnects 2830A-2830B of the integrated circuit 2800.

[0329] The graphics processing unit 2910 includes one or more shader cores 2915A - 2915N (e.g., 2915A, 2915B, 2915C, 2915D, 2915E, 2915F to 2915N - 1, and 2915N), which provide a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, and the programmable shader code includes shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present can vary among embodiments and implementations. Additionally, the graphics processing unit 2910 includes an inter - core task manager 2905, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 2915A - 2915N, and a tile - based unit 2918 for accelerating tile - based operations for tile - based rendering, where rendering operations for a scene are subdivided in image space, e.g., for taking advantage of local spatial coherence within the scene or for optimizing the use of internal caches.

[0330] The present disclosure / application provides the following technical solutions:

[0331] 1. A device for facilitating the processing of sparse matrices, comprising:

[0332] A graphics processing unit, comprising:

[0333] A plurality of processing units, each including one or more processing elements, and the one or more processing elements comprising:

[0334] Logic for reading operands;

[0335] A multiplication unit for multiplying two or more operands; and

[0336] A scheduler for identifying operands having a zero value and preventing the scheduler of the multiplication unit from scheduling the operands having the zero value.

[0337] 2. The device according to technical solution 1, wherein the scheduler schedules non - zero value operands in the multiplication unit.

[0338] 3. The device according to technical solution 2, wherein when the operand is received at the logic for reading the operand, the scheduler retrieves the stored operand value.

[0339] 4. The device according to technical solution 3, further comprising write - result logic for writing the result of the product of the two or more operands in the multiplication unit, wherein the scheduler writes a zero value to the write - result logic for an operand having a zero value.

[0340] 5. The device according to Technical Solution 1 further includes pattern tracking logic for detecting one or more sparse data segments in the stored data blocks.

[0341] 6. The device according to Technical Solution 5, wherein the pattern tracking logic further includes pattern recognition logic for performing a bounding box operation on the data block to determine the similarity of the data.

[0342] 7. The device according to Technical Solution 6, wherein the pattern recognition logic tracks the data stored in the memory device.

[0343] 8. The device according to Technical Solution 6, wherein the pattern recognition logic tracks the data stored in the cache memory device.

[0344] 9. The device according to Technical Solution 6, wherein the pattern recognition logic tracks the data stored in the page table.

[0345] 10. The device according to Technical Solution 5, wherein the pattern tracking logic further includes recording the address locations of each detected sparse data segment.

[0346] 11. The device according to Technical Solution 1 further includes:

[0347] Logic for detecting a compressed sparse matrix; and

[0348] A sparse compression buffer for storing the compressed sparse matrix.

[0349] 12. The device according to Technical Solution 11, wherein the compressed sparse matrix is dynamically generated based on a sparse exponent.

[0350] 13. The device according to Technical Solution 12, wherein the compressed sparse matrix includes the sparse matrices frequently processed by the one or more processing units.

[0351] 14. A device includes:

[0352] A graphics processor including:

[0353] A plurality of execution units (EUs); and

[0354] Logic for partitioning the plurality of EUs and allocating each partition of the EUs to execute threads associated with a neural network layer.

[0355] 15. The device according to Technical Solution 14, wherein the partition of the EUs includes:

[0356] A first partition allocated to execute convolution layer threads;

[0357] A second partition allocated to execute bias layer threads;

[0358] A third partition allocated to execute rectified linear unit layer threads; and

[0359] A fourth partition allocated to execute pooling layer threads.

[0360] 16. The apparatus according to claim 14, wherein the logic for partitioning the plurality of EUs shares execution results between each neural network layer.

[0361] 17. A method for facilitating processing of a sparse matrix, comprising:

[0362] Receiving an operand at a processing element;

[0363] Determining whether one or more of the operands has a zero value; and

[0364] Blocking scheduling of the operand in a multiplication unit when it is determined that the operand has a zero value.

[0365] 18. The method according to claim 17, further comprising scheduling a multiplication including the operand in the multiplication unit when it is determined that the operand has a non - zero value.

[0366] 19. The method according to claim 17, further comprising detecting one or more sparse data segments in a stored data block.

[0367] 20. The method according to claim 19, wherein detecting the one or more sparse data segments in the stored data block comprises performing a bounding box operation on the data block to determine similarity of the data.

[0368] 21. The method according to claim 19, further comprising recording an address location of each detected sparse data segment.

[0369] Some embodiments relate to Example 1, which includes an apparatus for facilitating processing of a sparse matrix, the apparatus including a plurality of processing units each including one or more processing elements, the one or more processing elements including logic for reading an operand, a multiplication unit for multiplying two or more operands, and a scheduler for identifying an operand having a zero value and blocking scheduling of the operand having the zero value in the multiplication unit.

[0370] Example 2 includes the subject matter of Example 1, wherein the scheduler schedules non - zero value operands in the multiplication unit

[0371] Example 3 includes the subject matter described in Examples 1 and 2, where the scheduler retrieves the stored operand value when the operand is received at the logic for reading the operand.

[0372] Example 4 includes the subject matter described in Examples 1 - 3, further including write result logic for writing the result of the product of the two or more operands in the multiplication unit, where the scheduler writes a zero value to the write result logic for an operand having a zero value.

[0373] Example 5 includes the subject matter described in Examples 1 - 4, further including pattern tracking logic for detecting one or more sparse data segments in a stored data block.

[0374] Example 6 includes the subject matter described in Examples 1 - 5, where the pattern tracking logic further includes pattern recognition logic for performing a bounding box operation on the data block to determine the similarity of the data.

[0375] Example 7 includes the subject matter described in Examples 1 - 6, where the pattern recognition logic tracks data stored in a memory device.

[0376] Example 8 includes the subject matter described in Examples 1 - 7, where the pattern recognition logic tracks data stored in a cache memory device.

[0377] Example 9 includes the subject matter described in Examples 1 - 8, where the pattern recognition logic tracks data stored in a page table.

[0378] Example 10 includes the subject matter described in Examples 1 - 9, where the pattern tracking logic further includes logic for recording the address location of each detected sparse data segment.

[0379] Example 11 includes the subject matter described in Examples 1 - 10, further including logic for detecting a compressed sparse matrix, and a sparse compression buffer for storing the compressed sparse matrix.

[0380] Example 12 includes the subject matter described in Examples 1 - 11, where the compressed sparse matrix is dynamically generated based on a sparse index.

[0381] Example 13 includes the subject matter described in Examples 1 - 12, where the compressed sparse matrix includes sparse matrices frequently processed by the one or more processing units.

[0382] Some embodiments relate to Example 14, which includes a device that includes a graphics processor that includes a plurality of execution units (EUs), and logic for partitioning the plurality of EUs and allocating each partition of the EUs to execute threads associated with a neural network layer.

[0383] Example 15 includes the subject matter described in Example 14, wherein the partitioning of the EU includes a first partition assigned to execute threads of a convolutional layer, a second partition assigned to execute threads of a bias layer, a third partition assigned to execute threads of a rectified linear unit layer, and a fourth partition assigned to execute threads of a pooling layer.

[0384] Example 16 includes the subject matter described in Examples 14 and 15, wherein the logic for partitioning the plurality of EUs shares execution results between each neural network layer.

[0385] Some embodiments relate to Example 17, which includes a method for facilitating the processing of a sparse matrix, the method including receiving an operand at a processing element, determining whether one or more of the operands has a zero value, and preventing scheduling of the operand in a multiplication unit when it is determined that the operand has a zero value.

[0386] Example 18 includes the subject matter described in Example 17, further including scheduling a multiplication including the operand in the multiplication unit when it is determined that the operand has a non-zero value.

[0387] Example 19 includes the subject matter described in Examples 17 and 18, further including detecting one or more sparse data segments in a stored data block.

[0388] Example 20 includes the subject matter described in Examples 17 - 19, wherein detecting the one or more sparse data segments in the stored data block includes performing a bounding box operation on the data block to determine similarity of the data.

[0389] Example 21 includes the subject matter described in Examples 17 - 20, further including recording an address location of each detected sparse data segment.

[0390] The foregoing description and drawings are to be considered illustrative rather than restrictive. Those skilled in the art will understand that various modifications and changes can be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

Claims

1. A non-transitory machine-readable medium including instructions that, when executed by one or more processors, cause the one or more processors to perform operations associated with a machine learning framework for facilitating sparse matrix multiplication, the operations including: Load elements of a matrix into a first memory of a graphics processor of the one or more processors, where the first memory is a global memory of the graphics processor; Transfer non-zero value operands of the matrix from the first memory to a second memory of the graphics processor, the second memory being local to a set of processing resources of the graphics processor; And Trigger the execution of a compute kernel on the graphics processor, where the compute kernel will perform a sparse matrix multiplication operation on the non-zero value operands of the matrix, and the machine learning framework enables the compute kernel to specify one or more additional operations to perform on the output before the output of the sparse matrix multiplication is transferred to the first memory, the one or more additional operations including applying an activation function to the output, and the machine learning framework will provide machine learning primitives to enable the compute kernel to specify the one or more additional operations to perform on the output of the sparse matrix multiplication operation, wherein, the one or more additional operations include one or more of bias, activation, and pooling.

2. The non-transitory machine-readable medium of claim 1, wherein the one or more additional operations are performed after the sparse matrix multiplication is completed and when the output is stored in the second memory.

3. The non-transitory machine-readable medium of claim 2, wherein the activation function is a rectified linear unit function.

4. The non-transitory machine-readable medium of claim 2, wherein the one or more additional operations further include performing a bias operation before executing the activation function.

5. The non-transitory machine-readable medium of claim 1, wherein the compute kernel performs the sparse matrix multiplication operation on the non-zero value operands of the matrix via one or more machine learning primitives provided by the machine learning framework.

6. The non-transitory machine-readable medium of claim 5, wherein the machine learning framework provides machine learning primitives to perform 8-bit integer dot products.

7. A data processing system, comprising: A memory device; And One or more processors configured to execute instructions stored in the memory device, where the instructions cause the one or more processors to perform operations associated with a machine learning framework for facilitating sparse matrix multiplication, where the one or more processors include a graphics processor, and the instructions cause the one or more processors to: Load elements of a matrix into a first memory of the graphics processor of the one or more processors, where the first memory is a global memory of the graphics processor; Transfer non-zero value operands of the matrix from the first memory to a second memory of the graphics processor, the second memory being local to a set of processing resources of the graphics processor; And Trigger the execution of a compute kernel on the graphics processor, where the compute kernel will perform a sparse matrix multiplication operation on the non-zero value operands of the matrix, and the machine learning framework enables the compute kernel to specify one or more additional operations to perform on the output before the output of the sparse matrix multiplication is transferred to the first memory, the one or more additional operations including applying an activation function to the output, and the machine learning framework will provide machine learning primitives to enable the compute kernel to specify the one or more additional operations to perform on the output of the sparse matrix multiplication operation, wherein, the one or more additional operations include one or more of bias, activation, and pooling.

8. The data processing system of claim 7, wherein the one or more additional operations are performed after the sparse matrix multiplication is completed and when the output is stored in the second memory.

9. The data processing system of claim 8, wherein the activation function is a rectified linear unit function.

10. The data processing system of claim 8, wherein the one or more additional operations further include performing a bias operation before executing the activation function.

11. The data processing system according to claim 7, wherein the computing core performs the sparse matrix multiplication operation on the non-zero value operands of the matrix via one or more machine learning primitives provided by the machine learning framework.

12. The data processing system according to claim 11, wherein the machine learning framework provides machine learning primitives to perform 8-bit integer dot products.

13. A data processing method, comprising: Load elements of a matrix into a first memory of a graphics processor of one or more processors of a data processing system, where the first memory is a global memory of the graphics processor; Transfer non-zero value operands of the matrix from the first memory to a second memory of the graphics processor, the second memory being local to a set of processing resources of the graphics processor; And Trigger the execution of a compute kernel on the graphics processor, where the compute kernel will perform a sparse matrix multiplication operation on the non-zero value operands of the matrix, and a machine learning framework enables the compute kernel to specify one or more additional operations to be performed on the output before the output of the sparse matrix multiplication is transferred to the first memory, the one or more additional operations including applying an activation function to the output, and the machine learning framework will provide machine learning primitives to enable the compute kernel to specify the one or more additional operations to be performed on the output of the sparse matrix multiplication operation, wherein, the one or more additional operations include one or more of bias, activation, and pooling.

14. The method according to claim 13, wherein the one or more additional operations are performed after the sparse matrix multiplication is completed and when the output is stored in the second memory.

15. The method according to claim 14, wherein the activation function is a rectified linear unit function.

16. The method according to claim 14, wherein the one or more additional operations further include performing a bias operation before performing the activation function.

17. The method according to claim 13, wherein the computing core performs the sparse matrix multiplication operation on the non-zero value operands of the matrix via one or more machine learning primitives provided by the machine learning framework.

18. The method according to claim 17, wherein the machine learning framework provides machine learning primitives to perform 8-bit integer dot products.

19. A data processing system, comprising components for performing any of the methods of claims 13 to 18.

20. A data processing device, comprising: A component for loading elements of a matrix into a first memory of a graphics processor of one or more processors of a data processing system, where the first memory is the global memory of the graphics processor; A component for transferring the non-zero value operands of the matrix from the first memory to a second memory of the graphics processor, the second memory being local to a set of processing resources of the graphics processor; and A component for triggering the execution of a compute kernel on the graphics processor, where the compute kernel will perform a sparse matrix multiplication operation on the non-zero value operands of the matrix, and a machine learning framework enables the compute kernel to specify one or more additional operations to be performed on the output before the output of the sparse matrix multiplication is transferred to the first memory, the one or more additional operations including applying an activation function to the output, and the machine learning framework will provide machine learning primitives to enable the compute kernel to specify the one or more additional operations to be performed on the output of the sparse matrix multiplication operation, wherein, the one or more additional operations include one or more of bias, activation, and pooling.

21. The device according to claim 20, further comprising components for performing the one or more additional operations after the sparse matrix multiplication is completed and when the output is stored in the second memory.

22. The device according to claim 21, wherein the activation function is a rectified linear unit function.

23. The apparatus as claimed in claim 21, wherein the one or more additional operations further include performing a bias operation before performing the activation function.

24. The apparatus as claimed in claim 20, wherein the compute core performs the sparse matrix multiplication operation on the non-zero value operands of the matrix via one or more machine learning primitives provided by the machine learning framework.

25. The apparatus as claimed in claim 24, wherein the machine learning framework provides machine learning primitives to perform 8-bit integer dot products.

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