Semiconductor Structure and Method of Manufacturing the Same

Abstract

Embodiments of the present invention relate to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first redistribution structure, wherein the first redistribution structure includes a first conductive pattern. The semiconductor structure further includes a die on the first redistribution structure. The semiconductor structure further includes a molding on the first redistribution structure, wherein the molding surrounds the die, and the molding has a first dielectric constant. The semiconductor structure further includes a dielectric component extending through the molding, wherein the dielectric component has a second dielectric constant different from the first dielectric constant. The semiconductor structure further includes a second redistribution structure on the die, the dielectric component, and the molding, wherein the second redistribution layer includes an antenna on the dielectric component, and the antenna is electrically connected to the die.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of manufacturing the same. Background Art

[0002] Semiconductor devices are continuously getting smaller while having more functions and more integrated circuit systems. To adapt to the miniaturization scale of semiconductor devices, integrated circuits have become an effective alternative to further reduce the physical size of semiconductor devices. The wafer-level packaging (WLP) process is widely used due to its low cost and relatively simple manufacturing operations.

[0003] Various technologies and applications have been developed for wafer-level packaging, which involve a large number of different components with different materials. For example, millimeter (mm) wave antennas with RF integrated circuits (ICs) are used in high-frequency applications. Summary of the Invention

[0004] Embodiments of the present invention relate to a semiconductor structure, comprising: a first redistribution structure, wherein the first redistribution structure includes a first conductive pattern; a die on the first redistribution structure; a molding on the first redistribution structure, wherein the molding surrounds the die, and the molding has a first dielectric constant; a dielectric component extending through the molding, wherein the dielectric component has a second dielectric constant different from the first dielectric constant; and a second redistribution structure on the die, the dielectric component, and the molding, wherein the second redistribution layer includes an antenna on the dielectric component, and the antenna is electrically connected to the die.

[0005] Embodiments of the present invention relate to a semiconductor structure, comprising: a first redistribution structure; a molding on the first redistribution structure, wherein the molding has a first dielectric constant; a die surrounded by the molding; a plurality of dielectric components surrounded by the molding, wherein the dielectric constant of each of the plurality of dielectric components is different from the first dielectric constant; and a second redistribution structure on the die, wherein the second redistribution structure includes a plurality of antenna structures, each of the plurality of antenna structures is electrically connected to the die, and each of the plurality of antenna structures is on a corresponding dielectric component of the plurality of dielectric components.

[0006] Embodiments of the present invention relate to a method of forming a semiconductor structure, which includes: forming a first redistribution structure including a first conductive pattern; placing a die on the first redistribution structure; placing a molding material on the first redistribution structure to surround the die; removing a portion of the molding material to form an opening; placing a dielectric material into the opening to form a dielectric component; and forming a second redistribution structure on the molding material and the dielectric component, wherein the second redistribution structure includes an antenna structure on the dielectric component and electrically connected to the die. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, various components are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various components may be arbitrarily increased or decreased.

[0008] Figure 1 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present invention.

[0009] Figure 2 is along Figure 1 a schematic cross-sectional view taken along line A-A in

[0010] Figure 3 and Figure 4 is a schematic perspective view of an antenna structure of a semiconductor structure in accordance with some embodiments of the present invention.

[0011] Figures 5 to 7 is a schematic top view of a portion of a semiconductor structure in accordance with some embodiments of the present invention.

[0012] Figure 8 is a flowchart of a method for forming a semiconductor structure in accordance with some embodiments of the present invention.

[0013] Figures 9 to 28 is a schematic cross-sectional view of one or more stages of a method in accordance with some embodiments of the present invention. DETAILED DESCRIPTION

[0014] Numerous different embodiments or instances are disclosed below that provide for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on a second component can include embodiments in which the first component and the second component are formed in direct contact, and can also include embodiments in which additional components can be formed between the first component and the second component such that the first component and the second component do not directly contact. Additionally, the disclosure may repeat element symbols and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", and the like may be used herein to describe the relationship of an element or component to another (some) element or component, as illustrated in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein may thus be interpreted accordingly.

[0016] As used herein, although terms such as "first", "second", and "third" describe various elements, components, regions, layers, and / or sections, such elements, components, regions, layers, and / or sections should not be limited by such terms. Such terms may be used only to distinguish one element, component, region, layer, or section from another. The terms such as "first", "second", and "third" used herein do not imply a sequence or order unless the context clearly indicates otherwise.

[0017] Although the numerical ranges and parameters setting forth the broad scope of the present invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the corresponding testing measurements. In addition, as used herein, the terms "substantially", "approximately" and "about" generally mean within the values or ranges expected by one of ordinary skill in the art. Alternatively, the terms "substantially", "approximately" and "about" mean within the acceptable standard error of the mean as considered by one of ordinary skill in the art. One of ordinary skill in the art will appreciate that the acceptable standard error may vary depending on the technology. Except in the operating / working examples, or unless otherwise expressly specified, all numerical ranges, amounts, values and percentages disclosed herein (e.g., numerical ranges, amounts, values and percentages of material quantities, durations, temperatures, operating conditions, ratios and the like) should be understood to be modified in all instances by the term "substantially", "approximately" or "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and the appended claims are approximations that may vary according to the desired application. Finally, each numerical parameter should be construed in light of the number of significant digits reported and by applying ordinary rounding techniques. Ranges may be expressed herein as from one endpoint to another endpoint or between two endpoints. Unless otherwise specified, all ranges disclosed herein include the endpoints.

[0018] Other features and processes may also be included. For example, test structures may be included to assist in the verification testing of 3D packaging or 3DIC devices. The test structures may include, for example, test pads formed in the redistribution layer or on the substrate to allow testing of the 3D packaging or 3DIC, using probes and / or probe cards and the like. Verification testing may be performed on intermediate structures and final structures. Additionally, the structures and methods disclosed herein may be used in combination with test methods for intermediate verification of known good dies to improve yield and reduce costs.

[0019] In the present disclosure, a semiconductor structure and a method of manufacturing the same are provided. Specifically, a semiconductor structure having one or more antenna structures will be described below. Additionally, a method of forming a semiconductor structure including one or more antenna structures will also be provided below. Other features and processes may also be included. The semiconductor structure includes a dielectric component configured to resonate with the antenna structure. The dielectric component provided according to some embodiments of the present invention may increase the reflection coefficient of the antenna structure in the semiconductor structure, particularly in high-frequency applications employing antenna efficiency at 5.8 GHz or higher frequencies. The dielectric component also helps to reduce unwanted coupling between the antenna structure and adjacent circuits, and prevents unwanted noise from the circuit from reaching the antenna structure. In addition, the resonant frequency of the antenna structure may be tuned as desired by adjusting the size of the dielectric component or the material used to form the dielectric component.

[0020] Figure 1 is a schematic top view of a semiconductor structure 100 in accordance with aspects of the present invention in some embodiments. Figure 2 is a schematic cross-sectional view of the semiconductor structure 100 in accordance with aspects of the present invention taken along Figure 1 line A-A.

[0021] In some embodiments, with reference to Figure 1 and Figure 2 , the semiconductor structure 100 includes: a first redistribution structure 110 that includes a first conductive pattern 111; a die 120 placed on the first redistribution structure 110; and a molding 130 placed on the first redistribution structure 110 and surrounding the die 120. In some embodiments, the semiconductor structure 100 further includes: a dielectric component 134 that extends through the molding 130; a first conductive via 131 that extends through the molding 130 and is placed adjacent to the dielectric component 134; and a second redistribution structure 140 that includes a second conductive pattern 141 placed on the die 120, the dielectric component 134, and the molding 130. The second conductive pattern 141 includes an antenna structure 144 placed on the dielectric component 134 and electrically connected to the die 120. In some embodiments, the dielectric constant (k) of the dielectric component 134 is substantially different from the dielectric constant of the molding 130. The semiconductor structure 100 is suitably configured to meet the specifications of future fourth-generation (5.8 GHz) and fifth-generation (including 12 GHz or 38 GHz) high-frequency RF transceivers in mobile communication applications.

[0022] In some embodiments, the first redistribution structure 110 includes any number of dielectric layers, metallization patterns, and vias. In some embodiments, the first redistribution structure 110 is a backside redistribution layer (RDL). In some embodiments, the first redistribution structure 110 includes a first dielectric layer 112. In some embodiments, the first dielectric layer 112 includes a polymer such as, for example, polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), amide buildup film (ABF), solder resist (SR), or the like. In some embodiments, the first dielectric layer 112 is a planar layer having a uniform thickness, where the thickness is between about 2 micrometers (μm) and about 40 μm. In some embodiments, the thickness is between about 5 μm and about 40 μm. The top and bottom surfaces of the first dielectric layer 112 are also planar. In some embodiments, the first dielectric layer 112 serves as a protective insulator of the semiconductor structure 100. In some embodiments, the first dielectric layer 112 includes a plurality of sub-dielectric layers. In some embodiments, the materials included in the sub-dielectric layers are the same material or different materials.

[0023] In some embodiments, the first conductive pattern 111 of the first redistribution structure 110 is formed on the first dielectric layer 112. In some embodiments, the first conductive pattern 111 comprises aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof. In some embodiments, the first conductive pattern 111 is a wiring pattern. In some embodiments, the first conductive pattern 111 comprises a ground metal pattern. In some embodiments, the thickness of the first conductive pattern 111 ranges from about 1 μm to about 40 μm. In some embodiments, as the thickness of the first conductive pattern 111 increases, the cost becomes too high. In some embodiments, as the thickness of the first conductive pattern 111 decreases, the resistance of the first conductive pattern 111 becomes too high. In some embodiments, the thickness of the first conductive pattern 111 ranges from about 1 μm to about 20 μm. In some embodiments, the thickness of the first conductive pattern 111 ranges from about 2 μm to about 8 μm. In some embodiments, the thickness of the first conductive pattern 111 is about 7 μm to minimize the resistance of the first conductive pattern 111. In some embodiments, a seed layer (not shown) is disposed between the first dielectric layer 112 and the first conductive pattern 111. In some embodiments, the seed layer blankets the first conductive pattern 111 and is conformal with the first conductive pattern 111. In some embodiments, the seed layer comprises a titanium / copper composite layer.

[0024] In some embodiments, a plurality of first conductive patterns 111 are disposed on the first dielectric layer 112. For clarity and simplicity, Figure 1 and Figure 2 only two first conductive patterns 111 are shown, but this example is for illustrative purposes only and is not intended to limit the embodiments. Those of ordinary skill in the art will readily understand that any suitable number of first conductive patterns 111 may alternatively be utilized, and all such combinations are fully intended to be included within the scope of the embodiments. Additionally, the first conductive patterns 111 have similar characteristics; this is for illustrative purposes only and is not intended to limit the embodiments, as in some embodiments, the first conductive patterns 111 have similar or different structures to meet the desired functional capabilities.

[0025] One or more dies 120 are attached to the first redistribution structure 110. For simplicity and illustration, Figure 1 and Figure 2Only one die 120 is shown; however, in some embodiments, the die 120 in the figure represents one or more dies 120. In some embodiments, the die 120 is placed on the first dielectric layer 112. In some embodiments, the die 120 is adjacent to the first conductive pattern 111. In some embodiments, the die 120 is a radio frequency (RF) integrated circuit (IC) die. The die 120 has a back surface 120a and a front surface 120b opposite to the back surface 120a. In some embodiments, the back surface 120a of the die 120 is attached (or adhered) to the first redistribution structure 110 through an adhesive layer 121. In some embodiments, the adhesive layer 121 includes a die attach film (DAF) or another material having adhesive properties. The front surface 120b of the die 120 faces the second redistribution structure 140.

[0026] In some embodiments, the die 120 includes a semiconductor substrate 122 whose back surface is the back surface 120a of the die 120 and is in contact with the adhesive layer 121. In some embodiments, the die 120 includes a plurality of conductive pads 123 placed on the semiconductor substrate 122 and a plurality of conductive pillars 124 exposed from the front surface 120b of the die 120 and configured to electrically connect the die 120 to other conductive devices and / or interconnect structures in the semiconductor structure 100.

[0027] In some embodiments, the semiconductor substrate 122 is a silicon substrate including active components (such as transistors or the like) and passive components (such as resistors, capacitors, inductors or the like) formed therein. In some embodiments, the conductive pads 123 are aluminum pads, copper pads or other suitable metal pads. In some embodiments, the conductive pillars 124 are made of a conductive material and placed on the conductive pads 123. For example, in some embodiments, the material of the conductive pillars 124 includes copper, copper alloy or the like. A die dielectric layer 125 is placed between the conductive pillars 124 and exposed from the front surface 120b of the die 120. In some embodiments, the top surface of the die dielectric layer 125 and the top surface of the conductive pillars 124 are at the same level. In some embodiments, the top surface of the die dielectric layer 125 is at a level higher than the top surface of the conductive pillars 124. However, the present disclosure is not limited thereto.

[0028] The molded part 130 is placed on the first redistribution structure 110. In some embodiments, the molded part 130 surrounds or encapsulates the first conductive via 131 and the die 120. In some embodiments, the molded part 130 fills the gap between the die 120 and the first conductive via 131 and contacts a portion of the first conductive pattern 111 and the first dielectric layer 112. In some embodiments, the top surface of the molded part 130 is generally at the same level as the top surface of the conductive pillars 124 of the die 120. In some embodiments, the molded part 130 comprises a molding compound, a polymeric compound, an underfill material, a resin, an epoxy resin, or the like. In some embodiments, the molded part 130 comprises a filler. In some embodiments, the molded part 130 has a dielectric constant (k) less than or equal to 3.0, preferably between 2.8 and 3.0. In some embodiments, the molded part 130 comprises a high-k or low-k dielectric material.

[0029] In some embodiments, the first conductive via 131 is placed on the first redistribution structure 110 and adjacent to the die 120.

[0030] In some embodiments, the first conductive via 131 extends generally perpendicular to the first conductive pattern 111. In some embodiments, the first conductive via 131 is a through-insulating via (TIV) that extends through the molded part 130. In some embodiments, the height of the first conductive via 131 is between about 100 μm and about 500 μm. In some embodiments, as the height of the first conductive via 131 increases, the process parameters of the current process become inapplicable. In some embodiments, as the height of the first conductive via 131 decreases, the resistance of the first conductive via 131 becomes too high. In some embodiments, the height of the first conductive via 131 is between about 120 μm and about 250 μm. In some embodiments, as the width of the first conductive via 131 increases, the process parameters of the current process become inapplicable. In some embodiments, as the width of the first conductive via 131 decreases, the resistance of the first conductive via 131 becomes too high. In some embodiments, the width (or diameter) of the first conductive via 131 is about 100 μm to about 200 μm. In some embodiments, the width of the first conductive via 131 is about 150 μm.

[0031] In some embodiments, the semiconductor structure 100 comprises a plurality of first conductive vias 131. In some embodiments, the first conductive vias 131 are placed at one or more sides of the die 120. In some embodiments, Figure 2In the cross-sectional view shown, die 120 is placed between first conductive vias 131 such that the first conductive vias 131 are placed on two opposite sides of die 120. In some embodiments, the front surface 120b of die 120 is generally coplanar with the top surface 131t of the first conductive vias 131 or at a level below or above the top surface 131t of the first conductive vias 131. In some embodiments, the first conductive vias 131 surround die 120. At least one of the first conductive vias 131 is placed along one side of die 120. Those of ordinary skill in the art will understand that Figure 2 the number of the first conductive vias 131 in

[0032] is merely illustrative, and the number of the first conductive vias 131 can vary based on the design of the semiconductor device 100. In some embodiments, the semiconductor structure 100 further includes second conductive vias 132. In some embodiments, the second conductive vias 132 are placed on the first redistribution structure 110 and adjacent to the first conductive vias 131 and die 120. In some embodiments, the second conductive vias 132 extend generally perpendicular to the first conductive pattern 111. In some embodiments, a plurality of second conductive vias 132 are placed at one or more sides of die 120. In some embodiments, the second conductive vias 132 are also referred to as TIVs extending through the molding 130. In some embodiments, the height of the second conductive vias 132 is between about 100 μm and about 500 μm. In some embodiments, as the height of the second conductive vias 132 increases, the process parameters of the current process become inapplicable. In some embodiments, as the height of the second conductive vias 132 decreases, the resistance of the second conductive vias 132 becomes too high. In some embodiments, the height of the second conductive vias 132 is between about 120 μm and about 250 μm. In some embodiments, as the width of the second conductive vias 132 increases, the process parameters of the current process become inapplicable. In some embodiments, as the width of the second conductive vias 132 decreases, the resistance of the second conductive vias 132 becomes too high. In some embodiments, the width (or diameter) of the second conductive vias 132 is about 100 μm to about 200 μm. In some embodiments, the width of the second conductive vias 132 is about 150 μm. In some embodiments, the first conductive vias 131 and the second conductive vias 132 have a similar structural configuration.

[0033] In some embodiments, the first conductive via 131 is electrically connected to the first conductive pattern 111 of the first redistribution structure 110. In some embodiments, the first conductive via 131 is isolated from the second conductive pattern 141 of the second redistribution structure 140. In some embodiments, the second conductive via 132 is electrically connected to the first conductive pattern 111 of the first redistribution structure 110 and the second conductive pattern 141 of the second redistribution structure 140. In some embodiments, the second conductive via 132 is connected between the first conductive pattern 111 and the second conductive pattern 141 and is further electrically connected to an interconnect structure such as a conductive bump 150.

[0034] In some embodiments, the seed layer 133 is placed between the first conductive via 131 and the molding 130 and / or between the second conductive via 132 and the molding 130. In some embodiments, the seed layer 133 is placed between the first conductive via 131 and the first conductive pattern 111. In some embodiments, the seed layer 133 is placed between the second conductive via 132 and the first conductive pattern 111. In some embodiments, the seed layer 133 is blanket-coated on the corresponding first conductive via 131 and is conformal to the corresponding first conductive via 131. In some embodiments, the seed layer 133 is blanket-coated on the corresponding second conductive via 132 and is conformal to the corresponding second conductive via 132. In some embodiments, the seed layer 133 includes a titanium / copper composite layer.

[0035] In some embodiments, the dielectric component 134 extending through the molding 130 is placed on the first conductive pattern 111. In some embodiments, the dielectric component 134 is placed on the molding 130. In some embodiments, the dielectric component 134 is in contact with the first conductive pattern 111. In some embodiments, the dielectric component 134 is adjacent to the first conductive via 131. In some embodiments, the dielectric component 134 is placed between the first conductive vias 131. Those of ordinary skill in the art should understand that Figure 1 the number of the dielectric components 134 shown is only for illustrative purposes, and the number of the first conductive vias 131 can vary based on the design of the semiconductor device 100. Those of ordinary skill in the art should readily understand that any suitable number of dielectric components 134 can be alternatively utilized, and all such combinations are fully intended to be included within the scope of the embodiments. Additionally, the dielectric components 134 have similar features; this is for illustrative purposes and not intended to limit the embodiments, because in some embodiments, the dielectric components 134 have similar structures or different structures to meet the desired functional capabilities. In some embodiments, both the dielectric component 134 and the first conductive via 131 are surrounded by the molding 130.

[0036] In some embodiments, the configuration and size of the dielectric component 134 depend on the material of the dielectric component 134, the material of the molded part 130, and the configuration and size of the antenna structure 144. In some embodiments, the dielectric component 134 has a dielectric constant different from that of the molded part 130. In some embodiments, the dielectric constant of the dielectric component 134 is substantially greater than that of the molded part 130. In some embodiments, the dielectric constant of the dielectric component 134 is substantially equal to or greater than 3. In some embodiments, the dielectric constant of the dielectric component 134 is equal to or greater than 4. In some embodiments, the dielectric constant of the dielectric component 134 is equal to or greater than 7. In some embodiments, the dielectric constant of the dielectric component 134 is equal to or greater than 10. In some embodiments, the dielectric constant of the dielectric component 134 is equal to or greater than 80. In some embodiments, the dielectric constant of the dielectric component 134 is equal to or greater than 100. In some embodiments, the dielectric constant of the dielectric component 134 is equal to or greater than 200 to help optimize the size reduction of the dielectric component 134. The greater the dielectric constant of the dielectric component 134, the smaller the size of the dielectric component 134 can be. In some embodiments, the dielectric component 134 includes SiO 2 , SiN x , SiO x N y , ZrO 2 , Al 2 O 3 , HfO x , HfSiO x , ZrTiO x , TiO 2 , TaO x , SrTiO 3 , BaTiO 3 , BaSrTiO 3 , PbZrTiO 3 , high-k polymers, or combinations thereof.

[0037] In some embodiments, a plurality of first conductive vias 131 are placed along the periphery of the dielectric component 134. Figure 3 And Figure 4 are perspective views of portions of the semiconductor structure 100. Referring to Figure 3 , in some embodiments, each of the first conductive vias 131 is formed as a single continuous wall structure electrically connected to the first conductive pattern 111 to enclose the dielectric component 134 under the antenna structure 144. In some embodiments, the dielectric component 134 has a square shape in a top view. In some embodiments, the dielectric component 134 is (but not limited to) circular, oval, rectangular, square, or other shapes in a top view.

[0038] In some embodiments, referring to Figure 4 , the dielectric component 134 is surrounded by a plurality of first conductive vias 131, and the plurality of first conductive vias 131 together define the periphery of the dielectric component 134. The spacing S between adjacent first conductive vias 131 can be adjusted according to the wavelength of the signal that the antenna structure 144 is desired to transmit or receive during operation. In some embodiments, the spacing S is about 10 μm. In some embodiments, the spacing S between a pair of adjacent first conductive vias 131 is different from the spacing S between different pairs of adjacent first conductive vias 131. The space between the first conductive vias 131 is filled with a molding 130. In some embodiments, two or more first conductive vias 131 are continuous segments that together enclose the dielectric component 134.

[0039] Returning to the reference Figure 1 and Figure 2 , a second redistribution structure 140 including a second conductive pattern 141 is placed on the die 120, the dielectric component 134, the molding 130, the first conductive vias 131, and the second conductive vias 132. In some embodiments, the second conductive pattern 141 includes a wiring pattern at least partially on the die 120 and / or a wiring pattern at least partially on the molding 130. The second redistribution structure 140 provides an electrical connection between the die 120 and an interconnect structure (such as conductive bumps 150 placed on the second redistribution structure 140). The conductive bumps 150 can provide an electrical connection to a next-level package, such as (for example) a printed circuit board (PCB) or an interposer. In some embodiments, the first conductive pattern 111 of the first redistribution structure 110 is electrically connected to the conductive bumps 150 through the second conductive pattern 141 of the second redistribution structure 140. In some embodiments, the conductive bumps 150 include solder.

[0040] In some embodiments, the second redistribution structure 140 includes any number of dielectric layers, metallization patterns, and vias. In some embodiments, the second redistribution structure 140 includes a second dielectric layer 142. In some embodiments, the second dielectric layer 142 includes a polymer, which can be (for example) polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), accumulative film of flavor enhancer (ABF), solder resist (SR), or the like.

[0041] In some embodiments, the second conductive pattern 141 of the second redistribution structure 140 is placed in the second dielectric layer 142. In some embodiments, the second conductive pattern 141 includes aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof. In some embodiments, the second conductive pattern 141 is a wiring pattern.

[0042] In some embodiments, the second redistribution structure 140 includes a first redistribution layer 145, a second redistribution layer 146, and a third redistribution layer 147, each of which includes a plurality of conductive patterns. Those of ordinary skill in the art will understand that Figure 2 the number of redistribution layers shown in Figure 2 is merely illustrative and may include a different number of redistribution layers. Each of the first redistribution layer 145, the second redistribution layer 146, and the third redistribution layer 147 includes a redistribution line (RDL) and vias, where the RDL and vias are metal patterns that provide electrical interconnections through and within the second redistribution structure 140. In some embodiments, the RDL and vias include copper. In the first redistribution layer 145, a first-level conductor 145c and a first-level via 145v provide interconnections. In the first redistribution layer 145, a first insulating layer 145i is placed on the first-level conductor 145c, die 120, dielectric component 134, molding 130, first conductive via 131, and TIV 132. In the second redistribution layer 146, a second-level conductor 146c and a second-level via 146v provide interconnections. In the second redistribution layer 146, a second insulating layer 146i is placed on the second-level conductor 146c. In the third redistribution layer 147 (which is the last redistribution layer), a third-level conductor 147c and an under-bump metal (UBM) pad 147p provide interconnections. Conductive bumps 150 are formed on the UBM pad 147p. In the third redistribution layer 147, a third insulating layer 147i is provided on the second insulating layer 146i.

[0043] The second conductive pattern 141 includes one or more antenna structures 144 placed on the dielectric component 134 and electrically connected to the die 120. In some embodiments, the antenna structures 144 are correspondingly placed on a plurality of dielectric components 134 and electrically connected to the die 120. In some embodiments, two antenna structures 144 are placed opposite each other, and in Figure 1 a top view, the die 120 is placed between the two antenna structures 144. In some embodiments, in a top view like Figure 1 the antenna structures 144 surround the die 120. Those of ordinary skill in the art will readily understand that in some embodiments, alternatively, any suitable number of antenna structures 144 may be utilized, and all such combinations are fully intended to be included within the scope of the embodiments. Additionally, the antenna structures 144 have similar characteristics; this is for illustration and not intended to limit the embodiments, as in some embodiments, the antenna structures 144 have similar or different structures to meet the desired functional capabilities.

[0044] In some embodiments, the antenna structure 144 is configured to radiate electromagnetic radiation for wireless transmission or receive electromagnetic radiation for wireless reception, and the dielectric component 134 is configured to improve the antenna performance and efficiency in high-frequency applications. In some embodiments, the antenna structure 144 is a patch antenna. In some embodiments, the patch antenna is a microstrip antenna including a flat rectangular metal sheet or "patch" mounted on a larger metal sheet called a ground plane (e.g., the first conductive pattern 111). In some embodiments, the antenna structure 144 is a transceiver.

[0045] Each antenna structure 144 corresponds to a dielectric component 134 below the corresponding antenna structure 144. In some embodiments, the second conductive pattern 141 includes conductive lines 143 that electrically couple the antenna structure 144 to the die 120. In some embodiments, the conductive lines 143 extend from each antenna structure 144 to the die 120.

[0046] In some embodiments, the antenna structure 144 is placed in one of the first redistribution layer 145, the second redistribution layer 146, and the third redistribution layer 147. In some embodiments, the antenna structure 144 is placed in the second redistribution layer 146. The antenna structure 144 is isolated from the dielectric component 134. In some embodiments, a first insulating layer 145i is placed between the dielectric component 134 and the antenna structure 144 and is configured to isolate the antenna structure 144 from the dielectric component 134. The dielectric component 134 is sandwiched between the antenna structure 144 and the first conductive pattern 111.

[0047] Figures 5 to 7 is a schematic diagram of a part of the semiconductor structure 100. Refer to Figure 1 、 Figure 2 、 Figures 5 to 7 and, from a top-down perspective, the dielectric component 134 overlaps the antenna structure 144. In some embodiments, the antenna structure 144 covers the dielectric component 134 in a top view. In some embodiments, the width W 134 of the dielectric component 134 is generally less than or equal to the width of the antenna structure 144. In some embodiments, the higher the dielectric constant of the dielectric component 134, the 134 smaller the width W of the dielectric component 134 can be. In some embodiments, the surface area of the dielectric component 134 is generally less than or equal to the surface area of the antenna structure 144. In some embodiments, when the difference between the dielectric constants k of the dielectric component 134 and the antenna structure 144 is large, the difference between the surface areas of the dielectric component 134 and the antenna structure 144 is also large. In some embodiments, as the dielectric constant k of the dielectric component 134 increases, the surface area of the dielectric component 134 decreases. In some embodiments, as in Figures 5 to 7In a top view thereof, a first conductive path 131 disposed along the periphery of the dielectric component 134 overlaps with the antenna structure 144.

[0048] In some embodiments, as Figure 5 , the first conductive path 131 is a continuous segment that together encloses the dielectric component 134 below the antenna structure 144. The spacing S between a pair of adjacent first conductive paths 131 is substantially equal to the spacing S between other pairs of adjacent first conductive paths 131. In some embodiments, referring to Figure 6 , the first conductive path 131 is a discontinuous segment and is placed adjacent to the corners of the dielectric component 134. In some embodiments, as Figure 7 , the first conductive path 131 is a discontinuous segment that together encloses the dielectric component 134 below the antenna structure 144. In some embodiments, the spacing S between a pair of adjacent first conductive paths 131 is different from the spacing S between other pairs of adjacent first conductive paths 131.

[0049] Figure 8 is a flowchart of a method 200 for forming a semiconductor structure according to some embodiments of the present invention. Method 200 includes the following operations: (201) forming a first redistribution structure including a first conductive pattern; (202) forming a plurality of conductive paths on the first redistribution structure; (203) placing a die on the first redistribution structure; and (204) placing a molding material on the first redistribution structure to surround the plurality of conductive paths and the die. Method 200 further includes: (205) removing a portion of the molding material to form an opening; (206) placing a dielectric material into the opening to form a dielectric component; and (207) forming a second redistribution structure on the molding material, the plurality of conductive paths, and the dielectric component. The second redistribution structure includes an antenna structure located on the dielectric component and electrically connected to the die.

[0050] Figures 9 to 28 is a schematic cross-sectional view of a semiconductor device formed using method 200 according to some embodiments of the present invention. In some embodiments, method 200 is configured to form a semiconductor structure 100 as shown in Figure 1 and Figure 2 . Referring to Figure 9 , a support substrate 113 is provided on which an adhesive layer 114 is placed. In some embodiments, the adhesive layer 114 is formed on the top surface of the support substrate 113. In some embodiments, the support substrate 113 is a glass substrate and the adhesive layer 114 is a light-to-heat conversion (LTHC) release layer applied on the support substrate 113. However, the present disclosure is not limited thereto. In some alternative embodiments, other suitable materials are applicable to the support substrate 113 and the adhesive layer 114.

[0051] As shown in Figure 10, a first dielectric layer 112 is formed on the adhesive layer 114. In some embodiments, the first dielectric layer 112 is formed by a suitable manufacturing technique such as spin coating, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or the like. In some embodiments, the first dielectric layer 112 is a single layer or multiple layers stacked on each other. In some embodiments, the first dielectric layer 112 comprises a polymeric material. In some embodiments, the polymeric material comprises low temperature polyimide (LTPI), epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. In some embodiments, the polymeric material is dissolved in a solvent to enhance coating fluidity. In some embodiments, after the polymeric material is uniformly coated on the adhesive layer 114, a curing process is performed to evaporate the solvent. For example, in some embodiments, the first dielectric layer 112 is cured by a soft baking process.

[0052] As Figure 11 , a plurality of first conductive patterns 111 are formed on the first dielectric layer 112. The first conductive patterns 111 are formed by (for example) electroplating, deposition, and / or photolithography and etching. In some embodiments, the first conductive patterns 111 are formed by the following process. First, a seed layer (not shown) is formed blanketly on the first dielectric layer 112. In some embodiments, the seed layer comprises a titanium / copper composite layer and is formed by a sputtering process. Then, a first mask pattern with openings (not shown) is formed on the seed layer. The openings of the first mask pattern expose the desired positions for the subsequently formed first conductive patterns 111. Then, a plating process is performed to form a conductive material layer on the portions of the seed layer exposed by the openings of the first mask pattern. In some embodiments, the conductive material layer comprises aluminum, titanium, copper, nickel, tungsten, and / or an alloy thereof. Then, the first mask pattern and the seed layer are removed by a lift-off process and / or an etching process. Then, the remaining seed layer and the remaining conductive material layer constitute the first conductive patterns 111. In some embodiments, the first conductive patterns 111 are formed with a height H between about 1 μm and about 40 μm 111 of the first conductive patterns 111. In some embodiments, as the height H 111 of the first conductive patterns 111 increases, the cost will be too high. In some embodiments, as the height H 111 of the first conductive patterns 111 decreases, the resistance of the first conductive patterns 111 will be too high.

[0053] Refer to Figure 12, a first patterned photoresist 302 is applied to the exposed portions of the first conductive pattern 111 and the first dielectric layer 112. In some embodiments, the first patterned photoresist 302 includes a first groove 303. The first groove 303 exposes some portions of the first conductive pattern 111. In some embodiments, a first patterned photoresist 302 having a height H between about 100 μm and about 500 μm is formed. 302 In some embodiments, as the height H of the first patterned photoresist 302 302 increases, the cost of the first patterned photoresist 302 becomes too high. In some embodiments, as the height H of the first patterned photoresist 302 302 decreases, the process parameters of the current process become inapplicable. In some embodiments, a first conductive via 131 and a second conductive via 132 are formed within the first groove 303. In some embodiments, the first groove 303 has a depth between about 50 μm and about 500 μm. In some embodiments, the depth of the first groove 303 varies with the height H of the first patterned photoresist 302. 302 In some embodiments, as the depth of the first groove 303 increases, the cost of the first patterned photoresist 302 becomes too high. In some embodiments, as the depth of the first groove 303 decreases, the process parameters of the current process become inapplicable. In some embodiments, the depth of the first groove 303 ranges from about 120 μm to about 250 μm. In some embodiments, the depth of the first groove 303 is 180 μm. The depth of the first groove 303 is determined based on the thickness of the first patterned photoresist 302.

[0054] In some embodiments, on Figure 12 a structure, a seed layer (not shown) having a thickness between 1000 angstroms and is formed to prepare for electroplating deposition of the first conductive via 131 and the second conductive via 132. In some embodiments, as the thickness of the seed layer increases, the cost of the seed layer becomes too high. In some embodiments, as the thickness of the seed layer decreases, the process parameters of the current process become inapplicable. In some embodiments, the seed layer covers the surface of the first patterned photoresist 302 and the exposed portions of the first redistribution structure 110, such as the first conductive pattern 111 at the bottom of the first groove 303.

[0055] Refer to Figure 13, in some embodiments, the conductive material 138 is deposited into the first groove 303 through a plating process. The first groove 303 is filled with the conductive material 138 to form the first conductive path 131 and the second conductive path 132. In some embodiments, the plating process includes, for example, electroplating, electroless plating, immersion plating, or the like. However, the present disclosure is not limited thereto. In some embodiments, the conductive material 138 includes, for example, copper, copper alloy, or the like. In some embodiments, on the seed layer, the first groove 303 in the first photoresist 302 is filled with the conductive material 138 through plating (which is electroplating or electroless plating) to form the first conductive path 131 and the second conductive path 132.

[0056] Next, referring to Figure 14 , in some embodiments, the excess portion of the conductive material 138 is removed through a grinding process to expose the top surface of the first patterned photoresist 302. The grinding process includes, for example, a mechanical grinding process, a chemical mechanical polishing (CMP) process, or the like. However, the present disclosure is not limited thereto. In some alternative embodiments, the grinding process is omitted in some embodiments.

[0057] In some embodiments, as Figure 15 , the first patterned photoresist 302 is removed and thus the first conductive path 131 and the second conductive path 132 are formed. In some embodiments, the first patterned photoresist 302 is removed through a stripping process, an etching process, and / or a cleaning process. For example, the first patterned photoresist 302 is removed by applying chemicals such as dimethyl sulfoxide (DMSO), water (H 2 O), and tetramethylammonium hydroxide (TMAH). In some embodiments, after the first patterned photoresist 302 is removed, a portion of the seed layer (not shown) is exposed from the first conductive path 131 and the second conductive path 132. Subsequently, the exposed portion of the seed layer is removed through an etching process. In some embodiments, the etching process includes an anisotropic etching process (such as dry etching) or an isotropic etching process (such as wet etching). In some embodiments, the etchant for wet etching includes a combination of hydrogen fluoride (HF), copper (Cu), and ammonia (NH 3 ), a combination of HF and TMAH, or the like. In some embodiments, the conductive material and the remaining seed layer are collectively referred to as the first conductive path 131 and the second conductive path 132.

[0058] In some embodiments, as Figure 16, the die 120 is placed on the first dielectric layer 112. In some embodiments, the die 120 is attached to the first dielectric layer 112 by a pick-and-place method. For example, the die 120 is attached to a blank wafer (not shown). Then, the blank wafer is flipped so that the die 120 is attached to the first dielectric layer 112. Then, the blank wafer is detached from the die 120, for example, by mechanical stripping. After the die 120 is placed on the first dielectric layer 112, annealing is optionally performed. In some embodiments, an adhesive layer 121 can be used to adhere the die 120 to the first dielectric layer 112. The die 120 can include a semiconductor substrate 122 that contacts the adhesive layer 121. In some embodiments, the conductive pillars 124 of the die 120 are formed as part of the front surface 120b of the die 120. A die dielectric layer 125 is formed at the front surface 120b of the die 120 and fills the space between the conductive pillars 124, where at least the lower portion of the conductive pillars 124 is located in the die dielectric layer 125.

[0059] In some embodiments, referring to Figure 17 , a molding material 139 is applied over the die 120 and the first conductive path 131 and the second conductive path 132, and then the molding material 139 is cured. In some embodiments, the molding material 139 surrounds or encapsulates the die 120 and the first conductive path 131 and the second conductive path 132, and the molding material 139 contacts any exposed portions of the first dielectric layer 112 and the first conductive pattern 111. In some embodiments, the molding material 139 includes a molding compound, which is a liquid epoxy resin, such as a liquid epoxy resin containing fine-grained silica, spin-on glass (SiO 2 )(SOG) or ceramics. A molding compound such as a liquid epoxy resin is suitable for use as a coating and is then cured and hardened at a low temperature (about 180 °C). In some embodiments, the top surface of the molding material 139 is higher than the top surface 120b of the die 120 and the tops of the first conductive path 131 and the second conductive path 132.

[0060] In some embodiments, referring to Figure 18 , the molding material 139 is polished until the top surface 120b of the die 120 and the top surfaces 131t, 132t of the first conductive path 131 and the second conductive path 132 are exposed. In some embodiments, the molding material 139 is polished by a mechanical polishing process and / or a CMP process. In some embodiments, the polishing causes the tops of the conductive pillars 124 and the first conductive path 131 and the second conductive path 132 to be generally flush (coplanar). In some embodiments, the polishing step leaves some metal residues, such as metal particles, on the top surface of the molding material 139. Thus, in some embodiments, after the polishing step, cleaning is performed, for example, by wet etching, to remove the metal residues.

[0061] After grinding the molded material 139, a molded part 130 having a bottom surface 130b and a top surface 130t opposite to the bottom surface 130b is formed. In some embodiments, the molded part 130 is placed on the first redistribution structure 110 to at least laterally encapsulate the die 120. One or more first conductive vias 131 and second conductive vias 132 are placed within the molded part 130 and extend from the first conductive pattern 111 toward the top surface 130t of the molded part 130.

[0062] In some embodiments, referring to Figure 19 , a second patterned photoresist 304 is applied over the molded part 130 and the first conductive vias 131 and second conductive vias 132. A portion of the molded part 130 placed within the opening is removed to form a second recess 306. In some embodiments, the molded part 130 can be removed by a wet etching process. In some embodiments, the second recess 306 is formed between the first conductive vias 131 and exposes some portions of the first conductive pattern 111. The first conductive vias 131 and their associated first conductive pattern 111 define the periphery of the second recess 306.

[0063] In some embodiments, referring to Figure 20 , the second patterned photoresist 304 is removed by a lift-off process, an etching process, and / or a cleaning process. In some embodiments, removing the second patterned photoresist 304 is similar to removing the first patterned photoresist 302, and thus, its repeated description is omitted herein.

[0064] In some embodiments, referring to Figure 21 , a dielectric paste 307 is deposited into the second recess 306 and applied over the die 120, the molded part 130, and the first conductive vias 131 and second conductive vias 132. In some embodiments, the dielectric paste 307 has a dielectric constant k that is substantially greater than the dielectric constant k of the molded part 130. In some embodiments, the dielectric paste 307 can contact the first conductive pattern 111. In some embodiments, the dielectric paste 307 includes SiO 2 , SiN x , SiO x N y , ZrO 2 , Al 2 O 3 , HfO x , HfSiO x , ZrTiO x , TiO 2 , TaO x , SrTiO 3 , BaTiO 3 , BaSrTiO 3 , PbZrTiO3 , a high-k polymer or a combination thereof. In some embodiments, the high-k polymer is PBO, PI, or a combination thereof. In some embodiments, the dielectric paste 307 is in a liquid phase at room temperature. In some embodiments, the dielectric paste 307 is a slurry paste. In some embodiments, the dielectric paste 307 includes a solvent for enhancing the fluidity of the coating. In some embodiments, a dielectric material having a dielectric constant k that is substantially greater than the dielectric constant k of the molded part 130 is deposited to fill the second groove 306 and placed on the molded part 130 and the first conductive path 131 and the second conductive path 132.

[0065] In some embodiments, referring to Figure 22 , a portion of the dielectric paste 307 is removed until the front surface 120b of the die 120 and the top surfaces 131t, 132t of the first conductive path 131 and the second conductive path 132 are exposed. In some embodiments, the portion of the dielectric paste 307 is removed by a squeegee. In some embodiments, the removal causes the top surfaces of the dielectric paste 307, the die 120, and the first conductive path 131 and the second conductive path 132 to be substantially flush (coplanar) with the top surface 130t. In some embodiments, after removing the portion of the dielectric paste 307, a curing process or a hardening process is performed to evaporate the solvent. For example, in some embodiments, the dielectric paste 307 is cured by a soft bake process, and the temperature for curing the dielectric paste 307 is lower than 250°C. In some embodiments, the curing temperature is lower than 210°C and more preferably lower than 180°C.

[0066] After curing the dielectric paste 307 placed in the second groove 306, a dielectric component 134 is formed and placed on the first redistribution structure 110 and between the first conductive path 131 and the molded part 130. In some embodiments, the dielectric component 134 extends from the first conductive pattern 111 to the top surface 130t of the molded part 130.

[0067] In some embodiments, as in Figure 23 , for forming the first-stage conductor 145c of the first redistribution layer 145, a conductive material layer (such as copper) 311 is deposited on the top surface 130t of the molded part 130 by plating such as electroplating or electroless plating. To achieve electroplating, in some embodiments, a seed layer of Ti / Cu having a thickness of to (not shown) is deposited on the top surface 130t, and the conductive material layer 311 is applied on the seed layer. Then, the conductive material layer 311 is patterned and etched to leave the first-stage conductor 145c on the first conductive path 131 and the second conductive path 132 and the conductive posts 124 of the die 120.

[0068] Then, referring to Figure 24, in some embodiments, a first insulating layer 312 (e.g., PBO) is applied to the resulting structure. The first insulating layer 312 has a thickness between about 3 μm and about 20 μm. In some embodiments, as the thickness of the first insulating layer 312 increases, the cost of the first insulating layer 312 becomes too high. In some embodiments, as the thickness of the first insulating layer 312 decreases, the process parameters of the current process become inapplicable. In some embodiments, the first insulating layer 312 has a thickness between about 3 μm and about 7 μm. In some embodiments, the first insulating layer 312 has a thickness of about 6 μm.

[0069] In some embodiments, after forming the second redistribution structure 140, the first insulating layer 312 is patterned and openings for vias are formed, which are then filled with a conductive material (e.g., copper) to form first-level vias 145v, a first insulating layer 145i, and the first redistribution layer 145 is completed. The top surface of the first redistribution layer 145 is polished and planarized. In some embodiments, a second redistribution layer 146 is then formed on the first redistribution layer 145. To form the second redistribution layer 146, a conductive metal layer (e.g., copper) is deposited on the first redistribution layer 145 and then patterned and etched to leave second-level conductors 146c on the first redistribution layer 145.

[0070] In some embodiments, referring to Figure 25 , a second insulating layer (e.g., PBO) 313 is then applied to the resulting structure. In some embodiments, some of the second-level conductors 146c include antenna structures 144. The antenna structures 144 are formed on the dielectric component 134 surrounded by the first conductive vias 131 and the first conductive patterns 111.

[0071] After forming the second redistribution structure 140, the second insulating layer 313 is patterned and openings are formed, which are then filled with a conductive metal (e.g., copper) to form second-level vias 146v, and the second redistribution layer 146 is completed. The top surface of the second redistribution layer 146 is polished and planarized. Then, a third redistribution layer 147 is formed on the second redistribution layer 146. To form the third redistribution layer 147, a conductive metal layer (e.g., copper) is deposited on the second redistribution layer 146 and then patterned and etched to leave third-level conductors 147c on the second redistribution layer 146.

[0072] In some embodiments, referring to Figure 26 , a third insulating layer (e.g., PBO) 314 is then applied to the resulting structure. In some embodiments, the material and formation method of the third insulating layer 314 are similar to those of the first insulating layer 312 and the second insulating layer 313, and thus, for the sake of brevity, their repeated descriptions are omitted herein.

[0073] In some embodiments, referring to Figure 27, after forming the second redistribution structure 140, the third insulating layer 314 is patterned and an opening for a under-bump metal (UBM) pad 147p is formed (which is then filled with a conductive metal to form the UBM pad 147p), and the third redistribution layer 147 is completed.

[0074] In some embodiments, conductive bumps 150 are placed on the UBM pads 147p. In some embodiments, the conductive bumps 150 are attached to the UBM pads 147p by a solder flux. In some embodiments, the conductive bumps 150 are placed on the second redistribution structure 140 by a ball placement process and / or a reflow process. In some embodiments, forming the conductive bumps 150 includes performing a plating step to form a solder region on the UBM pads 147p and then reflowing the solder region.

[0075] After mounting the conductive bumps 150 on the second redistribution structure 140, the adhesive layer 114 and the support substrate 113 are removed or detached from the first redistribution structure 110, as Figure 28 . In some embodiments, the adhesive layer 114 (such as an LTHC release layer) is irradiated with a UV laser such that the support substrate 113 and the adhesive layer 114 can be peeled off from the first dielectric layer 112. However, the detachment process is not limited thereto. Other suitable methods may be used in some embodiments. Thereafter, a singulation process is performed to form a plurality of semiconductor structures 100. In some embodiments, the cutting process or the singulation process generally involves using a rotating blade or a laser beam to cut. In other words, the cutting or singulation process is (for example) a laser cutting process, a mechanical cutting process, or another suitable process. In some embodiments, the semiconductor structure 100 is referred to as an integrated fan-out (InFO) package. However, the present disclosure is not limited thereto. In some embodiments, the semiconductor structure 100 is another type of package.

[0076] Aspects of the present invention relate to a semiconductor structure. The semiconductor structure includes a first redistribution structure, where the first redistribution structure includes a first conductive pattern. The semiconductor structure further includes a die on the first redistribution structure. The semiconductor structure further includes a molding on the first redistribution structure, where the molding surrounds the die, and the molding has a first dielectric constant. The semiconductor structure further includes a dielectric component extending through the molding, where the dielectric component has a second dielectric constant different from the first dielectric constant. The semiconductor structure further includes a second redistribution structure on the die, the dielectric component, and the molding, where the second redistribution layer includes an antenna on the dielectric component, and the antenna is electrically connected to the die. In some embodiments, the second dielectric constant is greater than the first dielectric constant. In some embodiments, the semiconductor structure further includes a conductive via extending through the molding, where the conductive via is electrically connected to the first conductive pattern. In some embodiments, the conductive via contacts the dielectric component. In some embodiments, the dielectric component is isolated from the antenna. In some embodiments, the dielectric component is between the antenna and the first conductive pattern. In some embodiments, the dielectric component contacts the first conductive pattern. In some embodiments, the dielectric component overlaps the antenna in a plan view. In some embodiments, the second dielectric constant is equal to or greater than 3. In some embodiments, the dielectric component includes SiO 2 、SiN x 、SiO x N y 、ZrO 2 、Al 2 O 3 、HfO x 、HfSiO x 、ZrTiO x 、TiO 2 、TaO x 、SrTiO 3 、BaTiO 3 、BaSrTiO 3 、PbZrTiO 3 、a high-k polymer, or a combination thereof. In some embodiments, the width of the dielectric component is greater than or equal to the width of the antenna.

[0077] Aspects of the present invention relate to a semiconductor structure. The semiconductor structure includes a first redistribution structure. The semiconductor structure further includes a molding on the first redistribution structure, wherein the molding has a first dielectric constant. The semiconductor structure further includes a die surrounded by the molding. The semiconductor structure further includes a plurality of dielectric components surrounded by the molding, wherein the dielectric constant of each of the plurality of dielectric components is different from the first dielectric constant. The semiconductor structure further includes a second redistribution structure on the die, wherein the second redistribution structure includes a plurality of antenna structures, each of the plurality of antenna structures being electrically connected to the die and each of the plurality of antenna structures being located on a corresponding one of the plurality of dielectric components. In some embodiments, the semiconductor structure further includes a plurality of conductive vias extending through the molding, wherein each of the plurality of conductive vias is along a periphery of a corresponding one of the plurality of dielectric components. In some embodiments, the second redistribution structure further includes a plurality of conductive lines, and each of the plurality of conductive lines extends from a corresponding one of the plurality of antenna structures. In some embodiments, the first redistribution structure includes a ground conductive pattern. In some embodiments, the dielectric constant of each of the plurality of dielectric components is greater than the first dielectric constant.

[0078] Aspects of the present invention relate to a method of forming a semiconductor structure. The method includes forming a first redistribution structure including a first conductive pattern. The method further includes placing a die on the first redistribution structure. The method further includes placing a molding material on the first redistribution structure to surround the die. The method further includes removing a portion of the molding material to form an opening. The method further includes placing a dielectric material into the opening to form a dielectric component. The method further includes forming a second redistribution structure on the molding material and the dielectric component, wherein the second redistribution structure includes antenna structures on the dielectric component and electrically connected to the die. In some embodiments, the dielectric constant of the dielectric material is different from the dielectric constant of the molding material. In some embodiments, the method further includes forming a plurality of conductive vias extending through the molding, wherein forming the opening includes forming the opening surrounded by the plurality of conductive vias. In some embodiments, the method further includes forming conductive bumps on the second redistribution structure.

[0079] The features of several embodiments have been outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructs should not depart from the spirit and scope of the present invention, but rather various changes, substitutions, and alterations can be made to this disclosure without departing from the spirit and scope of the present invention.

[0080] Symbol Explanation

[0081] 100: Semiconductor structure / semiconductor device

[0082] 110: First redistribution structure

[0083] 111: First conductive pattern

[0084] 112: First dielectric layer

[0085] 113: Support substrate

[0086] 114: Adhesive layer

[0087] 120: Die

[0088] 120a: Back surface

[0089] 120b: Front surface

[0090] 121: Adhesive layer

[0091] 122: Semiconductor substrate

[0092] 123: Conductive pad

[0093] 124: Conductive pillar

[0094] 125: Dielectric layer of die

[0095] 130: Molding

[0096] 130b: Bottom surface

[0097] 130t: Top surface

[0098] 131: First conductive via

[0099] 131t: Top surface

[0100] 132: Second conductive via

[0101] 132t: Top surface

[0102] 133: Seed layer

[0103] 134: Dielectric component

[0104] 138: Conductive material

[0105] 139: Molding material

[0106] 140: Second cloth structure

[0107] 141: Second conductive pattern

[0108] 142: Second dielectric layer

[0109] 143: Conductive wire

[0110] 144: Antenna structure

[0111] 145: First cloth layer

[0112] 145c: First-level conductor

[0113] 145i: First insulating layer

[0114] 145v: First-level via

[0115] 146: Second cloth layer

[0116] 146c: Second-level conductor

[0117] 146i: Second insulating layer

[0118] 146v: Second-level via

[0119] 147: Third cloth layer

[0120] 147c: Third-level conductor

[0121] 147i: Third insulating layer

[0122] 147p: Under-bump metallization (UBM) pad

[0123] 150: Conductive bump

[0124] 200: Method

[0125] 201: Operation

[0126] 202: Operation

[0127] 203: Operation

[0128] 204: Operation

[0129] 205: Operation

[0130] 206: Operation

[0131] 207: Operation

[0132] 302: First patterned photoresist

[0133] 303: First groove

[0134] 304: Second patterned photoresist

[0135] 306: Second groove

[0136] 307: Dielectric paste

[0137] 311: Conductive material layer

[0138] 312: First insulating layer

[0139] 313: Second insulating layer

[0140] 314: Third insulating layer

[0141] H 111 : Height

[0142] H 302 : Height

[0143] S: Spacing

[0144] W 134 : Width.

Claims

1. A semiconductor structure, which comprises: A first redistribution structure, wherein the first redistribution structure includes a first conductive pattern; A die, which is on the first redistribution structure; A molding, which is on the first redistribution structure, wherein the molding surrounds the die, and the molding has a first dielectric constant; A conductive via, which extends through the molding and is electrically connected to the first conductive pattern; A dielectric component, which extends through the molding, wherein the dielectric component has a second dielectric constant different from the first dielectric constant, at least a part of the molding is between the dielectric component and the conductive via, and the dielectric component contacts the molding; and A second redistribution structure, which is on the die, the dielectric component and the molding, wherein the second redistribution structure includes an antenna on the dielectric component, and the antenna is electrically connected to the die.

2. The semiconductor structure according to claim 1, wherein the second dielectric constant is greater than the first dielectric constant.

3. The semiconductor structure according to claim 1, wherein the conductive via contacts the molding.

4. The semiconductor structure according to claim 1, wherein the conductive via contacts the dielectric component and the molding.

5. The semiconductor structure according to claim 1, wherein the dielectric component is isolated from the antenna.

6. The semiconductor structure according to claim 1, wherein the dielectric component is between the antenna and the first conductive pattern.

7. The semiconductor structure according to claim 1, wherein the dielectric component contacts the first conductive pattern.

8. The semiconductor structure according to claim 1, wherein the dielectric component and the antenna overlap in a plan view.

9. The semiconductor structure according to claim 1, wherein the second dielectric constant is equal to or greater than 3.

10. The semiconductor structure according to claim 1, wherein the dielectric component comprises SiO 2 , SiN x , SiO x N y , ZrO 2 , Al 2 O 3 , HfO x , HfSiO x , ZrTiO x , TiO 2 , TaO x , SrTiO 3 , BaTiO 3 , BaSrTiO 3 , PbZrTiO 3 , a high-k polymer, or a combination thereof.

11. The semiconductor structure according to claim 1, wherein the width of the dielectric component is greater than or equal to the width of the antenna.

12. A semiconductor structure, which comprises: A first redistribution structure; A molding, which is on the first redistribution structure, wherein the molding has a first dielectric constant; A die, which is surrounded by the molding; A plurality of dielectric components, which are surrounded by the molding, wherein the dielectric constant of each of the plurality of dielectric components is different from the first dielectric constant; A plurality of conductive vias, which extend through the molding, wherein each of the plurality of conductive vias is along the periphery of the corresponding dielectric component of the plurality of dielectric components; and A second redistribution structure, which is on the die, wherein the second redistribution structure includes a plurality of antenna structures, each of the plurality of antenna structures is electrically connected to the die, and each of the plurality of antenna structures is on the corresponding dielectric component of the plurality of dielectric components, wherein at least a part of the molding is between each of the plurality of dielectric components and the corresponding conductive via of the plurality of conductive vias, and the plurality of dielectric components contact the molding.

13. The semiconductor structure according to claim 12, wherein each of the plurality of conductive vias is surrounded by the molding.

14. The semiconductor structure according to claim 12, wherein the second redistribution structure further includes a plurality of conductive lines, and each of the plurality of conductive lines extends from a corresponding one of the plurality of antenna structures.

15. The semiconductor structure according to claim 12, wherein the first redistribution structure includes a ground conductive pattern.

16. The semiconductor structure according to claim 12, wherein the dielectric constant of each of the plurality of dielectric components is greater than the first dielectric constant.

17. A method of forming a semiconductor structure, which comprises: forming a first redistribution structure including a first conductive pattern; placing a die on the first redistribution structure; placing a molding material on the first redistribution structure to surround the die; removing a portion of the molding material to form an opening; placing a dielectric material into the opening to form a dielectric component; and forming a second redistribution structure on the molding material and the dielectric component, wherein the second redistribution structure includes antenna structures on the dielectric component and electrically connected to the die.

18. The method according to claim 17, wherein the dielectric constant of the dielectric material is different from the dielectric constant of the molding material.

19. The method according to claim 17, further comprising forming a plurality of conductive vias extending through the molding material, wherein forming the opening includes forming the opening surrounded by the plurality of conductive vias.

20. The method according to claim 17, which further comprises: forming conductive bumps on the second redistribution structure.

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