Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, first and second buffer chips on an upper portion of the substrate, a plurality of nonvolatile memory chips on the upper portion of the substrate and including first and second nonvolatile memory chips, the first nonvolatile memory chip being electrically connected to the first buffer chip and the second nonvolatile memory chip being electrically connected to the second buffer chip, a plurality of external connection terminals connected to a lower portion of the substrate, and a rewiring pattern inside the substrate. The rewiring pattern is configured to fork an external electrical signal received through one of the plurality of external connection terminals into a first signal and a second signal, transmit the first signal to the first buffer chip, and transmit the second signal to the second buffer chip.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0011060, filed on January 30, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0004] Traditionally, hard disk drives (HDDs), which include disks, have been used as data storage devices in electronic systems such as computer systems. With the development of semiconductor technology and portable devices, hard disk drives have been gradually replaced by solid-state drives (SSDs), which include non-volatile memory such as flash memory (e.g., NAND flash memory).

[0005] Compared to hard disk drives (HDDs), solid-state drives (SSDs) generate less heat and noise. Furthermore, SSDs offer faster access speeds, higher integration, and greater resistance to external shocks compared to HDDs. Additionally, SSDs can achieve data transfer rates significantly faster than HDDs.

[0006] Solid-state drive devices may include multiple non-volatile memory chips and multiple channels, where each channel is connected to one or more non-volatile memory chips. As the storage capacity of solid-state drive devices increases, the number of multiple non-volatile memory chips connected to each of the multiple channels also increases. However, when many non-volatile memory chips are connected to the same channel, some of these non-volatile chips may be connected to the memory controller at a distance that increases latency and reduces product density. Summary of the Invention

[0007] At least one exemplary embodiment of the present invention provides a semiconductor package in which points are formed inside a substrate where external signals (e.g., control signals) are bifurcated, and a non-volatile memory chip for receiving the bifurcated signals is placed on the substrate.

[0008] At least one exemplary embodiment of the present invention also provides a method for manufacturing a semiconductor package in which points are formed inside a substrate where external signals (e.g., control signals) are bifurcated, and a non-volatile memory chip for receiving the bifurcated signals is placed on the substrate.

[0009] According to an exemplary embodiment of the present inventive concept, there is provided a semiconductor package including a substrate, first and second buffer chips on an upper portion of the substrate, a plurality of nonvolatile memory chips on the upper portion of the substrate and including first and second nonvolatile memory chips, the first nonvolatile memory chip electrically connected to the first buffer chip and the second nonvolatile memory chip electrically connected to the second buffer chip, a plurality of external connection terminals connected to a lower portion of the substrate, and a re-wiring pattern inside the substrate. The re-wiring pattern is configured to fork an external electrical signal received through one of the plurality of external connection terminals into a first signal and a second signal, transmit the first signal to the first buffer chip, and transmit the second signal to the second buffer chip.

[0010] According to an exemplary embodiment of the present inventive concept, there is provided a semiconductor package including a controller transmitting a control signal including first and second channel signals, and first and second sub-nonvolatile memory packages receiving the first and second channel signals, respectively, wherein the first and second sub-nonvolatile memory packages are on a single substrate and the first and second channel signals are forked from the control signal in the substrate.

[0011] According to an exemplary embodiment of the present inventive concept, there is provided a semiconductor package including a substrate, first and second buffer pads on an upper portion of the substrate, first and second buffer chips electrically connected to each of the first and second buffer pads, a plurality of nonvolatile memory chips on the upper portion of the substrate and including first and second nonvolatile memory chips, the first nonvolatile memory chip electrically connected to the first buffer chip and the second nonvolatile memory chip electrically connected to the second buffer chip, a plurality of external connection terminals connected to a lower portion of the substrate, a controller transmitting a control signal including first and second channel signals to one of the plurality of external connection terminals, and a re-wiring pattern inside the substrate, the re-wiring pattern being configured to fork the control signal into the first and second channel signals, transmit the first channel signal to the first buffer chip, and transmit the second channel signal to the second buffer chip. BRIEF DESCRIPTION OF DRAWINGS

[0012] The present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

[0013] Figure 1is an exemplary block diagram illustrating a storage system including a semiconductor package according to exemplary embodiments of the inventive concept.

[0014] Figure 2 is an exemplary block diagram illustrating a storage device including a semiconductor package according to exemplary embodiments of the inventive concept.

[0015] Figure 3 is an exemplary circuit diagram illustrating an array of memory cells in a storage device including a semiconductor package according to exemplary embodiments of the inventive concept.

[0016] Figure 4 is an exemplary diagram illustrating a semiconductor package according to exemplary embodiments of the inventive concept.

[0017] Figure 5 is a cross-sectional view of the semiconductor package of Figure 4 according to exemplary embodiments taken along line A-A'.

[0018] Figure 6 is a cross-sectional view of the semiconductor package of Figure 4 according to exemplary embodiments taken along line B-B'.

[0019] Figures 7 to 12 is a schematic diagram illustrating other semiconductor packages according to some exemplary embodiments of the inventive concept.

[0020] Figures 13 to 14 is an exemplary diagram for explaining intermediate steps of a method for manufacturing a semiconductor package according to exemplary embodiments of the inventive concept. DETAILED DESCRIPTION

[0021] Figure 1 is an exemplary block diagram illustrating a storage system including a semiconductor package according to exemplary embodiments of the inventive concept.

[0022] Referring to Figure 1 , the storage system 1000a includes a host 1100 (e.g., a host device) and a storage device 1200.

[0023] According to some embodiments, the storage device 1200 includes a plurality of non-volatile memory packages (NVM PKGs) 100-1, 100-2, through 100-n and a controller 200 (e.g., a control circuit). The plurality of non-volatile memory packages 100-1, 100-2, through 100-n can serve as storage media for the storage device 1200. Each of the plurality of non-volatile memory packages 100-1, 100-2, through 100-n can include a plurality of non-volatile memory chips. In exemplary embodiments, each of the plurality of non-volatile memory chips includes a flash memory device.

[0024] The controller 200 can be connected to each of the plurality of nonvolatile memory packages 100-1, 100-2, and 100-n through a plurality of channels CH1 to CHn. For example, the first nonvolatile memory package 100-1 can be connected to the controller 200 through the first channel CH1. The first nonvolatile memory package 100-1 can include a plurality of sub nonvolatile memory packages. Each of the sub nonvolatile memory packages can include a plurality of nonvolatile memory chips. It will be described in detail later that the controller 200 can control the plurality of nonvolatile memory chips through the plurality of channels CH1 to CHn. Figure 4 This will be described in detail.

[0025] The controller 200 can transmit and receive a signal SGL to and from the host 1100 through the signal connector 210. In some embodiments, the signal SGL can include a command, an address, and data. According to a command of the host 1100, the controller 200 can write data to the plurality of nonvolatile memory packages 100-1, 100-2, and 100-n, or can read data from the plurality of nonvolatile memory packages 100-1, 100-2, and 100-n.

[0026] The storage device 1200 according to some embodiments can further include an auxiliary power supply 300. The auxiliary power supply 300 can receive an input of power PWR from the host 1100 through the power connector 310, and can supply power to the controller 200.

[0027] In the storage device 1200 according to some embodiments, the auxiliary power supply 300 can be located inside the storage device 1200, or can be located outside the storage device 1200. For example, the auxiliary power supply 300 can be located on a motherboard, and can provide auxiliary power to the storage device 1200. The auxiliary power supply 300 can receive a state of the storage device 1200 from the controller 200, and can transmit power.

[0028] The plurality of nonvolatile memory packages 100-1, 100-2, and 100-n and the controller 200 according to some embodiments can be located on the same printed circuit board (PCB). In an exemplary embodiment, the plurality of nonvolatile memory packages 100-1, 100-2, and 100-n and the controller 200 are connected to each other through wiring formed on the printed circuit board.

[0029] Figure 2 is an exemplary block diagram illustrating a storage device including a semiconductor package according to an exemplary embodiment of the present inventive concept.

[0030] Referring to Figure 2The storage device 400 according to an exemplary embodiment of the inventive concept includes a memory cell array 410, an address decoder 420 (e.g., a decoder circuit), a page buffer circuit 430, a data input / output (I / O) circuit 440, a voltage generator 450, and a control circuit 460.

[0031] Figure 3 is an exemplary circuit diagram illustrating a memory cell array in a storage device including a semiconductor package according to an exemplary embodiment of the inventive concept.

[0032] The memory cell array 410 can be connected to the address decoder 420 through a string select line SSL, a plurality of word lines WL, and a ground select line GSL. Also, the memory cell array 410 can be connected to the page buffer circuit 430 through a plurality of bit lines BL. The memory cell array 410 can include a plurality of memory cells connected to the plurality of word lines WL and the plurality of bit lines BL.

[0033] In some embodiments, the memory cell array 410 can be a three-dimensional memory cell array formed as a three-dimensional structure (or a vertical structure) on a substrate. In this case, the memory cell array 410 can include vertical memory cell strings including a plurality of memory cells formed by being stacked on each other. However, embodiments of the inventive concept are not limited thereto, and the memory cell array 410 can be a two-dimensional memory cell array formed as a two-dimensional structure (or a horizontal structure) on a substrate.

[0034] Reference will be made to Figure 3 The memory cell array 410 will be described in detail. The memory cell array 410 can include a plurality of memory cell strings NS11 to NS33 connected between bit lines BL1 to BL3 and a common source line CSL. Each of the plurality of memory cell strings NS11 to NS33 can include a string select transistor SST, a plurality of memory cells MC1, MC2, …, MC8, and a ground select transistor GST. Although Figure 3 It is illustrated that each of the plurality of memory cell strings NS11 to NS33 includes eight memory cells MC1 to MC8, but the number and type of memory cells are not limited thereto.

[0035] The string select transistor SST can be connected to a corresponding string select line SSL. Each of the plurality of memory cells MC1, MC2, …, MC8 can be connected to a corresponding word line WL1, WL2, …, WL8. The ground select transistor GST can be connected to one of the corresponding ground select lines GSL1 to GSL3. The string select transistor SST can be connected to a corresponding one of the bit lines BL1 to BL3, and the ground select transistor GST can be connected to the common source line CSL. Although Figure 3It is shown that the memory cell array 410 is connected to eight word lines WL1 to WL8 and three bit lines BL1 to BL3, but embodiments of the inventive concept are not limited thereto.

[0036] Referring again to Figure 1 and Figure 2 , the control circuit 460 can receive a command signal CMD and an address signal ADDR from the controller 200, and can control a program operation, a read operation, or an erase operation of the memory cell array 410 based on the command signal CMD and the address signal ADDR.

[0037] For example, the control circuit 460 can generate a control signal CON for controlling the voltage generator 450 based on the command signal CMD, and can generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 460 can provide the row address R_ADDR to the address decoder 420, and can provide the column address C_ADDR to the data I / O circuit 440.

[0038] The address decoder 420 can be connected to the memory cell array 410 through a string select line SSL, a plurality of word lines WL, and a ground select line GSL. In a program operation and a read operation, the address decoder 420 can determine one of the plurality of word lines WL as a selected word line based on the row address R_ADDR provided from the control circuit 460, and can determine the remaining word lines of the plurality of word lines WL other than the selected word line as unselected word lines.

[0039] The voltage generator 450 can generate a word line voltage VWL required for an operation of the memory device 1200 based on the control signal CON provided from the control circuit 460. The word line voltage VWL generated from the voltage generator 450 can be applied to the plurality of word lines WL through the address decoder 420.

[0040] In a program operation, the voltage generator 450 can generate a program voltage and a program pass voltage. The program voltage can be applied to the selected word line through the address decoder 420, and the program pass voltage can be applied to the unselected word lines through the address decoder 420.

[0041] Further, in a read operation, the voltage generator 450 can generate a read voltage and a read pass voltage. The read voltage can be applied to the selected word line through the address decoder 420, and the read pass voltage can be applied to the unselected word lines through the address decoder 420.

[0042] The page buffer circuit 430 can be connected to the memory cell array 410 through a plurality of bit lines BL.

[0043] The page buffer circuit 430 can include a plurality of page buffers. In some embodiments, one page buffer can be connected to one bit line BL. Without being limited thereto, in some embodiments, two or more bit lines BL can be connected to one page buffer.

[0044] The page buffer circuit 430 can temporarily store data to be programmed in a selected page at the time of a program operation, and can temporarily store data read from a selected page at the time of a read operation.

[0045] The data I / O circuit 440 can be connected to the page buffer circuit 430 through a data line DL. At the time of a program operation, the data I / O circuit 440 receives program data DATA from the controller 200, and can provide the program data DATA to the page buffer circuit 430 based on a column address C_ADDR provided from the control circuit 460. At the time of a read operation, the data I / O circuit 440 can provide read data DATA stored in the page buffer circuit 430 to the controller 200 based on a column address C_ADDR provided from the control circuit 460.

[0046] In an exemplary embodiment, external electrical signals (e.g., command signals CMD, address signals ADDR, and / or data DATA) transmitted from the controller 200 can be transmitted through one channel from the controller 200. Then, according to some embodiments, the external electrical signals transmitted through one channel can diverge and be diverted to the non-volatile memory package. At this time, by placing a diverged / diverging / diversion point within a substrate in the non-volatile memory package according to an exemplary embodiment of the present inventive concept, the density of the semiconductor package can be improved, and the speed of transmitting external electrical signals from the controller 200 can also be improved. This will be described in detail with reference to the following drawings.

[0047] Figure 4 FIG. 1 is a schematic diagram illustrating a semiconductor package according to an exemplary embodiment of the present inventive concept.

[0048] Referring to Figure 4 A semiconductor package according to an exemplary embodiment of the present inventive concept includes a first sub non-volatile memory package 101-1 and a second sub non-volatile memory package 101-2.

[0049] In an exemplary embodiment, the first sub-nonvolatile memory package 101-1 and the second sub-nonvolatile memory package 101-2 are placed on a single same substrate 102. A plurality of external connection terminals 170 can be formed under the substrate 102 to receive external electrical signals. The external connection terminals 170 can directly contact the substrate 102. For example, at least one of the plurality of external connection terminals 170 can receive external electrical signals (e.g., command signals, address signals, and / or data signals) from the controller 200 through the first channel CH1.

[0050] The first sub-nonvolatile memory package 101-1 and the second sub-nonvolatile memory package 101-2 can respectively include a first nonvolatile memory chip (NVM) 110-1 and a second nonvolatile memory chip 110-2. The first nonvolatile memory chip 110-1 and / or the second nonvolatile memory chip 110-2 included in each of the first sub-nonvolatile memory package 101-1 and the second sub-nonvolatile memory package 101-2 can include a NAND flash memory, a vertical NAND flash memory (VNAND), a NOR flash memory, a resistive random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), or a spin transfer torque random access memory (STT-RAM). In addition, the first nonvolatile memory chip 110-1 and / or the second nonvolatile memory chip 110-2 according to some embodiments can include a three-dimensional array structure.

[0051] The first nonvolatile memory chip 110-1 and the second nonvolatile memory chip 110-2 are placed on the substrate 102, and each of the first nonvolatile memory chip 110-1 and the second nonvolatile memory chip 110-2 can include a plurality of nonvolatile memory chips. The shape of the plurality of nonvolatile memory chips on which the first nonvolatile memory chip 110-1 and the second nonvolatile memory chip 110-2 are formed is not limited to the drawings.

[0052] The first sub-nonvolatile memory package 101-1 and the second sub-nonvolatile memory package 101-2 can respectively include a first buffer chip 160-1 and a second buffer chip 160-2. The first buffer chip 160-1 and the second buffer chip 160-2 can be placed on the substrate 102. The first buffer chip 160-1 and the second buffer chip 160-2 can be electrically connected to the first nonvolatile memory chip 110-1 and the second nonvolatile memory chip 110-2, respectively. In an exemplary embodiment, the buffer chip temporarily stores data to be written to or read from the nonvolatile memory chip.

[0053] In an example embodiment, the first buffer chip 160-1 is electrically connected to the first plurality of first non-volatile memory chips 110-1 by the first wire 112-1. Additionally, in this embodiment, the first buffer chip 160-1 is electrically connected to another second plurality of first non-volatile memory chips 110-1 by the second wire 112-2. In an example embodiment, the second buffer chip 160-2 is electrically connected to the first plurality of second non-volatile memory chips 110-2 by the fourth wire 112-4. Additionally, in this embodiment, the second buffer chip 160-2 is electrically connected to another second plurality of second non-volatile memory chips 110-2 by the fifth wire 112-5. Although Figure 4 While each sub-non-volatile memory package is shown as including two groups of semiconductor chips stacked on top of each other, in alternative embodiments, each sub-non-volatile memory package includes only a single group, and the wires 112-2 and 112-5 are omitted.

[0054] The first buffer pad 162-1 and the second buffer pad 162-2 can be placed on the substrate 102. The first buffer pad 162-1 and / or the second buffer pad 162-2 can include a conductive substance. For example, the first buffer pad 162-1 and the second buffer pad 162-2 can include gold (Au), silver (Ag), copper (Cu), nickel (Ni), or aluminum (Al). In an example embodiment, the first buffer pad 162-1 is electrically connected to the first buffer chip 160-1 by the third wire 112-3. In an example embodiment, the second buffer pad 162-2 is electrically connected to the second buffer chip 160-2 by the sixth wire 112-6.

[0055] The first buffer pad 162-1 and the second buffer pad 162-2 can be connected to the re- wiring patterns 140-1, 140-2, 140-3, 141-1, 141-2, and 141-3. In an example embodiment, the re- wiring patterns 140-1, 140-2, 140-3, 141-1, 141-2, and 141-3 are arranged inside the substrate 102. The re-wiring patterns 140-1, 140-2, 140-3, 141-1, 141-2, and 141-3 can also be electrically connected to at least some of the plurality of external connection terminals 170. The re-wiring patterns 140-1, 140-2, 140-3, 141-1, 141-2, and 141-3 and the plurality of external connection terminals 170 can include gold (Au), silver (Ag), copper (Cu), nickel (Ni), or aluminum (Al).

[0056] In the following drawings, although the plurality of external connection terminals 170 are illustrated as solder balls, embodiments of the inventive concept are not limited thereto. For example, the plurality of external connection terminals 170 can be solder bumps, a land grid array, or a conductive sheet. Also, the number and arrangement of the plurality of external connection terminals 170 are not limited to those illustrated in the drawings.

[0057] That is, an external electrical signal (e.g., a first channel signal) transmitted from the controller 200 can be transmitted to at least one of the external connection terminals 170 through the first channel CH1. At least one of the external connection terminals 170 can be electrically connected to the re-wiring patterns 140-1, 140-2, 140-3, 141-1, 141-2, and 141-3. The re-wiring patterns 140-1, 140-2, 140-3, 141-1, 141-2, and 141-3 can be electrically connected to the first buffer pad 162-1 and the second buffer pad 162-2. As a result, an external electrical signal (e.g., a first channel signal) transmitted from the controller 200 can be transmitted to the first sub-nonvolatile memory package 101-1 and the second sub-nonvolatile memory package 101-2 through the first buffer chip 160-1 and the second buffer chip 160-2, respectively.

[0058] The signals transmitted to each of the first sub-nonvolatile memory package 101-1 and the second sub-nonvolatile memory package 101-2 can be different from each other. That is, a first channel signal CH1 transmitted from the controller 200 is transmitted along the third vertical re-wiring pattern 140-3, and can be branched into a 1-1 channel signal CH1-1 and a 1-2 channel signal CH1-2 at a branching point P.

[0059] More specifically, the 1-1 channel signal CH1-1 branched from the first channel signal CH1 at the branching point P travels along the first horizontal re-wiring pattern 141-1, and is transmitted to the first buffer pad 162-1 through the first vertical re-wiring pattern 140-1 connected to the first horizontal re-wiring pattern 141-1. The 1-2 channel signal CH1-2 branched from the first channel signal CH1 is transmitted to the second buffer pad 162-2 through the third horizontal re-wiring pattern 141-3, the second vertical re-wiring pattern 140-2 connected to the third horizontal re-wiring pattern 141-3, and the second horizontal re-wiring pattern 141-2 connected to the second vertical re-wiring pattern 140-2.

[0060] That is, the first channel signal CH1 received from the controller 200 is split at the split point P in the substrate 102, and the corresponding split first-1 channel signal CH1-1 is transmitted to the first sub-nonvolatile memory package 101-1 including the first nonvolatile memory chip 110-1, and the split first-2 channel signal CH1-2 is transmitted to the second sub-nonvolatile memory package 101-2 including the second nonvolatile memory chip 110-2.

[0061] In the semiconductor package according to the exemplary embodiment of the present inventive concept, by splitting the external signal (e.g., a control signal, etc.) received from the controller 200 inside the substrate 102, the integration of the semiconductor package according to some embodiments can be improved, the signal transmitted from the controller 200 can be split more, and the operation speed of the storage device including the semiconductor package according to some embodiments can be improved.

[0062] In Figure 4 In the illustrated embodiment, the split point P is located at the center in the second direction y, in which the first buffer chip 160-1 and the second buffer chip 160-2 are spaced apart from each other. For example, the split point P can be located at the center of the substrate 120. In the exemplary embodiment, a first length D1 from the split point P to a point at which the first buffer pad 162-1 meets or contacts the re-wiring pattern 140-1 is the same as a second length D2 from the split point P to a point at which the second buffer pad 162-2 meets or contacts the re-wiring pattern 141-2. That is, the first channel signal CH1 is split at the split point P, and the lengths to which the first-1 channel signal CH1-1 and the first-2 channel signal CH1-2 are transmitted to the first buffer pad 162-1 and the second buffer pad 162-2, respectively, can be equal.

[0063] In the exemplary embodiment, the lengths of the paths 141-1 and 140-1 are equal to the lengths of the paths 141-3, 140-2, and 141-2, the first-1 channel signal CH1-1 split from the first channel signal CH1 travels along the paths 141-1 and 140-1, and the first-2 channel signal CH1-2 split from the first channel signal CH1 travels along the paths 141-3, 140-2, and 141-2.

[0064] The first buffer chip 160-1 and / or the second buffer chip 160-2 can include a plurality of I / O terminals. If connection between the plurality of I / O terminals is performed inside the substrate 102, connection lines of the plurality of different I / O terminals can become entangled with each other. In an exemplary embodiment of the inventive concept, the re-distribution pattern 141-1 connected to the first buffer chip 160-1 and the re-distribution pattern 141-2 connected to the second buffer chip 160-2 are placed in different layers from each other, so that connections of the same I / O terminals do not become entangled with each other. This will be described in detail below with reference to Figure 5 and Figure 6 This will be described in detail below. In an exemplary embodiment, the depth of the re-distribution pattern 141-1 is different from the depth of the re-distribution pattern 141-2 within the substrate 102.

[0065] Figure 5 is a cross-sectional view of the semiconductor package of Figure 4 according to an exemplary embodiment of the inventive concept, taken along line A-A'. Figure 6 is a cross-sectional view of the semiconductor package of Figure 4 according to an exemplary embodiment of the inventive concept, taken along line B-B'. Hereinafter, for convenience of description, a layer taken along line A-A' is referred to as a first layer, and a layer taken along line B-B' is referred to as a second layer.

[0066] Referring to Figure 5 , each of the first buffer pad 162-1 and the second buffer pad 162-2 includes a plurality of I / O pads I / O 0 to I / O 7. The form and number of the plurality of I / O pads I / O 0 to I / O 7 are not limited to Figure 5 the form and number shown in FIG. 1. For convenience of illustration, the corresponding I / O pads I / O 0 to I / O 7 or some portions thereof located above the first layer are indicated by dotted lines.

[0067] In the first layer, a re-distribution pattern (e.g., 141-2) is formed on each of the I / O pads I / O 0 to I / O 7. In an exemplary embodiment, the re-distribution patterns formed to be connected to the corresponding I / O pads I / O 0 to I / O 7 do not cross each other. At the end of the re-distribution pattern formed by each of the I / O pads I / O 0 to I / O 7, a re-distribution pattern to be connected to the layer below (e.g., the second layer) is formed in the first direction x (e.g., 140-2). As the first I / O pad I / O 0 of the first buffer pad 162-1 and the eighth I / O pad I / O 7 of the second buffer pad 162-2, a re-distribution pattern (e.g., 140-1) to be directly connected to the layer below can also be formed in the pad.

[0068] A second layer will be described with reference to FIGS. 2A and 2B. Figure 6 The redistribution pattern of the second layer will be described. In order to incorporate the I / O pads I / O 0 to I / O 7 of the first buffer pad 162-1 and the I / O pads I / O 0 to I / O 7 of the second buffer pad 162-2 inside the substrate, the redistribution pattern (e.g., 141-1 and 141-3) can be formed by the redistribution pattern (e.g., 140-2) connecting the first layer to the second layer.

[0069] As an example, the first I / O pad I / O 0 of the first buffer pad 162-1 and the first I / O pad I / O 0 of the second buffer pad 162-2 will be described in detail. The first I / O pad I / O 0 of the first buffer pad 162-1 has the first vertical redistribution pattern 140-1 formed in the first layer to electrically connect the first layer and the second layer. The first I / O pad I / O 0 of the second buffer pad 162-2 is connected to the second horizontal redistribution pattern 141-2 in the first layer to electrically connect the first layer and the second layer through the second vertical redistribution pattern 140-2.

[0070] Then, in the second layer, the first I / O pad I / O 0 is connected from the first vertical redistribution pattern 140-1 to the bifurcation point P through the first horizontal redistribution pattern 141-1, and is connected from the second vertical redistribution pattern 140-2 to the bifurcation point P through the third horizontal redistribution pattern 141-3. That is, the first horizontal redistribution pattern 141-1 formed in the second layer can not be entangled with the redistribution pattern (a portion shown by a dotted line) formed in the first layer.

[0071] That is, since the bifurcation point P formed in one layer (e.g., the second layer) is lower than the redistribution pattern layer (e.g., the first layer) formed by directly meeting the first buffer pad 162-1 and the second buffer pad 162-2, when connecting the I / O pads I / O 0 to I / O 7 different from each other in the first buffer pad 162-1 and the second buffer pad 162-2, they can not be connected to each other. The layer exemplified here is not limited thereto, but can include various forms of layers.

[0072] Figures 7 to 12 FIGS. 3A and 3B are schematic diagrams illustrating other semiconductor packages according to some exemplary embodiments of the inventive concept. Hereinafter, a repeated explanation of the foregoing will not be provided, and differences will be mainly described.

[0073] Referring to Figure 7 , as Figure 4Unlike other buffer chips, the first buffer chip 160-1 and / or the second buffer chip 160-2 can be electrically connected to the redistribution patterns 140-1, 140-2, 140-3, 141-1, 141-2 and 141-3 in the form of flip chips.

[0074] In an exemplary embodiment, a first connection terminal 168-1 connected to the first buffer chip 160-1 is electrically connected to a first buffer pad 162-1. In an embodiment, a second connection terminal 168-2 connected to the second buffer chip 160-2 is electrically connected to a second buffer pad 162-2. The first connection terminal 168-1 and / or the second connection terminal 168-2 may include gold (Au), silver (Ag), copper (Cu), nickel (Ni), or aluminum (Al). For example, the first connection terminal 168-1 and / or the second connection terminal 168-2 may be a solder ball, a solder bump, or a combination thereof.

[0075] Reference Figure 8 ,and Figure 4 The difference is that at least some of the external connection terminals 170 connected to the first channel signal CH1 sent from the controller 200 are not located in the direction of vertical descent from the bifurcation point P in the first direction x. That is, the signal before the bifurcation can be sent from the outside (e.g., the controller 200) without restricting certain paths. For example, the connection terminals 170 connected to the bifurcation point P do not need to be directly below the bifurcation point P, but rather... Figure 8 As shown, it can be offset to the left of the center by a certain distance. Alternatively, the connection terminal 170 connected to the bifurcation point P can be offset to the right of the center by a certain distance.

[0076] Reference Figure 9 ,and Figure 8 Unlike other buffer chips, the first buffer chip 160-1 and the second buffer chip 160-2 are electrically connected to the redistribution patterns 140-1, 140-2, 140-3, 141-1, 141-2 and 141-3 respectively in the form of flip-chip.

[0077] Reference Figure 10 The semiconductor package according to an exemplary embodiment of the present invention also includes a branched chip 164.

[0078] The branch chip 164 can be placed on the substrate 102. For example, the bottom surface of the branch chip 164 can contact the top surface of the substrate 102.

[0079] The bifurcation chip 164 can receive transmission of the first channel signal CH1 received from the controller 200 through the re-wiring pattern 142. More specifically, the bifurcation chip 164 can be electrically connected to the second bifurcation chip pad 166-2, and can receive the first channel signal CH1.

[0080] The bifurcation chip 164 can then transmit the first channel signal CH1 to the bifurcation point P through the re-wiring pattern 143. In an exemplary embodiment, the bifurcation chip 164 is electrically connected to the first bifurcation chip pad 166-1, and transmits the first channel signal CH1 to the re-wiring pattern 143. In an exemplary embodiment, the bifurcation chip 164 is connected to the bifurcation chip pads 166-1 and 166-2 through corresponding wires. In an exemplary embodiment, the bifurcation chip 164 is implemented by a transmitter. In an exemplary embodiment, the bifurcation chip 164 includes an amplifier that can be used to increase the intensity of the first channel signal CH1 under certain conditions.

[0081] The first bifurcation chip pad 166-1 and / or the second bifurcation chip pad 166-2 can include gold (Au), silver (Ag), copper (Cu), nickel (Ni), or aluminum (Al).

[0082] That is, the first channel signal CH1 can travel to the bifurcation point P along the re-wiring pattern 143 formed in the substrate 102. The first channel signal CH1 traveling to the bifurcation point P can be bifurcated into a 1-1 channel signal CH1-1 and a 1-2 channel signal CH1-2. The bifurcated 1-1 channel signal CH1-1 can be transmitted to the first sub-nonvolatile memory package 101-1 along the first horizontal re-wiring pattern 141-1 and the first vertical re-wiring pattern 140-1. In addition, the bifurcated 1-2 channel signal CH1-2 can be transmitted to the second sub-nonvolatile memory package 101-2 along the second horizontal re-wiring pattern 141-2 and the second vertical re-wiring pattern 140-2.

[0083] In this drawing, although the first horizontal re-wiring pattern 141-1 and the second horizontal re-wiring pattern 141-2 are shown as being formed in the same layer, these patterns can be formed in different layers, as Figure 4 indicated.

[0084] Referring Figure 11 to Figure 10 differently, the bifurcation chip 164 is electrically connected to the re-wiring patterns 142 and 143 in the form of a flip chip.

[0085] In an exemplary embodiment, the bifurcation chip 164 is electrically connected to the re-wiring pattern 142 through a second bifurcation chip connection terminal 169-2, and can receive the first channel signal CH1 from the controller 200. In this embodiment, the bifurcation chip 164 is electrically connected to the re-wiring pattern 143 through a first bifurcation chip connection terminal 169-1, and can transmit the first channel signal CH1 received from the controller 200 to the bifurcation point P. The first bifurcation chip connection terminal 169-1 and the second bifurcation chip connection terminal 169-2 can include gold (Au), silver (Ag), copper (Cu), nickel (Ni), or aluminum (Al).

[0086] Referring to Figure 12 Unlike the Figure 10 and Figure 11 bifurcation chip 164 is formed inside the substrate 102.

[0087] The bifurcation chip 164 according to an exemplary embodiment of the inventive concept is formed in the substrate 102, and receives the first channel signal CH1 transmitted from the controller 200. In an exemplary embodiment, the bifurcation chip 164 is electrically connected to a third vertical re-wiring pattern 140-3, which is electrically connected to at least one of a plurality of external connection terminals 170, and receives the first channel signal CH1 from the controller 200.

[0088] Then, the bifurcation chip 164 can function as the bifurcation point P. That is, the bifurcation chip 164 can receive the first channel signal CH1 and bifurcate (e.g., split) it into a 1-1 channel signal CH1-1 and a 1-2 channel signal CH1-2. The bifurcated 1-1 channel signal CH1-1 can be transmitted to the first sub-nonvolatile memory package 101-1 along the first horizontal re-wiring pattern 141-1 and the first vertical re-wiring pattern 140-1. Also, the bifurcated 1-2 channel signal CH1-2 can be transmitted to the second sub-nonvolatile memory package 101-2 along the third horizontal re-wiring pattern 141-3, the second vertical re-wiring pattern 140-2, and the second horizontal re-wiring pattern 141-2.

[0089] In this drawing, although the first horizontal re-wiring pattern 141-1 and the second horizontal re-wiring pattern 141-2 are shown as being formed in the same layer, they can be formed in different layers from each other, as Figure 4 indicated.

[0090] Figures 13 to 14 is a schematic diagram for explaining an intermediate step of a method for manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept.

[0091] First, referring to Figure 13A rewiring pattern for branching an external electrical signal (e.g., a first channel signal CH1) is formed inside the substrate 102. In an exemplary embodiment, a third vertical rewiring pattern 140-3 extending vertically in a first direction x around the branching point P is formed, a first horizontal rewiring pattern 141-1 and a third horizontal rewiring pattern 141-3 extending in a second direction y around the branching point P are formed. In an exemplary embodiment, a first recess is formed in a bottom surface of the substrate 102, and the third vertical rewiring pattern 140-3 is formed in the first recess. Although the first horizontal rewiring pattern 141-1 and the third horizontal rewiring pattern 141-3 are shown as being formed on the same layer in Figure 13 the present inventive concept is not limited thereto.

[0092] In an embodiment, a first vertical rewiring pattern 140-1 connected to the first horizontal rewiring pattern 141-1 and extending in the first direction x is formed inside the substrate 102. In an exemplary embodiment, a second recess is formed in a top surface of the substrate 102, and the first vertical rewiring pattern 140-1 is formed in the second recess. Also, in an embodiment, a second vertical rewiring pattern 140-2 connected to the third horizontal rewiring pattern 141-3 and extending in the first direction x is formed. In an exemplary embodiment, a third recess is formed in the top surface of the substrate 102, and the second vertical rewiring pattern 140-2 is formed in the third recess. Then, a second horizontal rewiring pattern 141-2 connected to the second vertical rewiring pattern 140-2 is formed. For example, a fourth recess wider than the third recess and adjacent to the third recess can be formed in the top surface of the substrate, and the second horizontal rewiring pattern 141-2 can be formed in the fourth recess. The recesses described above can be formed by performing etching to remove some portions of the substrate 102.

[0093] The rewiring patterns 140-1, 140-2, 140-3, 141-1, 141-2, and 141-3 can be located inside the substrate 102. Also, one or more external connection terminals 170 for receiving an external electrical signal (e.g., a first channel signal CH1 received from the controller 200) are formed.

[0094] That is, at least one of the plurality of external connection terminals 170 receives the first channel signal CH1 transmitted from the controller 200, and can transmit it to the third vertical rewiring pattern 140-3. For example, one of the external connection terminals 170 is formed to contact the third vertical rewiring pattern 140-3.

[0095] Hereinafter, a description will be given with reference to Figure 14The first sub-nonvolatile memory package 101-1 and the second sub-nonvolatile memory package 101-2 can be formed to include first and second buffer chips 160-1 and 160-2, respectively, and first and second nonvolatile memory chips 110-1 and 110-2, respectively.

[0096] First and second buffer pads 162-1 and 162-2 can also be formed on the substrate 102 to be electrically connected to the first and second nonvolatile memory chips 110-1 and 110-2, respectively. For example, a conductive line 112-3 can be formed to connect the first buffer pad 162-1 to the first buffer chip 160-1, a conductive line 112-1 can be formed to connect the first buffer chip 160-1 to a first group of nonvolatile memory chips in the first sub-nonvolatile memory package 101-1, a conductive line 112-2 can be formed to connect the first buffer chip 160-1 to a second group of nonvolatile memory chips in the first sub-nonvolatile memory package 101-1, a conductive line 112-6 can be formed to connect the second buffer pad 162-2 to the second buffer chip 160-2, a conductive line 112-4 can be formed to connect the second buffer chip 160-2 to a first group of nonvolatile memory chips in the second sub-nonvolatile memory package 101-2, and a conductive line 112-5 can be formed to connect the second buffer chip 160-2 to a second group of nonvolatile memory chips in the second sub-nonvolatile memory package 101-2.

[0097] As a summary of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the exemplary embodiments without substantially departing from the principles of the present inventive concept.

Claims

1. A semiconductor package comprising: a substrate; a first buffer chip and a second buffer chip on an upper portion of the substrate; a first buffer pad and a second buffer pad on the substrate, the first buffer pad and the second buffer pad being spaced apart from each other and both the first buffer chip and the second buffer chip being interposed between the first buffer pad and the second buffer pad, the first buffer pad being electrically connected to the first buffer chip, the second buffer pad being electrically connected to the second buffer chip; a plurality of nonvolatile memory chips on the upper portion of the substrate, the plurality of nonvolatile memory chips including a first nonvolatile memory chip and a second nonvolatile memory chip, the first nonvolatile memory chip being electrically connected to the first buffer chip, the second nonvolatile memory chip being electrically connected to the second buffer chip; a plurality of external connection terminals connected to a lower portion of the substrate; and a rewiring pattern within the substrate, the rewiring pattern being configured to bifurcate an external electrical signal received through one of the plurality of external connection terminals into a first signal and a second signal, to transmit the first signal to the first buffer pad, and to transmit the second signal to the second buffer pad, wherein the external electrical signal is bifurcated into the first signal and the second signal at a bifurcation point in the rewiring pattern, and a first length of the rewiring pattern from the bifurcation point to a point at which the rewiring pattern contacts the first buffer pad is the same as a second length of the rewiring pattern from the bifurcation point to a point at which the rewiring pattern contacts the second buffer pad. 2.The semiconductor package of claim 1, further comprising: a bifurcation chip, wherein the bifurcation chip receives the external electrical signal from the one of the plurality of external connection terminals, and transmits the received external electrical signal to the rewiring pattern. The bifurcation chip is on the upper portion of the substrate.

3. The semiconductor package of claim 2, wherein, 4.The semiconductor package of claim 1, wherein the first buffer chip and the second buffer chip are spaced apart from each other in a first direction, and the bifurcation point is at a center of the rewiring pattern in the first direction. The rewiring pattern includes:

5. The semiconductor package of claim 1, wherein, a first vertical rewiring pattern and a first horizontal rewiring pattern configured to transmit the first signal to the first buffer chip, and a second vertical rewiring pattern and a second horizontal rewiring pattern configured to transmit the second signal to the second buffer chip, the first vertical rewiring pattern and the second vertical rewiring pattern extend in a first direction, the first horizontal rewiring pattern and the second horizontal rewiring pattern extend in a second direction perpendicular to the first direction, and the first horizontal rewiring pattern is lower than the second horizontal rewiring pattern in the first direction. ​ 6. The semiconductor package of claim 5, wherein, The re-wiring pattern includes a third vertical re-wiring pattern including a first end connected to the one external connection terminal, and the third vertical re-wiring pattern extends in the first direction, and The external electrical signal is forked at another second end of the third vertical re-wiring pattern.

7. The semiconductor package of claim 1, wherein, The first buffer chip and the second buffer chip are connected to the re-wiring pattern in a flip-chip form. 8.A semiconductor package comprising: a controller that transmits a control signal including a first lane signal and a second lane signal; and a first sub-nonvolatile memory package that receives the first lane signal and a second sub-nonvolatile memory package that receives the second lane signal, wherein the first sub-nonvolatile memory package and the second sub-nonvolatile memory package are located on a single substrate, wherein the first sub-nonvolatile memory package receives the first lane signal through a first buffer pad located on the single substrate, the second sub-nonvolatile memory package receives the second lane signal through a second buffer pad located on the single substrate, the first sub-nonvolatile memory package and the second sub-nonvolatile memory package are both interposed between the first buffer pad and the second buffer pad spaced apart from each other, and the first lane signal and the second lane signal are forked from the control signal at a fork point in the substrate, a first length of a transmission path of the first lane signal from the fork point to the first buffer pad is the same as a second length of a transmission path of the second lane signal from the fork point to the second buffer pad. 9.The semiconductor package of claim 8, further comprising: a fork chip, wherein the fork chip receives the control signal and forks the received control signal into the first lane signal and the second lane signal.

10. The semiconductor package of claim 9, wherein, The fork chip is located on an upper portion of the substrate.

11. The semiconductor package of claim 9, wherein, The fork chip is located within the substrate.

12. The semiconductor package of claim 8, wherein, The first lane signal is transmitted to the first sub-nonvolatile memory package through a first horizontal path and a first vertical path, the second lane signal is transmitted to the second sub-nonvolatile memory package through a second horizontal path and a second vertical path, the first vertical path and the second vertical path extend in a first direction, the first horizontal path and the second horizontal path extend in a second direction perpendicular to the first direction, and the first horizontal path is lower than the second horizontal path in the first direction.

13. The semiconductor package of claim 12, wherein, The control signal is transmitted through a third vertical path extending in the first direction before being forked.

14. The semiconductor package of claim 8, wherein, The substrate includes a first layer and a second layer located at different heights from each other in a first direction perpendicular to the substrate, the first lane signal and the second lane signal are transmitted through both the first layer and the second layer, and a transmission length of the first lane signal transmitted through the first layer is longer than a transmission length of the second lane signal transmitted through the first layer. 15.A semiconductor package comprising: a substrate; a first buffer pad and a second buffer pad on an upper portion of the substrate; a first buffer chip electrically connected to the first buffer pad and a second buffer chip electrically connected to the second buffer pad, both of the first buffer chip and the second buffer chip being interposed between the first buffer pad and the second buffer pad spaced apart from each other; a plurality of nonvolatile memory chips on the upper portion of the substrate, the plurality of nonvolatile memory chips including a first nonvolatile memory chip electrically connected to the first buffer chip and a second nonvolatile memory chip electrically connected to the second buffer chip; a plurality of external connection terminals connected to a lower portion of the substrate; a controller that transmits a control signal including a first channel signal and a second channel signal to one of the plurality of external connection terminals; and a rewiring pattern within the substrate that forks the control signal into the first channel signal and the second channel signal, transmits the first channel signal to the first buffer pad, and transmits the second channel signal to the second buffer pad, wherein the control signal is forked into the first channel signal and the second channel signal at a fork point in the rewiring pattern, and a first length of the rewiring pattern from the fork point to a point at which the rewiring pattern contacts the first buffer pad is the same as a second length of the rewiring pattern from the fork point to a point at which the rewiring pattern contacts the second buffer pad.

16. The semiconductor package of claim 15, wherein, The rewiring pattern includes: a first vertical rewiring pattern and a first horizontal rewiring pattern in which the first channel signal is transmitted to the first buffer chip, a second vertical rewiring pattern and a second horizontal rewiring pattern in which the second channel signal is transmitted to the second buffer chip, the first vertical rewiring pattern and the second vertical rewiring pattern extend in a first direction, the first horizontal rewiring pattern and the second horizontal rewiring pattern extend in a second direction perpendicular to the first direction, and the first horizontal rewiring pattern is lower than the second horizontal rewiring pattern in the first direction.

17. The semiconductor package of claim 16, wherein, The rewiring pattern further includes a third vertical rewiring pattern including a first end connected to the one external connection terminal, and the third vertical rewiring pattern extends in the first direction, and the control signal is forked at a second other end of the third vertical rewiring pattern.

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