LIDAR System with Dynamic Resolution

Abstract

The present invention is titled "LIDAR System with Dynamic Resolution". The present invention discloses an imaging system that may include a silicon photomultiplier having single-photon avalanche diodes (SPADs). The imaging system may be a LIDAR imaging system having a LIDAR processing circuit. To reduce the memory requirements in the LIDAR processing circuit, a dynamic resolution storage scheme may be used. The LIDAR processing circuit may include an autonomous dynamic resolution circuit that receives an input from a time-to-digital converter (TDC). The autonomous dynamic resolution circuit may include a plurality of repositories having different resolutions. Based on the magnitude of the input from the TDC, an appropriate repository may be selected. In parallel, an address encoder may select a storage bin based on the input from the TDC.

Description

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 963,655, filed on January 21, 2020, which is hereby incorporated by reference in its entirety. BACKGROUND OF THE INVENTION

[0002] The present invention relates generally to imaging systems, and more particularly to light detection and ranging (LIDAR)-based imaging systems.

[0003] Conventional LIDAR imaging systems illuminate a target with light, typically coherent laser pulses. The LIDAR imaging system measures the round-trip time of light reflected from the target to determine the distance to the target, and measures the light intensity to generate a three-dimensional image of the scene.

[0004] LIDAR imaging systems can have design requirements such as low uncertainty (e.g., less than 0.1% uncertainty) and ranging over a broad distance range (e.g., between 3 meters and 300 meters). Conventional LIDAR imaging systems with these requirements require very large amounts of memory.

[0005] Accordingly, there is a desire to provide improved LIDAR imaging systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. is a circuit diagram showing an exemplary single-photon avalanche diode pixel according to one embodiment.

[0007] Figure 2 FIG. is a diagram showing an exemplary silicon photomultiplier according to one embodiment.

[0008] Figure 3 FIG. is a schematic diagram of an exemplary silicon photomultiplier having a fast output terminal according to one embodiment.

[0009] Figure 4 FIG. is a diagram showing an exemplary silicon photomultiplier including a microcell array.

[0010] Figure 5 FIG. is a schematic diagram of an exemplary imaging system including a silicon photomultiplier and LIDAR processing circuitry according to one embodiment.

[0011] Figure 6 FIG. is a graph of ranging uncertainty versus distance for a LIDAR system according to one embodiment.

[0012] Figure 7 FIG. is a schematic diagram of an autonomous dynamic resolution (ADR) circuit according to one embodiment, which can be included in the LIDAR processing circuitry to reduce memory requirements.

[0013] Figure 8Schematic diagram showing an address encoder according to an embodiment, which can output a truncated version of the input of a time-to-digital converter (TDC) as an address.

[0014] Figure 9 Table of exemplary TDC bits according to an embodiment, showing how the address encoder can truncate the TDC input.

[0015] Figure 10 Schematic diagram of an exemplary LIDAR processing circuit according to an embodiment, which includes a time-to-digital converter (TDC) and an auto dynamic resolution (ADR) circuit. Detailed Description

[0016] Embodiments of the present invention relate to imaging systems including single-photon avalanche diodes (SPADs).

[0017] Some imaging systems include an image sensor that senses light by converting incident photons into electrons or holes that accumulate (are collected) in pixel photodiodes within a sensor array. After completing an accumulation cycle, the collected charge is converted into a voltage that is provided to the output terminals of the sensor. In a complementary metal-oxide-semiconductor (CMOS) image sensor, the charge-to-voltage conversion is done directly within the pixel itself, and the analog pixel voltage is transferred to the output terminals through various pixel addressing and scanning schemes. The analog pixel voltage can also subsequently be converted into a digital equivalent on-chip and processed in various ways in the digital domain.

[0018] On the other hand, in single-photon avalanche diode (SPAD) devices (such as the devices combined with Figures 1 to 4 those described), the photon detection principle is different. The photosensing diode is biased above its breakdown point, and when an incident photon generates an electron or a hole, the carrier initiates an avalanche breakdown through the additional carriers being generated. Avalanche multiplication can produce a current signal that can be easily detected by a readout circuit associated with the SPAD. The avalanche process can be stopped (or quenched) by reducing the diode bias below its breakdown point. Thus, each SPAD can include passive and / or active quenching circuits for stopping the avalanche.

[0019] This concept can be used in two ways. First, the arriving photons can simply be counted (e.g., in low-light applications). Second, SPAD pixels can be used to measure the time-of-flight (ToF) of photons from a synchronized light source to a scene object point and back to the sensor, and this time-of-flight can be used to obtain a three-dimensional image of the scene.

[0020] Figure 1 Is the circuit diagram of an exemplary SPAD device 202. AsFigure 1 As shown, the SPAD device 202 includes a SPAD 204 serially coupled with a quenching circuit 206 between a first power supply voltage terminal 210 (e.g., a ground power supply voltage terminal) and a second power supply voltage terminal 208 (e.g., a positive power supply voltage terminal). Specifically, the SPAD device 202 includes a SPAD 204 having an anode terminal connected to the power supply voltage terminal 210 and a cathode terminal directly connected to the quenching circuit 206. The SPAD device 202 including the SPAD 204 serially connected with the quenching resistor 206 is sometimes collectively referred to as a light trigger unit or a "microcell". During the operation of the SPAD device 202, the power supply voltage terminals 208 and 210 can be used to bias the SPAD 204 to a voltage higher than the breakdown voltage (e.g., applying a bias voltage Vbias to the terminal 208). The breakdown voltage is the maximum reverse voltage that can be applied to the SPAD 204 without causing an exponential increase in the leakage current in the diode. When the SPAD 204 is reverse biased above the breakdown voltage in this way, the absorption of a single photon can trigger a short but relatively large avalanche current through impact ionization.

[0021] The quenching circuit 206 (sometimes referred to as the quenching element 206) can be used to reduce the bias voltage of the SPAD 204 to a level below the breakdown voltage. Reducing the bias voltage of the SPAD 204 below the breakdown voltage will stop the avalanche process and the corresponding avalanche current. There are various ways to form the quenching circuit 206. The quenching circuit 206 can be a passive quenching circuit or an active quenching circuit. Once the avalanche is initiated, the passive quenching circuit can automatically quench the avalanche current without external control or monitoring. For example, Figure 1 An example of using a resistor component to form the quenching circuit 206 is shown. This is an example of a passive quenching circuit.

[0022] This example of the passive quenching circuit is merely illustrative. An active quenching circuit can also be used in the SPAD device 202. The active quenching circuit can reduce the time taken for the SPAD device 202 to reset. This can allow the SPAD device 202 to detect incident light at a faster rate than when using a passive quenching circuit, thereby improving the dynamic range of the SPAD device. The active quenching circuit can adjust the SPAD quenching resistor. For example, before detecting a photon, the quenching resistor is set to a higher value, and then once a photon is detected and the avalanche is quenched, the quenching resistor is minimized to reduce the recovery time.

[0023] The SPAD device 202 may further include a readout circuit 212. There are various ways to form the readout circuit 212 to obtain information from the SPAD device 202. The readout circuit 212 may include a pulse counting circuit for counting the arriving photons. Alternatively or in addition, the readout circuit 212 may include a time-of-flight (ToF) circuit for measuring the time of flight of photons. The photon time-of-flight information can be used to perform depth sensing. In one example, photons can be counted by an analog counter to form a light intensity signal as the corresponding pixel voltage. The ToF signal can also be obtained by converting the photon time of flight into a voltage. The example of the analog pulse counting circuit included in the readout circuit 212 is merely illustrative. If desired, the readout circuit 212 may include a digital pulse counting circuit. If desired, the readout circuit 212 may further include an amplification circuit.

[0024] Figure 1 The example in which the readout circuit 212 is coupled to the node between the diode 204 and the quenching circuit 206 is merely illustrative. The readout circuit 212 can be coupled to the terminal 208 or any desired part of the SPAD device. In some cases, the quenching circuit 206 can be considered to be integral with the readout circuit 212.

[0025] Since the SPAD device can detect individual incident photons, the SPAD device can effectively image scenes with low light levels. Each SPAD can detect the number of photons received within a given time period (e.g., using a readout circuit including a counting circuit). However, as described above, whenever a photon is received and the avalanche current starts, the SPAD device must be quenched and reset before it is ready to detect another photon. When the incident light level increases, the reset time becomes limited by the dynamic range of the SPAD device (e.g., once the incident light level exceeds a given level, the SPAD device is triggered immediately upon reset).

[0026] Multiple SPAD devices can be grouped together to help increase the dynamic range. Figure 2 is a circuit diagram of an exemplary group 220 of SPAD devices 202. A group or array of SPAD devices is sometimes referred to as a silicon photomultiplier (SiPM). As Figure 2 shown, the silicon photomultiplier 220 may include a plurality of SPAD devices coupled in parallel between a first power supply voltage terminal 208 and a second power supply voltage terminal 210. Figure 2 Shows N SPAD devices 202 (e.g., SPAD device 202-1, SPAD device 202-2, SPAD device 202-3, SPAD device 202-4,..., SPAD device 202-N) coupled in parallel. More than two SPAD devices, more than ten SPAD devices, more than one hundred SPAD devices, more than one thousand SPAD devices, etc. may be included in a given silicon photomultiplier 220.

[0027] Each SPAD device 202 may sometimes be referred to herein as a SPAD pixel 202. Although not explicitly shown in Figure 2 , the readout circuit for the silicon photomultiplier 220 may measure the combined output current from all of the SPAD pixels in the silicon photomultiplier. Configured in this way, the dynamic range of an imaging system including SPAD pixels can be increased. When an incident photon is received, it is not guaranteed that each SPAD pixel will have a triggered avalanche current. A SPAD pixel may have an associated probability of triggering an avalanche current when an incident photon is received. There is a first probability of generating an electron when a photon arrives at the diode, and then a second probability of the electron triggering an avalanche current. The total probability of a photon triggering an avalanche current may be referred to as the photon detection efficiency (PDE) of the SPAD. Thus, grouping multiple SPAD pixels together in a silicon photomultiplier allows for a more accurate measurement of the incoming incident light. For example, if the PDE of a single SPAD pixel is 50% and one photon is received over a certain period of time, there is a 50% chance that the photon will not be detected. Using Figure 2 silicon photomultiplier 220, two out of four SPAD pixels may detect the photon, thus improving the image data for the provided period of time.

[0028] Figure 2 The example of

[0029] As described above, although there are multiple possible use cases for SPAD pixels, the underlying technology for detecting incident light is the same. All of the above examples of devices using SPAD pixels are collectively referred to as SPAD-based semiconductor devices. A silicon photomultiplier including multiple SPAD pixels with a common output can be referred to as an SPAD-based semiconductor device. An SPAD pixel array with pixel-by-pixel readout capability can be referred to as an SPAD-based semiconductor device. A silicon photomultiplier array with silicon photomultiplier-by-silicon photomultiplier readout capability can be referred to as an SPAD-based semiconductor device.

[0030] Figure 3 A silicon photomultiplier 30 is shown. As Figure 3 shown, the SiPM 30 has a third terminal 35 capacitively coupled to each cathode terminal 31 to provide fast readout of the avalanche signal from the SPAD 33. When the SPAD 33 emits a current pulse, a portion of the voltage change generated at the cathode 31 will be capacitively coupled into the third ("fast") output terminal 35 via the mutual capacitance. Using the third terminal 35 for readout avoids degraded transient performance due to the relatively large RC time constant associated with the biasing circuit at the top terminal of the bias quenching resistor.

[0031] Those skilled in the art will understand that a silicon photomultiplier includes a main bus 44 and a secondary bus 45 as Figure 4 shown. The secondary bus 45 can be directly connected to each individual microcell 25. The secondary bus 45 is then coupled to the main bus 44, which is connected to the bond pads associated with terminals 37 and 35. Generally, the secondary bus 45 extends vertically between the columns of the microcells 25, while the main bus 44 extends horizontally adjacent to the outer rows of the microcells 25.

[0032] Figure 5 is a schematic diagram of an exemplary system including a LIDAR imaging system. Figure 5 The system 100 can be a vehicle safety system (e.g., an active braking system or other vehicle safety system), a surveillance system, a medical imaging system, a general machine vision system, or any other desired type of system.

[0033] The system 100 includes a LIDAR-based imaging system 102, sometimes referred to as a LIDAR module. The LIDAR module 102 can be used to capture an image of a scene and measure the distance to an obstacle in the scene.

[0034] In a vehicle safety system, information from a LIDAR module is available for use by the vehicle safety system to determine the environmental conditions around the vehicle. For example, the vehicle safety system may include systems such as a parking assistance system, an automatic or semi-automatic cruise control system, an automatic braking system, a collision avoidance system, a lane keeping system (sometimes referred to as a lane drift avoidance system), a pedestrian detection system, etc. In at least some cases, the LIDAR module may form part of a semi-autonomous or autonomous driverless vehicle.

[0035] The LIDAR module 102 may include a laser 104 that emits light 108 to illuminate an obstacle 110. The laser may emit light 108 of any desired wavelength (e.g., infrared light, visible light, etc.). Optical devices and beam steering equipment 106 may be used to direct the beam from the laser 104 towards the obstacle 110. The light 108 may illuminate the obstacle 110 and return as a reflection 112 to the LIDAR module. One or more lenses in the optical devices and beam steering 106 may focus the reflected light 112 onto a silicon photomultiplier (SiPM) 114 (sometimes referred to as the SiPM sensor 114).

[0036] The silicon photomultiplier 114 is a SPAD-based semiconductor device, as described above in connection with Figures 1 to 4 that. In other words, the silicon photomultiplier 114 may include a plurality of single photon avalanche diodes.

[0037] The LIDAR module 102 may also include a transmitter 116 and a receiver 118. The LIDAR processing circuit 120 may control the transmitter 116 and the laser 104. The LIDAR processing circuit 120 may also receive data from the receiver 118 (and the SiPM 114). Based on the data from the SiPM 114, the LIDAR processing circuit 120 may determine the distance to the obstacle 110. The LIDAR processing circuit 120 may communicate with the system processing circuit 101. The system processing circuit 101 may take corresponding actions (e.g., at the system level) based on the information from the LIDAR module 102.

[0038] The LIDAR processing circuit 120 may include a time-to-digital converter (TDC) circuit 132 and an autonomous dynamic resolution circuit 134 (sometimes referred to as a signal processing circuit 134, a storage circuit 134, a dynamic resolution circuit 134, a dynamic resolution storage circuit 134, etc.). The time-to-digital converter circuit 132 may use time stamps to determine the length of time between the laser emitting light and the SiPM 114 receiving the reflection. The TDC 132 may output a digital value representing the length of time (and thus the distance to the obstacle 110).

[0039] Multiple laser cycles are used to implement the readout of a direct time-of-flight (ToF) LIDAR to create a histogram in memory based on timestamps generated by a SPAD and a time-to-digital converter (TDC). The peak of the histogram is used to determine the time it takes for the laser signal to travel to the target and return to the sensor.

[0040] Whenever the laser emits light, the length of time between the emitted laser and the sensed reflection can be measured. The length of time can be converted into a digital value (e.g., a digital value representing the laser return time). The memory within the LIDAR processing circuit can include multiple bins. Each bin can have an address associated with a corresponding length of time. The digital value representing the length of time can be used to identify the corresponding bin in the memory. Whenever a matching return time is observed, the counter in that bin can then be incremented.

[0041] For example, consider a first bin, a second bin, and a third bin each having an associated length of time. For example, the first bin can be associated with 100 picoseconds, the second bin can be associated with 200 picoseconds, and the third bin can be associated with 300 picoseconds. A first laser pulse can be measured as having a return time of 200 picoseconds. Therefore, after this determination, the count in the second bin is incremented by 1. A second laser pulse can be measured as having a return time of 100 picoseconds. Therefore, after this determination, the count in the first bin is incremented by 1. A third laser pulse can be measured as having a return time of 300 picoseconds. Therefore, after this determination, the count in the third bin is incremented by 1. For many laser pulses, this process can be repeated. The end result is that the memory includes a histogram of the counts (and associated lengths of time) for each bin. The peak of the histogram (e.g., the bin with the highest count) can be used as a measure of the reflection delay (and thus the distance to the obstacle). As a simple example, after 10 laser pulses, the count in the second bin may ultimately be 7, the count in the first bin may be 2, and the count in the third bin may be 1. Therefore, the time associated with the second bin (200 picoseconds) is considered the return time of the laser. This return time has an associated distance to the obstacle. In this way, the peak of the histogram identifies both the return time and the distance to the obstacle.

[0042] The LIDAR imaging system may have a requirement of 0.1% ranging uncertainty over the entire measurement range. For a 300 meter (m) ranging system, this means that a target at 300 m must be detected with 30 cm uncertainty. This corresponds to a time resolution of the least significant bit (LSB) of the TDC of ~2 nanoseconds (ns). However, when the target is in a closer range of 30 m, the required uncertainty becomes 3 centimeters (cm), corresponding to a ~200 picosecond LSB time resolution. Finally, a target that appears at 3 m requires a 20 ps LSB resolution for 3 mm (0.1%) uncertainty.

[0043] To operate with less than 0.1% uncertainty over the entire measurement range from 3m to 300m, the LiDAR system will thus need to be designed with a 20ps LSB time resolution (to have sufficient resolution at the low end of the range).

[0044] To have the required resolution at the low end of the sensing range (e.g., 3mm resolution for 0.1% uncertainty at 3 meters), while still measuring at the highest end of the sensing range (300m), a 17-bit dynamic range TDC will be required. In other words, 300m / 3mm = 100,000, and at least 17 bits are needed to reach 100,000. The number of TDC bits directly translates to the histogram memory requirement.

[0045] In one example, the SPAD array can include 640 x 480 pixels. The memory required to build the histogram is 128kB / pixel (assuming 8 bits / histogram bin). Thus, a column of 480 pixels will require 60MB (which is undesirably high).

[0046] Targets that appear at long ranges do not require such high resolution. Thus, memory can be saved by dynamically adjusting the resolution and keeping the number of bits fixed to a lower value.

[0047] Figure 6 is a graph showing the uncertainty versus distance for various TDC bit parameters. As shown, in the case of 17 bits, over the entire range, the uncertainty can be less than 0.1%. At 16 bits, in most of the range, the uncertainty is less than 0.1%. However, at low distances, the uncertainty can exceed 0.1%. At 12 bits, at the high end of the range (e.g., at distances greater than about 75m), the uncertainty can be less than 0.1%. However, at distances less than 75m, the uncertainty is greater than 0.1%. At 10 bits, only at the highest end of the range (e.g., around 300m), the uncertainty is less than 0.1%.

[0048] To reduce the amount of memory required, a non-fixed LSB resolution scheme can be used. With non-fixed LSB resolution, the LSB resolution can be very high at short distances, but at medium and longer distances, the LSB resolution becomes smaller. This allows for a significant reduction in histogram memory while meeting the 0.1% ranging uncertainty requirement over the entire measurement range.

[0049] An Autonomous Dynamic Resolution (ADR) scheme can be used to meet the uncertainty and ranging requirements while minimizing memory. The Autonomous Dynamic Resolution scheme dynamically applies a data mask to selectively crop the data from the TDC output, thereby reducing the required histogram memory size for achieving the maximum ToF ranging required with a fixed relative uncertainty.

[0050] The autonomous dynamic resolution scheme dynamically applies a data mask to the TDC to selectively crop the timestamp data according to which sub-range the timestamp data falls into. The MSB of the TDC output is used to encode an SRAM repository pointer, which is used to select an appropriate repository for the sub-range to which the timestamp belongs. The repositories form a histogram that has bins scaled by a factor of two compared to adjacent repositories. In this way, the TDC resolution of the repository corresponding to the shortest sub-range is the highest, and the TDC resolution of each subsequent repository corresponding to an increasing sub-range distance increases by a factor of two gradually.

[0051] The LSB resolution of the TDC can be set high enough to measure a target at a certain minimum distance (e.g., 3m) with high precision (e.g., 0.1%).

[0052] The TDC output data can be dynamically cropped based on the result of the MSB. The MSB provides coarse information defining the sub-range in which the target is located.

[0053] The histogram memory is divided into a number of banks, where each bank stores ToF information corresponding to a different sub-range. The bins in bank 0 represent the shortest distance and have the highest TDC resolution. The next bank corresponds to the next sub-range and has half the TDC resolution of the previous bank. The next bank corresponds to the next sub-range and has half the TDC resolution of the previous bank, and so on.

[0054] Figure 7 FIG. 15 is a schematic diagram of the autonomous dynamic resolution circuit 134. As shown, the ADR circuit 134 can receive a TDC value as an input. The TDC value can be a digital value indicating a time length. The TDC value can have any desired number of bits (e.g., 15 bits, 14 bits, 13 bits, 12 bits, less than 12 bits, more than 14 bits, between 6 bits and 20 bits, etc.).

[0055] The ADR circuit 134 includes a repository 506. The repository can be a random access memory (RAM), such as a static random access memory (SRAM) or another desired type of memory. As shown, the memory 506 includes a number of banks (sometimes referred to as pages). Each bank can include a number of bins. Each bin can include a number of bits.

[0056] To reduce the memory requirements of the system, different repositories may have different associated resolutions. For example, repository 0 may have the least significant bit (e.g., bin 0 in the repository) associated with a first time length. Repository 1 may have the least significant bit (LSB) associated with a second time length that is different from (e.g., greater than or less than) the first time length (e.g., bin 0 in the repository). Each repository may have an LSB that is twice the difference from the LSB of an adjacent repository. As an illustrative example, repository 0 may have an LSB associated with 20 picoseconds, repository 1 may have an LSB associated with 40 picoseconds, repository 2 may have an LSB associated with 80 picoseconds, and so on.

[0057] In one example, the number of bits in each bin in memory 506 may be the same (even across different repositories). Considering the above example, compared to a repository with a higher LSB (e.g., 80 picoseconds) but higher overall resolution, the repository with an LSB of 20 picoseconds has a smaller total range. Thus, low TDC values may be stored in the repository with a low LSB (such that the uncertainty remains low even at short distances). High TDC values may be stored in the repository with a high LSB (where the uncertainty remains below the target threshold while reducing memory requirements).

[0058] The ADR circuit 134 may include a repository selection circuit 502 that identifies which repository in the repository 506 should be used. The LSB of each repository is known (e.g., pre-determined). The repository selection circuit 502 may select an appropriate repository for the TDC value based on the magnitude of the TDC value. For example, a low-magnitude input TDC value (e.g., associated with 3 meters) may be assigned to repository 0 (which has the lowest LSB). A high-magnitude input TDC value (e.g., associated with 300 meters) may be assigned to repository n (which has the highest LSB).

[0059] The ADR circuit 134 (sometimes referred to as a dynamic resolution circuit) also includes an address encoder 504 (sometimes referred to as address encoder circuit 504, bin selection circuit 504, etc.). The address encoder 504 may select a subset of bits from the input TDC value to be used as the bin address. The address encoder may select the most relevant bits from the TDC input to act as the address. In other words, the address is a truncated version of the TDC input (where some number of bits are removed from the TDC input to form the address).

[0060] Figure 8 Shown is how the address encoder 504 may output a subset of the input bits as the address. In this example, the address encoder 504 receives a TDC input with a total of 14 bits. The output address has a total of 10 bits. The address encoder 504 selects which 10 bits are used as the output address based on the magnitude of the TDC input. In Figure 8 the example shown, the 10 selected bits include the LSBs for the highest resolution.

[0061] Figure 9 A table showing how the address encoder can select bits for the output address. In the first row, bits 9 to 13 of the TDC input value are 0. Therefore, the least significant bits (bits 0 to 9) can be output as the address (to bank 0). In the second row, bits 10 to 13 of the TDC input value are 0. Similarly, the least significant bits (bits 0 to 9) can be output as the address (to bank 1). In row 2, bit 10 is 1 and bits 11 to 13 are 0. Therefore, bit 0 of the TDC input can be discarded (as shown by 'D'), and bits 1 to 10 can be output as the address (to bank 2). In row 3, bit 11 is 1 and bits 12 to 13 are 0. Therefore, bits 0 and 1 of the TDC input can be discarded, and bits 2 to 11 can be output as the address (to bank 3). In row 4, bit 12 is 1 and bit 13 is 0. Therefore, bits 0, 1, and 2 of the TDC input can be discarded, and bits 3 to 12 can be output as the address (to bank 4). In row 5, bit 13 is 1. Therefore, bits 0, 1, 2, and 3 of the TDC input can be discarded, and bits 4 to 13 can be output as the address (to bank 5). Note that the resolution of each bank is flexible. In this particular example, the first 2 banks both have the same resolution (LSB = bit 0) to give the highest resolution over an extended range.

[0062] The output address can identify the bin address in the memory 506. These banks can all have the same number of bins. Therefore, the output address from the encoder 504 only identifies the bin number (which can apply to any bank as identified by the bank selection circuit 502). When the bin number is selected by the address encoder 504, the counter for that bin is incremented. This process can be repeated for many input TDC values to build the aforementioned histogram.

[0063] Figure 10 A schematic diagram of a LIDAR processing circuit that includes a time-to-digital converter (TDC) circuit 132 and an autonomous dynamic resolution circuit 134. As shown, the output from the TDC 132 is provided to both the bank selection circuit 502 and the address encoder 504. The bank selection circuit 502 selects an appropriate bank from the memory 506 based on the TDC input. The address encoder 504 outputs a subset of the bits in the TDC input as an address. The address output by the address encoder 504 identifies the corresponding bin. After the bin is selected by the address from the encoder 504, the counter for that bin is updated. Figure 10 The embedded part 508 in shows an example of a counter that can be used to increment the count in the memory 506.

[0064] The address encoder 504 includes a plurality of multiplexers 510. In Figure 10In this case, each multiplexer has five inputs and one corresponding output. The multiplexer outputs a selected one of the five inputs based on the magnitude of the TDC input. For example, if the TDC input is low, the multiplexer may output bits 0 to 9 (as Figure 9 shown). If the TDC input is high, the multiplexer may output bits 4 to 13 and discard bits 0 to 3 (as Figure 9 shown).

[0065] In other words, the TDC input can be classified within a given sub-range. The multiplexer inputs can also each have a corresponding sub-range. For example, the first input to each multiplexer is associated with a first sub-range, the second input to each multiplexer is associated with a second sub-range, the third input to each multiplexer is associated with a third sub-range, and so on. If the TDC input is within the first sub-range, each multiplexer may output its first input (associated with the first sub-range) as the output. If the TDC input is within the second sub-range, each multiplexer may output its second input (associated with the second sub-range) as the output, and so on.

[0066] It should be noted that the resolution of each bank (e.g., the time and thus the distance associated with the LSB) and the size (e.g., the number of bins) are flexible. The resolution of each successive bank does not have to be less than the previous bank, and the size of each bank does not have to be the same.

[0067] In one example, the memory 506 includes six banks, each having 512 bins. This example is merely illustrative, and in general, the memory 506 can include any number of banks and any number of bins per bank. Each bin can include any desired number of bits.

[0068] When outputting the address, the address encoder 504 can remove any desired number of bits from the TDC input. For example, the output address can be 1 bit, 2 bits, 3 bits, 4 bits (as Figure 8 shown), 5 bits, 6 bits, 7 bits, more than 7 bits, between (and including) 3 bits and 6 bits, etc., smaller than the TDC input.

[0069] ADR (as Figures 5 to 10 shown) improves the maximum ranging distance for a fixed memory size. For a fixed memory of 24 kbps / pixel, ADR has a 6× ranging improvement compared to the fixed resolution.

[0070] Some key benefits of this autonomous dynamic resolution scheme are that no information is lost. A linear "full" histogram with dynamic resolution is used to achieve constant uncertainty across the entire measurement range. There are no boundary condition issues. The memory requirements can be significantly reduced using the ADR scheme (compared to a fixed LSB scheme). The frame rate is not reduced due to bin iteration. The readout scheme can also be applied to any desired range measurement. In other words, the design is flexible and can be applied to LIDAR systems regardless of the specific range of interest.

[0071] The autonomous dynamic resolution scheme enables a high-resolution SPAD array for LIDAR imaging systems. Memory compression helps reduce die size. Memory compression allows for more pixels to be used in LiDAR systems with limited and fixed memory resources. Memory compression directly impacts die area, yield, and test requirements, resulting in lower manufacturing costs. The TDC operates at a fixed frequency without the need to control (multiplex) the clock frequency. It is easy to implement and reuse even for different TDC resolutions.

[0072] According to one embodiment, a system may include: a semiconductor device including single-photon avalanche diodes; and a processing circuit configured to receive an output signal from the semiconductor device. The processing circuit may include a time-to-digital converter configured to output a value representing a time length based on the output signal from the semiconductor device, and a dynamic resolution storage circuit that receives the value. The dynamic resolution storage circuit may include a first repository having an associated first resolution and a second repository having an associated second resolution different from the first resolution.

[0073] According to another embodiment, the second resolution differs from the first resolution by a factor of two.

[0074] According to another embodiment, the first repository may include a first plurality of bins, each of the first plurality of bins may include a corresponding first plurality of bits, the second repository may include a second plurality of bins, and each of the second plurality of bins may include a corresponding second plurality of bits.

[0075] According to another embodiment, the number of bins in the first plurality of bins may be the same as the number of bins in the second plurality of bins.

[0076] According to another embodiment, the number of bits in the first plurality of bits may be the same as the number of bits in the second plurality of bits.

[0077] According to another embodiment, the least significant bit of the first repository may be associated with a first time length, and the least significant bit of the second repository may be associated with a second time length different from the first time length.

[0078] According to another embodiment, the second time length may differ from the first time length by a factor of two.

[0079] According to another embodiment, the first repository and the second repository are part of a plurality of repositories, and the dynamic resolution storage circuit may include a repository selection circuit configured to select one of the plurality of repositories based on a value from a time-to-digital converter.

[0080] According to another embodiment, the dynamic resolution storage circuit may include an address encoder configured to output an address based on a value from a time-to-digital converter.

[0081] According to another embodiment, the address may be a truncated version of the value, the truncated version including fewer bits than the value.

[0082] According to another embodiment, the address encoder may include a plurality of multiplexers, each having a plurality of inputs, and each multiplexer may be configured to output a selected one of the plurality of inputs.

[0083] According to another embodiment, the system may further include a laser configured to emit light. The value representing the time length may represent the return time associated with the light emitted by the laser.

[0084] According to one embodiment, a system may include: a semiconductor device including a single-photon avalanche diode; and a processing circuit configured to receive an output signal from the semiconductor device. The processing circuit may include: a time-to-digital converter configured to output a value representing a time length based on the output signal from the semiconductor device; a plurality of repositories, where each repository includes a plurality of bins; a repository selection circuit configured to select one of the plurality of repositories based on the value; and an address encoder configured to output an address of one of the plurality of bins based on the value.

[0085] According to another embodiment, each repository may have a corresponding least significant bit quantity value, and the least significant bit quantity values of at least two different repositories may be different.

[0086] According to another embodiment, the address encoder may include a plurality of multiplexers. Each multiplexer has a plurality of inputs, each of the plurality of inputs receiving a corresponding bit of the value, and each multiplexer may be configured to output a selected one of the plurality of inputs.

[0087] According to another embodiment, the address may be a truncated version of the value, the truncated version including fewer bits than the value.

[0088] According to another embodiment, different repositories among the plurality of repositories may have different resolutions.

[0089] According to one embodiment, a system may include a silicon photomultiplier and processing circuitry configured to receive an output signal from the silicon photomultiplier. The processing circuitry may include a time-to-digital converter and an address encoder. The time-to-digital converter is configured to output a value representing a length of time based on the output signal from the silicon photomultiplier, where the value includes a first number of bits. The address encoder is configured to receive the value and output a truncated version of the value, the truncated version including a second number of bits, where the second number is less than the first number.

[0090] According to another embodiment, the system may further include a plurality of bins. The truncated version of the value may identify a bin among the plurality of bins.

[0091] According to another embodiment, the bin identified by the truncated version of the value may have a counter that increments by 1 when identified by the truncated version of the value.

[0092] The foregoing are merely illustrative descriptions of the principles of the present invention, and those skilled in the art can make various modifications. The above embodiments can be implemented individually or in any combination.

Claims

1. A light detection and ranging system, comprising: a semiconductor device including a single photon avalanche diode; and a processing circuit configured to receive an output signal from the semiconductor device, wherein the processing circuit includes: a time-to-digital converter configured to output a value representing a time length based on the output signal from the semiconductor device; and a dynamic resolution storage circuit that receives the value, wherein the dynamic resolution storage circuit includes a first repository having an associated first resolution and a second repository having an associated second resolution different from the first resolution, wherein each repository includes a plurality of bins, and wherein the dynamic resolution storage circuit includes an address encoder configured to output an address of one of the plurality of bins based on the value from the time-to-digital converter.

2. The light detection and ranging system according to claim 1, wherein the second resolution differs from the first resolution by a factor of two.

3. The light detection and ranging system according to claim 1, wherein the first repository includes a first plurality of bins, wherein each bin in the first plurality of bins includes a corresponding first plurality of bits, wherein the second repository includes a second plurality of bins, and wherein each bin in the second plurality of bins includes a corresponding second plurality of bits.

4. The light detection and ranging system according to claim 3, wherein the number of bins in the first plurality of bins is the same as the number of bins in the second plurality of bins, and wherein the number of bits in the first plurality of bits is the same as the number of bits in the second plurality of bits.

5. The light detection and ranging system according to claim 3, wherein the least significant bit of the first repository is associated with a first time length, wherein the least significant bit of the second repository is associated with a second time length different from the first time length, and wherein the second time length differs from the first time length by a factor of two.

6. The light detection and ranging system according to claim 1, wherein the first repository and the second repository are part of a plurality of repositories, and wherein the dynamic resolution storage circuit includes a repository selection circuit configured to select one of the plurality of repositories based on the value from the time-to-digital converter.

7. The light detection and ranging system according to claim 6, wherein the address is a truncated version of the value, the truncated version including fewer bits than the value, and wherein the address encoder includes a plurality of multiplexers, each of the plurality of multiplexers having a plurality of inputs, and wherein each multiplexer is configured to output a selected one of the plurality of inputs.

8. The light detection and ranging system according to claim 1, further comprising: a laser configured to emit light, wherein the value representing the time length represents a return time associated with the light emitted by the laser.

9. A light detection and ranging system, comprising: A semiconductor device, the semiconductor device including a single photon avalanche diode; and A processing circuit, the processing circuit being configured to receive an output signal from the semiconductor device, wherein the processing circuit includes: A time-to-digital converter, the time-to-digital converter being configured to output a value representing a time length based on the output signal from the semiconductor device; A plurality of repositories, wherein each repository includes a plurality of bins; A repository selection circuit, the repository selection circuit being configured to select one of the plurality of repositories based on the value; and An address encoder, the address encoder being configured to output an address of one of the plurality of bins based on the value.

10. A light detection and ranging system, comprising: A silicon photomultiplier; and A processing circuit, the processing circuit being configured to receive an output signal from the silicon photomultiplier, wherein the processing circuit includes: A time-to-digital converter, the time-to-digital converter being configured to output a value representing a time length based on the output signal from the silicon photomultiplier, wherein the value includes a first number of bits; An address encoder, the address encoder being configured to receive the value and output a truncated version of the value, the truncated version including a second number of bits, wherein the second number is less than the first number; and A plurality of storage bins, wherein the truncated version of the value identifies an address of one of the plurality of storage bins.

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