Readout IC

Abstract

A readout integrated circuit is provided, the readout integrated circuit being configured to read out a sensing signal from an optical sensing panel, the optical sensing panel comprising a sensor array for fingerprint sensing. The readout integrated circuit comprises a plurality of input terminals, a comparator circuit and a control circuit. The plurality of input terminals are used to couple to a plurality of output terminals of the optical sensing panel. The comparator circuit is coupled to one of the plurality of input terminals. The comparator circuit is configured to receive an output voltage from one of the plurality of output terminals of the optical sensing panel and at least one reference voltage, compare the output voltage with the at least one reference voltage and output a comparison result. The control circuit is coupled to the comparator circuit. The control circuit is configured to receive the comparison result and determine the amount of supplementary charge to be charged to the output terminal or to be discharged from the output terminal according to the comparison result.

Description

Technical Field

[0001] The present invention relates to an electronic circuit, and more particularly to a readout integrated circuit. Background Art

[0002] In an in-display fingerprint sensing panel with an optical sensor, an optical sensor array is fabricated on a lower substrate of a display panel. The optical sensor is configured as a sensor array for sensing reflected light of a finger on the fingerprint sensing panel to generate a fingerprint sensing signal, and a fingerprint sensing integrated circuit receives the fingerprint sensing signal through a sensing line and an output terminal of the fingerprint sensing panel. The fingerprint sensing integrated circuit is configured to read out the fingerprint sensing signal and further transmit the fingerprint sensing signal converted into digital sensing data to a processor unit for fingerprint recognition. For example, a handheld device such as a mobile phone includes a touch display screen with an in-display fingerprint sensing panel, and the fingerprint sensing integrated circuit of the mobile phone transmits the fingerprint sensing data to an application processor. The application processor then performs image processing on the fingerprint sensing data to generate a fingerprint image for fingerprint recognition.

[0003] However, when the size of the fingerprint sensing panel is large, the transmission distances from optical sensors (called fingerprint sensing pixels) at different positions to the output terminals of the fingerprint sensing panel are different. Some optical sensors are closer to the corresponding output terminals and transmit fingerprint sensing signals at a shorter distance, while other optical sensors are farther from the corresponding output terminals and transmit fingerprint sensing signals at a longer distance. For optical sensors that are farther from the corresponding output terminals, the fingerprint sensing signals are transmitted on the sensing lines with a large load. This may have a negative impact on the fingerprint sensing signals. For example, the settling time of the fingerprint sensing signal may be too long, thereby deteriorating the quality of the fingerprint image generated based on the fingerprint sensing signal. Summary of the invention

[0004] The present invention relates to a readout integrated circuit, in which the stabilization time of a fingerprint sensing signal is short to improve the quality of a fingerprint image.

[0005] An embodiment of the present invention provides a readout integrated circuit, which is configured to read out a sensing signal from an optical sensing panel, wherein the optical sensing panel includes a sensor array for fingerprint sensing. The readout integrated circuit includes a plurality of input terminals, a comparator circuit, and a control circuit. The plurality of input terminals are used to couple to a plurality of output terminals of the optical sensing panel. The comparator circuit is coupled to one of the plurality of input terminals. The comparator circuit is configured to receive an output voltage of one of the plurality of output terminals of the optical sensing panel and at least one reference voltage, compare the output voltage with the at least one reference voltage, and output a comparison result. The control circuit is coupled to the comparator circuit. The control circuit is configured to receive the comparison result and determine the amount of supplementary charge to be charged to the output terminal or to be discharged from the output terminal according to the comparison result.

[0006] In an embodiment of the present invention, the comparator circuit compares the output voltage with the at least one reference voltage at different time points to generate at least one comparison result. Based on the corresponding comparison result, the control circuit determines the amount of the supplementary charge to be charged to the output terminal or to be discharged from the output terminal.

[0007] In an embodiment of the present invention, the at least one reference voltage includes a first reference voltage. When the comparison result indicates that the output voltage is within a range from the first reference voltage to a maximum reference voltage, the control circuit determines a first charge amount as the supplementary charge amount to be charged to the output terminal according to the comparison result. When the comparison result indicates that the output voltage is less than the first reference voltage, the control circuit determines a charge amount less than the first charge amount as the supplementary charge amount to be charged to the output terminal according to the comparison result.

[0008] In an embodiment of the present invention, the at least one reference voltage further includes a second reference voltage that is smaller than the first reference voltage. When the comparison result indicates that the output voltage is within the range from the second reference voltage to the first reference voltage, the control circuit determines a second charge amount as the supplementary charge amount to be charged to the output terminal according to the comparison result. When the comparison result indicates that the output voltage is smaller than the second reference voltage, the control circuit determines a charge amount smaller than the second charge amount as the supplementary charge amount to be charged to the output terminal according to the comparison result.

[0009] In an embodiment of the present invention, the at least one reference voltage further includes a third reference voltage that is smaller than the second reference voltage. When the comparison result indicates that the output voltage is within the range from the third reference voltage to the second reference voltage, the control circuit determines a third charge amount as the supplementary charge amount to be charged to the output terminal according to the comparison result. When the comparison result indicates that the output voltage is smaller than the third reference voltage, the control circuit determines a charge amount smaller than the third charge amount as the supplementary charge amount to be charged to the output terminal according to the comparison result.

[0010] In an embodiment of the present invention, the at least one reference voltage includes a first reference voltage. When the comparison result indicates that the output voltage is within a range from the first reference voltage to a minimum reference voltage, the control circuit determines a first charge amount as the supplementary charge amount to be discharged from the output terminal according to the comparison result. When the comparison result indicates that the output voltage is greater than the first reference voltage, the control circuit determines a charge amount less than the first charge amount as the supplementary charge amount to be discharged from the output terminal according to the comparison result.

[0011] In an embodiment of the present invention, the at least one reference voltage further includes a second reference voltage greater than the first reference voltage. When the comparison result indicates that the output voltage is within the range from the second reference voltage to the first reference voltage, the control circuit determines a second charge amount as the supplementary charge amount to be discharged from the output terminal according to the comparison result. When the comparison result indicates that the output voltage is greater than the second reference voltage, the control circuit determines a charge amount less than the second charge amount as the supplementary charge amount to be discharged from the output terminal according to the comparison result.

[0012] In an embodiment of the present invention, the at least one reference voltage further includes a third reference voltage greater than the second reference voltage. When the comparison result indicates that the output voltage is within the range from the third reference voltage to the second reference voltage, the control circuit determines a third charge amount as the supplementary charge amount to be discharged from the output terminal according to the comparison result. When the comparison result indicates that the output voltage is greater than the third reference voltage, the control circuit determines a charge amount less than the third charge amount as the supplementary charge amount to be discharged from the output terminal according to the comparison result.

[0013] In an embodiment of the present invention, the readout integrated circuit further comprises a first charging / discharging circuit. The first charging / discharging circuit is coupled to the output terminal. The first charging / discharging circuit is configured to be controlled by the control circuit to charge or discharge the output terminal by a first current. The first charging / discharging circuit comprises a first current source controlled by a first voltage to generate the first current.

[0014] In an embodiment of the present invention, the first charging / discharging circuit further comprises a switching element. The switching element is coupled to a control terminal of the first current source, so that the on-period of the switching element determines the period during which the first current source outputs the first current. The amount of supplementary charge is determined based on the first current and the period during which the first current source outputs the first current.

[0015] In an embodiment of the present invention, the switch element is coupled to the control circuit and is turned on or off by a control signal from the control circuit. The control signal is generated by the control circuit according to the determined amount of the supplementary charge.

[0016] In an embodiment of the present invention, the first charge / discharge circuit further comprises a conversion circuit. The conversion circuit is coupled to a control terminal of the first current source and the control circuit. The conversion circuit is configured to generate a control voltage to be output to the control terminal of the first current source according to a control signal from the control circuit. The amount of the first current is determined according to the control voltage.

[0017] In an embodiment of the present invention, a period during which the first current source outputs the first current is determined by the control signal from the control circuit.

[0018] In an embodiment of the present invention, the readout integrated circuit further comprises a first charging / discharging circuit. The first charging / discharging circuit is coupled to the output terminal. The first charging / discharging circuit is configured to be controlled by the control circuit to charge or discharge the output terminal. The first charging / discharging circuit comprises a buffer circuit. The buffer circuit is configured to receive an input voltage from the control circuit and a timing control signal from the control circuit and output a driving voltage to charge or discharge the output terminal. The period of the buffer circuit outputting the driving voltage is controlled by the timing control signal.

[0019] In an embodiment of the present invention, the readout integrated circuit further comprises a second charging / discharging circuit. The second charging / discharging circuit is coupled to the output terminal. The second charging / discharging circuit is configured to charge or discharge the output terminal through a second current.

[0020] In an embodiment of the present invention, the output terminal is coupled to a second charging / discharging circuit. The second charging / discharging circuit is disposed in a display panel provided with the sensor array. The second charging / discharging circuit is configured to charge or discharge the output terminal through a second current.

[0021] In an embodiment of the present invention, the readout integrated circuit further comprises a storage circuit. The storage circuit is coupled to the control circuit. The storage circuit is configured to store a lookup table. Lookup table information of different charge amounts corresponds to a plurality of pre-configured comparison results.

[0022] In order to make the above contents easier to understand, several embodiments with drawings are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0024] Figure 1 is a schematic block diagram of a readout integrated circuit and an optical sensing panel according to an embodiment of the present invention.

[0025] Figure 2 According to an embodiment of the present invention Figure 1 A schematic block diagram of a readout integrated circuit is shown in FIG.

[0026] Figure 3 is a schematic diagram of multiple sensor circuits according to an embodiment of the present invention.

[0027] Figure 4 is a schematic block diagram showing a readout integrated circuit according to another embodiment of the present invention.

[0028] Figure 5 is a schematic diagram showing a sensor circuit and a readout integrated circuit according to an embodiment of the present invention.

[0029] Figure 6 1 is a waveform diagram of different output voltages at the output terminal during different operation cycles according to an embodiment of the present invention.

[0030] Figure 7 4 is a waveform diagram of different output voltages at the output terminal during different operation cycles according to another embodiment of the present invention.

[0031] Figure 8 4 is a waveform diagram of different output voltages at the output terminal during different operation cycles according to another embodiment of the present invention.

[0032] Fig. 9is a schematic diagram showing a sensor circuit and a readout integrated circuit according to an embodiment of the present invention.

[0033] Fig.10 1 is a waveform diagram of different output voltages at the output terminal during different operation cycles according to an embodiment of the present invention.

[0034] Fig.11 4 is a waveform diagram of different output voltages at the output terminal during different operation cycles according to another embodiment of the present invention.

[0035] Fig.12 4 is a waveform diagram of different output voltages at the output terminal during different operation cycles according to another embodiment of the present invention.

[0036] Fig.13 FIG. 5 is a schematic diagram showing a sensor circuit and a readout integrated circuit according to another embodiment of the present invention.

[0037] Fig.14 FIG. 5 is a schematic diagram showing a sensor circuit and a readout integrated circuit according to another embodiment of the present invention.

[0038] Fig.15 FIG. 5 is a schematic diagram showing a sensor circuit and a readout integrated circuit according to another embodiment of the present invention.

[0039] Fig.16 FIG. 5 is a schematic diagram showing a sensor circuit and a readout integrated circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following embodiments are provided to elaborate on the present disclosure, but the present disclosure is not limited to the provided embodiments, and the provided embodiments may be appropriately combined. The terms "coupling / coupled" or "connecting / connected" used in this specification (including claims) of the present application may refer to any direct or indirect connection method. For example, "a first device is coupled to a second device" should be interpreted as "a first device is directly connected to a second device" or "a first device is indirectly connected to a second device via other devices or connection methods." In addition, the term "signal" may refer to current, voltage, charge, temperature, data, electromagnetic waves, or any one or more signals.

[0041] Figure 1 FIG. 1 is a schematic block diagram of a readout integrated circuit and an optical sensing panel according to an embodiment of the present invention. In this embodiment, the optical sensing panel is an under-screen fingerprint sensing panel fabricated on a display panel. Figure 2 According to an embodiment of the present invention Figure 1 A schematic block diagram of a readout integrated circuit is shown in FIG. Figure 3is a schematic diagram of a plurality of sensor circuits according to an embodiment of the present invention, which is arranged in Figure 1 A column of sensor circuits in a sensor array of an optical sensing panel.

[0042] Reference Figures 1 to 3 , the optical sensing panel 200 includes a sensor array, a plurality of sensing lines 204, and a plurality of output terminals 202. The sensor array is formed by a plurality of sensor circuits 210 as sensing pixels. The output terminals 202 can output fingerprint sensing signals. Each column of the sensor circuit is coupled to a respective sensing line 204. The number of output terminals 202 of the optical sensing panel 200 can be the same as or less than the number of sensing lines 204.

[0043] The readout integrated circuit 100 includes a plurality of input terminals 206. The input terminals 206 are configured to be coupled to some output terminals 202 in the optical sensing panel 200. It should be noted that, for the fingerprint sensing operation, the number of fingerprint sensing signals processed simultaneously by the readout integrated circuit 100 is determined based on the circuit design of the readout integrated circuit 100, and the processing number may be related to the number of analog front-end circuits in the readout integrated circuit 100, but is not limited thereto, and the analog front-end circuit may process the received fingerprint sensing signals in parallel. The position and number of the sensor circuits 210 for performing the fingerprint sensing operation may not be all the sensor circuits in the optical sensing panel 200. The sensor circuits 210 for performing the fingerprint sensing operation may be a preset part of the sensor array, or may be determined based on the touch position of the touch event. In one embodiment, the optical sensing panel 200 has 1080 rows of sensor circuits, 1080 sensing lines, and 1080 output terminals, and the readout integrated circuit 100 includes 250 input terminals, and only 250 of the 1080 output terminals of the optical sensing panel 200 are respectively coupled to the 250 input terminals of the readout integrated circuit 100. Therefore, at the same time, the fingerprint sensing signals generated from the 250 sensor circuits in the same row can be transmitted to the readout integrated circuit 100 through the 250 output terminals.

[0044] exist Figure 3, only the sensor circuit 210 coupled to the same column of sensing lines 204 is shown as an example, but the present invention is not limited thereto. From the perspective of the readout integrated circuit 100, the input terminal 206 of the readout integrated circuit 100 is coupled to a portion of the sensing line 204 through a portion of the output terminal 202 of the optical sensing panel 200. The readout integrated circuit 100 is configured to read out the output voltage Vout of the output terminal 202. The output voltage Vout can ideally be expected to be equal to the output voltage of the sensor circuit (which is referred to as the sensing voltage Vs). However, the farther the distance between the sensor circuit and the output terminal 202, the greater the load of the resistor and capacitor on the sensing line 204, which will make the output voltage Vout of the output terminal 202 stabilize to the sensing voltage Vs. It should be noted that with respect to the output voltage Vout of the output terminal 202 during the reading period, the output voltage Vout of the output terminal 202 at the beginning of the reading period can be referred to as the initial output voltage. At the beginning of the read period, if the initial output voltage Vout is greater than the sensing voltage Vs, the process from the initial output voltage Vout to the actual output of the sensing voltage Vs by the sensor circuit can be regarded as a discharging process. Here, the initial output voltage Vout of the output terminal 202 at the beginning of the read period can be determined according to the circuit design of the readout integrated circuit 100. In other embodiments, at the beginning of the read period, if the initial output voltage Vout is less than the sensing voltage Vs, the process from the initial output voltage Vout to the actual output of the sensing voltage Vs by the sensor circuit can be regarded as a charging process.

[0045] The readout integrated circuit 100 includes a comparator circuit 140 and a control circuit 130. Figure 3As shown in FIG. 1 , the comparator circuit 140 is coupled to one of the input terminals 206 among the plurality of input terminals 206. That is, the comparator circuit 140 is coupled to one of the output terminals 202 of the plurality of output terminals 202 of the optical sensing panel 200 through the input terminal 206. The comparator circuit 140 is configured to receive an output voltage Vout from the output terminal 202 and at least one reference voltage VREF. The comparator circuit 140 compares the output voltage Vout with the at least one reference voltage VREF, and outputs a comparison result 300 to the control circuit 130. The control circuit 130 is coupled to the comparator circuit 140. The control circuit 130 is configured to receive the comparison result 300, and determine the amount of supplementary charge to be charged to the output terminal 202 or to be discharged from the output terminal 202 according to the comparison result 300, so that the voltage of the output terminal 202 can be close to the corresponding target voltage (that is, the sensing voltage output by the sensor circuit 2 without considering the resistance and capacitance load). The stabilization time of the fingerprint sensing signal (that is, the output voltage) is short to improve the quality of the fingerprint image. The stabilization time is the time required for the output voltage Vout to reach and remain within a given frequency band.

[0046] In an embodiment, the control circuit 130 may include a controller implemented by one or more processing elements, such as a logic gate array, an arithmetic logic unit, a digital signal processor, a microcomputer, a programmable logic controller, a field programmable gate array, a programmable logic array, a microprocessor, or any other device or combination of devices configured to respond to instructions in a defined manner and execute the instructions to achieve a desired result.

[0047] Figure 4 FIG. 2 is a schematic block diagram showing a readout integrated circuit according to another embodiment of the present invention. Figure 2 and Figure 4 The readout integrated circuit 400 of this embodiment is similar to Figure 2 The readout integrated circuit 100 is shown in the figure, and the main difference between the readout integrated circuit 400 and the readout integrated circuit 100 is, for example, that the readout integrated circuit 400 further includes a first charge / discharge circuit 110 and a second charge / discharge circuit 120. In an embodiment, the second charge / discharge circuit 120 is disposed in the readout integrated circuit 400, and the readout integrated circuit 400 is implemented in a single semiconductor chip or circuit system, but the present invention is not limited thereto. In another embodiment, the second charge / discharge circuit 120 may be implemented in a device different from the readout integrated circuit 400. For example, the second charge / discharge circuit 120 may be disposed in a display panel (not shown) provided with the sensor array 200.

[0048] The first charge / discharge circuit 110 is coupled to the output terminal 202. Figure 5As shown in FIG. 1 , the first charge / discharge circuit 110 is configured to be controlled by the control circuit 130 via a control signal Vctrl to charge or discharge the output terminal 202 through a first current I1. The second charge / discharge circuit 120 is coupled to the output terminal 202. Figure 5 As shown in , the second charge / discharge circuit 120 is configured to charge or discharge the output terminal 202 through the second current I2. In an embodiment, the second charge / discharge circuit 120 can also be controlled by the control circuit 130.

[0049] Figure 5 Schematic diagram showing a sensor circuit and a readout integrated circuit according to an embodiment of the present invention. Figure 5 The readout integrated circuit 400A includes a first charge / discharge circuit 110A, a second charge / discharge circuit 120A, a control circuit 130, a comparator circuit 140, and a storage circuit 150. Figure 5 2 further illustrates the circuit structure of the sensor circuit 210, the first charging / discharging circuit 110A, and the second charging / discharging circuit 120A. However, the circuit structure is not intended to limit the present invention.

[0050] An active pixel structure of four transistors is used as an example of the sensor circuit 210. During the reset period, the reset transistor M RS is turned on, and the voltage at the node Nr is pulled up to the high voltage VDD to turn off the transistor M SF The source follower is formed. During the reset period, the output voltage Vout of the output terminal 202 is discharged. During the exposure period, the light sensing mechanism is implemented, and the photodiode PD generates a current. During the readout period, the transistor M is selected. SEL is turned on, and then the reset transistor M RS Next, the transfer transistor M TG is turned on, and the sensing voltage about the fingerprint information is transmitted to the node Nr. Therefore, the voltage at the node Nr changes from the high voltage VDD to the sensing voltage, which is lower than the high voltage VDD. During the readout period, the output voltage Vout when reaching a steady state is determined by the voltage at the node Nr. For example, when the voltage at the node Nr during the readout period is a stable voltage of 2V, the stable output voltage Vout is close to the voltage 2V-Vgs, where Vgs is the voltage generated by the transistor M. SF The voltage difference between the gate terminal and the source terminal of the source follower is formed. Therefore, the output voltage Vout is read out during the readout period and used as a sense signal.

[0051] The first charge / discharge circuit 110A operates as a charging circuit. The first charge / discharge circuit 110A includes a first current source 112 and a switch element 114. The first current source 112 is controlled by a first voltage Vb1 to generate a first current I1. The first current source 112 includes a first terminal, a second terminal, and a control terminal. The first current I1 is transmitted from the first terminal to the second terminal. The first terminal of the first current source 112 is coupled to a high voltage VDD. The second terminal of the first current source 112 is coupled to the output terminal 202 and the comparator circuit 140. The control terminal of the first current source 112 is coupled to the first voltage Vb1. The switch element 114 is controlled by a control signal Vctrl. The switch element 114 includes a first terminal, a second terminal, and a control terminal. The first terminal of the switch element 114 is coupled to the first voltage Vb1. The second terminal of the switch element 114 is coupled to the control terminal of the first current source 112. The control terminal of the switch element 114 is coupled to the control signal Vctrl.

[0052] Specifically, the switch element 114 is coupled to the control circuit 130. The switch element 114 is turned on or off by the control signal Vctrl from the control circuit 130. The control signal Vctrl is generated by the control circuit 130 according to the determined amount of supplementary charge. The switch element 114 is coupled to the control terminal of the first current source I1, so that the on-period of the switch element 114 determines the period of the first current source 112 outputting the first current I1. The amount of supplementary charge is determined based on the first current I1 and the period of the first current source 112 outputting the first current I1. For example, when the first current source 112 is turned on, the amount of supplementary charge is determined based on the value of the first current I1. The larger the value of the first current I1, the larger the amount of supplementary charge. In addition, the longer the period of the first current source 112 outputting the first current I1, the larger the amount of supplementary charge.

[0053] The second charge / discharge circuit 120A also operates as a charging circuit. The second charge / discharge circuit 120A is coupled to the output terminal 202 of the sensor array 200. The second charge / discharge circuit 120A is configured to charge the output terminal 202 by the second current I2 during the readout cycle. The second charge / discharge circuit 120A includes a second current source 122. The second current source 122 is controlled by a second voltage Vb2 to generate a second current I2. The second current source 122 includes a first terminal, a second terminal and a control terminal. The second current I2 is transmitted from the first terminal to the second terminal. The first terminal of the second current source 122 is coupled to the high voltage VDD. The second terminal of the second current source 122 is coupled to the output terminal 202. The control terminal of the second current source 122 is coupled to the second voltage Vb2.

[0054] In one embodiment, the first current I1 is greater than the second current I2, so that the charging operation is dominated by the first charging / discharging circuit 110A, but the invention is not limited thereto. In another embodiment, the first current I1 may be equal to or less than the second current I2.

[0055] The control circuit 130 is coupled to the first charge / discharge circuit 110A. The control circuit 130 receives the comparison result 300 and determines the amount of supplementary charge to be charged to the output terminal 202 according to the comparison result 300, so that the voltage of the output terminal 202 can be close to the corresponding target voltage. The target voltage (i.e., the sensing voltage) follows the voltage at the node Nr. The control circuit 130 outputs a control signal Vctrl to control the operation cycle of the first charge / discharge circuit 110A. The operation cycle of the first charge / discharge circuit 110A indicates the cycle in which the first charge / discharge circuit 110A charges the output terminal 202 of the sensor array 200.

[0056] Figure 6 is a waveform diagram of different output voltages at the output terminal during different operation cycles according to an embodiment of the present invention. Figure 5 and Figure 6 , the voltage at the output terminal 202 can be regarded as the output voltage Vout. Figure 6 In the example, the signal range SR is the input voltage range of the analog-to-digital converter. The input voltage range is the voltage range between the highest input voltage (maximum reference voltage) V1 and the lowest input voltage (minimum reference voltage) V2.

[0057] The comparator circuit 140 compares the output voltage Vout with the reference voltage VREF1 (first reference voltage) at different time points T1 and T2 to generate a comparison result 300. According to the comparison result 300, the control circuit 130 determines the amount of supplementary charge to be charged to the output terminal 202.

[0058] For example, when the comparison result 300 indicates that the output voltage Vout1 is within the range from the first reference voltage VREF1 to the maximum reference voltage V1, the control circuit 130 determines the first charge amount Q1 as the supplementary charge amount to be charged to the output terminal 202 according to the comparison result 300. At the time point T1, when the comparison result 300 indicates that the output voltage Vout2 is less than the first reference voltage VREF1, the control circuit 130 determines the charge amount Q2 less than the first charge amount Q1 as the supplementary charge amount to be charged to the output terminal 202 according to the comparison result 300. At the time point T2, the control circuit 130 performs the above-described operation, and can determine another different supplementary charge amount in response to the same comparison result as that at the time point T1. The control circuit 130 can perform the above-described operation at more time points, and the length of time between one time point and the next time point can be determined by the control circuit 130.

[0059] In the present embodiment, the storage circuit 150 is coupled to the control circuit 130 and is configured to store a lookup table. The control circuit 130 determines the amount of supplementary charge based on the information stored in the lookup table and the comparison result 300. The lookup table information of different charge amounts corresponds to a plurality of pre-configured comparison results. That is, the lookup table information includes a corresponding relationship between the amount of supplementary charge and the comparison result. The storage circuit 150 may include a memory circuit and / or a register circuit to store the lookup table information, but the present invention is not limited thereto.

[0060] Figure 7 is a waveform diagram of different output voltages at the output terminal during different operation cycles according to another embodiment of the present invention. Figure 5 and Figure 7 , the comparator circuit 140 compares the output voltage Vout1 with the first reference voltage VREF1 and the second reference voltage VREF2 at different time points T1, T2 and T3 to generate at least one comparison result 300. The second reference voltage VREF2 is less than the first reference voltage VREF1. According to the corresponding comparison result 300, the control circuit 130 determines the amount of supplementary charge to be charged to the output terminal 202.

[0061] For example, at the time point T1, T2 or T3, when the comparison result 300 indicates that the output voltage Vout1 is within the range from the first reference voltage VREF1 to the maximum reference voltage V1, the control circuit 130 determines the first charge amount Q1 as the supplementary charge amount to be charged to the output terminal 202 according to the comparison result 300. At the time point T1, T2 or T3, when the comparison result 300 indicates that the output voltage Vout2 is within the range from the second reference voltage VREF2 to the first reference voltage VREF1, the control circuit 130 determines the second charge amount Q2 as the supplementary charge amount to be charged to the output terminal 202 according to the comparison result 300. At the time point T1, T2 or T3, when the comparison result 300 indicates that the output voltage Vout3 is less than the second reference voltage VREF2, the control circuit 130 determines the charge amount Q3 less than the second charge amount Q2 as the supplementary charge amount to be charged to the output terminal 202 according to the comparison result 300. It should be noted that, for example, since time point T2 is closer to the time when the output voltage Vout stabilizes at the target voltage than time point T1, the amount of supplementary charge determined based on a comparison result at time point T2 (for example, the output voltage Vout2 is within the range from the second reference voltage VREF2 to the first reference voltage VREF1) is different from the amount of supplementary charge determined based on the same comparison result at time point T1 (that is, as mentioned above, the output voltage Vout2 is within the range from the second reference voltage VREF2 to the first reference voltage VREF1).

[0062] Figure 8 is a waveform diagram of different output voltages at the output terminal during different operation cycles according to another embodiment of the present invention. Figure 5 and Figure 8 , the comparator circuit 140 compares the output voltage Vout with the first reference voltage VREF1, the second reference voltage VREF2 and the third reference voltage VREF3 at different time points T1, T2 and T3 to generate at least one comparison result 300. The third reference voltage VREF3 is less than the second reference voltage VREF2. According to the corresponding comparison result 300, the control circuit 130 determines the amount of supplementary charge to be charged to the output terminal 202.

[0063] For example, at time point T1, when the comparison result 300 indicates that the output voltage Vout3 is within the range from the third reference voltage VREF3 to the second reference voltage VREF2, the control circuit 130 determines the third charge amount Q3 as the supplementary charge amount to be charged to the output terminal 202 according to the comparison result 300. At time point T1, T2 or T3, when the comparison result 300 indicates that the output voltage Vout4 is less than the third reference voltage VREF3, the control circuit 130 determines the charge amount Q4 less than the third charge amount Q3 as the supplementary charge amount to be charged to the output terminal 202 according to the comparison result 300.

[0064] Fig. 9 Schematic diagram showing a sensor circuit and a readout integrated circuit according to an embodiment of the present invention. Fig. 9 The readout integrated circuit 400B includes a first charge / discharge circuit 110B, a second charge / discharge circuit 120B, a control circuit 130, a comparator circuit 140, and a storage circuit 150. Fig. 9 2 further shows the circuit structure of the first charging / discharging circuit 110B and the second charging / discharging circuit 120B. However, the circuit structure is not intended to limit the present invention.

[0065] The first charge / discharge circuit 110B operates as a discharge circuit. The first charge / discharge circuit 110B includes a first current source 112 and a switch element 114. The first current source 112 is controlled by a first voltage Vb1 to generate a first current I1. The first current source 112 includes a first terminal, a second terminal, and a control terminal. The first current I1 is transmitted from the first terminal to the second terminal. The first terminal of the first current source 112 is coupled to the output terminal 202 and the comparator circuit 140. The second terminal of the first current source 112 is coupled to the ground voltage GND. The control terminal of the first current source 112 is coupled to the first voltage Vb1. The switch element 114 is controlled by a control signal Vctrl. The switch element 114 includes a first terminal, a second terminal, and a control terminal. The first terminal of the switch element 114 is coupled to the first voltage Vb1. The second terminal of the switch element 114 is coupled to the control terminal of the first current source 112. The control terminal of the switch element 114 is coupled to the control signal Vctrl.

[0066] Specifically, the switch element 114 is coupled to the control circuit 130. The switch element 114 is turned on or off by the control signal Vctrl from the control circuit 130. The control signal Vctrl is generated by the control circuit 130 according to the determined amount of supplementary charge. The switch element 114 is coupled to the control terminal of the first current source I1, so that the on-period of the switch element 114 determines the period of the first current source 112 outputting the first current I1. The amount of supplementary charge is determined based on the first current I1 and the period of the first current source 112 outputting the first current I1. For example, when the first current source 112 is turned on, the amount of supplementary charge is determined based on the value of the first current I1. The larger the value of the first current I1, the larger the amount of supplementary charge. In addition, the longer the period of the first current source 112 outputting the first current I1, the larger the amount of supplementary charge.

[0067] The control circuit 130 is coupled to the first charge / discharge circuit 110B. The control circuit 130 outputs a control signal Vctrl to control an operation cycle of the first charge / discharge circuit 110B. The operation cycle of the first charge / discharge circuit 110B indicates a cycle in which the first charge / discharge circuit 110B discharges the output terminal 202 of the sensor array 200.

[0068] The second charge / discharge circuit 120B also operates as a discharge circuit. The second charge / discharge circuit 120B is coupled to the output terminal 202 of the sensor array 200. The second charge / discharge circuit 120B is configured to discharge the output terminal 202 by the second current I2 during the readout cycle. The second charge / discharge circuit 120B includes a second current source 122. The second current source 122 is controlled by a second voltage Vb2 to generate a second current I2. The second current source 122 includes a first terminal, a second terminal and a control terminal. The second current I2 is transmitted from the first terminal to the second terminal. The first terminal of the second current source 122 is coupled to the output terminal 202. The second terminal of the second current source 122 is coupled to the ground voltage. The control terminal of the second current source 122 is coupled to the second voltage Vb2.

[0069] In one embodiment, the first current I1 is greater than the second current I2, so that the discharge operation is dominated by the first charge / discharge circuit 110B, but the invention is not limited thereto. In another embodiment, the first current I1 may be equal to the second current I2.

[0070] Fig.10 is a waveform diagram of different output voltages at the output terminal during different operation cycles according to an embodiment of the present invention. Fig. 9 and Fig.10The comparator circuit 140 compares the output voltage Vout with the reference voltage VREF1 (first reference voltage) at different time points T1 and T2 to generate a comparison result 300. According to the comparison result 300, the control circuit 130 determines the amount of supplementary charge to be discharged from the output terminal 202.

[0071] For example, at the time point T1 or T2, when the comparison result 300 indicates that the output voltage Vout1 is within the range from the first reference voltage VREF1 to the minimum reference voltage V2, the control circuit 130 determines the first charge amount Q1 as the supplementary charge amount to be discharged from the output terminal 202 according to the comparison result 300. At the time point T1 or T2, when the comparison result 300 indicates that the output voltage Vout2 is greater than the first reference voltage VREF1, the control circuit 130 determines the charge amount Q2 less than the first charge amount Q1 as the supplementary charge amount to be discharged from the output terminal 202 according to the comparison result 300.

[0072] Fig.11 is a waveform diagram of different output voltages at the output terminal during different operation cycles according to another embodiment of the present invention. Fig. 9 and Fig.11 , the comparator circuit 140 compares the output voltage Vout with the first reference voltage VREF1 and the second reference voltage VREF2 at different time points T1, T2 and T3 to generate at least one comparison result 300. The second reference voltage VREF2 is greater than the first reference voltage VREF1. According to the corresponding comparison result 300, the control circuit 130 determines the amount of supplementary charge to be discharged from the output terminal 202.

[0073] For example, at the time point T1, T2 or T3, when the comparison result 300 indicates that the output voltage Vout1 is within the range from the first reference voltage VREF1 to the minimum reference voltage V2, the control circuit 130 determines the first charge amount Q1 as the supplementary charge amount to be discharged from the output terminal 202 according to the comparison result 300. At the time point T1, T2 or T3, when the comparison result 300 indicates that the output voltage Vout2 is within the range from the second reference voltage VREF2 to the first reference voltage VREF1, the control circuit 130 determines the second charge amount Q2 as the supplementary charge amount to be discharged from the output terminal 202 according to the comparison result 300. At the time point T1, T2 or T3, when the comparison result 300 indicates that the output voltage Vout3 is greater than the second reference voltage VREF2, the control circuit 130 determines the charge amount Q3 less than the second charge amount Q2 as the supplementary charge amount to be discharged from the output terminal 202 according to the comparison result 300.

[0074] Fig.12is a waveform diagram of different output voltages at the output terminal during different operation cycles according to another embodiment of the present invention. Fig. 9 and Fig.12 , the comparator circuit 140 compares the output voltage Vout with the first reference voltage VREF1, the second reference voltage VREF2 and the third reference voltage VREF3 at different time points T1, T2 and T3 to generate at least one comparison result 300. The third reference voltage VREF3 is greater than the second reference voltage VREF2. According to the corresponding comparison result 300, the control circuit 130 determines the amount of supplementary charge to be discharged from the output terminal 202.

[0075] For example, at time point T1, when the comparison result 300 indicates that the output voltage Vout3 is within the range from the third reference voltage VREF3 to the second reference voltage VREF2, the control circuit 130 determines the third charge amount Q3 as the supplementary charge amount to be discharged from the output terminal 202 according to the comparison result 300. At time point T1, T2 or T3, when the comparison result 300 indicates that the output voltage Vout4 is greater than the third reference voltage VREF3, the control circuit 130 determines the charge amount Q4 less than the third charge amount Q3 as the supplementary charge amount to be discharged from the output terminal 202 according to the comparison result 300.

[0076] Fig.13 is a schematic diagram showing a sensor circuit and a readout integrated circuit according to another embodiment of the present invention. Figure 5 and Fig.13 The readout integrated circuit 400C of this embodiment is similar to Figure 5 The readout integrated circuit 400A is shown, and the main difference between the readout integrated circuit 400C and the readout integrated circuit 400A lies in the circuit structure of the first charging / discharging circuit 110C, for example.

[0077] Specifically, the first charge / discharge circuit 110C operates as a charging circuit. The first charge / discharge circuit 110C includes a first current source 112 and a conversion circuit 116. The conversion circuit 116 may be a digital-to-analog converter (DAC). The first current source 112 is controlled by a first voltage Vb1 to generate a first current I1. The conversion circuit 116 is coupled to a control terminal of the first current source 112 and a control circuit 130. The conversion circuit 116 is configured to generate a control voltage Vb1. The control voltage Vb1 is output to the control terminal of the first current source 112 according to a control signal Vctrl from the control circuit 130. The amount of the first current I1 is determined according to the control voltage Vb1. Since the control voltage Vb1 is output according to the control signal Vctrl from the control circuit 130, the period during which the first current source 112 outputs the first current I1 is also determined by the control signal Vctrl from the control circuit 130.

[0078] In the present embodiment, the control circuit 130 outputs a digital control signal Vctrl according to the lookup table stored in the storage circuit 150 and the comparison result 300. The conversion circuit 116 converts the digital control signal Vctrl into an analog control voltage Vb1, and outputs the analog control voltage Vb1 to the first current source 112. The analog control voltage Vb1 can adjust the amount of the first current I1, and thus the amount of the first current I1 is determined according to the control voltage Vb1. Therefore, the amount of supplementary charge to be charged to the output terminal 202 is also determined according to the control voltage Vb1.

[0079] The operation of the readout integrated circuit 400C described in the embodiment of the present invention is Figure 5 It is fully taught, suggested and embodied in the embodiments shown in the accompanying drawings, and therefore, no further description is provided herein.

[0080] Fig.14 is a schematic diagram showing a sensor circuit and a readout integrated circuit according to another embodiment of the present invention. Fig. 9 and Fig.14 The readout integrated circuit 400D of this embodiment is similar to Fig. 9 The readout integrated circuit 400B is shown, and the main difference between the readout integrated circuit 400D and the readout integrated circuit 400B lies in the circuit structure of the first charging / discharging circuit 110D, for example.

[0081] Specifically, the first charge / discharge circuit 110D operates as a discharge circuit. The first charge / discharge circuit 110D includes a first current source 112 and a conversion circuit 116. The first current source 112 is controlled by a first voltage Vb1 to generate a first current I1. The conversion circuit 116 is coupled to a control terminal of the first current source 112 and a control circuit 130. The conversion circuit 116 is configured to generate a control voltage Vb1. The control voltage Vb1 is output to the control terminal of the first current source 112 according to a control signal Vctrl from the control circuit 130. The amount of the first current I1 is determined according to the control voltage Vb1.

[0082] In the present embodiment, the control circuit 130 outputs a digital control signal Vctrl according to the lookup table stored in the storage circuit 150 and the comparison result 300. The conversion circuit 116 converts the digital control signal Vctrl into an analog control voltage Vb1, and outputs the analog control voltage Vb1 to the first current source 112. The analog control voltage Vb1 can adjust the amount of the first current I1, and thus the amount of the first current I1 is determined according to the control voltage Vb1. Therefore, the amount of supplementary charge to be discharged from the output terminal 202 is also determined according to the control voltage Vb1.

[0083] The operation of the readout integrated circuit 400D described in the embodiment of the present invention is Fig. 9 It is fully taught, suggested and embodied in the embodiments shown in the accompanying drawings, and therefore, no further description is provided herein.

[0084] Fig.15 is a schematic diagram showing a sensor circuit and a readout integrated circuit according to another embodiment of the present invention. Figure 5 and Fig.15 The readout integrated circuit 400E of this embodiment is similar to Figure 5 The readout integrated circuit 400A is shown, and the main difference between the readout integrated circuit 400E and the readout integrated circuit 400A lies in the circuit structure of the first charging / discharging circuit 110E, for example.

[0085] Specifically, the first charge / discharge circuit 110E operates as a charging circuit. The first charge / discharge circuit 110E includes a buffer circuit 118. The buffer circuit 118 may be a buffer or a source follower. The control circuit 130 outputs an input voltage Vin and a timing control signal Vctrl_t. The buffer circuit 118 is configured to receive an input voltage Vin from the control circuit 130 and a timing control signal Vctrl_t from the control circuit 130, and output a driving voltage Vdri to charge the output terminal 202. For example, the driving voltage Vdri may be a positive voltage to directly pull up the voltage of the output terminal 202. The period at which the buffer circuit 118 outputs the driving voltage Vdri is controlled by the timing control signal Vctrl_t.

[0086] The operation of the readout integrated circuit 400E described in the embodiment of the present invention is Figure 5 It is fully taught, suggested and embodied in the embodiments shown in the accompanying drawings, and therefore, no further description is provided herein.

[0087] Fig.16 is a schematic diagram showing a sensor circuit and a readout integrated circuit according to another embodiment of the present invention. Fig. 9 and Fig.16 The readout integrated circuit 400F of this embodiment is similar to Fig. 9 The readout integrated circuit 400B is shown, and the main difference between the readout integrated circuit 400F and the readout integrated circuit 400B lies in the circuit structure of the first charging / discharging circuit 110E, for example.

[0088] Specifically, the first charge / discharge circuit 110E operates as a discharge circuit. The first charge / discharge circuit 110E includes a buffer circuit 118. The buffer circuit 118 may be a buffer or a source follower. The control circuit 130 outputs an input voltage Vin and a timing control signal Vctrl_t. The buffer circuit 118 is configured to receive an input voltage Vin from the control circuit 130 and a timing control signal Vctrl_t from the control circuit 130, and output a driving voltage Vdri to discharge the output terminal 202. For example, the driving voltage Vdri may be a negative voltage to directly pull down the voltage of the output terminal 202. The period at which the buffer circuit 118 outputs the driving voltage Vdri is controlled by the timing control signal Vctrl_t.

[0089] The operation of the readout integrated circuit 400F described in the embodiment of the present invention is Figure 5 It is fully taught, suggested and embodied in the embodiments shown in the accompanying drawings, and therefore, no further description is provided herein.

[0090] In summary, in the embodiment of the present invention, the amount of supplementary charge to be charged to or discharged from the output terminal is determined according to the comparison result of the output voltage and the reference voltage. Therefore, the charging or discharging speed of the fingerprint sensing signal can become faster, and the stabilization time of the fingerprint sensing signal is short to improve the quality of the fingerprint image.

[0091] It will be appreciated by those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In summary, the present disclosure is intended to cover the modifications and variations provided as long as they fall within the scope of the above claims and their equivalents.

Claims

1. A readout integrated circuit configured to read out a sensing signal from an optical sensing panel, the optical sensing panel comprising a sensor array for fingerprint sensing, the readout integrated circuit comprising: a plurality of input terminals for coupling to a plurality of output terminals of the optical sensing panel; a comparator circuit coupled to one of the plurality of input terminals and configured to receive an output voltage from one of the plurality of output terminals of the optical sensing panel and at least one reference voltage, compare the output voltage with the at least one reference voltage, and output a comparison result; a control circuit coupled to the comparator circuit and configured to receive the comparison result and determine an amount of supplementary charge to be charged to or discharged from the output terminal according to the comparison result; as well as a first charging / discharging circuit coupled to the output terminal and configured to be controlled by the control circuit to charge or discharge the output terminal with a first current, wherein the first charging / discharging circuit includes a first current source controlled by a first voltage to generate the first current, The amount of the supplementary charge is determined based on the first current and a period during which the first current source outputs the first current.

2. A readout integrated circuit according to claim 1, wherein the comparator circuit compares the output voltage with the at least one reference voltage at different time points to generate at least one comparison result, and based on the corresponding comparison result, the control circuit determines the amount of the supplementary charge to be charged to the output terminal or to be discharged from the output terminal.

3. The readout integrated circuit of claim 2 , wherein the at least one reference voltage comprises a first reference voltage, and When the comparison result indicates that the output voltage is within the range from the first reference voltage to a maximum reference voltage, the control circuit determines a first charge amount as the supplementary charge amount to be charged to the output terminal according to the comparison result; and When the comparison result indicates that the output voltage is less than the first reference voltage, the control circuit determines an amount of charge less than the first amount of charge as the supplementary charge amount to be charged to the output terminal according to the comparison result.

4. The readout integrated circuit of claim 3 , wherein the at least one reference voltage further comprises a second reference voltage that is smaller than the first reference voltage, and When the comparison result indicates that the output voltage is within the range from the second reference voltage to the first reference voltage, the control circuit determines a second charge amount as the supplementary charge amount to be charged to the output terminal according to the comparison result; and When the comparison result indicates that the output voltage is less than the second reference voltage, the control circuit determines an amount of charge less than the second amount of charge as the supplementary charge amount to be charged to the output terminal according to the comparison result.

5. The readout integrated circuit of claim 4, wherein the at least one reference voltage further comprises a third reference voltage that is smaller than the second reference voltage, and When the comparison result indicates that the output voltage is within the range from the third reference voltage to the second reference voltage, the control circuit determines a third charge amount as the supplementary charge amount to be charged to the output terminal according to the comparison result; and When the comparison result indicates that the output voltage is less than the third reference voltage, the control circuit determines an amount of charge less than the third amount of charge as the supplementary charge amount to be charged to the output terminal according to the comparison result.

6. The readout integrated circuit of claim 2, wherein the at least one reference voltage comprises a first reference voltage, and When the comparison result indicates that the output voltage is within the range from the first reference voltage to a minimum reference voltage, the control circuit determines a first charge amount as the supplementary charge amount to be discharged from the output terminal according to the comparison result; and When the comparison result indicates that the output voltage is greater than the first reference voltage, the control circuit determines an amount of charge smaller than the first amount of charge as the supplementary charge amount to be discharged from the output terminal according to the comparison result.

7. The readout integrated circuit of claim 6, wherein the at least one reference voltage further comprises a second reference voltage greater than the first reference voltage, and When the comparison result indicates that the output voltage is within the range from the second reference voltage to the first reference voltage, the control circuit determines a second charge amount as the supplementary charge amount to be discharged from the output terminal according to the comparison result; and When the comparison result indicates that the output voltage is greater than the second reference voltage, the control circuit determines an amount of charge smaller than the second amount of charge as the supplementary charge amount to be discharged from the output terminal according to the comparison result.

8. The readout integrated circuit of claim 7, wherein the at least one reference voltage further comprises a third reference voltage greater than the second reference voltage, and when the comparison result indicates that the output voltage is within the range from the third reference voltage to the second reference voltage, the control circuit determines a third charge amount as the supplementary charge amount to be discharged from the output terminal according to the comparison result; and When the comparison result indicates that the output voltage is greater than the third reference voltage, the control circuit determines an amount of charge smaller than the third amount of charge as the supplementary charge amount to be discharged from the output terminal according to the comparison result.

9. The readout integrated circuit of claim 1 , wherein the first charge / discharge circuit further comprises: A switch element is coupled to a control terminal of the first current source, so that a turn-on period of the switch element determines the period during which the first current source outputs the first current.

10. The readout integrated circuit according to claim 9, wherein the switch element is coupled to the control circuit and is turned on or off by a control signal from the control circuit, and The control signal is generated by the control circuit according to the determined amount of supplementary charge.

11. The readout integrated circuit of claim 1 , wherein the first charge / discharge circuit further comprises: A conversion circuit is coupled to the control terminal of the first current source and the control circuit, and is configured to generate a control voltage to be output to the control terminal of the first current source according to a control signal from the control circuit, wherein the amount of the first current is determined according to the control voltage. 12 . The readout integrated circuit according to claim 11 , wherein a period during which the first current source outputs the first current is determined by the control signal from the control circuit.

13. A readout integrated circuit configured to read out a sensing signal from an optical sensing panel, the optical sensing panel comprising a sensor array for fingerprint sensing, the readout integrated circuit comprising: a plurality of input terminals for coupling to a plurality of output terminals of the optical sensing panel; a comparator circuit coupled to one of the plurality of input terminals and configured to receive an output voltage from one of the plurality of output terminals of the optical sensing panel and at least one reference voltage, compare the output voltage with the at least one reference voltage, and output a comparison result; a control circuit coupled to the comparator circuit and configured to receive the comparison result and determine an amount of supplementary charge to be charged to or discharged from the output terminal according to the comparison result; as well as a first charging / discharging circuit coupled to the output terminal and configured to be controlled by the control circuit to charge or discharge the output terminal, wherein the first charging / discharging circuit includes a buffer circuit configured to receive an input voltage from the control circuit and a timing control signal from the control circuit and output a driving voltage to charge or discharge the output terminal, and The period at which the buffer circuit outputs the driving voltage is controlled by the timing control signal, and the amount of the supplementary charge is determined according to the driving voltage and the period at which the buffer circuit outputs the driving voltage.

14. The readout integrated circuit of claim 1, further comprising: The second charging / discharging circuit is coupled to the output terminal and is configured to charge or discharge the output terminal through a second current.

15. A readout integrated circuit according to claim 1, wherein the output terminal is coupled to a second charge / discharge circuit, and the second charge / discharge circuit is arranged in a display panel provided with the sensor array, and wherein the second charge / discharge circuit is configured to charge or discharge the output terminal through a second current.

16. The readout integrated circuit of claim 1, further comprising: The storage circuit is coupled to the control circuit and is configured to store a lookup table, wherein lookup table information of different charge amounts corresponds to a plurality of preconfigured comparison results.

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