Non-volatile memory device, storage device, and programming method thereof

Abstract

Provided are a non-volatile memory device, a storage device, and a programming method thereof. The programming method of the non-volatile memory device includes receiving a write address and write data, generating a seed corresponding to the write address, generating a random sequence by using the seed, randomizing the write data by using the random sequence, and programming the randomized write data to a storage area corresponding to the write address. The seed can provide state shaping that varies according to a position of a word line at which the received write data will be programmed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0007972, filed on January 21, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some exemplary embodiments of the inventive concepts disclosed herein relate to semiconductor memory devices, and more specifically, to non-volatile memory devices, storage devices, and / or methods for programming non-volatile memory devices. Background Technology

[0004] Flash memory devices are being widely used as data storage media for voice and image data in information devices such as computers, smartphones, personal digital assistants (PDAs), digital cameras, portable camcorders, recorders, MP3 players, and handheld PCs. Flash memory devices are becoming increasingly popular as storage devices. Today, to improve the integration density of flash memory devices, semiconductor memory devices with three-dimensional array structures are widely used. In a flash memory device with a three-dimensional array structure, the cell strings are stacked along a direction perpendicular to the substrate. That is, the memory cells are arranged in rows and columns on the substrate and stacked in a direction perpendicular to the substrate, thus forming a three-dimensional structure.

[0005] As semiconductor manufacturing technology continues to advance, the integration and capacity of flash memory storage devices are constantly increasing. High integration can reduce the cost of manufacturing storage devices. However, the reduction in storage device size due to high integration has brought about various new problems. These problems can lead to data corruption, thereby reducing the reliability of the storage device. There is a continuous need for methods and / or devices that can improve the reliability of storage devices. Summary of the Invention

[0006] Some exemplary embodiments of the present invention provide programming methods for non-volatile memory devices and / or non-volatile memory devices that can solve read interference caused by high integration or reliability degradation caused by charge leakage.

[0007] According to an example embodiment, a programming method for a non-volatile memory device includes: receiving a write address and write data; generating a seed corresponding to the write address; generating a random sequence using the seed; randomizing the write data using the random sequence; and programming the randomized write data into a memory region corresponding to the write address. The seed provides state shaping based on word line position variations.

[0008] According to an example embodiment, a storage device includes: a storage controller configured to receive write data and a write address from a host, and to perform randomization on the write data to perform state shaping on a storage cell selected according to the write address; and a non-volatile storage device configured to: under the control of the storage controller, program the randomized write data into a storage region corresponding to the write address, wherein the storage controller is further configured to perform the state shaping using a seed based on word line position variations.

[0009] According to an example embodiment, a non-volatile memory device includes: a cell array comprising a plurality of memory cells having multiple programming states; an on-chip randomizer configured to randomize write data from an external source; a page buffer configured to program the randomized write data provided by the on-chip randomizer into the memory array; and control logic configured to select a memory cell from the plurality of memory cells in the cell array in response to a command and address provided from the external source, and to control the page buffer and the on-chip randomizer such that the randomized write data is programmed into the selected memory cell. The on-chip randomizer is configured to perform state shaping on the write data based on the position of a word line. Attached Figure Description

[0010] The above and other objects and features of the present invention will become apparent from a detailed description of some exemplary embodiments of the invention with reference to the accompanying drawings.

[0011] Figure 1 This is a block diagram illustrating an example embodiment of a storage device according to a concept of the present invention.

[0012] Figure 2 It is shown by Figure 1 The flowchart shows the method by which the state shaping engine shapes the state of each region.

[0013] Figure 3 It is shown Figure 1 A block diagram of the configuration of the storage controller.

[0014] Figure 4 This is a block diagram illustrating an example embodiment of a non-volatile storage device according to a concept of the present invention.

[0015] Figure 5 The circuit diagram of the memory block is shown.

[0016] Figure 6 It is shown Figure 5 A diagram illustrating the structure of a single cell string CS included in a storage block.

[0017] Figure 7 It is shown Figure 3 A block diagram of an example configuration for a state shaping engine.

[0018] Figures 8A to 8C This is a diagram illustrating the result of a seed selection state shaping operation according to the present invention.

[0019] Figure 9 This is a diagram illustrating a seed table of an exemplary embodiment of the concept according to the present invention.

[0020] Figure 10 This is a diagram illustrating a seed table of another exemplary embodiment of the concept according to the present invention.

[0021] Figure 11A and Figure 11B This is a diagram illustrating another example of a seed selection state shaping operation according to the concept of the present invention.

[0022] Figure 12A and Figure 12B This is a diagram illustrating a seed table of another exemplary embodiment of the concept according to the present invention.

[0023] Figure 13 This is a block diagram of a non-volatile memory device that performs on-chip randomization operations according to another exemplary embodiment of the present invention.

[0024] Figure 14 It is shown Figure 13 A block diagram of an exemplary configuration of an on-chip randomizer is shown.

[0025] Figure 15 It is shown Figure 14 An example diagram of a random sequence generator.

[0026] Figure 16 This is a diagram illustrating an exemplary non-volatile storage device. Detailed Implementation

[0027] It should be understood that the foregoing general description and the following detailed description are provided by way of example and should be considered as providing additional description. Reference numerals are described in detail in some exemplary embodiments of the inventive concept, examples of which are shown in the accompanying drawings. The same reference numerals are used wherever possible in the drawings and specification to denote the same or similar parts.

[0028] Although the terms “same,” “equivalent,” or “equal” are used in the description of the example embodiments, it should be understood that some imprecisions may exist. Therefore, when an element is described as being the same as another element, it should be understood that an element or value is identical to another element or value within a desired range of manufacturing or operational tolerances (e.g., ±10%).

[0029] When the terms “approximately” or “substantially” are used in conjunction with numerical values ​​in this specification, the relevant numerical value includes manufacturing or operational tolerances (e.g., ±10%) around the value. Furthermore, when the words “usually” and “substantially” are used in conjunction with geometry, it means that the geometry is not required to be precise, but the dimensions of the shape are within the scope of this disclosure. Moreover, whether a numerical value or shape is modified to “approximately” or “substantially”, it will be understood that these numerical values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around the value or shape.

[0030] Below, non-volatile storage devices are used as examples to describe the features and functions of the inventive concept. However, based on the disclosure herein, those skilled in the art will readily understand other advantages and performance characteristics of the inventive concept. Furthermore, the term "state shaping" as used in the inventive concept refers to the operation of encoding a pattern of data stored in a non-volatile storage device. That is, "state shaping" refers to an encoding operation that adjusts the threshold voltage distribution of each region on a state-by-state basis, the threshold voltage distribution of each region being formed by writing data programmed into the non-volatile storage device. For example, "state shaping" may include a randomization operation applied to the written data to form the threshold voltage distribution of each region.

[0031] The inventive concept can also be implemented or applied through any other exemplary embodiments. Furthermore, the detailed description may be changed or modified according to viewpoints and applications without departing from the claims, the scope and spirit of the inventive concept, and any other purpose.

[0032] Figure 1 This is a block diagram illustrating an exemplary embodiment of a storage device according to a concept of the present invention. (Refer to...) Figure 1 Storage device 100 may include storage controller 110 and non-volatile storage device (NVM) 120. In example embodiments, both storage controller 110 and non-volatile storage device 120 may be implemented using a single chip, a package, or a module. In some example embodiments, storage controller 110 and non-volatile storage device 120 may be implemented using a single chip, a package, or a module to form a storage system such as a memory card, memory stick, or solid-state drive (SSD).

[0033] The storage controller 110 can be configured to control the non-volatile storage device 120. For example, in response to a request from the host, the storage controller 110 can write data to the non-volatile storage device 120 or read data stored in the non-volatile storage device 120. To access the non-volatile storage device 120, the storage controller 110 can provide commands, addresses, data, and control signals to the non-volatile storage device 120.

[0034] For example, according to an exemplary embodiment of the present invention, the storage controller 110 may include a state shaping engine 118. The state shaping engine 118 may encode patterns of written data that could degrade the reliability of the non-volatile storage device 120 into stable patterns. Furthermore, the state shaping engine 118 may decode patterns of read data to recover the original patterns.

[0035] In the programming operation, the state shaping engine 118 encodes the write data received from the host. For example, the state shaping engine 118 can perform encoding to provide a different distribution for each region of the non-volatile memory device 120. For example, the state shaping engine 118 can encode the pattern of the write data into a data pattern with an optimal distribution based on the fragility or vulnerability of each word line of the non-volatile memory device 120. Here, it is well understood that the unit of the write data pattern being shaped is not limited to word lines. Furthermore, the encoding can include randomization operations that randomly arrange the logical values ​​of the write data. The data encoded by the state shaping engine 118 can be programmed into the non-volatile memory device 120.

[0036] Under the control of the memory controller 110, the non-volatile storage device 120 can store data received from the memory controller 110, or can send data stored therein to the memory controller 110. The non-volatile storage device 120 may include multiple memory blocks BLK1 to BLKi. Each of the multiple memory blocks BLK1 to BLKi has a three-dimensional memory structure in which word line layers are stacked in a direction perpendicular to the substrate. Each of the multiple memory blocks BLK1 to BLKi can be managed by the memory controller 110 using information about wear leveling, such as "erase count EC".

[0037] As described above, according to an exemplary embodiment of the present invention, the storage device 100 can encode patterns of written data that could reduce the reliability of the non-volatile storage device 120. For this purpose, the storage controller 110 may include a state shaping engine 118 for encoding patterns of written data into an optimal distribution pattern based on word lines. The operation of the state shaping engine 118 will be described more fully with reference to the accompanying drawings. According to an exemplary embodiment of the present invention, it is feasible to provide state shaping for optimal reliability based on the differences in reliability characteristics between word lines appearing in the three-dimensional non-volatile storage device 120.

[0038] Figure 2 It is shown by Figure 1 The flowchart shows the method executed by the state shaping engine 118 to shape the state of each region. (See attached diagram.) Figure 2 State Shaping Engine 118 (reference) Figure 1 This can perform randomization operations to shape the state of the data to be programmed based on regions (e.g., word lines). In an example embodiment, a word line can be divided into, for example, three regions (which can be interchanged with word line portions, word line zones, word line sections, word line stages, etc.): such as a lower region adjacent to the substrate, an upper region adjacent to the bit line (or string select line), and an intermediate region located between the lower and upper regions.

[0039] In operation S110, the storage controller 110 receives write requests from a host or external source. Write requests may include commands, write data, addresses (also known as address ADDR or write address ADDR), etc. The received write requests can be provided to the status shaping engine 118.

[0040] In operation S120, the state shaping engine 118 generates or selects a seed for state shaping with reference to the write address ADDR. The state shaping engine 118 can select from a seed table the seed corresponding to the location of the word line where the received data is to be programmed. For example, if the row address of the received write address ADDR corresponds to a word line belonging to the lower region, the state shaping engine 118 can select a seed mapped to the selected word line. Memory cells connected to word lines belonging to the lower region near the substrate may be fragile or susceptible to damage from read interference. When programming data based on a seed mapped to the word line in the lower region, the number of memory cells included in the erase state "E" can be reduced. As the number of memory cells in the erase state "E" decreases, characteristic degradation due to read interference can be reduced.

[0041] Furthermore, when the row address of the received write address ADDR corresponds to a word line belonging to the middle region, the state shaping engine 118 can select a seed different from the seed of the lower region. Charge leakage characteristics occur at memory cells belonging to the middle region between the substrate and the bit line. When programming memory cells connected to word lines in the middle region, the reliability reduction due to charge leakage can be reduced by decreasing the number of memory cells to be programmed into high programming states (e.g., programming states P14 and P15 in a quadruple level cell (QLC)).

[0042] In operation S130, state shaping engine 118 generates a random sequence using a selected seed. State shaping engine 118 may include, for example, a random sequence generator for generating a random sequence RS using the selected seed as a source.

[0043] In operation S140, the generated random sequence RS and the written data are processed, that is, a randomization operation is performed on the written data. For example, to randomize, an XOR operation can be performed on each bit of the written data and each bit of the random sequence RS.

[0044] In operation S150, randomized write data can be programmed to the memory region selected by address ADDR.

[0045] The above process describes the following example embodiment of the inventive concept: state shaping is applied differently depending on the position of the word line targeted for programming operations. According to some programming methods of the inventive concept, when programming data to memory cells belonging to word lines in the lower region (or near the substrate), a seed is used (or selected) in a way that reduces the number of memory cells included in the erase state "E". Therefore, as the number of memory cells with erase state "E" decreases, characteristic degradation due to read interference can be reduced. Furthermore, when programming memory cells connected to word lines in the middle region, reliability reduction due to charge leakage can be reduced by decreasing the number of memory cells to be programmed into high programming states (e.g., P14 and P15).

[0046] Figure 3 It is shown Figure 1 A block diagram illustrating the configuration of the storage controller 110. (Refer to...) Figure 3The storage controller 110 of this invention includes a processing unit 111, a working memory 113, a host interface 115, an error correction code block 117, a state shaping engine 118, and a memory interface 119. However, it will be well understood that the components of the storage controller 110 are not limited to the above components. For example, the storage controller 110 may also include a read-only memory (ROM) storing code data for initial startup operations.

[0047] Processing unit 111 may include a central processing unit (CPU) or a microprocessor. Processing unit 111 can manage the overall operation of storage controller 110. Processing unit 111 is configured to drive firmware used to drive storage controller 110.

[0048] Software (or firmware) or data used to control the storage controller 110 can be loaded into the working memory 113. The stored software and data can be driven or processed by the processing unit 111. For example, according to an exemplary embodiment of the present invention, a flash translation layer 114 that performs functions such as address management, wear leveling, and garbage collection can be loaded into the working memory 113.

[0049] Host interface 115 provides an interface between the host and storage controller 110. The host and storage controller 110 can be connected via one of a variety of standardized interfaces. These standardized interfaces include various interfaces such as: Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, External SATA (e-SATA) interface, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI) interface, Fast PCI (PCI-E) interface, Universal Serial Bus (USB) interface, IEEE 1394 interface, Universal Flash Memory (UFS) interface, and card interface.

[0050] Error correction block 117 can correct errors caused by data corruption due to various reasons. For example, error correction block 117 can perform operations to detect or correct errors in data read from non-volatile storage device 120. For example, error correction block 117 can detect the number of erroneous bits or bit error rate (BER) of data read from storage cells on a word line basis, according to a request from flash translation layer 114. When the state shaping technique of the present invention is applied, state shaping can be applied to each word line, thereby improving data reliability. Therefore, the BER of data written to the storage block can be improved.

[0051] The state shaping engine 118 encodes the write data received from the host and provides the encoded data to the non-volatile memory device 120. For example, the state shaping engine 118 can perform encoding such that the state shaping is different for each region of the non-volatile memory device 120. The state shaping engine 118 can encode the write data based on the fragility or vulnerability of the word lines in the non-volatile memory device 120. When the encoded write data is programmed into the non-volatile memory device 120, a threshold voltage distribution with optimal reliability can be formed for each word line. Here, it is well understood that the unit at which the write data pattern is shaped is not limited to word lines.

[0052] Memory interface 119 provides an interface between memory controller 110 and non-volatile storage device 120. For example, data processed by processing unit 111 is stored in non-volatile storage device 120 via memory interface 119. In another example, data stored in non-volatile storage device 120 is provided to processing unit 111 via memory interface 119.

[0053] The components of the storage controller 110 have been described above. The state shaping engine 118 included in the storage controller 110, as conceived in this invention, can perform state shaping based on word lines or blocks. Therefore, state shaping can take into account the vulnerabilities or contingencies present in each storage region, thereby improving the reliability of programmed data.

[0054] Figure 4 This is a block diagram illustrating an example embodiment of a non-volatile storage device according to a concept of the present invention. (Refer to...) Figure 4 The non-volatile storage device 120 includes a cell array (i.e., a memory cell array) 121, a decoder 122, a page buffer 123, an input / output buffer 124, and control logic circuitry 125.

[0055] Cell array 121 is connected to decoder 122 via word line WL and select lines SSL and GSL. Cell array 121 is connected to page buffer 123 via bit line BL. Cell array 121 includes multiple memory blocks BLK1 to BLKi. Each memory block BLK1 to BLKi includes multiple NAND cell strings. Data can be written to cell array 121 in units of pages. Erase operations can be performed in units of memory blocks.

[0056] According to an exemplary embodiment of the present invention, the cell array 121 can be implemented using a three-dimensional (3D) memory array. The 3D memory array can be monolithically formed in one or more physical layers of a memory cell array having active regions disposed on a silicon substrate and on circuitry related to the operation of the memory cells.

[0057] In an exemplary embodiment of the present invention, the 3D memory array includes vertically oriented vertical NAND strings, such that at least one memory cell is positioned above another memory cell. At least one memory cell includes a charge trapping layer. Each vertical NAND string may include at least one select transistor positioned above the memory cell. The at least one select transistor may have the same structure as the memory cell and may be monolithically formed together with the memory cell.

[0058] Decoder 122 is responsive to one of the memory blocks BLK1 to BLKi of the address ADDR select cell array 121. Decoder 122 can provide a word line voltage corresponding to the operating mode to the word line of the selected memory block. Decoder 122 can provide select signals to select lines SSL and GSL to select the memory block. In a read operation, a read voltage Vrd can be applied to the selected word line of the memory block, and the read voltage Vread can be provided to the unselected word line.

[0059] Page buffer 123 can be used as a write driver or a sense amplifier depending on the operating mode. During programming operations, page buffer 123 supplies a bit line voltage corresponding to the data to be programmed to the bit lines of cell array 121. During read operations, page buffer 123 senses data stored in a selected memory cell via the bit lines. Page buffer 123 latches the sensed data and outputs the latched data externally.

[0060] Input / output buffer 124 provides write data received during programming operations to page buffer 123. Input / output buffer 124 outputs data provided from page buffer 123 to the outside during read operations. Input / output buffer 124 can provide received addresses or received commands to control logic circuit 125 or decoder 122.

[0061] Control logic circuit 125 responds to command CMD or control signal CTRL to control decoder 122 and page buffer 123. Control logic circuit 125 can control decoder 122 to generate biases in various schemes according to programming commands. For example, control logic circuit 125 can output information about programming results based on a request from memory controller 110.

[0062] To achieve high-capacity memory devices, the number of word lines in each memory block stacked in memory blocks BLK1 to BLKi is increased. Furthermore, the number of bits of data to be stored in each memory cell is increased. For example, within a memory block, the fragility of a memory cell can vary depending on its relative position to the substrate. For instance, memory cells closer to the substrate are fragile or susceptible to damage from read interference. In contrast, charge leakage characteristics occur in memory cells located in the intermediate region between the substrate and the bit lines.

[0063] As described above, state shaping that achieves optimal distribution can be applied depending on the location of the memory cell. Specifically, when the memory cell is located in the lower region of the memory block, state shaping can be applied in a way that reduces the number of memory cells with the erase state "E". When the memory cell is located in the middle region of the memory block, state shaping can be applied in a way that reduces the number of memory cells with the highest state P15 (in the case of QLC). By performing state shaping as described above, reliability degradation due to vulnerabilities such as read interference or charge leakage can be reduced.

[0064] Figure 5 The circuit diagram of memory block BLK1 is shown. (Refer to...) Figure 5 The cell string CS is formed between bit lines BL1, BL2, BL3 and BL4 and the common source line CSL.

[0065] Cell strings CS are formed between bit line BL1 and common source line CSL. Multiple cell strings CS are formed in the same manner between bit lines BL2, BL3, and BL4 and common source line CSL. In each cell string CS, a string select transistor SST is connected to the corresponding bit line BL. The string select transistor SST of a cell string CS can be controlled by string select lines SSL (e.g., SSL1, SSL2, SSL3, and SSL4). In each cell string CS, a ground select transistor GST is connected to the common source line CSL. In each cell string CS, a memory cell is disposed between the string select transistor SST and the ground select transistor GST.

[0066] Each cell string CS includes a ground selection transistor GST. The ground selection transistor GST of the cell string CS can be controlled by ground selection lines GSL (e.g., GSL1, GSL2, GSL3, and GSL4). In some example embodiments, although not shown in the figures, the cell string can be controlled by different ground selection lines for each row.

[0067] One layer can be molded as a word line. Multiple memory cells (MCs) are connected to a word line. In a memory block with the above three-dimensional structure, the characteristics of the memory cells can vary depending on their relative distance from the substrate (SUB). For example, memory cells connected to word lines belonging to the lower region (or close to the substrate SUB) may be fragile or susceptible to damage from read interference. In contrast, charge leakage characteristics are relatively pronounced at memory cells connected to word lines belonging to the middle region located between the substrate SUB and bit lines BL1 to BL4.

[0068] To compensate for the characteristics of the aforementioned locations, state shaping can be applied to the memory cells located in the lower region of the memory block, thereby reducing the number of memory cells with the erase state "E". Furthermore, state shaping can be applied to the memory cells located in the middle region of the memory block, thereby reducing the number of memory cells with the highest state P15 (in the case of QLC).

[0069] The circuit structure of a memory cell included in a memory block has been briefly described above. However, Figure 5 The circuit structure shown is a simplified structure for ease of description, and the actual memory block is not limited to this. Figure 5 The example shown illustrates this. That is, it's easy to understand that a memory block can include more semiconductor layers, more bit lines, and more string select lines.

[0070] Figure 6 It is shown Figure 5 A diagram illustrating the structure of a single cell string CS within a storage block. (Refer to...) Figure 6 A columnar structure PL is provided that extends in a direction perpendicular to the substrate SUB and contacts the substrate SUB.

[0071] Here, the ground select line GSL, word line WL, and string select line SSL can be formed of a conductive material (e.g., a metallic material) parallel to the substrate SUB. A pillar PL can pass through the conductive material forming the string select line SSL, word line WL, and ground select line GSL and contact the substrate SUB. Furthermore, the word line WL may include dummy word lines connected to dummy memory cells not used for storing data (in... Figure 6 (Not specifically shown in the text). Dummy word lines can be used for various purposes.

[0072] During the fabrication of the cell string CS, the shorter the distance from the substrate SUB, the smaller the width of the pillar PL, or the smaller the cross-sectional area parallel to the upper surface of the substrate SUB. Therefore, when the same voltage is applied to the body of the ground select transistor GST, the memory cell MC, and the string select transistor SST, and the same voltage is applied to the ground select line GSL, the word line WL, and the string select line SSL, the electric field formed at the memory cell or ground select transistor GST adjacent to the substrate SUB is greater than the electric field formed at the memory cell or string select transistor SST farther from the substrate SUB. These characteristics affect programming interference that occurs during programming operations.

[0073] To address the problem based on the geometric characteristics of the aforementioned unit string CS, state shaping based on the present invention concept, which varies according to the position of the selected word line, can be applied.

[0074] Figure 7 It is shown Figure 3 A block diagram of an example configuration for the state shaping engine 118. (See also...) Figure 7 The state shaping engine 118 may include a seed generator 118a, a random sequence generator 118b, and a mixer 118c.

[0075] The threshold voltage distribution of memory cells after a programming operation can be adjusted based on a seed used in the randomization operation of the data to be programmed. For example, in a programming operation of a four-level cell (QLC) with one of 16 threshold voltage states, the number of memory cells included in a particular state can be reduced or increased based on the seed value used in the randomization operation. State shaping is a technique for generating or selecting a seed used in a randomization operation to increase or decrease the number of memory cells included in a particular state.

[0076] Seed generator 118a generates a seed corresponding to a specific region by referring to the received address ADDR. Here, the specific region may correspond to a page, word line, group of word lines, or region such as a block or plane in the non-volatile memory device 120. That is, seed generator 118a generates seeds that can be allocated on a unit basis for specific regions. For example, seed generator 118a may be implemented in the form of a lookup table, thereby selecting different seeds based on the position of the word lines in the non-volatile memory device 120. In this case, seed generator 118a may refer to address ADDR and retrieve a seed for each word line from the lookup table. When a seed corresponding to a word line is selected, seed generator 118a provides the generated seed to random sequence generator 118b.

[0077] Random sequence generator 118b generates a random sequence RS using a seed provided from seed generator 118a. Random sequence generator 118b generates a random sequence RS using an input seed as a source. For example, random sequence generator 118b can be implemented using a linear feedback shift register (LSFR) with Fibonacci configuration operation.

[0078] The mixer 118c mixes the random sequence RS generated by the random sequence generator 118b for randomization operations with the input data Din. For example, the output data Dout can be generated by performing an XOR operation on each bit of the random sequence RS and each bit of the input data Din. Here, the input data Din can be multiple pages of data to be stored in a memory cell connected to a word line. The randomized data Dout generated by the mixer 118c can be provided to the page buffer 123 of the non-volatile memory device 120 to be programmed in a selected area.

[0079] Figures 8A to 8C This is a diagram illustrating the result of a seed selection state shaping operation according to the present invention. Figure 8A This is a diagram showing the result of state shaping by allocating an equal number of memory units to each state. Figure 8B and Figure 8C This is a diagram illustrating the application of state shaping differently for each word line. The features of the inventive concept will be described by assuming that each memory cell of the non-volatile memory device 120 is a quad-level cell (QLC) with one of 16 threshold voltage states.

[0080] exist Figure 8A The example shown is an equal-size integer that allocates an equal amount of storage units to each of the states from state "E" to state P15 in a programming operation.

[0081] When applying equal shaping, the number of memory cells allocated to each of states "E" through P15 in the selected region is equal or substantially similar. Here, the cell ratio can indicate the ratio of the number of memory cells included in the corresponding state to the base value. Here, the base value can indicate the number of memory cells included in each state when allocating an equal number of memory cells to each state. That is, a cell ratio of 100% can be understood as equal shaping without state shaping of the corresponding state. In other words, when applying equal shaping, each programming state can include an equal number of memory cells when the programming operation is completed.

[0082] exist Figure 8B The diagram illustrates state shaping associated with a memory cell connected to word line WLi, according to an example embodiment of the present invention. Figure 8BThe first seed SED1 for state shaping shown can be used in randomized operations for programming memory cells connected to word lines WLi. For example, the percentage of cells with erased state "E" can be 51%. This means that, compared to the case of applying equal shaping, the number of memory cells with erased state "E" among the memory cells connected to word lines WLi is reduced by up to 49% after the programming operation.

[0083] Furthermore, the cell ratio for each of the programming states P13, P14, and P15, corresponding to a relatively high threshold voltage distribution, is 95%. This means that the number of memory cells programmed into each of the programming states P13, P14, and P15 is reduced by up to 5% compared to the case where equal shaping is applied.

[0084] Similarly, the cell ratio for programming state P1 is 60%. This means that, compared to the case of applying equal shaping, the number of memory cells programmed to programming state P1 among the memory cells connected to the word line WLi is reduced by up to 40%.

[0085] In contrast, the cell ratio for each programming state in programming states P5, P6, P9, and P10 is 110%. This means that, compared to the case of applying equal shaping, the number of memory cells connected to the word line WLi after the programming operation with each programming state in programming states P5, P6, P9, and P10 increases by up to 10%. Furthermore, the cell ratio for each programming state in programming states P7 and P8 is 120%. This means that, compared to the case of applying equal shaping, the number of memory cells connected to the word line WLi after the programming operation with each programming state in programming states P7 and P8 increases by up to 20%. Additionally, the cell ratio for each programming state in programming states P3, P4, P11, and P12 is 100%. This means that, after the programming operation, the number of memory cells with each programming state in programming states P3, P4, P11, and P12 is equal to the number of memory cells with each programming state in programming states P3, P4, P11, and P12 under the case of applying equal shaping.

[0086] exist Figure 8C The diagram illustrates state shaping associated with memory cells connected to word line WLj, according to an exemplary embodiment of the present invention. A second seed SED2, different from the first seed SED1, can be used in a randomization operation for programming the memory cells connected to word line WLj. In this case, the cell ratio with erase state "E" can be 95%. This means that, compared to the case of applying equal shaping, the number of memory cells with erase state "E" among the memory cells connected to word line WLj after the programming operation is reduced by up to 5%.

[0087] Furthermore, the cell ratio for each programming state in programming states P14 and P15, corresponding to a relatively high threshold voltage distribution, is 51%. This means that the number of memory cells programmed into each programming state in programming states P14 and P15 is reduced by up to 49% compared to the case where equal shaping is applied. The cell ratio for programming state P13 is 60%. This means that the number of memory cells programmed into programming state P13 is reduced by up to 40% compared to the case where equal shaping is applied.

[0088] The cell ratio for each programming state in programming states P7 and P8 is 120%. This means that, compared to the case of applying equal shaping, the number of memory cells connected to word line WLj after the programming operation that have each programming state in programming states P7 and P8 increases by up to 20%. The cell ratio for each programming state in programming states P5, P6, P9, and P10 is 110%. This means that, compared to the case of applying equal shaping, the number of memory cells connected to word line WLj after the programming operation that have each programming state in programming states P5, P6, P9, and P10 increases by up to 10%.

[0089] The cell ratio for each of the programming states P1, P2, P3, P4, P11, and P12 is 100%. This means that after the programming operation, the number of memory cells with each of the programming states P1, P2, P3, P4, P11, and P12 is equal to the number of memory cells with each of the programming states P1, P2, P3, P4, P11, and P12 when equal integer shaping is applied.

[0090] The above briefly describes an example of state shaping according to an exemplary embodiment of the present invention. Based on the state shaping of the memory cells connected to the word line WLi, the number of memory cells included in the erase state "E" is reduced. As the number of memory cells with the erase state "E" decreases, characteristic degradation due to read interference can be reduced. In a three-dimensional non-volatile memory device, characteristic degradation due to read interference occurs at memory cells corresponding to word lines closer to the substrate. Therefore, the word line WLi can be a lower word line closer to the substrate.

[0091] In contrast, the number of memory cells included in each of the high-programmability states P13, P14, and P15, which have relatively high threshold voltages, is reduced according to the state shaping of the memory cells connected to the word line WLj. After the memory cells are programmed, the threshold voltage drop due to charge leakage is more pronounced at the memory cells in high-programmability states P13, P14, and P15. Therefore, the reliability reduction due to charge leakage can be reduced by decreasing the number of memory cells with high-programmability states P13, P14, and P15. For example, the reliability (or retention) reduction due to charge leakage is more pronounced at memory cells connected to word lines in the middle region of a three-dimensional non-volatile memory device. Therefore, the word line WLj can be an intermediate word line between the substrate and the bit line.

[0092] The above describes how read interference characteristics can be improved and / or hold characteristic degradation can be mitigated or prevented through word line-based state shaping. However, characteristic degradation based on the position of each word line is not limited to the characteristics described above. It is easy to understand that seed SEDs applied to various state shapings can be applied to word lines from which characteristic degradation is detected differently.

[0093] Figure 9 This is a diagram illustrating a seed table according to an exemplary embodiment of the concept of the present invention. (Refer to...) Figure 9 Seed generator 118a (refer to) Figure 7 This can include seeds SED1 to SED92, each assigned to a word line. Each seed in SED1 to SED92 determines the state shape of the memory cell connected to the corresponding word line. Here, the smaller the number "k" of the word line WLk, the closer the word line can be to the substrate.

[0094] Seed SED1 can be assigned to word line WL1. When the data to be programmed is randomized using a random sequence generated by seed SED1, the number of memory cells included in lower states "E", P1, P2, and P3 is reduced. With seed SED1 assigned to word line WL1, the cell ratio for erase state "E" and programming states P1, P2, and P3 can all be set to 50%. The cell ratio for programming states P4 to P12 can all be set to 110%, the cell ratio for programming state P13 can be set to 90%, and the cell ratio for high programming states P14 and P15 can all be set to 95%.

[0095] Similarly, when seed SED2 is assigned to word line WL2, the cell ratio for erase state "E" can be set to 52%, and the cell ratios for programming states P1, P2, and P3 can all be set to 73%. The cell ratios for programming states P4 to P12 can all be set to 110%, and the cell ratios for high programming states P13 to P15 can all be set to 95%. When seed SED3 is assigned to word line WL3, the cell ratio for erase state "E" can be set to 53%, and the cell ratios for programming states P1, P2, and P3 can all be set to 73%. The cell ratios for programming states P4 to P12 can all be set to 105%, the cell ratios for programming states P13 and P14 can all be set to 98%, and the cell ratio for programming state P15 can be set to 95%. When seed SED4 is assigned to word line WL4, the cell ratio for erase state "E" can be set to 53%, and the cell ratios for programming states P1, P2, and P3 can all be set to 73%. The cell ratios for programming states P4 through P12 can all be set to 105%, the cell ratios for programming states P13 and P14 can all be set to 98%, and the cell ratio for programming state P15 can be set to 96%.

[0096] Word lines WL1 to WL4 correspond to the lower word lines near the substrate (or to word lines belonging to the lower region of the memory block). Therefore, the memory cells connected to word lines WL1 to WL4 are fragile or susceptible to damage from read interference. When data is programmed based on a seed corresponding to the word line as described above, the number of memory cells included in the erase state "E" can be reduced. As the number of memory cells in the erase state "E" decreases, the characteristic degradation due to read interference can be reduced.

[0097] Seed SED44 can be allocated to word line WL44. When the data to be programmed is randomized using a random sequence generated by seed SED44, the number of memory cells included in the highest programming state P15 is reduced. That is, when seed SED44 is allocated to word line WL44, the cell ratio of the highest programming state P15 can be set to 50%, and the cell ratio of programming state P14, which is lower than the highest programming state P15, can be set to 60%. The cell ratio of programming state P13 can be set to 70%. When seed SED44 is applied to word line WL44, the cell ratio of erase state "E" and programming states P1, P2, and P3 can all be set to 95%, and the cell ratio of programming states P4 to P12 can all be set to 110%.

[0098] When seed SED45 is assigned to word line WL45, the cell ratio for the highest programming state P15 can be set to 51%, the cell ratio for programming state P14 (below the highest programming state P15) can be set to 61%, and the cell ratio for programming state P13 can be set to 71%. When seed SED45 is applied to word line WL45, the cell ratio for erase state "E" and programming states P1, P2, and P3 can all be set to 95%, and the cell ratio for programming states P4 to P12 can all be set to 110%.

[0099] When seed SED46 is assigned to word line WL46, the cell ratio for the highest programming state P15 can be set to 51%, the cell ratio for programming state P14 (below the highest programming state P15) can be set to 60%, and the cell ratio for programming state P13 can be set to 70%. When seed SED46 is applied to word line WL46, the cell ratio for erase state "E" and programming states P1, P2, and P3 can all be set to 96%, and the cell ratio for programming states P4 to P12 can all be set to 110%.

[0100] When seed SED47 is assigned to word line WL47, the cell ratio for the highest programming state P15 can be set to 50%, the cell ratio for programming state P14 (below the highest programming state P15) can be set to 62%, and the cell ratio for programming state P13 can be set to 69%. When seed SED47 is applied to word line WL47, the cell ratio for erase state "E" and programming states P1, P2, and P3 can all be set to 96%, and the cell ratio for programming states P4 to P12 can all be set to 105%.

[0101] Word lines WL44 to WL47 correspond to the word lines WL1 to WL92 that are located in the intermediate region between the substrate and the bit lines. Therefore, the charge leakage characteristics of the memory cells connected to word lines WL44 to WL47 are relatively significant. When programming memory cells connected to word lines in the intermediate region, the reliability reduction due to charge leakage can be reduced by decreasing the number of memory cells to be programmed into high programming states (e.g., programming states P14 and P15).

[0102] Seeds SED89 to SED92 can be assigned to word lines WL89 to WL92, respectively. When the data to be programmed is randomized using a random sequence generated from each of the seeds SED89 to SED92, the cell ratio for the erase state "E" and programming states P1, P2, and P3 can all be set to 99%, and the cell ratio for programming states P4 to P12 can all be set to 105%. The cell ratio for high-programming states P13, P14, and P15 can all be set to 98%.

[0103] By assigning seeds to selected word lines based on the aforementioned seed table, the characteristic degradation of memory cells that occurs depending on the word line's location can be addressed. Specifically, for memory cells connected to word lines near the lower region of the substrate, reducing the number of memory cells with erase state "E" reduces characteristic degradation due to read interference. Furthermore, when programming memory cells connected to word lines located in the middle region between the substrate and the bit lines, reducing the number of memory cells to be programmed into high programming states (e.g., P14 and P15) reduces reliability degradation due to charge leakage.

[0104] Figure 10 This is a diagram illustrating a seed table of another exemplary embodiment of the concept according to the present invention. (Refer to...) Figure 10 Seed generator 118a (refer to) Figure 7 The seed generator 118a may include seeds SED_a to SED_c, which are respectively assigned to word line groups. The seed generator 118a may store and manage seeds SED_a to SED_c in the form of a seed table. Each seed in SED_a to SED_c can determine the state shape of a memory cell belonging to the corresponding word line group.

[0105] The first seed SED_a can be assigned to the first word line groups WL1 to WL9. When the data to be programmed is randomized using a random sequence generated by the first seed SED_a, the cell ratio for the erase state "E" can be set to 50%. Furthermore, the cell ratios for programming states P1, P2, and P3, corresponding to relatively low threshold voltages, can all be set to 70%. The cell ratios for programming states P4 to P12 can all be set to 110%, and the cell ratios for each of the high programming states P13, P14, and P15 can be set to 90% or 95%.

[0106] In a three-dimensional structure where the cell string is formed perpendicular to the substrate, the memory cells in the first word line group WL1 to WL9 located at the bottom of the memory block are fragile or susceptible to damage from read interference. When the first seed SED_a is applied while programming the memory cells in the first word line group WL1 to WL9, the number of memory cells included in the erase state "E" or low programming states (e.g., P1 to P3) can be reduced. For example, as the number of memory cells in the erase state "E" decreases, the characteristic degradation due to read interference can be reduced.

[0107] The second seed SED_b can be assigned to the second word line groups WL10 to WL78. When the data to be programmed is randomized using a random sequence generated by the second seed SED_b, the cell ratio for the erase state "E" can be set to 95%, and the cell ratios for programming states P1, P2, and P3 can all be set to 96%. The cell ratios for programming states P4 to P12 can all be set to 110%, the cell ratio for programming state P13 can be set to 71%, the cell ratio for programming state P14 can be set to 61%, and the cell ratio for programming state P15 can be set to 51%.

[0108] In a three-dimensional structure where the cell string is formed perpendicular to the substrate, the charge leakage characteristics of the memory cells in the second word line group WL10 to WL78, located in the middle portion of the memory block, are relatively significant. When programming memory cells connected to word lines belonging to the middle portion, the reliability reduction due to charge leakage can be reduced by decreasing the number of memory cells to be programmed into high-programmability states (e.g., P13, P14, and P15).

[0109] The third seed SED_c can be assigned to the third word line groups WL79 to WL92. When the data to be programmed is randomized using a random sequence generated by the third seed SED_c, the cell ratio for the erase state "E" and the low programming states P1, P2, and P3 can all be set to 99%. The cell ratio for programming states P4 to P12 can all be set to 105%, and the cell ratio for high programming states P13, P14, and P15 can all be set to 98%. Compared to the cell ratio of states formed using the first seed SED_a and the second seed SED_b, the cell ratio of states formed using the third seed SED_c can be relatively uniform. This is because, compared to the first and second word line groups, the memory cells included in the third word line groups WL79 to WL92 are relatively less affected or relatively less susceptible to read interference or charge leakage characteristics.

[0110] The above briefly describes an example of a seed table where the seed is applied in units of word lines. However, the range of word lines and the unit ratio values ​​for each state described above are merely examples. It is easy to understand that the range of word lines and the unit ratio values ​​for each state can vary depending on various purposes.

[0111] Figure 11A and Figure 11B This is a diagram illustrating another example of a seed selection state shaping operation according to the concept of the present invention. Figure 11A This is a diagram showing the state shaping associated with word lines (hereinafter referred to as "lower word lines") arranged in the lower region of the memory block; Figure 11BThis is a diagram illustrating the state shaping associated with word lines (hereinafter referred to as "intermediate word lines") arranged in the middle region of a memory block. It is assumed that a non-volatile memory device 120 (refer to...) Figure 1 Each storage cell is a triple-level cell (TLC) with one of eight threshold voltage states to describe the features of the inventive concept.

[0112] exist Figure 11A The diagram illustrates the state shaping associated with the memory cell connected to the lower word line WLi. Figure 11A The seed shown for state shaping can be used in randomized operations for programming memory cells connected to word lines WLi. In this case, the cell ratio for erasing state "E" can be 51%. This means that compared to the case of applying equal shaping, the number of memory cells with erasing state "E" among the memory cells connected to word lines WLi is reduced after the programming operation. Furthermore, the cell ratio for programming state P1 is 70%. The cell ratios for programming states P2 and P6 can both be set to 100%, the cell ratios for programming states P3 and P5 can both be set to 110%, the cell ratio for programming state P4 can be set to 120%, and the cell ratio for the highest programming state P7 can be set to 95%.

[0113] The word line WLi can be a lower word line close to the substrate. Memory cells connected to the word line WLi located at the bottom of the memory block are fragile or susceptible to damage from read interference. As described above, when data is programmed based on a seed corresponding to the lower word line, the number of memory cells included in the erase state "E" can be reduced. With a reduction in the number of memory cells in the erase state "E", characteristic degradation due to read interference can be reduced.

[0114] exist Figure 11B The diagram shows the state shaping associated with the memory cell connected to the intermediate word line WLj. Figure 11B The seed shown for state shaping can be used in randomization operations for programming memory cells connected to word line WLj. In this case, the cell ratio for erasing state "E" can be 95%. Furthermore, the cell ratio for programming state P1 is 97%. The cell ratios for programming states P2 and P6 can both be set to 100%, the cell ratios for programming states P3 and P5 can both be set to 110%, the cell ratio for programming state P4 can be set to 120%, and the cell ratio for the highest programming state P7 can be set to 51%.

[0115] and Figure 11AThe different seeds shown can be applied to word line WLi in randomization operations used to program memory cells connected to word line WLj. In this case, the cell ratio for erasure state "E" can be 95%, and the cell ratio for the highest programming state P7 is 51%. This means that the number of memory cells to be programmed to the highest programming state P7 is relatively reduced.

[0116] Based on the state shaping of the memory cells connected to the word line WLj, the number of memory cells included in the highest programming state P7, which has a relatively high threshold voltage, is reduced. After a memory cell is programmed, the threshold voltage drop due to charge leakage is more pronounced at the memory cell with the highest programming state P7. Therefore, the reliability reduction due to charge leakage can be reduced by decreasing the number of memory cells with the highest programming state P7.

[0117] As an example, the state shaping results of memory cells corresponding to word lines WLi arranged at the bottom and WLj arranged in the middle are described. Based on the state shaping of the memory cells connected to word line WLi, the number of memory cells included in the erase state "E" is reduced. With the reduction in the number of memory cells in the erase state "E", characteristic degradation due to read interference can be reduced. In contrast, based on the state shaping of the memory cells connected to word line WLj, the number of memory cells included in the highest programming state P7, which has a relatively high threshold voltage, is reduced. After programming the memory cells, a threshold voltage drop due to charge leakage occurs at the memory cells with the highest programming state P7. Therefore, the reliability reduction due to charge leakage can be reduced by reducing the number of memory cells with the highest programming state P7.

[0118] The above describes how read interference characteristics can be improved and how hold characteristic degradation can be mitigated or prevented through word line-based state shaping. However, characteristic degradation based on the position of each word line is not limited to the characteristics described above. It is easy to understand that seed SEDs applied to various state shapings can be applied to word lines from which characteristic degradation is detected differently.

[0119] Figure 12A and Figure 12B This is a diagram illustrating a seed table of another exemplary embodiment of the concept according to the present invention. Figure 12A A seed table is shown for performing state shaping based on storage blocks. Figure 12B A seed table is shown for performing state shaping based on storage segments.

[0120] Reference Figure 12A Seed generator 118a (refer to) Figure 7The seed generator 118a may include seeds SED_i to SED_l allocated based on memory blocks or groups of memory blocks. The seed generator 118a may store and manage seeds SED_i to SED_l in the form of a seed table. Each seed in SED_i to SED_l can determine the state shape of the memory cell connected to a selected word line.

[0121] The first seed SED_i can be assigned to the first block group BLK0 to BLK2999. When the data to be programmed is randomized using a random sequence generated by the first seed SED_i, the cell ratio for the erase state "E" can be set to 50%. Furthermore, the cell ratios for programming states P1, P2, and P3, corresponding to relatively low threshold voltages, can all be set to 70%. The cell ratios for programming states P4 to P12 can all be set to 110%, and the cell ratios for each of the high programming states P13, P14, and P15 can be set to 90% or 95%.

[0122] The second seed SED_j can be assigned to the second block group BLK3000 to BLK3399. When the data to be programmed is randomized using a random sequence generated by the second seed SED_j, the cell ratio for the erase state "E" can be set to 95%, and the cell ratios for programming states P1, P2, and P3 can all be set to 96%. The cell ratios for programming states P4 to P12 can all be set to 110%, the cell ratio for programming state P13 can be set to 71%, the cell ratio for programming state P14 can be set to 61%, and the cell ratio for programming state P15 can be set to 51%.

[0123] The third seed SED_k can be assigned to the third block group BLK3400 to BLK3799. When the data to be programmed is randomized using a random sequence generated by the third seed SED_k, the cell ratio for the erase state "E" and the low programming states P1, P2, and P3 can all be set to 99%. The cell ratio for programming states P4 to P12 can all be set to 105%, and the cell ratio for high programming states P13, P14, and P15 can all be set to 98%.

[0124] The fourth seed SED_l can be assigned to the fourth block group BLK3800 to BLK6799. When randomizing the data to be programmed using a random sequence generated by the fourth seed SED_l, the cell ratio for the erase state "E" can be set to 95%, and the cell ratios for programming states P1, P2, and P3 can all be set to 97%. The cell ratios for programming states P4 to P12 can all be set to 105%, the cell ratio for programming state P13 can be set to 97%, and the cell ratios for high-programming states P14 and P15 can both be set to 95%.

[0125] The above briefly describes an example of a seed table where seeds SED_i to SED_l are applied on a block-group basis. However, the range of storage block groups and the unit ratio values ​​for each state described above are merely examples. It is easy to understand that the range of storage block groups and the unit ratio values ​​for each state can be varied for various purposes.

[0126] Reference Figure 12B Seed generator 118a (refer to) Figure 7 The seed generator 118a may include seeds SED_i to SED_l based on slice allocation. The seed generator 118a may store and manage seeds SED_i to SED_l in the form of a seed table. Each seed in SED_i to SED_l can determine the state shape of the memory cell connected to the selected word line.

[0127] The first seed SED_i can be assigned to a first group of patches, including patches 1 through 5. When the data to be programmed is randomized using a random sequence generated by the first seed SED_i, the cell ratio for the erase state "E" can be set to 50%. Furthermore, the cell ratios for programming states P1, P2, and P3, corresponding to relatively low threshold voltages, can all be set to 70%. The cell ratios for programming states P4 through P12 can all be set to 110%, and the cell ratios for each of the high programming states P13, P14, and P15 can be set to 90% or 95%.

[0128] The second seed SED_j can be assigned to the second group of patches, including patches 6 to 10. When the data to be programmed is randomized using a random sequence generated by the second seed SED_j, the cell ratio for the erase state "E" can be set to 95%, and the cell ratios for programming states P1, P2, and P3 can all be set to 96%. The cell ratios for programming states P4 to P12 can all be set to 110%, the cell ratio for programming state P13 can be set to 71%, the cell ratio for programming state P14 can be set to 61%, and the cell ratio for programming state P15 can be set to 51%.

[0129] The third seed SED_k can be assigned to the third group of patches, including patches 11 to 15. When the data to be programmed is randomized using a random sequence generated by the third seed SED_k, the cell ratios for the erase state "E" and the low-programming states P1, P2, and P3 can all be set to 99%. The cell ratios for programming states P4 to P12 can all be set to 105%, and the cell ratios for high-programming states P13, P14, and P15 can all be set to 98%.

[0130] The fourth seed SED_l can be assigned to the fourth group of patches, including patches 16 to 20. When the data to be programmed is randomized using a random sequence generated by the fourth seed SED_l, the cell ratio for the erase state "E" can be set to 95%, and the cell ratios for programming states P1, P2, and P3 can all be set to 97%. The cell ratios for programming states P4 to P12 can all be set to 105%, the cell ratio for programming state P13 can be set to 97%, and the cell ratios for high-programming states P14 and P15 can both be set to 95%.

[0131] The above briefly describes an example of a seed table where seeds SED_i to SED_l are applied on a per-segment basis to non-volatile memory devices. However, the range of segment groups and the cell ratio values ​​for each state described above are merely examples. It is readily understood that the range of segment groups and the cell ratio values ​​for each state can vary depending on various purposes. Furthermore, an example of seed allocation based on blocks or segments is described, but it is readily understood that seeds can be allocated based on various memory region units to improve reliability.

[0132] Figure 13 This is a block diagram of a non-volatile memory device performing on-chip randomization operations according to another exemplary embodiment of the present invention. (Refer to...) Figure 13 The non-volatile memory device 200 includes a cell array (i.e., a memory cell array) 210, a decoder 220, a page buffer 230, an on-chip randomizer 240, an input / output buffer 250, and control logic circuitry 260.

[0133] Cell array 210 is connected to decoder 220 via word line WL and select lines SSL and GSL. Cell array 210 is connected to page buffer 230 via bit line BL. Cell array 210 includes multiple memory blocks BLK1 to BLKi. Each memory block BLK1 to BLKi includes multiple NAND cell strings.

[0134] Decoder 220 can select one of the memory blocks BLK1 to BLKi of cell array 210 in response to row address ADDR. Decoder 220 can select one of the word lines of the selected memory block. Decoder 220 transmits word line voltage to the selected word line. Decoder 220 transmits a select signal to the select line (e.g., SSL or GSL) of the selected memory block. Decoder 220 can transmit programming / verification voltage to the selected word line and pass voltage to the unselected word line.

[0135] Page buffer 230 can be used as a write driver or a sense amplifier depending on the operating mode. During programming, page buffer 230 supplies a bit line voltage corresponding to the data to be programmed to the bit lines of cell array 210. During read operations, page buffer 230 senses data stored in a selected memory cell via the bit lines. Page buffer 230 can latch the sensed data and can output the latched data externally.

[0136] On-chip randomizer 240 is configured to perform randomization operations on data to be programmed into cell array 210. On-chip randomizer 240 can select a seed to be used for the randomization operation by referring to address ADDR. When a seed is selected, on-chip randomizer 240 can perform state shaping based on regions (e.g., based on word lines). Furthermore, on-chip randomizer 240 can perform derandomization operations on data sensed from cell array 210 and subsequently stored in page buffer 230. The seed used in the derandomization operation can be used in the derandomization operation.

[0137] The on-chip randomizer 240 randomizes the data to be programmed and outputs the randomized data to the page buffer 230. For example, the on-chip randomizer 240 can perform encoding to provide a different threshold voltage distribution for each region of the cell array 210. The on-chip randomizer 240 can encode the data to be programmed based on the vulnerability characteristics according to the position of the word lines of the cell array 210. As the encoded data is programmed into the cell array 210, a threshold voltage distribution with optimal reliability can be formed for each word line. Here, it is well understood that the unit of encoding for state shaping performed by the on-chip randomizer 240 is not limited to the word line unit.

[0138] The on-chip randomizer 240 can generate a seed from address ADDR, or can select a seed based on address ADDR. The on-chip randomizer 240 can generate a random sequence RS with reference to the seed. The on-chip randomizer 240 can randomize the data to be stored in the target area using the generated random sequence RS, and can provide the randomized data to the page buffer 230.

[0139] Input / output buffer 250 provides write data received during programming operations to page buffer 230. During read operations, input / output buffer 250 outputs data provided by page buffer 230 to the outside. Input / output buffer 250 provides received addresses or commands to control logic circuit 260, decoder 220, or on-chip randomizer 240.

[0140] Control logic circuit 260 controls page buffer 230 and on-chip randomizer 240 in response to commands CMD and address ADDR from input / output buffer 250. Control logic circuit 260 performs operations corresponding to write commands, read commands, or erase commands provided through input / output buffer 250 for selected memory regions.

[0141] According to an exemplary embodiment of the present invention, the non-volatile memory device 200 includes an on-chip randomizer 240 that performs different state shaping for each region. For example, the on-chip randomizer 240 can apply a seed to perform state shaping on a word-line basis. For example, memory cells connected to lower word lines near the substrate are fragile or susceptible to read interference. When programming memory cells connected to lower word lines, the on-chip randomizer 240 can use a seed that allows for a reduction in the number of memory cells with erase state "E". As the number of memory cells with erase state "E" decreases, characteristic degradation due to read interference can be reduced. Furthermore, when programming memory cells connected to word lines arranged in the middle region of a three-dimensional memory block, the on-chip randomizer 240 can perform randomization operations such that the number of memory cells to be programmed to a high-programmability state is reduced, thereby minimizing reliability degradation due to charge leakage.

[0142] Figure 14 It is shown Figure 13 A block diagram of an example configuration of the on-chip randomizer is shown. (Refer to...) Figure 14 The on-chip randomizer 240 may include a seed generator 242, a random sequence generator 244, and a mixer 246.

[0143] Seed generator 242 generates a seed corresponding to a specific region by referring to the received address ADDR. Here, the specific region may correspond to a page, word line, word line group, or region such as a memory block or slice in cell array 210. That is, seed generator 242 generates a seed that can be allocated on a unit basis for a specific region. For example, seed generator 242 may be implemented in the form of a lookup table, thereby selecting different seeds based on the position of the word line. In this case, seed generator 242 may retrieve the seed for each word line from the lookup table by referring to address ADDR. When a seed corresponding to a word line is selected, seed generator 242 provides the generated seed to random sequence generator 244.

[0144] Random sequence generator 244 generates a random sequence RS using a seed provided from seed generator 242. Random sequence generator 244 generates a random sequence RS using the input seed as a source. For example, random sequence generator 244 can be implemented using a linear feedback shift register (LSFR) with Fibonacci configuration operation.

[0145] The mixer 246 mixes the random sequence RS generated by the random sequence generator 244 for randomization operations with the input data Din. For example, the output data Dout can be generated by performing an XOR operation on each bit of the random sequence RS and each bit of the input data Din. Here, the input data Din can be one or more pages of data provided from the input / output buffer 250.

[0146] The mixer 246 mixes the random sequence RS generated by the random sequence generator 244 for randomization operations with the input data Din. For example, the output data Dout can be generated by performing an XOR operation on each bit of the random sequence RS and each bit of the input data Din. Here, the input data Din can be multiple pages of data to be stored in a memory cell connected to a word line. The randomized data Dout generated by the mixer 246 can be provided to the page buffer 230 for programming in a selected area.

[0147] Figure 15 It is shown Figure 14 An example diagram of a random sequence generator. Figure 15 The diagram shows a random sequence generator 244 implemented with four triggers for generating random sequences in a Fibonacci configuration. The generator polynomial g(X) of the random sequence generator 244 is represented by Equation 1 below.

[0148] [Formula 1]

[0149] g(X) = X 4 +X+1

[0150] That is, a random sequence generator 244 can be implemented using a linear feedback shift register (LSFR) comprising multiple flip-flops. Here, the binary values ​​stored in flip-flops D0, D1, D2, and D3 correspond to the seed, respectively. The bit stream output as the clock switches can be a random sequence RS.

[0151] Assume the initial values ​​of flip-flops D0, D1, D2, and D3 in the random sequence generator 244 are [1 0 0 0]. After 15 clock cycles, the values ​​of flip-flops D0, D1, D2, and D3 are set to their initial values. When the clock cycle "T" is 15, the data states of flip-flops D0, D1, D2, and D3 can be set to their initial values. The bit stream output from flip-flop D3 can be provided as a random sequence. Figure 15 The random sequence generator 244 shown is merely an example for generating random sequences in a Fibonacci configuration. It is easy to understand that various types of random sequence generators are available.

[0152] According to exemplary embodiments of the present invention, problems arising from read interference or charge leakage (e.g., reduced reliability) due to the high integration of non-volatile memory devices can be solved.

[0153] Figure 16 This is a diagram illustrating an exemplary non-volatile storage device. (Refer to...) Figure 16 The memory device 500 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip by bonding. For example, the bonding method may include electrically connecting a bonding metal formed on the topmost metal layer of the upper chip to a bonding metal formed on the topmost metal layer of the lower chip. For example, when the bonding metal can be formed of copper (Cu), the bonding method can be a Cu-Cu bonding, and the bonding metal can also be formed of aluminum or tungsten.

[0154] The peripheral circuit area PERI and cell area CELL of the storage device 500 can each include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0155] The Peripheral Circuit Area (PERI) may include: a first substrate 310, an interlayer insulating layer 315, a plurality of circuit elements 320a, 320b, and 320c formed on the first substrate 310, first metal layers 330a, 330b, and 330c respectively connected to the plurality of circuit elements 320a, 320b, and 320c, and second metal layers 340a, 340b, and 340c formed on the first metal layers 330a, 330b, and 330c. In an example embodiment, the first metal layers 330a, 330b, and 330c may be formed of tungsten, which has relatively high resistance, and the second metal layers 340a, 340b, and 340c may be formed of copper, which has relatively low resistance.

[0156] exist Figure 16 In the example embodiments shown, although first metal layers 330a, 330b, and 330c and second metal layers 340a, 340b, and 340c are shown and described, they are not limited thereto, and one or more metal layers may be formed on the second metal layers 340a, 340b, and 340c. At least a portion of the one or more metal layers formed on the second metal layers 340a, 340b, and 340c may be formed of aluminum or the like, having a lower resistance than the copper used to form the second metal layers 340a, 340b, and 340c.

[0157] An interlayer insulating layer 315 may be disposed on a first substrate 310 and cover a plurality of circuit elements 320a, 320b and 320c, first metal layers 330a, 330b and 330c and second metal layers 340a, 340b and 340c. The interlayer insulating layer 315 may include an insulating material such as silicon oxide or silicon nitride.

[0158] The lower bonding metals 371b and 372b can be formed on the second metal layer 340b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 371b and 372b in the peripheral circuit region PERI can be electrically connected to the upper bonding metals 471b and 472b in the cell region CELL in a bonding manner, and the lower bonding metals 371b and 372b and the upper bonding metals 471b and 472b can be formed of aluminum, copper, tungsten, etc.

[0159] Furthermore, the upper bonding metals 471b and 472b in the cell region CELL can be referred to as the first metal pads, while the lower bonding metals 371b and 372b in the peripheral circuit region PERI can be referred to as the second metal pads. Moreover, the first and second metal pads can be connected to each other in a bonding manner.

[0160] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 410 and a common source line 420. Multiple word lines 431 to 438 (i.e., 430) may be stacked on the second substrate 410 in a direction perpendicular to the upper surface of the second substrate 410 (Z-axis direction). At least one string select line and at least one ground select line may be arranged on and below the multiple word lines 430, respectively, and the multiple word lines 430 may be positioned between the at least one string select line and the at least one ground select line.

[0161] In the bit line bonding area BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 410 and pass through multiple word lines 430, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 450c and the second metal layer 460c. For example, the first metal layer 450c may be a bit line contact, and the second metal layer 460c may be a bit line. In an example embodiment, the bit line 460c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 410.

[0162] exist Figure 16 In the example embodiment shown, the region provided with the channel structure CH, bit line 460c, etc., can be defined as the bit line bonding region BLBA. In the bit line bonding region BLBA, bit line 460c can be electrically connected to circuit element 320c that provides page buffer 493 in the peripheral circuit region PERI. For example, bit line 460c can be connected to upper bonding metals 471c and 472c in the cell region CELL, and upper bonding metals 471c and 472c can be connected to lower bonding metals 371c and 372c that are connected to the circuit element 320c of the page buffer 493.

[0163] In the word line bonding area (WLBA), multiple word lines 430 can extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 410 and can be connected to multiple cell contacts 441 to 447 (i.e., 440). The multiple word lines 430 and the multiple cell contacts 440 can be connected to each other by pads provided by at least a portion of the multiple word lines 430 extending in the second direction at different lengths. A first metal layer 450b and a second metal layer 460b can be sequentially connected to the upper portion of the multiple cell contacts 440 connected to the multiple word lines 430. The multiple cell contacts 440 can be connected in the word line bonding area (WLBA) to the peripheral circuit area (PERI) via upper bonding metals 471b and 472b in the cell area (CELL) and lower bonding metals 371b and 372b in the peripheral circuit area (PERI).

[0164] Multiple unit contact pins 440 can be electrically connected to circuit element 320b, which provides a row decoder 494 in the peripheral circuitry region PERI. In an example embodiment, the operating voltage of circuit element 320b providing the row decoder 494 may differ from the operating voltage of circuit element 320c providing the page buffer 493. For example, the operating voltage of circuit element 320c providing the page buffer 493 may be greater than the operating voltage of circuit element 320b providing the row decoder 494.

[0165] A common source contact 480 can be disposed in the external pad bonding region PA. The common source contact 480 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 420. A first metal layer 450a and a second metal layer 460a can be sequentially stacked on top of the common source contact 480. For example, the region where the common source contact 480, the first metal layer 450a, and the second metal layer 460a are disposed can be defined as the external pad bonding region PA.

[0166] Input-output pads 305 and 405 can be set in the external pad bonding area PA. (See reference...) Figure 16 A lower insulating film 301 covering the lower surface of the first substrate 310 can be formed below the first substrate 310, and a first input-output pad 305 can be formed on the lower insulating film 301. The first input-output pad 305 can be connected to at least one of a plurality of circuit elements 320a, 320b, and 320c disposed in the peripheral circuit region PERI via a first input-output contact 303, and can be separated from the first substrate 310 by the lower insulating film 301. In addition, a side insulating film can be disposed between the first input-output contact 303 and the first substrate 310 to electrically separate the first input-output contact 303 from the first substrate 310.

[0167] Reference Figure 16 An upper insulating film 401 covering the upper surface of the second substrate 410 can be formed on the second substrate 410, and a second input-output pad 405 can be disposed on the upper insulating layer 401. The second input-output pad 405 can be electrically connected to at least one of a plurality of circuit elements 320a, 320b and 320c disposed in the peripheral circuit region PERI via a second input-output contact 403.

[0168] According to an embodiment, the second substrate 410 and the common source line 420 may not be located in the region where the second input-output contact 403 is provided. Furthermore, the second input-output pad 405 may not overlap with the word line 430 in the third direction (Z-axis direction). (Refer to...) Figure 16 The second input-output contact 403 can be separated from the second substrate 410 in a direction parallel to the upper surface of the second substrate 410, and can pass through the interlayer insulating layer 415 in the cell region CELL to connect to the second input-output pad 405 and the lower bonding metals 371a and 372a in the peripheral circuit region PERI.

[0169] According to embodiments, the first input-output pad 305 and the second input-output pad 405 can be selectively formed. For example, the storage device 500 may include only the first input-output pad 305 disposed on the first substrate 310 or the second input-output pad 405 disposed on the second substrate 410. Alternatively, the storage device 500 may include both the first input-output pad 305 and the second input-output pad 405.

[0170] In each of the external pad bonding area PA and bit line bonding area BLBA included in the cell region CELL and the external pad bonding area PA and bit line bonding area BLBA included in the peripheral circuit region PERI, the metal pattern in the uppermost metal layer can be set as a dummy pattern or the uppermost metal layer may not exist.

[0171] In the external pad bonding area PA, the storage device 500 may include a lower metal pattern 373a in the uppermost metal layer of the peripheral circuit area PERI, which corresponds to the upper metal pattern 472a formed in the uppermost metal layer of the cell area CELL and has the same shape as the upper metal pattern 472a in the cell area CELL. In the peripheral circuit area PERI, the lower metal pattern 373a formed in the uppermost metal layer of the peripheral circuit area PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern may be formed in the uppermost metal layer of the cell area CELL, which corresponds to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit area PERI and has the same shape as the lower metal pattern in the peripheral circuit area PERI.

[0172] Lower bonding metals 371b and 372b can be formed on the second metal layer 340b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 371b and 372b in the peripheral circuit region PERI can be electrically connected to the upper bonding metals 471b and 472b in the cell region CELL via Cu-Cu bonding.

[0173] Furthermore, in the bit line bonding region BLBA, the upper metal pattern 492 can be formed in the topmost metal layer of the cell region CELL. The upper metal pattern 492 corresponds to the lower metal pattern 352 formed in the topmost metal layer of the peripheral circuit region PERI, and has the same shape as the lower metal pattern 352 in the peripheral circuit region PERI. Contacts may not be formed on the upper metal pattern 492 formed in the topmost metal layer of the cell region CELL.

[0174] In an example embodiment, a reinforcing metal pattern having the same shape as the metal pattern formed in the uppermost metal layer of one of the cell region (CELL) and the peripheral circuit region (PERI) can be formed in the uppermost metal layer of the other, and no contact may be formed on the reinforcing metal pattern.

[0175] As described in this disclosure, the various blocks, engines, controllers, and / or circuit elements included in the black box can be implemented using hardware components and combinations of software and hardware components. For example, hardware components may include microcontrollers, storage modules, sensors, amplifiers, bandpass filters, analog-to-digital converters, and processing devices. The processing device can be implemented using one or more hardware devices configured to perform and / or run program code by performing arithmetic, logical, and input / output operations. One or more processing devices may include processors, controllers, and arithmetic logic units, digital signal processors, microcomputers, field-programmable arrays, programmable logic units, microprocessors, or any other device capable of responding to and executing instructions in a defined manner. One or more processing devices may run an operating system (OS) and one or more software applications running on the OS. The processing device may also access, store, manipulate, process, and create data in response to the execution of software. For simplicity, the description of the processing device is used as the singular; however, those skilled in the art will understand that the processing device may include multiple processing elements and various types of processing elements. For example, the processing device may include multiple processors, or one processor and one controller. In addition, different processing configurations such as parallel processors, multi-core processors, and distributed processing are feasible.

[0176] Although the inventive concept has been described with reference to some exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A method for programming a non-volatile storage device, the method comprising: Receive the write address and write data; Generate a seed corresponding to the write address; A random sequence is generated using the seed; The written data is randomized using the random sequence. as well as The randomized write data is programmed into the storage area corresponding to the write address. The seed provides state shaping based on the positional changes of the letter lines. The generation of the seed includes: In response to the write address corresponding to a first word line, a first seed is generated, the first seed causing a first number of memory cells in a first memory region connected to the first word line to be in an erased state after the programming. In response to the write address corresponding to the second word line, a second seed is generated, the second seed causing a second number of memory cells in the second memory region connected to the second word line after the programming to be in the erase state, the second word line being farther from the substrate than the first word line, and the second number being greater than the first number.

2. The method according to claim 1, wherein, The third number of storage cells included in the highest programming state in the second storage region is less than the fourth number of storage cells included in the highest programming state in the first storage region.

3. The method according to claim 1, wherein, In the vertical direction, the first character line is closer to the substrate than the second character line.

4. The method according to claim 1, wherein, The second word line is located in the middle region and above the first word line, the middle region being located vertically between the substrate and the multiple bit lines.

5. The method according to claim 1, wherein, The generation of the seed includes: selecting one seed mapped to the write address from a plurality of pre-generated seeds as the seed.

6. The method according to claim 1, wherein, The seed is configured to provide state shaping that depends on the location of the storage block or slice of the non-volatile storage device.

7. A storage device, comprising: A storage controller configured to receive write data and a write address from a host, and to randomize the write data to perform state shaping on a storage cell selected based on the write address; as well as A non-volatile storage device configured to, under the control of the storage controller, program randomized write data into a storage area corresponding to the write address. The storage controller is further configured to perform the state shaping using a seed based on word line position changes, and the non-volatile storage device is configured to: in a first programming operation applying a first seed mapped to a first word line, program a first number of storage cells in a first storage region connected to the first word line into an erase state, and The non-volatile storage device is configured to: in a second programming operation that applies a second seed mapped to a second word line, program a second number of memory cells in a second memory region connected to the second word line to the erase state, wherein the second word line is farther from the substrate than the first word line, and the second number is greater than the first number.

8. The storage device according to claim 7, wherein, The storage controller is further configured to perform the state shaping on the selected storage cell using the write data and the write address.

9. The storage device according to claim 8, wherein, The storage controller is also configured to: Generate the seed corresponding to the write address; A random sequence is generated using the seed; and Randomization is performed by processing the written data and the random sequence using an XOR operation.

10. The storage device according to claim 9, wherein, The storage controller is also configured to include or be associated with a seed table, the seed table being configured to store a plurality of seeds mapped according to word line positions, the plurality of seeds including the first seed and the second seed.

11. The storage device according to claim 7, wherein, The third number of storage cells included in the highest programming state in the second storage region is less than the fourth number of storage cells included in the highest programming state in the first storage region.

12. The storage device according to claim 9, wherein, The storage controller is configured to include or be associated with a seed table, which is configured to store multiple seeds mapped according to the location of storage blocks or regions.

13. A non-volatile storage device, comprising: A cell array, the cell array comprising multiple storage cells having multiple programming states; An on-chip randomizer, configured to randomize write data from an external source; A page buffer, configured to program randomized write data provided by the on-chip randomizer into the memory array; as well as A control logic circuit configured to: select a memory cell from the plurality of memory cells of the cell array in response to a command and address provided from the external source, and control the page buffer and the on-chip randomizer such that randomized write data is programmed into the selected memory cell. The on-chip randomizer is configured to perform state shaping on the written data based on the word line position. The on-chip randomizer is further configured to: generate a first seed in response to the address corresponding to a first word line, and generate a second seed in response to the address corresponding to a second word line. The first seed provides a first state shaping with a first number of storage units in an erase state, and the second seed provides a second state shaping with a second number of storage units in the erase state. The second quantity is different from the first quantity.

14. The non-volatile storage device according to claim 13, wherein, The on-chip randomizer is configured as follows: Generate a seed corresponding to the address; A random sequence is generated using the seed; and Randomization is performed by processing the written data and the random sequence using an XOR operation.

15. The non-volatile storage device according to claim 13, wherein, The first word line is closer to the substrate than the second word line.

16. The non-volatile storage device according to claim 15, wherein, The highest state of the memory cells connected to the first word line includes a third number of memory cells, which is more than the fourth number of memory cells included in the highest state of the memory cells connected to the second word line.

17. The non-volatile storage device according to claim 15, wherein, The second word line is located in the middle region and above the first word line, the middle region being located vertically between the substrate and the multiple bit lines.

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