Data reading circuit and radio frequency front-end chip

Abstract

An embodiment of the present application discloses a data reading circuit, including: a controller, a first switching switch, a plurality of storage units, and a comparator; wherein, the controller is connected to the control end of the first switching switch; the comparator is connected to any one of the plurality of storage units through the first switching switch; the first switching switch is configured to connect the target storage unit among the plurality of storage units to the first input end of the comparator under the control of the controller; the comparator is configured to read the target data stored in the target storage unit after being connected to the target storage unit, and determine a reading result based on the target data. An embodiment of the present application also discloses a radio frequency front-end chip. The data reading circuit provided by the embodiment of the present application simplifies the structure of the reading circuit by repeatedly reading the data stored in a plurality of storage units by the comparator, reducing the area of the radio frequency front-end chip and the system cost.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor memory devices, and in particular to a data reading circuit and a radio frequency front-end chip. Background Art

[0002] In recent years, with the rapid development of the semiconductor industry, the application of RF front-end chips has become increasingly widespread. Generally speaking, the performance of RF front-end chips is easily affected by factors such as production process and ambient temperature. It is necessary to adjust the operating mode of RF front-end chips to improve their performance.

[0003] A common adjustment method is to add an electrically programmable fuse (eFUSE) memory circuit to the RF front-end chip. By reading the data stored in the eFUSE memory circuit, the RF front-end chip output is adjusted, thereby improving the RF front-end chip's operating performance. However, the existing eFUSE memory circuit has a relatively complex read circuit structure, resulting in a larger RF front-end chip area and higher system costs. Summary of the Invention

[0004] The embodiments of the present application provide a data reading circuit and a radio frequency front-end chip.

[0005] An embodiment of the present application provides a data reading circuit, comprising: a controller, a first switch, a plurality of storage units, and a comparator;

[0006] The controller is connected to the control end of the first switch; the comparator is connected to any one of the plurality of storage units through the first switch;

[0007] The first switch is configured to connect a target storage unit among the plurality of storage units to the first input terminal of the comparator under the control of the controller;

[0008] The comparator is configured to read target data stored in the target storage unit after being connected to the target storage unit, and determine a reading result based on the target data.

[0009] An embodiment of the present application further provides a radio frequency front-end chip, comprising a data reading circuit, wherein the data reading circuit comprises: a controller, a first switch, a plurality of storage units and a comparator;

[0010] The controller is connected to the control end of the first switch; the comparator is connected to any one of the plurality of storage units through the first switch;

[0011] The first switching switch is configured to connect a target storage unit among the multiple storage units to a first input end of the comparator under the control of the controller;

[0012] The comparator is configured to read target data stored in the target storage unit after being connected to the target storage unit, and determine a reading result based on the target data.

[0013] The data reading circuit provided by the embodiments of the present application simplifies the structure of the reading circuit, reduces the area of the radio frequency front-end chip and the system cost by repeatedly reading the data stored in multiple storage units through a comparator. At the same time, by reading the data stored in the storage unit through the comparator, the influence of the production process and the environment on the reading result is reduced. As long as the resistance value of the storage unit is slightly greater than or less than the reference resistance, the output result of the comparator will change, and the data stored in the storage unit can be accurately read, improving the reliability of data reading. Description of the Drawings

[0014] Figure 1 Schematic diagram of a programming circuit of an eFUSE memory circuit in a related technology provided by an embodiment of the present application;

[0015] Figure 2 Schematic diagram of a reading circuit of an eFUSE memory circuit in a related technology provided by an embodiment of the present application Figure 1 ;

[0016] Figure 3 Timing of a reading circuit in a related technology provided by an embodiment of the present application Figure 1 ;

[0017] Figure 4 Circuit of a reading circuit of an eFUSE memory circuit in a related technology provided by an embodiment of the present application Figure 2 ;

[0018] Figure 5 Timing of a reading circuit in a related technology provided by an embodiment of the present application Figure 2 ;

[0019] Figure 6 Schematic diagram of a data reading circuit provided by an embodiment of the present application;

[0020] Figure 7 Schematic diagram of the structure of a radio frequency front-end chip provided by an embodiment of the present application;

[0021] Figure 8 Schematic diagram of the process of a read operation of a radio frequency front-end chip provided by an embodiment of the present application;

[0022] Figure 9This is a timing diagram of the read operation of a radio frequency front-end chip provided by an embodiment of the present application. Specific embodiments

[0023] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0024] To make the purpose, technical solutions, and advantages of the present application clearer, the embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not intended to limit the embodiments of the present application.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include steps or units not listed, or may optionally further include other steps or units inherent to these processes, methods, products, or devices.

[0026] In addition, the term "and / or" in the embodiments of the present application is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0027] An electrically programmable fuse (eFUSE) is a one-time programmable memory. The information stored in the eFUSE will not be lost due to system power-off, and each fuse can only be programmed once. Therefore, eFUSEs are widely used in chip manufacturing for data storage. In an eFUSE, each fuse corresponds to a binary number. When the fuse is conducting, it represents the data "0", and after the fuse is blown, it represents the data "1". In the initial state, the data of all fuses is "0", and different data is stored by blowing the fuses that need to be rewritten as "1".

[0028] Figure 1 This is a circuit diagram of a programming circuit for an eFUSE memory circuit in a related technology provided by an embodiment of the present application. As Figure 1 shown, the resistance value of the eFUSE before programming is very small, about R1 (<200 ohms). By selecting a port (for example Figure 1The FSELECT port shown in selects the eFUSE to be programmed. During programming, the FSELECT port is set to a low level, and the field effect transistor M1 is turned on. At this time, a large current will flow through the eFUSE. When the current is large enough and the duration is long enough, the fuse will melt due to the electromigration effect, and the resistance value will increase, approximately to R2 (>1000 ohms). The resistance value of the eFUSE after programming can be determined by controlling the programming time and programming current.

[0029] Figure 2 The circuit diagram of the read circuit of the eFUSE memory circuit in a related technology provided by an embodiment of the present application Figure 1 , Figure 3 is Figure 2 the timing diagram of the read circuit.

[0030] Combined with Figure 2 and Figure 3 , before reading the eFUSE, the reset port (such as the FCLRN port shown in Figure 2 ) is set to a low level. At this time, the field effect transistors M5 and M6 are turned on, and the field effect transistors M2 and M3 are turned off. Regardless of whether the eFUSE has been programmed, the voltage jump point Vtrip is pulled high. The output port (such as the FT port shown in Figure 2 ) also outputs a high level.

[0031] When reading the eFUSE, the start port (such as the FSETP port shown in Figure 2 ) is set to a high level. At this time, the field effect transistor M4 is turned on. If the eFUSE has not been programmed, the resistance value is small, and the pull-down circuit composed of the field effect transistors M1, M4, and the eFUSE has a strong pull-down ability. In this way, the voltage jump point Vtrip is pulled low, the field effect transistor M6 is turned off, the field effect transistor M3 is turned on, the FCLRN port is at a high level, the field effect transistor M2 is turned on, and the field effect transistor M5 is turned off. After that, regardless of the level of the FSETP port, the pull-down circuit composed of the field effect transistors M2 and M3 keeps the voltage jump point Vtrip at a low level, and the FT port outputs a low level.

[0032] On the contrary, if the eFUSE has been programmed, the resistance value is large. After the FSETP port is set to a high level, the pull-down circuit composed of the field effect transistors M1, M4, and the eFUSE has a weak pull-down ability, and the voltage jump point Vtrip and the output of the FT port remain high. In this way, the stored data in the eFUSE can be read by judging the level of the FT port. That is to say, when reading the eFUSE, the FT port outputs a low level to represent data "0", and the FT port outputs a high level to represent data "1".

[0033] Although Figure 2The eFUSE reading circuit shown is simple in structure and can reduce the area of the RF front-end chip. However, since the resistance value of the eFUSE after programming is affected by the programming time and the programming current, if the resistance value after programming is not large enough, it will affect the result of the eFUSE reading circuit and will not be able to store accurate information. Figure 2 The conductive characteristics of the MOS device in the reading circuit shown may be affected by factors such as production process, power supply voltage and ambient temperature, resulting in errors. Figure 2 The reliability of the reading circuit shown is low, and the accuracy of the reading result is easily affected by the production process, programming conditions and environment, and the accuracy of the reading result cannot be guaranteed.

[0034] In addition, a reading circuit of an eFUSE memory circuit is also provided in the related art, referring to Figure 4 A circuit diagram of a read circuit of an eFUSE memory circuit in a related art is shown. Figure 2 ,as well as Figure 5 Shown Figure 4 The timing diagram of the reading circuit in Figure 4 and Figure 5 As shown, when reading eFUSE, the port (such as Figure 4 The FSENSE port shown in FIG is set to a high level, and the voltage values Va and Vb generated when the same current I flows through the eFUSE and the reference resistor are compared by the comparator. If the voltage value of the programmed eFUSE is greater than the voltage value of the reference resistor, the output port (for example Figure 4 The FT port shown in FIG1 outputs a high level, which can indicate that the data stored in the eFUSE is "1". Conversely, if the voltage value of the unprogrammed eFUSE is less than or equal to the voltage value of the reference resistor, the FT port outputs a low level, which can indicate that the data stored in the eFUSE is "0".

[0035] As can be seen, the comparator-based eFUSE read circuit is less affected by factors such as process errors. As long as the eFUSE resistance is slightly greater than or less than the reference resistance, the comparator output will change, allowing the data stored in the eFUSE to be accurately read. However, the comparator-based eFUSE read circuit generally has a large area. Each eFUSE requires a comparator to read the eFUSE. Therefore, the read circuit chip area of ​​the comparator to implement the read function is large and the cost is high.

[0036] In order to solve the above problems existing in the prior art, the embodiment of the present application provides a data reading circuit 60, such as Figure 6 As shown, the data reading circuit 60 may include: a controller 61, a first switch 62, a plurality of storage units 63 and a comparator 64.

[0037] Among them, the controller 61 is connected to the control end of the first switching switch 62; the comparator 64 is connected to any one of the multiple storage units 63 through the first switching switch 62; among them,

[0038] The first switching switch 62 is configured to connect the target storage unit among the multiple storage units 63 to the first input terminal 641 of the comparator 64 under the control of the controller 61;

[0039] The comparator 64 is configured to read the target data stored in the target storage unit after being connected to the target storage unit, and determine a reading result based on the target data.

[0040] Here, the controller 61 can be a read-write controller. The controller 61 is connected to the control end of the first switching switch 62. The controller 61 is configured to receive a read signal, determine the target storage unit based on the read signal, control the first switching switch 62 to connect the target storage unit to the comparator 64, so that the comparator 64 reads the target data stored in the target storage unit, and determine a reading result based on the target data, thereby realizing data reading.

[0041] Specifically, the comparator 64 can be connected to any one of the multiple storage units 63 through the first switching switch 62; the first switching switch 62 is configured to connect the target storage unit among the multiple storage units 63 to the first input terminal 641 of the comparator 64 under the control of the controller 61. That is to say, the multiple storage units 63 share one comparator 64, and the target storage unit to be read is selected through the first switching switch 62 to be connected to the comparator 64, and the comparator 64 is repeatedly used to read different storage units. In this way, the structure of the reading circuit can be greatly simplified, and the area of the radio frequency front-end chip and the system cost can be reduced.

[0042] Here, the comparator 64 is configured to read the target data stored in the target storage unit after being connected to the target storage unit, and determine a reading result based on the target data. After the comparator 64 is connected to the target storage unit through the first switching switch 62, it will read the target data stored in the target storage unit and determine a reading result according to the target data, thereby realizing data reading in the storage unit.

[0043] It can be seen that the data reading circuit provided by the embodiment of the present application simplifies the structure of the reading circuit and reduces the area of the radio frequency front-end chip and the system cost by repeatedly reading the data stored in multiple storage units by the comparator. At the same time, by reading the data stored in the storage unit by the comparator, the influence of the production process and the environment on the reading result is reduced. As long as the resistance value of the storage unit is slightly greater than or less than the reference resistance, the output result of the comparator will change, and the data stored in the storage unit can be accurately read, improving the reliability of data reading.

[0044] Based on the above embodiments, in an embodiment of the present application, the data reading circuit 60 may further include: a reference resistor 65, and the reference resistor 65 is connected to the second input terminal 642 of the comparator 64.

[0045] The comparator 64 is specifically configured to, after being connected to the target storage unit, read the voltage value corresponding to the target storage unit to obtain target data, and compare the target data with a reference voltage value. If the target data is greater than the reference voltage value, it is determined that the reading result is the first value; if the target data is less than or equal to the reference voltage value, it is determined that the reading result is the second value.

[0046] Specifically, after the comparator 64 is connected to the target storage unit, it will read the target data stored in the target storage unit. Here, the target data may be the voltage value generated after a unit current flows through the target storage unit. Since the voltage magnitude generated when the same current flows through different resistors is proportional to the resistor magnitude, the resistor magnitude can be determined by comparing the voltage value magnitudes. Therefore, the comparator 64 can determine the magnitude of the resistance value of the target storage unit and the reference resistor by comparing the voltage value generated when a unit current flows through the target storage unit with the reference voltage value generated when a unit current flows through the reference resistor 65, and further can determine whether the target storage unit has been programmed. [[ID=⑨]]

[0047] Exemplarily, after the comparator 64 reads the resistance value of the target storage unit, the comparator 64 will determine the magnitude of the resistance value of the target storage unit and the reference resistor 65 by comparing the magnitudes of the voltage values generated when the same current flows through the target storage unit and the reference resistor. If the resistance value stored in the target storage unit is larger than the resistance value of the reference resistor 65, it can be determined that the comparison result is greater than 1, and this comparison result greater than 1 is used as the first value and "1" is output, that is, the target storage unit has been programmed and the reading result is output as "1"; conversely, if the resistance value of the target storage unit is smaller than the resistance value of the reference resistor 65, it can be determined that the comparison result is less than 1, and this comparison result less than 1 is used as the second value and "0" is output, that is, the target storage unit has not been programmed and the reading result is output as "0".

[0048] By comparing the resistance value of the target storage unit with the resistance value of the reference resistor 65, it can be determined whether the target storage unit has been programmed, and then the data stored in the target storage unit can be read. For example, the programmed target storage unit stores the data "1", and the unprogrammed target storage unit stores the data "0".

[0049] It can be seen that the reading circuit based on the comparator 64 in the embodiment of the present application is less affected by factors such as process errors. As long as the resistance value of the target storage unit is slightly larger or smaller than the resistance value of the reference resistor 65, the output result of the comparator 64 will change, accurately output the result, and read the information stored in the target storage unit.

[0050] Based on the above embodiments, in an embodiment of the present application, the data reading circuit 60 may further include: a second switching switch 66 and a plurality of registers 67; the controller 61 is connected to the control end of the second switching switch 66; the comparator 64 is connected to any one of the plurality of registers 67 through the second switching switch 66, and the plurality of registers 67 correspond to the plurality of storage units 63 one by one;

[0051] The second switching switch 66 is configured to connect the output end 643 of the comparator 64 to the target register among the plurality of registers 67 under the control of the controller 61, so that the target register stores the reading result.

[0052] Specifically, after obtaining the reading result corresponding to the target storage unit, it is necessary to store the reading result corresponding to the target storage unit in the corresponding target register. Here, the plurality of registers 67 corresponding to the plurality of storage units 63 one by one are used to store the reading result corresponding to each storage unit. It should be noted that the comparison result of the comparator 64 corresponds to the reading result of the target storage unit. Therefore, here, the target register corresponding to the target storage unit among the plurality of registers 67 is connected to the output end 643 of the comparator 64 through the second switching switch 66 to store the corresponding reading result.

[0053] Specifically, the second switching switch 66 connects the output end 643 of the comparator 64 to the target register among the plurality of registers 67 under the control of the controller 61, so that the target register stores the reading result. So far, the reading and storage of data have been completed, and the working mode of the chip can be adjusted by obtaining the reading result stored in the target register, thereby improving the working performance of the chip.

[0054] Based on the above embodiments, in an embodiment of the present application, the above data reading circuit 60 may further include: a third switching switch and a power supply component 68;

[0055] The controller 61 is connected to the control end of the third switching switch; the power supply component 68 is connected to any one of the plurality of storage units through the third switching switch;

[0056] The third switching switch is configured to connect the target storage unit among the plurality of storage units 63 to the power supply component 68 under the control of the controller 61, so that the power supply component stores the target data in the target storage unit;

[0057] Wherein, the third switching switch is the same as or different from the first switching switch.

[0058] Here, the write operation of data is explained. For writing data, the first switching switch 62 can be reused or an independent third switching switch can be used to connect the target storage unit to the power supply component 68, so that the power supply component 68 stores the target data in the target storage unit. In the description of this article, preferably, the writing and reading of data are completed through the first switching switch 62. Similarly, the writing of data can also be completed through the third switching switch, and the reading of data can be completed through the first switching switch 62.

[0059] The power supply component 68 is connected to any one of the multiple storage units 63 through the first switching switch 62. The first switching switch 62 is further configured to select a target storage unit from the multiple storage units 63 and connect it to the power supply component 68 under the control of the controller 61, so that the power supply component 68 stores the target data in the target storage unit, thereby completing the write operation of the data.

[0060] Based on the above embodiments, in an embodiment of the present application, the controller 61 is configured to receive a write signal, determine a target storage unit based on the write signal, control the third switching switch to connect the target storage unit to the power supply component 68, so that the power supply component 68 stores the target data in the target storage unit; the controller 61 is further configured to receive a read signal, determine a target storage unit based on the read signal, and control the first switching switch 62 to connect the target storage unit to the comparator 64, so that the comparator reads the target data stored in the target storage unit.

[0061] Specifically, the controller 61 is configured to control the first switching switch 62 to connect the target storage unit to the power supply component 68 or connect the target storage unit to the comparator 64 according to the received write signal or read signal, thereby implementing the corresponding data writing and data reading operations.

[0062] Based on the above embodiments, in an embodiment of the present application, the storage unit can be an electrically programmable fuse eFUSE unit.

[0063] eFUSE is a one-time programmable memory. It is based on the principle of electromigration and realizes the programming function on the chip by fusing the fuse. As the requirements for chip indicators are getting higher and higher. As a dedicated module for parameter setting inside the chip, the overall area has become one of the important indicators of the eFUSE module.

[0064] It can be seen that the data reading circuit provided by the embodiments of the present application repeatedly reads the data stored in multiple storage units through a comparator, simplifies the structure of the reading circuit, and reduces the area and system cost of the radio frequency front-end chip. At the same time, by reading the data stored in the storage unit through a comparator, the influence of the production process and environment on the reading result is reduced. As long as the resistance value of the storage unit is slightly greater than or less than the reference resistance, the output result of the comparator will change, and the data stored in the storage unit can be accurately read, improving the reliability of data reading.

[0065] It should be noted that theoretically, only one comparator is required in the data reading circuit proposed in the embodiments of the present application, which can effectively reduce the chip area and system cost. However, if it is necessary to improve the reading speed, M comparators can be used for reading. Here, it is assumed that it takes one cycle for a comparator to read one storage unit, and it takes N cycles for a comparator to read N storage units. For M comparators to read N storage units, a total of N / M cycles are required. In this way, a good compromise can be made between the reading speed and the chip area, improving the applicable range of the chip.

[0066] Based on the above embodiments, the present application further provides a radio frequency front-end chip 70, as Figure 7 shown. The radio frequency front-end chip 70 includes a data reading circuit 60, and the data reading circuit 60 may include: a controller 61, a first switching switch 62, multiple storage units 63, and a comparator 64;

[0067] Among them, the controller 61 is connected to the control end 621 of the first switching switch 62; the comparator 64 is connected to any one of the multiple storage units 63 through the first switching switch 62;

[0068] The first switching switch 62 is configured to connect the target storage unit among the multiple storage units 63 to the first input end 641 of the comparator 64 under the control of the controller 61;

[0069] The comparator 64 is configured to read the target data stored in the target storage unit after being connected to the target storage unit, and determine a reading result based on the target data.

[0070] Here, the comparator 64 can be connected to any one of the multiple storage units 63 through the first switching switch 62; the first switching switch 62 is configured to connect the target storage unit among the multiple storage units 63 to the first input end 641 of the comparator 64 under the control of the controller 61.

[0071] That is to say, multiple storage units 63 share one comparator 64. The first switching switch 62 is used to select the storage unit to be read and connect it to the comparator 64, and the comparator 64 is reused to read different storage units. In this way, the structure of the reading circuit can be greatly simplified, and the area and system cost of the RF front-end chip can be reduced.

[0072] Here, the comparator 64 is configured to read the target data stored in the target storage unit after being connected to the target storage unit, and determine the reading result based on the target data. After the comparator 64 is connected to the target storage unit through the first switching switch 62, it will read the target data stored in the storage unit and determine the reading result according to the target data, so as to realize the reading of the data in the storage unit.

[0073] Based on the above embodiments, in an embodiment of the present application, the data reading circuit 60 may further include: a second switching switch 66 and multiple registers 67; the controller 61 is connected to the control end of the second switching switch 66; the comparator 64 is connected to any one of the multiple registers 67 through the second switching switch 66, and the multiple registers 67 correspond to the multiple storage units 63 one by one;

[0074] The second switching switch 66 is configured to connect the output end 643 of the comparator 64 to the target register among the multiple registers 67 under the control of the controller 61, so that the target register stores the reading result.

[0075] Specifically, after obtaining the reading result corresponding to the target storage unit, it is necessary to store the reading result corresponding to the target storage unit in the corresponding target register. Here, the multiple registers 67 corresponding to the multiple storage units 63 one by one are used to store the reading result corresponding to each storage unit. It should be noted that the comparison result of the comparator 64 corresponds to the reading result of the target storage unit. Therefore, here, the target register corresponding to the target storage unit among the multiple registers 67 is connected to the output end 643 of the comparator 64 through the second switching switch 66 to store the corresponding reading result.

[0076] Specifically, the second switching switch 66 connects the output end 643 of the comparator 64 to the target register among the multiple registers 67 under the control of the controller 61, so that the target register stores the reading result. So far, the reading and storage of data have been completed, and the working mode of the chip can be adjusted by obtaining the reading result stored in the target register, thereby improving the working performance of the chip.

[0077] Based on the above embodiments, in an embodiment of the present application, the data reading circuit 60 may further include: a third switching switch and a power supply component 68;

[0078] The controller 61 is connected to the control terminal of the third switching switch; the power supply component 68 is connected to any one of the multiple storage units through the third switching switch;

[0079] The third switching switch is used to connect the target storage unit in the multiple storage units 63 to the power supply component 68 under the control of the controller 61, so that the power supply component stores the target data into the target storage unit;

[0080] Wherein, the third switching switch is the same as or different from the first switching switch.

[0081] Here, the write operation of the data is explained. The write of the data can reuse the first switching switch 62 or use an independent third switching switch to connect the target storage unit to the power supply component 68, so that the power supply component 68 stores the target data into the target storage unit. In the description of this article, preferably, the write and read of the data are completed through the first switching switch 62. Similarly, the write of the data can also be completed through the third switching switch, and the read of the data can be completed through the first switching switch 62.

[0082] The power supply component 68 is connected to any one of the multiple storage units 63 through the first switching switch 62 to select the target storage unit to be written. The first switching switch 62 is also used to connect the target storage unit in the multiple storage units 63 to the power supply component 68 under the control of the controller 61, so that the power supply component 68 stores the target data into the target storage unit, thereby completing the write operation of the data.

[0083] Based on the above embodiments, in an embodiment of the present application, the radio frequency front-end chip 70 may further include: a Mobile Industry Processor Interface (MIPI) module 71;

[0084] The MIPI module 71 is connected to the controller 61;

[0085] The MIPI module 71 is used to send a write signal to the controller 61, so that the controller 61 determines the target storage unit based on the write signal, and controls the third switching switch to connect the target storage unit to the power supply component 68, and stores the target data into the target storage unit through the power supply component 68;

[0086] The MIPI module 71 is also used to send a read signal to the controller 61, so that the controller 61 determines the target storage unit based on the read signal, controls the first switching switch 62, connects the target storage unit to the comparator 64, and reads the target data stored in the target storage unit through the comparator 64.

[0087] Based on the above embodiments, the MIPI module 71 is further configured to receive a clock signal and send a write signal or a read signal to the controller according to the clock signal; the controller and / or the target register are further configured to receive the clock signal and control the controller and / or the target register to enter the working state according to the clock signal.

[0088] Wherein, when the clock signal is at the rising edge or the falling edge, the MIPI module 71 sends a write signal and / or a read signal to the controller 61 according to the clock signal. After determining to perform a write operation or a read operation, the controller 61 and / or the target register receive the clock signal and are in the working state. At this time, the controller 61 controls the first switch 62 to connect the target storage unit to the comparator 64, so that the comparator 64 reads the target data stored in the target storage unit; and the controller controls the second switch 66 to connect the output terminal 643 of the comparator 64 to the target register, so that the target register stores the read result.

[0089] Here, since both the controller 61 and the target register are sequential circuits, they need to be triggered to enter the working state by the clock signal. The radio frequency front-end chip 70 proposed in this application introduces the synchronous clock (SCLK) signal input by the host computer into the radio frequency front-end chip 70 through the MIPI interface built in the MIPI module 71, the controller 61 and the target register, without integrating a clock generation module inside the chip to generate a clock signal to trigger the controller and the target register to enter the working state, further saving the area of the chip and reducing the system cost.

[0090] Based on the above embodiments, in an embodiment of the present application, the radio frequency front-end chip 70 may further include: a radio frequency module 72;

[0091] The radio frequency module 72 is connected to a plurality of registers 73;

[0092] The radio frequency module 72 is configured to adjust the working mode of the radio frequency front-end chip 70 according to the read result.

[0093] Specifically, after the read result is stored in the plurality of memories 73, the radio frequency module 72 will, under the control of the internal digital circuit, adjust the bias voltage, bias current and frequency of the radio frequency module 72 according to the read result, so as to adjust the output of the radio frequency front-end chip 70, thereby improving the working performance of the chip.

[0094] Here, the write operation process of the radio frequency front-end chip 70 is described.

[0095] When the radio frequency front-end chip 70 performs a write operation, the clock signal sent through the SCLK port triggers the controller 61 to start working. The controller 61 connects the eFUSE storage unit to be programmed to the power supply component 68 through the first switching switch 62 for programming. The controller 61 adjusts the programming time length by counting the clock signal sent through the SCLK port. In this way, the programming effect of the eFUSE can be ensured, and the accuracy of data storage can be guaranteed.

[0096] Here, refer to Figure 8 and Figure 9 to describe the read operation process of the radio frequency front-end chip 70. Figure 8 It is a schematic flowchart of the read operation of a radio frequency front-end chip provided by an embodiment of the present application. Figure 9 It is a timing diagram of the read operation of a radio frequency front-end chip provided by an embodiment of the present application.

[0097] The radio frequency front-end chip 70 will be reset every time it is powered on and started. All registers in the reset radio frequency front-end chip 70 are cleared. When performing a read operation, the controller 61 needs to be triggered by a clock signal to start working. Before the radio frequency front-end chip 70 works, the host computer sends at least one instruction to the MIPI module 71 through the MIPI interface to configure the radio frequency front-end chip 70. The instruction contains information such as identification number, address, and data, and it takes several clock cycles to complete the sending. When the MIPI module 71 receives the first instruction, it will introduce the clock signal into the radio frequency front-end chip 70 through the MIPI interface. The controller 61 reads the data stored in the eFUSE storage unit one by one under the trigger of the clock signal and stores the read result in the corresponding register.

[0098] It should be noted that before the end of the first instruction, the reading circuit has already completed the update of all registers, without additional clock cycles. Subsequently, the radio frequency module 72 will adjust the bias voltage, bias current, and frequency of the radio frequency module 72 under the control of the internal digital circuit according to the read result, so as to adjust the output of the radio frequency front-end chip 70, thereby improving the working performance of the radio frequency front-end chip 70 and not affecting the response speed of the radio frequency front-end chip 70. Every time the radio frequency front-end chip 70 is powered off and then powered on again, a read operation will be performed again to update the data stored in the eFUSE storage unit to be read into the corresponding register.

[0099] Before the end of the first instruction received by the reading circuit proposed in this application after the radio frequency front-end chip 70 is powered on, the data stored in the storage unit can be updated to the register without additional clock cycles, which can ensure that the radio frequency front-end chip is configured before starting to work and will not affect the response speed of the radio frequency front-end chip. If it is necessary to further improve the reading speed, M comparators can be used to read the eFUSE storage unit, and a total of N / M clock cycles are required to complete the reading, ensuring that the data stored in all storage units is updated to the corresponding registers before the end of an instruction, and a good trade-off can be made between the reading rate and the chip area.

[0100] It should be noted that when using the method of multiplexing comparators to reduce the chip area and using one comparator to read multiple eFUSE storage units, the controller needs to be controlled by a clock signal. At this time, if the traditional method is used to integrate a clock generation circuit inside the chip to implement it, due to the relatively complex control logic of the clock, it will have an impact on the power consumption and radio frequency performance of the radio frequency front-end chip. Therefore, in the embodiment of this application, the synchronous clock signal sent by the host computer is input into the radio frequency front-end chip 70 through the MIPI interface for use by the MIPI module 71, the controller 61, and the target register, without the need to integrate a clock generation module inside the chip to generate a clock signal to trigger the controller and the target register to enter the working state, further saving the chip area and reducing the system cost.

[0101] It can be seen that the radio frequency front-end chip provided by the embodiment of this application simplifies the structure of the reading circuit by repeatedly reading the data stored in multiple storage units with a single comparator, reducing the area of the radio frequency front-end chip and the system cost. At the same time, by using the comparator to read the data stored in the storage unit, the influence of the production process and the environment on the reading result is reduced. As long as the resistance value of the storage unit is slightly greater or less than the reference resistance, the output result of the comparator will change, and the data stored in the storage unit can be accurately read, improving the reliability of the storage unit reading. Using the clock signal provided by the inherent MIPI interface in the radio frequency front-end chip to trigger the data reading circuit, without the need to integrate a clock generation module internally, further reduces the area and cost of the radio frequency front-end chip.

[0102] It can be understood that in this embodiment, the "unit" can be a part of the circuit, a part of the processor, a part of the program or software, etc. Of course, it can also be a module or non-modular. Moreover, the components in this embodiment can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software function module.

[0103] The specific implementation process of the embodiments of the present application will be described below:

[0104] In order to adjust the working mode of the RF front-end chip and thus improve the working performance of the chip, in the test stage of the chip, the embodiments of the present application store the data representing different working modes in the eFUSE. By writing different data into the eFUSE and reading the corresponding data during use, different functions are executed to improve the working performance of the chip. During use, the MIPI module receives the instructions and clock signals sent by the host computer to trigger the controller to execute the read operation. When the controller executes the read operation, it controls the first switch to select the eFUSE to be read, connects the eFUSE to be read to the comparator, reads the data stored in the eFUSE through the comparator to obtain the read result; then controls the second switch to connect the register to the comparator through the controller to store the read result, and the RF module obtains the read result from the register to adjust the output of the RF front-end chip, thereby improving the working performance of the chip.

[0105] It can be seen that the data reading circuit provided by the embodiments of the present application simplifies the structure of the reading circuit and reduces the area and system cost of the RF front-end chip by repeatedly reading the data stored in multiple storage units through the comparator. Reading the data stored in the storage unit through the comparator reduces the influence of the production process and environment on the read result. As long as the resistance value of the storage unit is slightly greater than or less than the reference resistance, the output result of the comparator will change, and the data stored in the storage unit can be accurately read, improving the reliability of data reading.

[0106] At the same time, through the above read operation program flow, the chip will be reset each time it is powered on and started, and all registers will be cleared. When the read operation is executed, the controller enters the working state under the trigger of the clock signal. The controller reads the data stored in the eFUSE storage unit one by one under the trigger of the clock signal and stores the read result in the corresponding register. Before the end of the first instruction, the reading circuit has completed the update of all registers without additional clock cycles. Subsequently, the RF module will adjust the bias voltage, bias current and frequency of the RF module according to the read result under the control of the internal digital circuit, so as to adjust the output of the RF front-end chip, thereby improving the working performance of the RF front-end chip without affecting the response speed of the RF front-end chip.

[0107] If it is necessary to further improve the reading speed, M comparators can be used to read the eFUSE storage unit, and a total of N / M clock cycles are required to complete the reading, ensuring that the data stored in all storage units is updated to the corresponding registers before the end of an instruction, and a good compromise can be made between the reading rate and the chip area.

[0108] It can be understood that the embodiments described herein can be implemented by hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions of the present application, or a combination thereof.

[0109] For software implementation, the techniques herein can be implemented by modules (e.g., procedures, functions, etc.) that execute the functions herein. The software code can be stored in a memory and executed by a processor. The memory can be implemented within the processor or external to the processor.

[0110] The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A data reading circuit, characterized in that, Comprising: A controller, a first switching switch, a plurality of storage units, a comparator, a second switching switch, and a plurality of registers; Wherein, the controller is connected to the control end of the first switching switch; the comparator is connected to any one of the plurality of storage units through the first switching switch; The first switching switch is configured to connect the target storage unit among the plurality of storage units to the first input end of the comparator under the control of the controller; The comparator is configured to read the target data stored in the target storage unit after being connected to the target storage unit, and determine a reading result based on the target data; The controller is connected to the control end of the second switching switch; the comparator is connected to any one of the plurality of registers through the second switching switch, and the plurality of registers correspond to the plurality of storage units one by one; The second switching switch is configured to connect the output end of the comparator to the target register among the plurality of registers under the control of the controller, so that the target register stores the reading result.

2. The data reading circuit according to claim 1, wherein Further comprising: A reference resistor, the reference resistor is connected to the second input end of the comparator; The comparator is specifically configured to read the voltage value corresponding to the target storage unit after being connected to the target storage unit to obtain the target data; and compare the target data with the reference voltage value of the reference resistor. If the target data is greater than the reference voltage value, determine that the reading result is a first value; if the target data is less than or equal to the reference voltage value, determine that the reading result is a second value.

3. The data reading circuit according to claim 1 or 2, characterized in that Further comprising: A third switching switch and a power supply component; The controller is connected to the control end of the third switching switch; The power supply component is connected to any one of the plurality of storage units through the third switching switch; The third switching switch is configured to connect the target storage unit among the plurality of storage units to the power supply component under the control of the controller, so that the power supply component stores the target data into the target storage unit; Wherein, the third switching switch is the same as or different from the first switching switch.

4. The data reading circuit according to claim 3, wherein The controller is configured to receive a write signal, determine the target storage unit based on the write signal, and control the third switching switch to connect the target storage unit to the power supply component, so that the power supply component stores the target data into the target storage unit; The controller is further configured to receive a read signal, determine the target storage unit based on the read signal, and control the first switching switch to connect the target storage unit to the comparator, so that the comparator reads the target data stored in the target storage unit.

5. The data reading circuit according to claim 1 or 2, characterized in that The storage unit is an electrically programmable fuse eFUSE unit.

6. A radio frequency front-end chip, characterized in that, Comprising a data reading circuit, wherein the data reading circuit includes: a controller, a first switching switch, a plurality of storage units, a comparator, a second switching switch, and a plurality of registers; Among them, the controller is connected to the control end of the first switching switch; the comparator is connected to any one of the multiple storage units through the first switching switch; The first switching switch is configured to connect the target storage unit among the multiple storage units to the first input end of the comparator under the control of the controller; The comparator is configured to read the target data stored in the target storage unit after being connected to the target storage unit, and determine a read result based on the target data; the controller is connected to the control end of the second switching switch; the comparator is connected to any one of the multiple registers through the second switching switch, and the multiple registers correspond to the multiple storage units one by one; The second switching switch is configured to connect the output end of the comparator to the target register among the multiple registers under the control of the controller, so that the target register stores the read result.

7. The radio frequency front-end chip according to claim 6, wherein The data reading circuit further includes: a third switching switch and a power supply component; The controller is connected to the control end of the third switching switch; the power supply component is connected to any one of the multiple storage units through the third switching switch; The third switching switch is configured to connect the target storage unit among the multiple storage units to the power supply component under the control of the controller, so that the power supply component stores the target data into the target storage unit; Among them, the third switching switch is the same as or different from the first switching switch.

8. The radio frequency front-end chip according to claim 7, wherein, The radio frequency front-end chip further includes: a Mobile Industry Processor Interface (MIPI) module; The MIPI module is connected to the controller; The MIPI module is configured to send a write signal to the controller, so that the controller determines the target storage unit based on the write signal, controls the third switching switch to connect the target storage unit to the power supply component, and stores the target data into the target storage unit through the power supply component; The MIPI module is further configured to send a read signal to the controller, so that the controller determines the target storage unit based on the read signal, controls the first switching switch to connect the target storage unit to the comparator, and reads the target data stored in the target storage unit through the comparator.

9. The radio frequency front-end chip according to claim 8, characterized in that The MIPI module is further configured to receive a clock signal, and send the write signal or the read signal to the controller according to the clock signal; The controller and / or the target register are further configured to receive the clock signal, and control the controller and / or the target register to enter a working state according to the clock signal; In the working state, the controller controls the first switching switch to connect the target storage unit to the comparator, so that the comparator reads the target data stored in the target storage unit; And the controller controls the second switching switch to connect the output end of the comparator to the target register, so that the target register stores the read result.

10. The radio frequency front-end chip according to claim 9, wherein The radio frequency front-end chip further includes: a radio frequency module; The radio frequency module is connected to the multiple registers; The radio frequency module is configured to adjust the working mode of the radio frequency front-end chip according to the reading result.

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