Compound semiconductor substrate

Abstract

A compound semiconductor substrate capable of reducing threading dislocations in a nitride semiconductor layer containing Al (aluminum) is provided. A compound semiconductor substrate comprises: a Si (silicon) substrate; a first Al nitride semiconductor layer formed on the Si substrate and being an inclined layer in which the Al concentration decreases along the thickness direction as it moves away from the Si substrate; a GaN (gallium nitride) layer formed on the first Al nitride semiconductor layer and having an average Al concentration lower than the average Al concentration of the first Al nitride semiconductor layer; and a second Al nitride semiconductor layer formed on the GaN layer and having an average Al concentration higher than the average Al concentration of the GaN layer. The threading dislocation density at any position in the thickness direction in the second Al nitride semiconductor layer is lower than the threading dislocation density at any position in the thickness direction in the first Al nitride semiconductor layer.

Description

Technical Field

[0001] The present invention relates to a compound semiconductor substrate, and more particularly to a compound semiconductor substrate capable of reducing threading dislocations in a nitride semiconductor layer containing Al (aluminum). Background Art

[0002] GaN (gallium nitride) is known as a wide bandgap semiconductor material with a larger bandgap and higher dielectric breakdown field strength than Si (silicon). GaN is expected to be applicable to low-loss power devices in the new era because it has higher dielectric breakdown resistance than other wide bandgap semiconductor materials.

[0003] When a Si substrate is used as an initial substrate (base substrate) of a semiconductor device using GaN, the large difference in lattice constant and thermal expansion coefficient between GaN and Si easily causes the substrate to warp or cracks to form in the GaN layer. Therefore, a technology has been proposed in which a compound semiconductor substrate having a SiC (silicon carbide) layer or the like formed on a Si substrate is used as a starting substrate, thereby alleviating the difference in lattice constant and thermal expansion coefficient between GaN and Si through the SiC layer or the like.

[0004] As such a technology, a technology for suppressing the warping and cracking of a substrate is disclosed in the following Patent Document 1 and the like. The following Patent Document 1 discloses a compound semiconductor substrate comprising: a SiC layer, an AlN (aluminum nitride) buffer layer formed on the SiC layer, an Al-containing nitride semiconductor layer formed on the AlN buffer layer, a first GaN layer formed on the nitride semiconductor layer, a first AlN intermediate layer in contact with the first GaN layer and formed on the first GaN layer, and a second GaN layer in contact with the first AlN intermediate layer and formed on the first AlN intermediate layer.

[0005] A semiconductor substrate having an existing GaN layer is also disclosed in the following patent document 2. The following patent document 2 discloses the following semiconductor structure: having: a substrate made of SiC, a nucleation layer made of AlN formed on the substrate, an inclined layer made of AlGaN (aluminum gallium nitride) formed on the nucleation layer, and a nitride layer made of GaN formed on the inclined layer.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: International Publication No. 2017 / 069087

[0009] Patent Document 2: Japanese Patent Application No. 2010-521065 Summary of the invention

[0010] Problems to be solved by the invention

[0011] In semiconductor substrates with existing GaN layers, Al-containing nitride semiconductor layers (such as AlGaN) are often used as buffer layers. However, the existing Al-containing nitride semiconductor layers have a problem of many internal threading dislocations. In addition, when a GaN layer is formed on the Al-containing nitride semiconductor layer, threading dislocations are also inherited in the GaN layer, and threading dislocations in the GaN layer also increase.

[0012] The present invention is made to solve the above-mentioned problems, and an object of the present invention is to provide a compound semiconductor substrate capable of reducing threading dislocations in a nitride semiconductor layer containing Al.

[0013] Means for solving problems

[0014] A compound semiconductor substrate in one embodiment of the present invention comprises: a Si substrate; a first nitride semiconductor layer, which is an Al-containing first nitride semiconductor layer formed on the Si substrate and is an inclined layer in which the Al concentration decreases along the thickness direction as it moves away from the Si substrate; a second nitride semiconductor layer, which is a second nitride semiconductor layer formed on the first nitride semiconductor layer and has an average Al concentration lower than the average Al concentration of the first nitride semiconductor layer; and a third nitride semiconductor layer, which is an Al-containing third nitride semiconductor layer formed on the second nitride semiconductor layer and has an average Al concentration higher than the average Al concentration of the second nitride semiconductor layer, and a threading dislocation density at any position in the thickness direction in the third nitride semiconductor layer is lower than a threading dislocation density at any position in the thickness direction in the first nitride semiconductor layer.

[0015] In the above compound semiconductor substrate, it is preferred that the second nitride semiconductor layer is made of GaN and has a thickness of 3 nm to 100 nm.

[0016] In the above compound semiconductor substrate, preferably, the first nitride semiconductor layer includes: a lower layer; and an upper layer formed on the lower layer and having an average Al concentration lower than an average Al concentration of the lower layer.

[0017] In the above-mentioned compound semiconductor substrate, it is preferred that when the threading dislocation density at any position in the thickness direction within the first nitride semiconductor layer is taken as the threading dislocation density DA and the threading dislocation density at any position in the thickness direction within the third nitride semiconductor layer is taken as the threading dislocation density DB, the ratio of the threading dislocation density DB to the threading dislocation density DA (DB / DA) is greater than 0 and is less than 0.6.

[0018] In the compound semiconductor substrate, preferably, a ratio ( W2 / W1 ) of a thickness W2 of the second nitride semiconductor layer to a thickness W1 of the first nitride semiconductor layer is greater than or equal to 0.007 and less than or equal to 0.26.

[0019] The above-mentioned compound semiconductor substrate preferably further includes a GaN layer formed on the third nitride semiconductor layer.

[0020] In the above-mentioned compound semiconductor substrate, it is preferred that when the threading dislocation density at any position in the thickness direction within the first nitride semiconductor layer is taken as the threading dislocation density DA and the threading dislocation density at any position in the thickness direction within the GaN layer is taken as the threading dislocation density DC, the ratio of the threading dislocation density DC to the threading dislocation density DA (DC / DA) is greater than 0 and is less than 0.3.

[0021] In the above-mentioned compound semiconductor substrate, it is preferred to further include an upper composite layer, the upper composite layer includes a plurality of upper GaN layers stacked in the up and down directions, and an Al-containing upper nitride semiconductor layer formed between each of the plurality of upper GaN layers, the GaN layer is the lowest upper GaN layer among the plurality of upper GaN layers, and the ratio (W4 / W3) of the thickness W4 of the upper nitride semiconductor layer to the thickness W3 of each of the plurality of upper GaN layers is greater than 0.0015 and less than 0.025.

[0022] The compound semiconductor substrate preferably further includes a SiC layer formed on the Si substrate and a buffer layer made of AlN formed on the SiC layer, and the first nitride semiconductor layer is formed on the buffer layer.

[0023] Effects of the Invention

[0024] According to the present invention, it is possible to provide a compound semiconductor substrate capable of reducing threading dislocations in a nitride semiconductor layer containing Al. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a cross-sectional view showing the structure of the compound semiconductor substrate CS1 in the first embodiment of the present invention.

[0026] Figure 2 It is a diagram showing the Al concentration distribution inside the composite layer 4 in the first embodiment of the present invention.

[0027] Figure 3 It is a diagram schematically showing the two-dimensional growth of GaN constituting the GaN layer 42 a.

[0028] Figure 4 It is a cross-sectional view showing the structure of a compound semiconductor substrate CS2 in the second embodiment of the present invention.

[0029] Figure 5 It is a cross-sectional view showing the manufacturing conditions of the compound semiconductor substrate CS1 in the first embodiment of the present invention and the measurement positions P1, P2, and P3 of the number of threading dislocations.

[0030] Figure 6 It is a cross-sectional view showing the manufacturing conditions of the compound semiconductor substrate CS100 in the first embodiment of the present invention and the measurement positions P1, P2, and P3 of the number of threading dislocations.

[0031] Figure 7 It is a graph showing the measurement results of the threading dislocation density in the first example of the present invention.

[0032] Figure 8 It is a diagram showing a microscope photograph of the surface of the outermost layer (Al nitride semiconductor layer 10) of the compound semiconductor substrate in the first example of the present invention and the measurement results of the etch pit density.

[0033] Fig. 9 It is a diagram showing the measurement results of the warpage amount of each of the samples C1, C2, and C3 in the second example of the present invention.

[0034] Fig.10 This is a graph showing the relationship between the thickness of the GaN layer 42 b and the warpage amount, which is obtained from the measurement results of the warpage amounts of the samples C1, C2, and C3 in the second example of the present invention.

[0035] Fig.11 It is a diagram showing the measurement results of the warpage amount of each of the samples D1, D2, and D3 in the second example of the present invention.

[0036] Fig.12 This is a graph showing the relationship between the thickness of the Al nitride semiconductor layers 52a and 52b and the warpage amount obtained from the measurement results of the warpage amounts of the samples D1, D2, and D3 in the second example of the present invention. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present invention will be described based on the drawings.

[0038] [First embodiment]

[0039] Figure 1 It is a cross-sectional view showing the structure of the compound semiconductor substrate CS1 in the first embodiment of the present invention.

[0040] Reference Figure 1The compound semiconductor substrate CS1 in this embodiment includes a HEMT (High Electron Mobility Transistor). The compound semiconductor substrate CS1 includes: a Si substrate 1 (an example of a Si substrate), a SiC layer 2 (an example of a SiC layer), an AlN buffer layer 3 (an example of a buffer layer), a composite layer 4, a composite layer 5 (an example of an upper composite layer), a GaN layer 7, and an Al nitride semiconductor layer 10.

[0041] The Si substrate 1 is made of, for example, p + The Si substrate 1 is made of n-type Si. The (111) surface of the Si substrate 1 is exposed. It should be noted that the Si substrate 1 can have an n-type conductivity, or can be semi-insulating. The (100) surface and the (110) surface can be exposed on the surface of the Si substrate 1. The Si substrate 1 has, for example, a diameter of 6 inches and a thickness of 1000 μm.

[0042] The SiC layer 2 is in contact with the Si substrate 1 and is formed on the Si substrate 1. The SiC layer 2 is formed of 3C-SiC, 4H-SiC, or 6H-SiC, etc. In particular, when the SiC layer 2 is epitaxially grown on the Si substrate 1, the SiC layer 2 is generally formed of 3C-SiC.

[0043] The SiC layer 2 can be formed as follows: on a base layer formed of SiC obtained by carbonizing the surface of the Si substrate 1, SiC is homoepitaxially grown using an MBE (Molecular Beam Epitaxy) method, a CVD (Chemical Vapor Deposition) method, or an LPE (Liquid Phase Epitaxy) method. The SiC layer 2 can also be formed by carbonizing the surface of the Si substrate 1 alone. In addition, the SiC layer 2 can also be formed by heteroepitaxially growing on the surface of the Si substrate 1 (or sandwiching a buffer layer). The SiC layer 2 is, for example, doped with N (nitrogen) and has an n-type conductivity. The SiC layer 2 has a thickness of, for example, more than 0.1 μm and less than 3.5 μm. It should be noted that the SiC layer 2 can have a p-type conductivity, or can also be semi-insulating.

[0044] It should be noted that a layer made of any material can be used as the base layer of the AlN buffer layer 3. As an example, the SiC layer 2 may not be formed on the Si substrate 1, but the AlN buffer layer 3 may be formed directly on the Si substrate 1. In this case, the base layer of the AlN buffer layer 3 becomes the Si substrate 1. However, by forming the SiC layer 2 between the Si substrate 1 and the AlN buffer layer 3, the SiC layer 2 can reliably suppress the melt-back etching (the phenomenon that the Ga diffusion in the GaN layer reacts with the Si in the Si substrate 1 and the Si substrate 1 is destroyed).

[0045] The AlN buffer layer 3 is in contact with the SiC layer 2 and is formed on the SiC layer 2. The AlN buffer layer 3 functions as a buffer layer that mitigates the difference in lattice constant between the SiC layer 2 and the Al nitride semiconductor layer constituting the composite layer 4. The AlN buffer layer 3 is formed, for example, using the MOCVD (Metal Organic Chemical Vapor Deposition) method. The growth temperature of the AlN buffer layer 3 is, for example, above 1000°C and below the melting point of Si. At this time, as an Al source gas, for example, TMA (Tri Methyl Aluminium), TEA (Tri Ethyl Aluminium), etc. can be used. As an N source gas, for example, NH3 (ammonia) can be used. The AlN buffer layer 3 has a thickness of, for example, more than 100nm and less than 1000nm.

[0046] The composite layer 4 is in contact with the AlN buffer layer 3 and is formed on the AlN buffer layer 3. The composite layer 4 includes: Figure 1 In other words, the composite layer 4 has a structure in which the Al nitride semiconductor layer and the GaN layer are stacked one or more times, and the uppermost layer and the lowermost layer of the composite layer 4 are both Al nitride semiconductor layers.

[0047] The number of Al nitride semiconductor layers constituting the composite layer 4 may be 2 or more layers, and preferably 9 or less layers. The number of GaN layers constituting the composite layer 4 may be 1 or more layers, and preferably 8 or less layers. The composite layer 4 of this embodiment includes two layers of Al nitride semiconductor layers 41a (an example of the first nitride semiconductor layer) and 41b (an example of the third nitride semiconductor layer) as Al nitride semiconductor layers, and one layer of GaN layer 42a (an example of the second nitride semiconductor layer) as GaN layer. The Al nitride semiconductor layer 41a is formed at the position closest to the Si substrate 1 among the two layers of Al nitride semiconductor layers 41a and 41b, and is in contact with the AlN buffer layer 3. The Al nitride semiconductor layer 41b is formed at the position farthest from the Si substrate 1 among the two layers of Al nitride semiconductor layers 41a and 41b. The GaN layer 42a is formed between the Al nitride semiconductor layer 41a and the Al nitride semiconductor layer 41b. In other words, the GaN layer 42 a is formed on the Al nitride semiconductor layer 41 a , and the Al nitride semiconductor layer 41 b is formed on the GaN layer 42 a .

[0048] Each of the Al nitride semiconductor layers constituting the composite layer 4 is formed of a nitride semiconductor containing Al, preferably AlGaN. x Ga 1-x In this case, by making the composition ratio x of Al greater than 0.5 and thus making the composition ratio of Ga less than 0.5, the warpage control effect of the composite layer 4 can be increased. In addition, each of the Al nitride semiconductor layers constituting the composite layer 4 can also be made of Al x In y Ga 1-x-y The Al nitride semiconductor layer constituting the composite layer 4 functions as a buffer layer for mitigating the difference in lattice constant between the AlN buffer layer 3 and the GaN layer in the composite layer 5. The total film thickness of the Al nitride semiconductor layer constituting the composite layer 4 is, for example, not less than 100 nm and not more than 3 μm, preferably not less than 900 nm and not more than 2 μm.

[0049] The Al nitride semiconductor layer constituting the composite layer 4 is formed by, for example, the MOCVD method. At this time, as the Ga source gas, for example, TMG (Tri Methyl Gallium), TEG (Tri Ethyl Gallium), etc. can be used. As the Al source gas, for example, TMA, TEA, etc. can be used. As the N source gas, for example, NH3, etc. can be used.

[0050] The GaN layer constituting the recombination layer 4 plays a role in causing the compound semiconductor substrate CS1 to warp in a concave shape as described later.

[0051] The GaN layer constituting the composite layer 4 is formed by, for example, MOCVD. At this time, as the Ga source gas, for example, TMG, TEG, etc. can be used, and as the N source gas, for example, NH 3, etc. can be used.

[0052] The GaN layer constituting the composite layer 4 has a thickness of, for example, 3 nm to 100 nm, preferably 3 nm to 50 nm. In the case where there are multiple GaN layers constituting the composite layer 4, each of the GaN layers constituting the composite layer 4 may have the same thickness, or may have different thicknesses from each other.

[0053] When the thickness of the Al nitride semiconductor layer 41 a is defined as thickness W1 and the thickness of the GaN layer 42 a is defined as thickness W2 , the ratio of thickness W2 to thickness W1 ( W2 / W1 ) is preferably 0.007 or more and 0.26 or less.

[0054] The composite layer 5 is in contact with the composite layer 4 (Al nitride semiconductor layer 41b) and is formed on the composite layer 4 (Al nitride semiconductor layer 41b). The composite layer 5 includes: Figure 1 In other words, the composite layer 5 has a structure in which the GaN layer and the Al nitride semiconductor layer are alternately stacked one or more times, and the uppermost layer and the lowermost layer of the composite layer 5 are both GaN layers.

[0055] The number of GaN layers constituting the composite layer 5 may be 2 or more layers, and preferably 9 or less layers. The number of Al nitride semiconductor layers constituting the composite layer 5 may also be 1 or more layers, and preferably 8 or less layers. The composite layer 5 of this embodiment includes 3 layers of GaN layers 51a, 51b, and 51c (an example of an upper GaN layer and a GaN layer) as GaN layers, and includes 2 layers of Al nitride semiconductor layers 52a and 52b (an example of an upper nitride semiconductor layer) as Al nitride semiconductor layers. The GaN layer 51a is formed at the position closest to the Si substrate 1 among the 3 layers of GaN layers 51a, 51b, and 51c, and is in contact with the composite layer 4 (Al nitride semiconductor layer 41b). The GaN layer 51b is formed at the second position closest to the Si substrate 1 among the 3 layers of GaN layers 51a, 51b, and 51c. The GaN layer 51c is formed at the position farthest from the Si substrate 1 among the three GaN layers 51a, 51b, and 51c. The Al nitride semiconductor layer 52a is formed between the GaN layer 51a and the GaN layer 51b. The Al nitride semiconductor layer 52b is formed between the GaN layer 51b and the GaN layer 51c.

[0056] It is preferred that each of the GaN layers constituting the composite layer 5 is doped with C (carbon). C plays a role in improving the insulating properties of the GaN layer. It is preferred that the GaN layer doped with C has a carbon content of 1×10 18 Pieces / cm 3 Above and 1×10 21 Pieces / cm 3 The average carbon atom concentration is preferably 3×10 18 Pieces / cm 3 Above and 2×10 19 Pieces / cm 3 The following average carbon concentration: When a plurality of C-doped GaN layers exist, these GaN layers may have the same average carbon atom concentration or may have average carbon atom concentrations different from each other.

[0057] When C is doped into the GaN layer constituting the composite layer 5, GaN growth conditions are adopted such that C contained in TMG is incorporated into the GaN layer. Specific methods for doping C into the GaN layer include a method of lowering the growth temperature of GaN, a method of lowering the growth pressure of GaN, or a method of increasing the molar flow ratio of TMG to NH3.

[0058] In addition, each of the GaN layers constituting the composite layer 5 has a thickness of, for example, 550 nm or more and 3000 nm or less, preferably 800 nm or more and 2500 nm or less. Each of the GaN layers constituting the composite layer 5 may have the same thickness, or may have mutually different thicknesses. The GaN layer constituting the composite layer 5 is formed in the same manner as the GaN layer constituting the composite layer 4.

[0059] The Al nitride semiconductor layer constituting the composite layer 5 plays a role in causing the compound semiconductor substrate CS1 to warp in a convex shape as described later.

[0060] The Al nitride semiconductor layer constituting the composite layer 5 is formed of a nitride semiconductor containing Al, preferably AlN. The Al nitride semiconductor layer constituting the composite layer 5 is formed of, for example, Al x Ga 1-x In this case, by making the composition ratio x of Al greater than 0.5 and thus making the composition ratio of Ga less than 0.5, the warpage control effect of the composite layer 4 can be increased. In addition, the Al nitride semiconductor layer constituting the composite layer 5 can also be made of Al x In y Ga 1-x-y The material represented by N (0<x≦1, 0≦y<1) is formed.

[0061] The Al nitride semiconductor layer constituting the composite layer 5 has a thickness of, for example, 3 nm or more and 50 nm or less, preferably 20 nm or less. In the case where there are multiple Al nitride semiconductor layers constituting the composite layer 5, each of the Al nitride semiconductor layers constituting the composite layer 5 may have the same thickness, or may have mutually different thicknesses. In addition, the Al composition ratio of each of the Al nitride semiconductor layers constituting the composite layer 5 is arbitrary. The Al nitride semiconductor layer constituting the composite layer 5 is formed by the same method as the Al nitride semiconductor layer constituting the composite layer 4.

[0062] When the thickness of each GaN layer constituting the composite layer 5 is taken as thickness W3 and the thickness of the Al nitride semiconductor layer constituting the composite layer 5 is taken as thickness W4, the ratio of thickness W4 to thickness W3 (W4 / W3) is preferably greater than or equal to 0.0015 and less than or equal to 0.025.

[0063] The GaN layer 7 is in contact with the composite layer 5 and is formed on the composite layer 5. The GaN layer 7 is undoped and semi-insulating. The GaN layer 7 becomes the electron transport layer of the HEMT. The GaN layer 7 has a thickness of, for example, 100 nm or more and 1500 nm or less. The GaN layer 7 is formed in the same manner as the GaN layer constituting the composite layer 4.

[0064] The Al nitride semiconductor layer 10 is in contact with the GaN layer 7 and is formed on the GaN layer 7. The Al nitride semiconductor layer 10 is formed of a nitride semiconductor containing Al, for example, Al x Ga 1-x N (0<x≦1) is formed. In addition, the Al nitride semiconductor layer 10 may also be made of Al x In y Ga 1-x-y The Al nitride semiconductor layer 10 is formed of a material represented by N (0<x≦1, 0≦y<1). The Al nitride semiconductor layer 10 serves as a barrier layer for the HEMT. The Al nitride semiconductor layer 10 has a thickness of, for example, 10 nm to 50 nm. The Al nitride semiconductor layer 10 is formed in the same manner as the GaN layer constituting the composite layer 4.

[0065] Figure 2 It is a diagram showing the Al concentration distribution inside the composite layer 4 in the first embodiment of the present invention.

[0066] Reference Figure 2 The Al nitride semiconductor layer 41a has an Al concentration that increases with the thickness direction away from the Si substrate 1 (towards Figure 1 In the present embodiment, the Al nitride semiconductor layer 41a includes: a lower layer 411 (an example of a lower layer), and an upper layer 412 (an example of an upper layer) formed on the lower layer 411. The lower layer 411 and the upper layer 412 each have a uniform Al concentration distribution in the thickness direction. The average Al concentration of the lower layer 411 is concentration S1a, and the average Al concentration of the upper layer 412 is concentration S1b. The average Al concentration (concentration S1b) of the upper layer 412 is lower than the average Al concentration (concentration S1a) of the lower layer 411. The average Al concentration of the Al nitride semiconductor layer 41a is concentration S1.

[0067] It should be noted that the Al nitride semiconductor layer 41 a may be a gradient layer in which the Al concentration decreases at a certain ratio as it moves away from the Si substrate 1 in the thickness direction.

[0068] The GaN layer 42a has an average Al concentration lower than the average Al concentration (concentration S1) of the Al nitride semiconductor layer 41a. The average Al concentration of the GaN layer 42a can of course be 0 (%). It should be noted that the GaN layer in the composite layer 4 can also be replaced by an Al nitride semiconductor layer having an average Al concentration greater than 0 and lower than the concentration S1.

[0069] The Al nitride semiconductor layer 41b has an average Al concentration higher than the average Al concentration of the GaN layer 42a. The average Al concentration of the Al nitride semiconductor layer 41b is a concentration S2. The concentration S2 may be higher or lower than the concentration S1.

[0070] The Al concentration of each layer constituting the composite layer 4 can be adjusted by the concentration ratio of the Al source gas in the raw material gas used when forming the film by MOCDV, the film forming temperature, etc. In addition, the Al concentration of each layer constituting the composite layer 4 is measured by a method such as SIMS (Secondary Ion Mass Spectrometry). In addition, the thickness of each layer constituting the compound semiconductor substrate is measured by observing the cross section of the compound semiconductor substrate using a TEM (Transmission Electron Microscope).

[0071] Next, the effects of this embodiment will be described.

[0072] Figure 3 It is a diagram schematically showing the two-dimensional growth of GaN constituting the GaN layer 42 a.

[0073] Reference Figure 3 The inventors of the present application have found that by forming a GaN layer 42a (a nitride semiconductor layer having an average Al concentration lower than the average Al concentration of the Al nitride semiconductor layer 41a) on the Al nitride semiconductor layer 41a as a tilted layer at a film formation temperature lower than the film formation temperature of the Al nitride semiconductor layer 41a, the two-dimensional growth of GaN is promoted ( Figure 3 As a result, the threading dislocations TD existing in the lower layer are covered by the GaN layer 42a, and the threading dislocations of the Al nitride semiconductor layer 41b, which is the upper layer of the GaN layer 42a, can be reduced. Furthermore, the threading dislocations of the GaN layers 51a, 51b, and 51c, which are the upper layers of the Al nitride semiconductor layer 41b, can be reduced.

[0074] Specifically, the threading dislocation density at any position in the thickness direction of the Al nitride semiconductor layer 41b is lower than the threading dislocation density at any position in the thickness direction of the Al nitride semiconductor layer 41a. In addition, when the threading dislocation density at any position in the thickness direction of the Al nitride semiconductor layer 41a is taken as the threading dislocation density DA, and the threading dislocation density at any position in the thickness direction of the Al nitride semiconductor layer 41b is taken as the threading dislocation density DB, the ratio of the threading dislocation density DB to the threading dislocation density DA (DB / DA) is greater than 0 and is less than 0.6. In addition, when the threading dislocation density at any position in the thickness direction of the GaN layer 51a, 51b or 51c is taken as the threading dislocation density DC, the ratio of the threading dislocation density DC to the threading dislocation density DA (DC / DA) is greater than 0 and is less than 0.3.

[0075] Furthermore, according to the present embodiment, the warping of the compound semiconductor substrate CS1 can be easily controlled.

[0076] It should be noted that the “convex shape” and “concave shape” in the following description refer to the convex shape and concave shape when the Si substrate 1 is on the lower side and the Al nitride semiconductor layer 10 is on the upper side.

[0077] Reference Figure 1 , focusing on the relationship between the GaN layer 42a in the composite layer 4, the Al nitride semiconductor layer 41a as a base layer of the GaN layer 42a, and the Al nitride semiconductor layer 41b as an upper layer of the GaN layer 42a.

[0078] The interface BR1 between the GaN layer 42a and the Al nitride semiconductor layer 41a becomes a slip plane. In other words, at the interface BR1, the crystals of the GaN layer 42a and the crystals of the Al nitride semiconductor layer 41a become mismatched. Therefore, the crystal structure of the Al nitride semiconductor layer 41a has little effect on the crystal structure of the GaN layer 42a, and the lattice constant of the Al nitride semiconductor layer 41a has little effect on the lattice constant of the GaN layer 42a.

[0079] On the other hand, the Al nitride semiconductor layer 41b grows in a manner consistent with the crystal plane of the surface of the GaN layer 42a as the base layer. Therefore, the crystal structure of the Al nitride semiconductor layer 41b is affected by the crystal structure of the GaN layer 42a, and the lattice constant of the Al nitride semiconductor layer 41b is affected by the lattice constant of the GaN layer 42a. Since the lattice constant of the material (AlGaN, AlN, etc.) constituting the Al nitride semiconductor layer 41b is smaller than the lattice constant of GaN constituting the GaN layer 42a, tensile stress is applied to the Al nitride semiconductor layer 41b, and tensile strain is generated inside the Al nitride semiconductor layer 41b. As a reaction to the tensile stress, the composite layer 4 causes a concave warping to be generated in the compound semiconductor substrate CS1.

[0080] It should be noted that by controlling the conditions (temperature, pressure, etc.) for the epitaxial growth of the GaN layer 42a, the interface BR1 between the GaN layer 42a and the Al nitride semiconductor layer 41a can be used as a slip plane. In addition, by controlling the conditions (temperature, pressure, etc.) for the epitaxial growth of the Al nitride semiconductor layer 41b, the Al nitride semiconductor layer 41b can be grown in a manner that does not cause slip on the crystal plane on the surface of the GaN layer 42a (coherent growth).

[0081] The effect of the composite layer 4 on causing the concave warping is greater as the GaN layer constituting the composite layer 4 is thicker. On the other hand, if the GaN layer constituting the composite layer 4 is too thick, cracks are likely to occur inside the GaN layer. In order to suppress the generation of cracks inside the GaN layer constituting the composite layer 4 and effectively cause the concave warping caused by the composite layer 4, the thickness of each GaN layer in the composite layer 4 is set to be greater than 3nm and less than 100nm, preferably greater than 3nm and less than 50nm, and the number of GaN layers in the composite layer 4 is preferably set to about 1 to 2 layers.

[0082] Next, attention will be paid to the relationship among the Al nitride semiconductor layer 52 b in the composite layer 5 , the GaN layer 51 b as a base layer of the Al nitride semiconductor layer 52 b , and the GaN layer 51 c as an upper layer of the Al nitride semiconductor layer 52 b .

[0083] The interface BR2 between the Al nitride semiconductor layer 52b and the GaN layer 51b becomes a slip plane. In other words, at the interface BR2, the crystals of the Al nitride semiconductor layer 52b and the crystals of the GaN layer 51b become mismatched. Therefore, the crystal structure of the GaN layer 51b has little effect on the crystal structure of the Al nitride semiconductor layer 52b, and the lattice constant of the GaN layer 51b has little effect on the lattice constant of the Al nitride semiconductor layer 52b.

[0084] On the other hand, the GaN layer 51c grows in a manner consistent with the crystal plane of the surface of the Al nitride semiconductor layer 52b as the base layer. Therefore, the crystal structure of the GaN layer 51c is affected by the crystal structure of the Al nitride semiconductor layer 52b, and the lattice constant of the GaN layer 51c is affected by the lattice constant of the Al nitride semiconductor layer 52b. Since the lattice constant of GaN constituting the GaN layer 51c is larger than the lattice constant of the material (AlGaN, AlN, etc.) constituting the Al nitride semiconductor layer 52b, compressive stress is applied to the GaN layer 51c, and compressive strain is generated inside the GaN layer 51c. As a reaction to the compressive stress, the composite layer 5 causes a convex warping to be generated in the compound semiconductor substrate CS1.

[0085] It should be noted that by controlling the conditions (temperature, pressure, etc.) for the epitaxial growth of the Al nitride semiconductor layer 52b, the interface BR2 between the Al nitride semiconductor layer 52b and the GaN layer 51b can be used as a slip plane. In addition, by controlling the conditions (temperature, pressure, etc.) for the epitaxial growth of the GaN layer 51c, the GaN layer 51c can be grown in a manner consistent with the crystal plane of the surface of the Al nitride semiconductor layer 52b.

[0086] The same can be said for the relationship between the Al nitride semiconductor layer 52a in the composite layer 5, the GaN layer 51a as the base layer of the Al nitride semiconductor layer 52a, and the GaN layer 51b as the upper layer of the Al nitride semiconductor layer 52a. That is, the influence of the crystal structure of the GaN layer 51a on the crystal structure of the Al nitride semiconductor layer 52a is small, and the influence of the lattice constant of the GaN layer 51a on the lattice constant of the Al nitride semiconductor layer 52a is small. On the other hand, the GaN layer 51b grows in a manner consistent with the crystal plane on the surface of the Al nitride semiconductor layer 52a as the base layer. Compressive stress is applied to the GaN layer 51b through the influence of the Al nitride semiconductor layer 52a, and compressive strain is generated inside the GaN layer 51b.

[0087] The effect of the composite layer 5 on causing the convex warp is greater as the Al nitride semiconductor layer constituting the composite layer 5 is thicker. On the other hand, if the Al nitride semiconductor layer constituting the composite layer 5 is too thick, cracks are likely to occur inside the Al nitride semiconductor layer. In order to suppress the generation of cracks inside the Al nitride semiconductor layer constituting the composite layer 5 and effectively cause the convex warp caused by the composite layer 5, the thickness of each Al nitride semiconductor layer in the composite layer 5 is set to be greater than 3 nm and less than 50 nm, preferably less than 20 nm, and the number of Al nitride semiconductor layers in the composite layer 5 is preferably set to about 1 to 2 layers.

[0088] According to this embodiment, by adjusting the composite layer 4 having the function of causing concave warping in the compound semiconductor substrate CS1 and the composite layer 5 having the function of causing convex warping in the compound semiconductor substrate CS1, the warping of the compound semiconductor substrate CS1 can be easily controlled.

[0089] Furthermore, since the semiconductor layer on the interfaces BR1 and BR2 as the slip planes can grow without being affected by the lattice constant difference and strain of the underlying layer, the generation of cracks can be suppressed. In addition, since the number of composite layers 4 is small, the compound semiconductor substrate CS2 can be easily manufactured.

[0090] [Second embodiment]

[0091] Figure 4 It is a cross-sectional view showing the structure of the compound semiconductor substrate CS2 in the second embodiment of the present invention.

[0092] Reference Figure 4 The composite layer 4 of this embodiment includes three layers of Al nitride semiconductor layers 41a, 41b, and 41c (an example of a plurality of lower nitride semiconductor layers) as Al nitride semiconductor layers, and two layers of GaN layers 42a and 42b (an example of a lower GaN layer) as GaN layers. The Al nitride semiconductor layer 41a is formed at a position closest to the Si substrate 1 among the three layers of Al nitride semiconductor layers 41a, 41b, and 41c, and is in contact with the AlN buffer layer 3. The Al nitride semiconductor layer 41b is formed at a position that is the second closest to the Si substrate 1 among the three layers of Al nitride semiconductor layers 41a, 41b, and 41c. The Al nitride semiconductor layer 41c is formed at a position that is farthest from the Si substrate 1 among the three layers of Al nitride semiconductor layers 41a, 41b, and 41c. The GaN layer 42a is formed between the Al nitride semiconductor layer 41a and the Al nitride semiconductor layer 41b. The GaN layer 42 b is formed between the Al nitride semiconductor layer 41 b and the Al nitride semiconductor layer 41 c .

[0093] Each of the Al nitride semiconductor layer 41a, the GaN layer 42a, and the Al nitride semiconductor layer 41b has Figure 2 The Al concentration distribution is the same as that of the first embodiment shown in the figure. The Al concentration of the Al nitride semiconductor layer 41c is arbitrary. The Al concentration of the Al nitride semiconductor layer 41c may decrease as it moves away from the Si substrate 1 in the thickness direction, or may be constant in the thickness direction.

[0094] Assuming that the thickness of the GaN layer constituting the composite layer 4 in the present embodiment is the same as that in the first embodiment, the effect of causing the concave-shaped warping by the composite layer 4 in the present embodiment is greater than the effect of causing the concave-shaped warping by the composite layer 4 in the first embodiment. Therefore, in the compound semiconductor substrate CS2, the amount of concave-shaped warping can be made larger than that of the compound semiconductor substrate CS1. On the other hand, in the case where the thickness of the GaN layer constituting the composite layer 4 in the present embodiment is made thinner than that in the first embodiment, in the compound semiconductor substrate CS2, the amount of warping can also be made equal to that of the compound semiconductor substrate CS1.

[0095] It should be noted that the configuration of the compound semiconductor substrate CS2 other than the above is the same as the configuration of the compound semiconductor substrate CS1 in the first embodiment, and thus the description thereof will not be repeated.

[0096] According to this embodiment, the same effects as those of the first embodiment can be obtained.

[0097] [Example]

[0098] As a first example, the inventors of the present application conducted the following experiment in order to confirm the effect of reducing threading dislocations obtained by forming the GaN layer 42 a .

[0099] Figure 5 1 is a cross-sectional view showing the manufacturing conditions of the compound semiconductor substrate CS1 in the first embodiment of the present invention and the measurement positions P1, P2, and P3 of the number of threading dislocations.

[0100] Reference Figure 5 As Example A of the present invention, Figure 1 The compound semiconductor substrate CS1 shown in FIG. 1 (compound semiconductor substrate having a GaN layer 42 a ) is used as the Si substrate 1 . + A 6-inch conductive substrate of the type was used. A lower layer 411 and an upper layer 412 were formed as the Al nitride semiconductor layer 41a. The thickness of the GaN layer 42a was set to 15 nm. The thickness of each of the Al nitride semiconductor layers 52a and 52b was set to 15 nm.

[0101] In the present invention example A, a position 0.1 μm downward from the interface between the Al nitride semiconductor layer 41a and the GaN layer 42a is set as the measurement position P1. A position 0.34 μm upward from the interface between the Al nitride semiconductor layer 41b and the GaN layer 42a is set as the measurement position P2. A position 1 μm upward from the interface between the GaN layer 51a and the Al nitride semiconductor layer 41b is set as the measurement position P3.

[0102] Next, the number of threading dislocations present in the cross section at each of the measurement positions P1, P2, and P3 was measured by observation using a TEM (Transmission Electron Microscope). The number of threading dislocations measured was divided by the area of ​​the cross section (here, 9.25×10 -9 cm 2 ). Thus, the threading dislocation density DA at the measurement position P1, the threading dislocation density DB at the measurement position P2, and the threading dislocation density DC at the measurement position P3 are calculated.

[0103] Next, by dividing the threading dislocation density DB by the threading dislocation density DA, the ratio (DB / DA) of the threading dislocation density DB to the threading dislocation density DA is calculated. Similarly, by dividing the threading dislocation density DC by the threading dislocation density DA, the ratio (DC / DA) of the threading dislocation density DC to the threading dislocation density DA is calculated. It should be noted that a small ratio (DB / DA) means that the reduction rate of the threading dislocation density DB in the Al nitride semiconductor layer 41b is large. A small ratio (DC / DA) means that the reduction rate of the threading dislocation density DC in the GaN layer 51a is large.

[0104] Figure 6 1 is a cross-sectional view showing the manufacturing conditions of the compound semiconductor substrate CS100 in the first embodiment of the present invention and the measurement positions P1, P2, and P3 of the number of threading dislocations.

[0105] Reference Figure 6 As Comparative Example B, a compound semiconductor substrate CS100 not containing the GaN layer 42a (a compound semiconductor substrate without the GaN layer 42a) was prepared. The structure of the compound semiconductor substrate CS100 other than the point where the GaN layer 42a is not contained is the same as that of the compound semiconductor substrate CS1 of Example A of the present invention.

[0106] In Comparative Example B, a position 0.1 μm downward from the interface between the Al nitride semiconductor layer 41a and the Al nitride semiconductor layer 41b was set as the measurement position P1. A position 0.34 μm upward from the interface between the Al nitride semiconductor layer 41b and the Al nitride semiconductor layer 41a was set as the measurement position P2. A position 1 μm upward from the interface between the GaN layer 51a and the Al nitride semiconductor layer 41b was set as the measurement position P3.

[0107] Next, using the same method as in Example A of the present invention, threading dislocation density DA at measurement position P1, DB at measurement position P2, and threading dislocation density DC at measurement position P3 are calculated, and the ratio (DB / DA) and the ratio (DC / DA) are calculated.

[0108] Figure 7 It is a graph showing the measurement results of the threading dislocation density in the first example of the present invention.

[0109] Reference Figure 7 In Example A of the present invention, the threading dislocation density DA at the measurement position P1 is 9.6×10 9 Pieces / cm 2 The threading dislocation density DB at the measurement position P2 is 5.2×10 9 Pieces / cm 2 The threading dislocation density DC at position P3 is 2.2×10 9 Pieces / cm 2 The ratio (DB / DA) is 0.55 and the ratio (DC / DA) is 0.23.

[0110] It should be noted that in Example A of the present invention, the threading dislocation density DA of each of the multiple measurement positions P1 with different depth positions in the Al nitride semiconductor layer 41a is measured, the threading dislocation density DB of each of the multiple measurement positions P2 with different depth positions in the Al nitride semiconductor layer 41b is measured, and the threading dislocation density DC of each of the multiple measurement positions P3 with different depth positions in the GaN layer 51a is measured. As a result, in any combination of the measurement positions, the ratio (DB / DA) is greater than 0 and less than 0.6, and the ratio (DC / DA) is greater than 0 and less than 0.3.

[0111] In Comparative Example B, the threading dislocation density DA at the measurement position P1 is 1.1×10 10 Pieces / cm 2 The threading dislocation density DB at the measurement position P2 is 7.2×10 9 Pieces / cm 2 The threading dislocation density DC at position P3 is 3.8×10 9 Pieces / cm 2 The ratio (DB / DA) is 0.67 and the ratio (DC / DA) is 0.35.

[0112] It should be noted that in Comparative Example B, the threading dislocation density DA of each of the multiple measurement positions P1 having different depth positions in the Al nitride semiconductor layer 41a was measured, the threading dislocation density DB of each of the multiple measurement positions P2 having different depth positions in the Al nitride semiconductor layer 41b was measured, and the threading dislocation density DC of each of the multiple measurement positions P3 having different depth positions in the GaN layer 51a was measured. As a result, in any combination of the measurement positions, the ratio (DB / DA) was greater than 0.6, and the ratio (DC / DA) was greater than 0.3.

[0113] Based on the above results, it can be seen that in Example A of the present invention, the threading dislocation density in the Al nitride semiconductor layer 41b is lower than the threading dislocation density in the Al nitride semiconductor layer 41a. In addition, it can be seen that the introduction of the GaN layer 42a significantly reduces the threading dislocations in the Al nitride semiconductor layer 41b and significantly reduces the threading dislocations in the GaN layer 51a.

[0114] Next, the inventors of the present application measured the density of etch pits present on the surface of the outermost layer (Al nitride semiconductor layer 10) of the compound semiconductor substrate CS1 for each of Inventive Example A and Comparative Example B. The surface of the Al nitride semiconductor layer 10 of each of Inventive Example A and Comparative Example B was etched using a molten KOH (potassium hydroxide) solution to corrode the surface of the Al nitride semiconductor layer 10. In general, it is known that by etching using a molten KOH solution, portions of the crystal surface with large lattice strain and portions of dislocation cores where dangling bonds exist are selectively etched. Next, the surface of the Al nitride semiconductor layer 10 was observed under a microscope, and the density of etch pits on a predetermined area (here 4.32×10 - 4 cm 2 The number of etch pits (hereinafter sometimes referred to as etch pits (large)) larger than the predetermined size existing in the region of the observed area (area) is then divided by the number of etch pits (large) by the area of ​​the observed region to calculate the density of etch pits (large). Similarly, the number of etch pits (large) existing in the predetermined area (here, 2.50×10 -7 cm 2 The density of the etch pits (small) is calculated by counting the number of etch pits (hereinafter sometimes referred to as etch pits (small)) smaller than a specified size that exist in an area (area).

[0115] It should be noted that the etch pits (large) are presumed to be derived from microscopic defects such as nanotubes based on conventional knowledge, and the etch pits (small) are presumed to be derived from threading dislocations based on the density level.

[0116] Figure 8 1 and 10 are diagrams showing a microscope photograph of the surface of the outermost layer (Al nitride semiconductor layer 10) of the compound semiconductor substrate in the first embodiment of the present invention and the measurement results of the etch pit density.

[0117] Reference Figure 8 In Example A of the present invention, the density of the etch pits (large) is 7.87×10 4 Pieces / cm 2 The density of the pits (small) is 1.04×10 8 Pieces / cm 2 In Comparative Example B, the density of the etch pits (large) is 2.78×105 Pieces / cm 2 The density of the pits (small) is 1.40×10 8 Pieces / cm 2 .

[0118] From the above results, it can be seen that the introduction of the GaN layer 42 a significantly reduces the number of micro defects and threading dislocations in the GaN layer 51 a .

[0119] As a second example, the inventors of the present application conducted the following experiment in order to confirm the warpage control effect of the compound semiconductor substrate of the present invention.

[0120] Three types of compound semiconductor substrates CS2 were produced, in which the thickness of the GaN layer 42b was set to 15 nm (sample C1), 45 nm (sample C2), or 60 nm (sample C3). In samples C1, C2, and C3, the thickness of each of the Al nitride semiconductor layers 52a and 52b was set to 15 nm, and the thickness of the GaN layer 42a was set to 15 nm. The Al nitride semiconductor layers 52a and 52b were AlN. The warpage of the obtained compound semiconductor substrates CS2 was measured.

[0121] Fig. 9 It is a graph showing the measurement results of the warpage amount of each of the samples C1, C2 and C3 in the second example of the present invention. Fig.10 Graph showing the relationship between the thickness of the GaN layer 42b and the warpage amount obtained from the measurement results of the warpage amounts of the samples C1, C2, and C3 in the second embodiment of the present invention. Fig.10 and Fig.12 In the figure, the direction of the warp that will become a convex shape is negative, and the direction of the warp that will become a concave shape is positive.

[0122] Reference Fig. 9 and Fig.10 , the sample C1 with a GaN layer 42b thickness of 15nm becomes a convex shape with a warpage of 90μm. The sample C2 with a GaN layer 42b thickness of 45nm becomes a convex shape with a warpage of 15μm. The sample C3 with a GaN layer 42b thickness of 60nm becomes a concave shape with a warpage of 39μm. In addition, as the thickness of the GaN layer 42b increases, the warpage of the compound semiconductor substrate CS2 increases at a roughly constant ratio in the direction of becoming a concave shape.

[0123] Next, three types of compound semiconductor substrates CS2 were prepared in which the thickness of the Al nitride semiconductor layer 52b / the thickness of the Al nitride semiconductor layer 52a was set to 15nm / 15nm (sample D1), 15nm / 10nm (sample D2), or 10nm / 10nm (sample D3). In samples D1, D2, and D3, the thickness of each of the GaN layers 42a and 42b was set to 15nm. The Al nitride semiconductor layers 52a and 52b were AlN. The warpage of the obtained compound semiconductor substrate CS2 was measured.

[0124] Fig.11 It is a graph showing the measurement results of the warpage amount of each of the samples D1, D2 and D3 in the second example of the present invention. Fig.12 Graph showing the relationship between the thickness and the warpage amount of the Al nitride semiconductor layers 52a and 52b obtained from the measurement results of the warpage amounts of the samples D1, D2, and D3 in the second example of the present invention.

[0125] Reference Fig.11 and Fig.12 , the sample D1 in which the thickness of the Al nitride semiconductor layer 52b / the thickness of the Al nitride semiconductor layer 52b is 15nm / 15nm becomes a convex shape with a warping amount of 90μm. The sample D2 in which the thickness of the Al nitride semiconductor layer 52b / the thickness of the Al nitride semiconductor layer 52b is 15nm / 10nm becomes a convex shape with a warping amount of 23μm. The sample D3 in which the thickness of the Al nitride semiconductor layer 52b / the thickness of the Al nitride semiconductor layer 52b is 10nm / 10nm becomes a concave shape with a warping amount of 46μm. In addition, as the total value of the thickness of the Al nitride semiconductor layer 52b and the thickness of the Al nitride semiconductor layer 52b decreases, the warping amount of the compound semiconductor substrate CS2 increases at a substantially constant ratio in the direction of becoming the concave shape.

[0126] From the above experimental results, it is understood that the warping of the compound semiconductor substrate CS1 can be easily controlled by adjusting the thickness of the GaN layer constituting the composite layer 4 or the thickness of the Al nitride semiconductor layer constituting the composite layer 5 .

[0127] [other]

[0128] The compound semiconductor substrate of the present invention may include: a Si substrate; a first nitride semiconductor layer, which is a first nitride semiconductor layer containing Al formed on the Si substrate, and is an inclined layer in which the Al concentration decreases along the thickness direction as it moves away from the Si substrate; a second nitride semiconductor layer, which is a second nitride semiconductor layer formed on the first nitride semiconductor layer, and has an average Al concentration lower than the average Al concentration of the first nitride semiconductor layer; and a third nitride semiconductor layer, which is a third nitride semiconductor layer containing Al formed on the second nitride semiconductor layer, and has an average Al concentration higher than the average Al concentration of the second nitride semiconductor layer. As an example, Figure 1 The composite layer 5, the GaN layer 7, and the Al nitride semiconductor layer 10 may be omitted, or other layers may be formed in place of these layers.

[0129] The above-mentioned embodiments can be combined as appropriate.

[0130] The above embodiments and examples are illustrative in all points and are not restrictive. The scope of the present invention is indicated by the claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0131] Description of Reference Numerals

[0132] 1 Si substrate

[0133] 2 SiC layer

[0134] 3 AlN buffer layer

[0135] 4.5 Composite layer

[0136] 7, 42a, 42b, 51a, 51b, 51c GaN layer

[0137] 10, 41a, 41b, 41c, 52a, 52b Al nitride semiconductor layer

[0138] 411 Lower Layer

[0139] 412 Upper Layer

[0140] BR1, BR2 interface

[0141] CS1, CS2, CS100 Compound semiconductor substrates

[0142] EP pits

[0143] P1, P2, P3 Measurement positions of threading dislocation numbers

[0144] TD Threading dislocation

Claims

1. A compound semiconductor substrate comprising: Si substrate; The first nitride semiconductor layer is a first nitride semiconductor layer containing Al formed on the Si substrate, and is a gradient layer in which the Al concentration decreases as it moves away from the Si substrate in the thickness direction; a second nitride semiconductor layer, formed on the first nitride semiconductor layer and made of GaN formed at a film formation temperature lower than that of the first nitride semiconductor layer, and having an average Al concentration lower than that of the first nitride semiconductor layer; and The third nitride semiconductor layer is an Al-containing third nitride semiconductor layer formed on the second nitride semiconductor layer and has an average Al concentration higher than the average Al concentration of the second nitride semiconductor layer. The threading dislocation density at any position in the thickness direction of the third nitride semiconductor layer is lower than the threading dislocation density at any position in the thickness direction of the first nitride semiconductor layer. At least a portion of threading dislocations present in the first nitride semiconductor layer is covered by the second nitride semiconductor layer, An interface between the first nitride semiconductor layer and the second nitride semiconductor layer is a slip plane.

2. The compound semiconductor substrate according to claim 1, wherein The second nitride semiconductor layer has a thickness of 3 nm to 100 nm.

3. The compound semiconductor substrate according to claim 1, wherein The first nitride semiconductor layer comprises: Lower layer; and An upper layer is formed on the lower layer and has an average Al concentration lower than an average Al concentration of the lower layer.

4. The compound semiconductor substrate according to claim 1, wherein When the threading dislocation density at any position in the thickness direction of the first nitride semiconductor layer is taken as the threading dislocation density DA and the threading dislocation density at any position in the thickness direction of the third nitride semiconductor layer is taken as the threading dislocation density DB, the ratio DB / DA of the threading dislocation density DB to the threading dislocation density DA is greater than 0 and is less than 0.

6.

5. The compound semiconductor substrate according to claim 1, wherein A ratio W2 / W1 of a thickness W2 of the second nitride semiconductor layer to a thickness W1 of the first nitride semiconductor layer is greater than or equal to 0.007 and less than or equal to 0.

26.

6. The compound semiconductor substrate according to claim 1, wherein It further includes a GaN layer formed on the third nitride semiconductor layer.

7. The compound semiconductor substrate according to claim 6, wherein: When the threading dislocation density at any position in the thickness direction of the first nitride semiconductor layer is taken as the threading dislocation density DA and the threading dislocation density at any position in the thickness direction of the GaN layer is taken as the threading dislocation density DC, the ratio DC / DA of the threading dislocation density DC to the threading dislocation density DA is greater than 0 and is less than 0.

3.

8. The compound semiconductor substrate according to claim 6, wherein: It also has an upper composite layer. The upper composite layer comprises: A plurality of upper GaN layers stacked in the up-down direction, and an upper nitride semiconductor layer containing Al formed between each of the plurality of upper GaN layers, The GaN layer is the lowest upper GaN layer among the plurality of upper GaN layers, A ratio W4 / W3 of a thickness W4 of the upper nitride semiconductor layer to a thickness W3 of each of the plurality of upper GaN layers is greater than or equal to 0.0015 and less than or equal to 0.

025.

9. The compound semiconductor substrate according to claim 1, wherein: Also available: A SiC layer formed on the Si substrate, and A buffer layer formed on the SiC layer and composed of AlN, The first nitride semiconductor layer is formed on the buffer layer.

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