Speculative exit from power-down mode for a DRAM bank

Abstract

A processing system (100) includes a memory controller (110) that preemptively exits a dynamic random access memory (DRAM) integrated circuit rank (115) from a low power mode, such as a power down mode, based on a predicted time at which the memory controller will receive a request (102) to access the DRAM rank. The memory controller tracks how long after the DRAM rank entered the low power mode before a request to access the DRAM rank is received by the memory controller. Based on a history of the timing of access requests, the memory controller predicts for each DRAM rank a predicted time that reflects how long after entering the low power mode a request to access each DRAM rank is expected to be received. The memory controller speculatively exits the DRAM rank from the low power mode based on the predicted time and before a request to access the DRAM IC rank is received.

Description

Background Art

[0001] Computer systems often use arrays of dynamic random access memory (DRAM) integrated circuits (ICs) for main memory. For example, conventional dual in-line memory modules (DIMMs) are implemented as a group of DRAM ICs mounted on a printed circuit board. A DIMM consists of one or more rows, where each row is a group of DRAM ICs connected to the same control line or chip select so that they are accessed simultaneously by a memory controller. In order to improve energy efficiency, DRAM ICs can be placed in multiple power states, such as active, standby, nap, power down, and self-refresh. The memory controller controls the power state of multiple DRAM rows on a row-by-row basis via chip select. For example, power down is a low-power state of DRAM that consumes a fraction (e.g., 1%) of the active power state, but also requires a delay in clock synchronization to re-enter the active state. Other low-power modes have different entry and exit delays. When the memory controller experiences a gap in access requests to the DRAM row, the memory controller ensures that the conditions for entering the power down mode are met and then sends a power down entry command to the DRAM via chip select. When the memory controller receives a new request from a processor core to access the DRAM row, the memory controller sends a power down exit command to the DRAM row. However, the memory controller must then wait for the DRAM rank to exit power-down mode and transition to active mode before it can access the DRAM, thereby incurring a latency penalty for using power-down mode. Summary of the invention

[0002] According to one aspect, a method includes predicting at a memory controller a time at which an access request to access a first rank of a dynamic random access memory (DRAM) integrated circuit in a low power mode is expected to be received at the memory controller. The method also includes exiting the first rank from the low power mode before the predicted time. In one embodiment, the prediction is based on a history of timing of access requests to access the first rank at the memory controller. The prediction may also be based on an average number of clock cycles between a first time the first rank enters the low power mode and a second time the memory controller receives an access request to access the first rank. In one embodiment, exiting the low power mode includes exiting the low power mode a predetermined number of clock cycles before the predicted time at which the access request will be received at the memory controller. In this case, the predetermined number of clock cycles may be based on a low power mode exit latency for the first rank. In one embodiment, the DRAM integrated circuit includes a plurality of ranks, and the method also includes: predicting at the memory controller a time at which an access request to access each rank of the DRAM in the low power mode will be received at the memory controller; and exiting the rank from the low power mode before the predicted time corresponding to each rank. In one embodiment, the method further includes adjusting the predicted time at the memory controller based on a latency penalty associated with a previous exit of the first rank from a low power mode.

[0003] According to another aspect, a method includes: exiting the first rank from a low power mode at a memory controller before receiving an access request to access a first rank of a DRAM integrated circuit and in response to a predicted time that the memory controller will receive the access request to access the first rank. The method may also include: predicting the time when the memory controller will receive the access request to access the first rank, wherein the prediction is based on a history of how long after the first rank enters the low power mode before the access request to access the first rank is received at the memory controller. In one embodiment, the prediction is based on the average number of clock cycles between a first time when the first rank enters the low power mode and a second time when the memory controller receives the access request to access the first rank. In one embodiment, exiting the low power mode includes exiting the low power mode a predetermined number of clock cycles before the predicted time when the access request will be received at the memory controller. In this case, the predetermined number of clock cycles is based on the low power mode exit latency of the first rank. In one embodiment, the DRAM integrated circuit includes a plurality of ranks, and the method further includes: predicting at the memory controller a time at which an access request to access each rank of the DRAM integrated circuit in the low power mode will be received at the memory controller; and exiting the rank from the low power mode before the predicted time corresponding to each rank. In one embodiment, the method further includes: adjusting the predicted time at the memory controller based on a latency penalty associated with a previous exit of the first rank from the low power mode.

[0004] According to yet another aspect, a system includes a memory controller configured to be coupled to a DRAM integrated circuit including a plurality of ranks. The memory controller is used to: predict a time when an access request to access a first rank of the DRAM integrated circuit in a low power mode will be received at the memory controller; and exit the first rank from the low power mode before the predicted time. In one embodiment, the memory controller is used to predict the time based on a history of how long after the first rank enters the low power mode before the access request to access the first rank is received at the memory controller. In one embodiment, the memory controller may also exit the first rank from the low power mode a predetermined number of clock cycles before the predicted time when the access request will be received at the memory controller. The predetermined number of clock cycles may be based on the low power mode exit latency of the first rank. In one embodiment, the memory controller is also used to: predict a time when an access request to access each rank of the DRAM integrated circuit in the low power mode will be received at the memory controller; and exit the rank from the low power mode before the predicted time corresponding to each rank. In one embodiment, the memory controller is also used to adjust the predicted time based on a latency penalty associated with a previous exit of the first rank from the low power mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] By referring to the accompanying drawings, the present disclosure may be better understood, and its numerous features and advantages become apparent to those skilled in the art. The use of the same reference numerals in different drawings indicates similar or identical items.

[0006] Figure 1 is a block diagram of a processing system that includes a memory controller that employs speculative retirement of power down from banks of DRAM, according to some embodiments.

[0007] Figure 2 is a diagram showing that according to some embodiments Figure 1 Block diagram of the power management unit and prediction unit of the memory controller.

[0008] Figure 3 is a diagram illustrating a power-down mode / active mode transition of a bank of DRAM utilizing a speculative exit from a power-down mode, according to some embodiments.

[0009] Figure 4 is a flow chart illustrating a method for speculatively exiting a power-down mode of a bank of DRAM, according to some embodiments. DETAILED DESCRIPTION

[0010] Figures 1 to 4Systems and techniques are shown for preemptively exiting DRAM banks from a low power mode, such as a power down mode, based on a predicted time at which a memory controller of the DRAM banks will receive a request to access the DRAM banks. The memory controller tracks how long after the DRAM banks enter the low power mode before a request to access the DRAM banks is received by the memory controller. Based on a history of the timing of access requests, the memory controller predicts for each DRAM bank a predicted time that reflects how long after entering the low power mode a request to access each DRAM bank is expected to be received. The memory controller speculatively sends a low power mode exit command to the DRAM banks based on the predicted time and before receiving a request to access the DRAM banks. In some embodiments, the memory controller sends a low power mode exit command before the predicted time based on the number of clock cycles required for the DRAM banks to exit the low power mode and transition back to an active state.

[0011] The memory controller monitors how long after each DRAM bank preemptively exits a low power mode before a request to access each DRAM bank is received by the memory controller, and adjusts the predicted time for each DRAM bank based on the history of the access requests. Similarly, in the event that the memory controller receives an on-demand access request to a DRAM bank before the predicted time, such that the memory controller must wait for the DRAM bank to exit the low power mode and transition back to an active state (i.e., a low power mode exit latency or a power-off exit latency), the memory controller adjusts the predicted time for the affected DRAM bank based on the power-off exit latency penalty incurred during a previous exit from the low power mode.

[0012] Figure 1A block diagram of a processing system 100 is shown, according to some embodiments, that includes a memory controller 110 that employs speculative exit from a power-down mode of a DRAM bank. The processing system 100 includes, for example, a server, a desktop computer, a laptop computer, a tablet computer, a mobile phone, a game console, etc. The processor system 100 includes a memory subsystem composed of memory modules for storing data to be accessed by instructions executed at a processor core 105. The memory subsystem is organized into a memory hierarchy with a main memory at the top of the hierarchy for storing all data accessible by executing instructions, and one or more caches at a lower level of the memory hierarchy for storing a subset of the data stored at the main memory. If the data requested by the processor core 105 is not found at the cache of the memory hierarchy, the cache controller issues a memory access request to the memory controller to retrieve the data from the main memory. In the depicted example, the processing system 100 includes one or more processor cores 105 coupled to a main memory 110 and a DIMM 115 including two DRAM IC banks (i.e., bank A 120 and bank B 130). In some embodiments, memory controller 110 controls more than two ranks of DRAM ICs.

[0013] The one or more processor cores 105 are implemented as a central processing unit (CPU) or a graphics processing unit (GPU) or a combination thereof, and include various stages or components for executing instructions from an operating system or an application being executed by the processor core 105, such as a prefetcher (not shown), an integer execution unit or arithmetic logic unit (ALU) (not shown), a floating point unit (FPU) (not shown), a retirement unit (not shown), etc. The one or more processor cores 105 also include one or more caches (not shown) that form a cache hierarchy for temporarily storing data, including instructions, that can be accessed by the execution pipeline with less latency than memory accesses to the DIMM 115.

[0014] The memory controller 110 provides various interface functions for the one or more processor cores 105, including interfacing with the DIMMs 115. In addition, the memory controller 110 provides power management functions for the DIMMs 115. To this end, the memory controller 110 includes a power management unit 145 coupled to the prediction unit 140. The power management unit 145 controls the power state of the rank A 120 of the DIMM 115 via the chip select 112, and controls the power state of the rank B 130 via the chip select 114.

[0015] In at least one embodiment, the rank A 120 and rank B 130 of the DIMM 115 have at least two general modes: an active mode, in which the DRAM ICs 121 to 128 of the rank A 120 and the DRAM ICs 131 to 138 of the rank B 130 service memory access requests, such as performing read and write transactions; and a power-down mode, in which the DRAM ICs 121 to 128 of the rank A 120 and the DRAM ICs 131 to 138 of the rank B 130 do not service memory access requests and consume significantly less power than during the active mode. When in the active mode, the DRAM ICs 121 to 128 of the rank A 120 and the DRAM ICs 131 to 138 of the rank B 130 adopt any of a variety of different performance states or operating points through corresponding pairs of clock frequencies and voltages, as controlled by the power management unit 145. When the DRAM rank is idle, if the power management unit 145 determines that the conditions for the power down mode are met, such as an expected gap in access requests to the DRAM rank, the power management unit 145 places the DRAM rank in the power down mode. There is an overhead associated with entering and exiting the power down mode in terms of energy cost and performance cost (such as latency associated with the delay of clock resynchronization). For example, if the memory controller 110 receives a request to access the DRAM rank in the power down mode (i.e., an "on-demand" exit from the power down mode), the memory controller 110 will have to restore the DRAM rank to the active state by sending a power down exit (PDX) command and then waiting for multiple clock cycles for the DRAM rank to resynchronize and complete the transition to the active mode (exit power down (tXP) cycle) before sending a read or write command to the DRAM rank. Therefore, the on-demand exit from the power down mode adds additional latency to requests to access the DRAM, especially in "unloaded" or "lightly loaded" scenarios. The unloaded scenario occurs when the memory controller 110 receives a request to access the DRAM ICs 121 to 128 or 131 to 138 after a certain time gap (e.g., when the processor is exiting an idle state, such as after waking up from a sleep mode). The lightly loaded scenario occurs when the memory controller 110 receives relatively few requests for the DRAM ICs 121 to 128 or 131 to 138, making the latency of the memory DIMM 115 a significant factor in the overall latency.

[0016] In order to mitigate the penalty of receiving a request to access a DRAM bank while the DRAM bank is in power-down mode, the prediction unit 140 predicts the duration of the current power-down mode of each DRAM bank (i.e., the iteration of the power-down mode that the DRAM bank has entered or is about to enter), and therefore predicts when it will exit from the power-down mode. The prediction unit 140 estimates or otherwise predicts the duration of the current power-down mode using any of a variety of prediction methods. For example, in some embodiments, the prediction unit 140 stores and analyzes information about the corresponding durations of many previously occurring power-down modes for each DRAM bank (i.e., from the first time the DRAM bank enters the power-down mode until the second time when the memory controller 110 receives a request from the processor core 105 to access the DRAM bank). The duration information for each DRAM bank is arranged in bins, and the prediction unit 145 then predicts the duration of the current power-down mode of each DRAM bank based on the binned information. In other embodiments, the prediction unit 140 uses a different prediction process, such as assuming a predefined average duration of all power-down modes for each DRAM bank, using a lookup table or other data structure that is pre-populated with a defined average power-down mode duration based on various criteria (such as access history to the DRAM bank before entering the power-down mode), and the like.

[0017] Using the predicted power-down mode duration provided by prediction unit 140, power management unit 145 determines when to predictively exit each DRAM rank from the power-down mode before receiving a request to access the DRAM rank to reduce latency associated with an on-demand exit from the power-down mode. In at least one embodiment, power management unit 145 triggers the exit power-down process prior to the predicted power-down mode duration, so that the DRAM rank has undergone a resynchronization and transition to an active state to service the incoming memory access request for a number of tXP cycles necessary when the predicted power-down mode duration expires.

[0018] To illustrate, in operation, the processor core 105 sends an access request 102 to the memory controller 110 to request access to data and instructions stored at the DIMM 115. The prediction unit 140 of the memory controller 110 tracks accesses to the DRAM ICs 121 to 128 of the rank A 120 and to the DRAM ICs 131 to 138 of the rank B 130. Based on the pattern of requests to access each of the rank A 120 and the rank B 130, the power management unit 145 determines whether the idle rank meets the conditions for the power-down mode, such as the expected gap in access requests to the DRAM rank. When the DRAM rank is idle, if the power management unit 145 determines that the conditions for the power-down mode are met, the power management unit 145 places the DRAM rank in the power-down mode.

[0019] When a DRAM rank is in power-down mode, prediction unit 140 stores and analyzes information about the duration of the power-down mode before memory controller 110 receives a request from processor core 105 to access the DRAM ICs of the rank in power-down mode. Based on this history of how long after the rank entered power-down mode an access request to access the rank was received at memory controller 110, prediction unit 140 predicts how long the next power-down mode of the rank will last before a request to access the rank is received at memory controller 110. In some embodiments, prediction unit 140 predicts the duration of the power-down mode of the rank based on the average number of clock cycles between the time the rank entered power-down mode and the time the memory controller received an access request to access the rank.

[0020] Based on the predicted duration of the power down mode of the bank, the power management unit 145 sends a preemptive PDX command to the bank before the predicted time that the memory controller 110 will receive a request to access the bank. The memory controller 110 waits for the bank to resynchronize and transition to the active state for a number of tXP cycles necessary, after which the memory controller 110 accesses the bank based on the next access request to the bank. The prediction unit 140 monitors how long after exiting the power down mode based on the preemptive PDX command the memory controller 110 receives a request to access the bank. Based on the latency associated with transitioning to the active state (or conversely, a premature preemptive exit from the power down mode), the prediction unit 140 adjusts the predicted power down mode duration of the bank.

[0021] The prediction unit 140 generates and adjusts the predicted power-down mode duration for each of the plurality of DRAM ranks. For example, in some embodiments, the processing system 100 includes a plurality of DIMMs 115, and each DIMM 115 includes one or more DRAM ranks 120, 130. Each DRAM rank 120, 130 within the DIMM 115 has a specific predicted power-down duration based on the access pattern to the particular DRAM rank 120, 130. Therefore, the prediction unit 140 generates and adjusts the predicted power-down mode duration corresponding to each of the plurality of DRAM ranks 120, 130.

[0022] Figure 2 is a diagram showing that according to some embodiments Figure 11. A block diagram of a power management unit 145 and a prediction unit 140 of a memory controller 110 of FIG. 1. In the depicted example, the prediction unit 140 includes an activity monitor 212 coupled to receive indications of access requests directed to various DRAM banks 120, 130. The types of activity monitored by the activity monitor 212 include read and write requests to memory addresses located at DRAM ICs 121 to 128, 131 to 138. The prediction unit 140 also includes a plurality of timers 213. Each of the DRAM banks monitored for activity may include a timer 213. In some embodiments, each of the timers 213 is reset when the activity monitor 212 detects activity from the corresponding DRAM bank of the timer. After being reset, a given timer 213 begins tracking the time since the most recent access request to the DRAM bank. Each timer 213 reports the time since the most recent activity was detected in the corresponding DRAM bank of the timer. After placing the DRAM bank in the power-down mode, the power management unit 145 signals the activity monitor 212 that the given DRAM bank is in the power-down mode. The activity monitor 212 records the time that the DRAM rank is in the power-down mode based on the time value received from the corresponding timer 213 until the DRAM rank exits the power-down mode and resumes servicing access requests.

[0023] When a DRAM row has resumed servicing access requests after being in power-down mode, the activity monitor 212 records the duration of the power-down mode in the DRAM row in the event storage device 214. In the illustrated embodiment, while the power-down mode time is being monitored for each of the DRAM rows, the event storage device 214 stores the duration of each of the most recent N instances of the power-down mode. In one embodiment, the event storage device 214 includes a plurality of first-in-first-out (FIFO) memories, one FIFO memory for each DRAM row. Each FIFO in the event storage device 214 stores the duration of the most recent N instances of the power-down mode of its corresponding DRAM row. When the duration of a new instance of the power-down mode is recorded in the FIFO corresponding to a given DRAM row, in some embodiments, the duration of the oldest power-down mode instance is overwritten.

[0024] In some embodiments, for each DRAM rank, a bin storage 215 (shown as a single joint storage with the event storage 214) stores counts of power down mode durations in corresponding bins in order to generate a distribution of power down mode durations. The bin storage 215 includes logic to read the recorded durations from the event storage 214 and generate count values ​​for each bin. Since the old duration data is overwritten by the new duration in the event of an additional instance of the power down mode, the logic in the bin storage 215 updates the count values ​​in the bins. Prediction logic 218 is coupled to the bin storage 215. Based on the distribution of power down mode durations for a given DRAM rank, the prediction logic 218 generates a prediction about the duration of the current power down mode. In some embodiments, the prediction logic 218 generates a prediction about the duration of the current power down mode for a given DRAM rank based on an average of the power down mode durations for the DRAM rank.

[0025] In addition to the prediction of the duration of the power-down mode, the prediction logic 218 may also generate an indication of a specified time at which the power-down mode may be exited based on the prediction of the duration of the power-down mode. For example, in one embodiment, if the DRAM bank is placed in the power-down mode, the power management unit 145 causes the DRAM bank to exit the power-down mode at the specified time based on the predicted duration of the power-down mode. Such an exit from the power-down mode is called in the absence of any other external events that would otherwise cause an exit from the power-down mode (e.g., the memory controller 110 receives an access request to the DRAM bank). In addition, in some embodiments, the exit from the power-down mode is called before the predicted duration of the power-down mode is completely passed. If the prediction of the duration of the power-down mode is quite accurate, the preemptive exit from the power-down mode provides various performance advantages. For example, resynchronization and transition to an active state occur before the memory controller 110 receives the next access request to the DRAM bank, thereby enabling the DRAM bank to begin servicing access requests faster than it would have been possible in the case of a reactive exit from the power-down mode.

[0026] The prediction made by the prediction logic 218 is forwarded to the decision unit 205 of the power management unit 145. In the depicted embodiment, the decision unit 205 uses the prediction of the power down mode time and other information to determine when to preemptively exit the DRAM bank from the power down mode. The power management unit 145 also includes a mode selector 207 for sending power down entry (PDE) and power down exit (PDX) commands to the DRAM bank. The mode selector 207 generates the commands based on the information provided to it by the decision unit 205.

[0027] Figure 3is a diagram illustrating utilizing a speculative exit from a power down mode according to some embodiments. Figure 1 Figure 1 shows the power-down mode / active mode transitions of a DRAM bank. In particular, Figure 3 The timeline 300 depicted in shows a sequence of events or phases that occur when a DRAM rank transitions to a power down mode in response to the memory controller 110 determining that conditions for the power down mode are met and then the DRAM rank transitions from the power down mode to an active mode to service incoming access requests.

[0028] At time t0, after determining that the conditions for the DRAM rank to enter the power down mode are met, the memory controller 110 prepares the DRAM rank to transition to the power down mode. At stage 301, the DRAM rank ends servicing pending access requests to the DRAM rank. At time t1, the memory controller 110 waits for a number of idle cycles to avoid DRAM rank stalling at stage 302. At time t2, the mode selector 207 of the power management unit 245 of the memory controller 110 sends a PDE command to the DRAM rank, triggering the DRAM rank to enter the power down mode at stage 305.

[0029] exist Figure 3 In a specific example of , the prediction unit 140 predicts an exit from the power down mode at time t5 based on a predicted time at which the next access request for the DRAM rank will be received by the memory controller 110. Based on the predicted time of the exit, the decision unit 205 determines that the DRAM rank preemptively exits the power down mode at time t3 (i.e., a predetermined number of cycles before the predicted exit). The mode selector 207 generates a PDX command to the DRAM rank based on the decision unit 205's determination to exit the power down mode. Based on the PDX command, the DRAM rank begins the process of resynchronizing and transitioning to the active state. The memory controller 110 waits a predetermined number of tXP cycles at stage 306 until time t4 so that the DRAM rank completes the transition to the active state. By sending the PDX command a predetermined number of tXP cycles before the predicted exit, the memory controller 110 avoids or reduces the chance of incurring a PDX penalty in the event that the memory controller 110 receives an access request for the DRAM rank before the transition to the active mode is completed. Therefore, starting at time t4, the DRAM rank is in the active state, ready to service the access request at stage 309.

[0030] Figure 4 is a diagram showing a method for speculatively exiting Figure 1Flowchart of method 400 for powering down a DRAM bank of a memory controller 110. At box 402, prediction unit 140 of memory controller 110 tracks a history of access requests to the DRAM bank after the DRAM bank entered the power down mode. At box 404, mode selector 207 of power management unit 145 sends a PDE command to the DRAM bank in response to decision unit 205 determining that a condition for the power down mode of the DRAM bank is met. At box 406, prediction unit 140 predicts the duration that the DRAM bank will be in the power down mode before transitioning back to the active mode due to memory controller 110 receiving an access request for the DRAM bank. As noted, prediction unit 140 predicts the duration using any of a variety of predictive exit techniques, such as based on the duration of a previous power down mode or an average of the previous N power mode durations of the DRAM bank.

[0031] With the predicted power down mode duration information from the prediction unit 140, at block 408, the power management unit 145 starts a countdown timer that is set to expire at a specified amount of time before the predicted exit from the power down mode. As described above, the specified time before the predicted exit may be a fixed amount of time, a predetermined number of clock cycles, etc. Once the countdown time has expired, at block 410, the power management unit 145 causes the DRAM bank to preemptively exit from the power down mode by sending a PDX command to the DRAM bank based on the predicted power down mode duration. At block 412, the memory controller 110 receives an access request 102 to access the DRAM bank. At block 412, the DRAM bank services the access request 102.

[0032] Computer-readable storage media may include any non-transitory storage media or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact disk (CD), digital versatile disk (DVD), Blu-ray disc), magnetic media (e.g., floppy disk, tape, or magnetic hard drive), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or storage media based on microelectromechanical systems (MEMS). Computer-readable media may be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., a magnetic hard drive), removably attached to a computing system (e.g., an optical disk or flash memory based on a universal serial bus (USB)), or coupled to a computer system via a wired or wireless network (e.g., a network accessible storage device (NAS)).

[0033] In some embodiments, certain aspects of the techniques described above may be implemented by one or more processors of a processing system that executes software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that manipulate one or more processors to perform one or more aspects of the techniques described above when executed by one or more processors. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device (such as a flash memory, a cache, a random access memory (RAM), or one or more other non-volatile memory devices), etc. The executable instructions stored on the non-transitory computer-readable storage medium may be source code, assembly language code, object code, or other instruction formats interpreted or otherwise executed by one or more processors.

[0034] It should be noted that not all activities or elements described above in the general description are required, a part of a specific activity or device may not be required, and in addition to the described activities or elements, one or more additional activities may be performed or one or more additional elements may be included. In addition, the order in which the activities are listed is not necessarily the order in which the activities are performed. In addition, concepts have been described with reference to specific embodiments. However, it will be appreciated by those of ordinary skill in the art that various modifications and changes may be made without departing from the scope of the present disclosure set forth in the appended claims. Therefore, this specification and the accompanying drawings will be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present disclosure.

[0035] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and any features that may make any benefit, advantage, or solution appear or become more prominent should not be interpreted as key, essential, or necessary features of any or all claims. In addition, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter may be modified and practiced in different but equivalent ways that are obvious to those skilled in the art who benefit from the teachings of this article. Except as described in the appended claims, it is not intended to limit the details of the construction or design shown herein. Therefore, it is obvious that the specific embodiments disclosed above may be changed or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the appended claims.

Claims

1. A method for exiting a low power mode, the method comprising: Predicting (406) at a memory controller (110) a time at which an access request (102) to access a first rank (120) of a dynamic random access memory DRAM integrated circuit in a low power mode is expected to be received at the memory controller, wherein the prediction includes: storing a count of low power mode duration instances for the first rank based on a history of a number of clock cycles between a first time the first rank entered the low power mode and a second time the memory controller received an access request to access the first rank, and predicting a duration of the low power mode for the first row based on the count of low power mode duration instances; and The first row is exited from the low power mode before the time (410). 2 . The method of claim 1 , wherein predicting the duration of the low power mode for the first row based on the count of low power mode duration instances is based on a distribution of the count of low power mode duration instances.

3. The method of claim 2 , wherein the time at which the access request to access the first rank of the DRAM integrated circuit in the low power mode is expected to be received at the memory controller is predicted based on an average number of clock cycles between the first time that the first rank enters the low power mode and the second time that the memory controller receives the access request to access the first rank. 4 . The method of claim 1 , wherein exiting the low power mode comprises exiting the low power mode a predetermined number of clock cycles before the time at which the access request is received at the memory controller.

5. The method of claim 4, wherein the predetermined number of clock cycles is based on a low power mode exit latency of the first bank.

6. The method of any one of claims 1 to 5, wherein the DRAM integrated circuit comprises a plurality of ranks (120, 130), and the method further comprises: predicting, at the memory controller, a time at which an access request to access each rank of the DRAM integrated circuit in the low power mode will be received at the memory controller; as well as Each rank is exited from the low power mode prior to the time corresponding to the rank.

7. The method of claim 1, further comprising: The time is adjusted at the memory controller based on a latency penalty associated with a previous exit of the first rank from a low power mode.

8. An apparatus (100) for exiting a low power mode, the apparatus comprising: A memory controller (110) configured to be coupled to a dynamic random access memory (DRAM) integrated circuit comprising a plurality of banks (120, 130), the memory controller being configured to: Predicting (406) a time when an access request to access a first rank of the plurality of ranks of the DRAM integrated circuit in a low power mode will be received at the memory controller, wherein predicting comprises: storing a count of low power mode duration instances for the first rank based on a history of a number of clock cycles between a first time the first rank entered the low power mode and a second time the memory controller received an access request to access the first rank, and predicting a duration of the low power mode for the first row based on the count of low power mode duration instances; and The first row is exited from the low power mode before the time (410). 9 . The apparatus of claim 8 , wherein predicting the duration of the low power mode of the first row based on the count of low power mode duration instances is based on a distribution of the count of low power mode duration instances.

10. The apparatus of claim 9, wherein the memory controller is to predict the time based on an average number of clock cycles between the first time that the first rank enters the low power mode and the second time that the memory controller receives the access request to access the first rank.

11. The apparatus of claim 10, wherein the memory controller is to cause the first rank to exit the low power mode a predetermined number of clock cycles before the time at which the access request is to be received at the memory controller.

12. The apparatus of claim 11, wherein the predetermined number of clock cycles is based on a low power mode exit latency of the first bank.

13. The apparatus of claim 11, wherein the memory controller is further configured to: predicting when an access request to access each rank of the DRAM integrated circuit in the low power mode will be received at the memory controller; and Each rank is exited from the low power mode prior to the time corresponding to the rank.

14. The apparatus of any one of claims 8 to 13, wherein the memory controller is further to adjust the time based on a latency penalty associated with a previous exit of the first rank from a low power mode.

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