Capacitance Balancing in Double-Sided Contact Switches

Abstract

A double-sided contact switch has a first independent drain / source region (372) of a multi-gate active device. The double-sided contact switch also has a first shared drain / source region (374) of the multi-gate active device. The double-sided contact switch has a second independent drain / source region (376) of the multi-gate active device, the second independent drain / source region being adjacent to the first shared drain / source region. The double-sided contact switch also has a second shared drain / source region of the multi-gate active device, the second shared drain / source region being adjacent to the first independent drain / source region. The double-sided contact switch has a gate region (356) between the first independent drain / source region and the first shared drain / source region and between the second independent drain / source region and the second shared drain / source region.

Description

[0001] Priority claim

[0002] This patent application claims priority to application No. 16 / 230,884, filed on December 21, 2018, and assigned to the assignee thereof, entitled “Capacitance Balancing in a Double-Sided Touch Switch,” which is hereby expressly incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to integrated circuits (ICs). More particularly, the present disclosure relates to capacitance and series resistance balancing in a double-sided radio frequency switch having front-side contacts and back-side contacts configured according to a checkerboard layout. Background Art

[0004] The design complexity of integrated circuits (e.g., mobile radio frequency (RF) chips or transceivers) is compounded by the additional circuit functionality required to support enhanced communications. The design of these mobile RF transceivers may include the use of silicon-on-insulator (SOI) technology. Silicon-on-insulator (SOI) technology replaces traditional semiconductor (e.g., silicon) substrates (e.g., wafers) with a layered silicon-insulator-silicon substrate to reduce parasitic device capacitance and improve performance.

[0005] Active devices on the SOI layer can include complementary metal oxide semiconductor (CMOS) transistors. RF switch devices for mobile RF transceivers can be fabricated using CMOS transistors on SOI substrates. Unfortunately, successfully fabricating transistors using SOI technology is complicated by parasitic environments (e.g., parasitic capacitance). Parasitic capacitance can be caused by the proximity of active devices on the semiconductor layer to the semiconductor substrate supporting the buried oxide (BOX) layer in the SOI device.

[0006] Parasitic capacitance can also be caused by interconnects to the gate and source / drain regions of CMOS transistors. This form of contact / interconnect-to-gate capacitance results from the proximity of back-end-of-line (BEOL) interconnects and / or middle-of-line (MOL) trench contacts / interconnects to the transistor gates and transistor gate interconnects. This parasitic capacitance can adversely affect the performance of CMOS devices, causing circuit delays and losses. This capacitance is particularly problematic for RF switching devices. Summary of the Invention

[0007] A double-sided contact switch includes a first independent drain / source region of a multi-gate active device. The double-sided contact switch also includes a first shared drain / source region of the multi-gate active device. The double-sided contact switch also includes a second independent drain / source region of the multi-gate active device, the second independent drain / source region being adjacent to the first shared drain / source region. The double-sided contact switch also includes a second shared drain / source region of the multi-gate active device, the second shared drain / source region being adjacent to the first independent drain / source region. The double-sided contact switch includes gate regions between the first independent drain / source region and the first shared drain / source region, and between the second independent drain / source region and the second shared drain / source region.

[0008] A method for manufacturing a double-sided contact switch includes forming a first independent drain / source region of a multi-gate active device. The method also includes forming a first shared drain / source region of the multi-gate active device. The method also includes forming a second independent drain / source region of the multi-gate active device, the second independent drain / source region being adjacent to the first shared drain / source region. The method also includes forming a second shared drain / source region of the multi-gate active device, the second shared drain / source region being adjacent to the first independent drain / source region. The method also includes forming gate regions between the first independent drain / source region and the first shared drain / source region, and between the second independent drain / source region and the second shared drain / source region.

[0009] A double-sided contact switch includes a first independent drain / source region of a multi-gate active device. The double-sided contact switch also includes a component for forming a portion of a first transistor and a second transistor. The multi-gate active device includes the first transistor and the second transistor. The double-sided contact switch also includes a second independent drain / source region of the multi-gate active device, the second independent drain / source region being adjacent to the transistor forming component. The double-sided contact switch includes a shared drain / source region of the multi-gate active device, the shared drain / source region being adjacent to the first independent drain / source region. The double-sided contact switch includes a gate region between the first independent drain / source region and the transistor forming component and between the second independent drain / source region and the shared drain / source region.

[0010] A radio frequency front-end module includes a double-sided contact switch having a first independent drain / source region of a multi-gate active device. The double-sided contact switch has a first shared drain / source region of the multi-gate active device. The double-sided contact switch also has a second independent drain / source region of the multi-gate active device, the second independent drain / source region being adjacent to the first shared drain / source region. The double-sided contact switch has a second shared drain / source region of the multi-gate active device, the second shared drain / source region being adjacent to the first independent drain / source region. The double-sided contact switch has a gate region between the first independent drain / source region and the first shared drain / source region. The double-sided contact switch also has a gate region between the second independent drain / source region and the second shared drain / source region. The radio frequency front-end module has an antenna coupled to the double-sided contact switch.

[0011] This has outlined rather broadly the features and technical advantages of the present disclosure so that the following detailed description may be better understood. Additional features and advantages of the present disclosure are described below. It will be appreciated by those skilled in the art that the present disclosure may readily serve as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the present disclosure in terms of its organization and method of operation, as well as other objects and advantages, will be better understood from the following description when considered in conjunction with the accompanying drawings. It will be expressly understood, however, that each of the figures in the accompanying drawings is provided for illustration and description purposes only and is not intended as a limitation upon the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a schematic diagram of a radio frequency (RF) front-end module.

[0014] Figures 2A to 2D A cross-sectional view of a radio frequency integrated circuit (RFIC) during a layer transfer process is shown.

[0015] Figure 3A Illustrated is a cross-section of a double-sided radio frequency switch according to aspects of the present disclosure.

[0016] Figure 3B Another cross-section of a double-sided radio frequency switch according to aspects of the present disclosure is illustrated.

[0017] Figure 3C Illustrated is a top view of a double-sided radio frequency switch having front-side contacts and back-side contacts configured according to a checkerboard layout, in accordance with aspects of the present disclosure.

[0018] Figure 4 is a process flow diagram illustrating a method of constructing a radio frequency integrated circuit switch using a bulk semiconductor layer transfer process according to aspects of the present disclosure.

[0019] Figure 5 is a block diagram illustrating an exemplary wireless communication system in which configurations of the present disclosure may be advantageously employed.

[0020] Figure 6 is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components according to one configuration of the present disclosure. DETAILED DESCRIPTION

[0021] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein may be practiced. The detailed description includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring these concepts.

[0022] As described herein, the use of the term "and / or" is intended to mean "inclusive OR", and the use of the term "or" is intended to mean "exclusive OR". As described herein, the term "exemplary" as used throughout this specification means "serving as an example, instance, or illustration", and is not necessarily to be construed as superior or preferable to other exemplary configurations. As described herein, the term "coupled" as used throughout this specification means "connected directly or indirectly through an intermediate connection (e.g., a switch), electrically, mechanically, or otherwise", and is not necessarily limited to physical connections. Additionally, these connections may cause the objects to be permanently connected or releasably connected. The connection may be through a switch. As described herein, the term "proximity" as used throughout this specification means "adjacent, very close, immediately adjacent, or close to". As described herein, the term "located on..." as used throughout this specification means "directly located on..." in some configurations and "indirectly located on..." in other configurations.

[0023] It should be understood that, unless otherwise specified, the term "layer" includes films and should not be interpreted as indicating vertical thickness or horizontal thickness. As described herein, the term "substrate" may refer to the substrate of a cut wafer or may refer to the substrate of an uncut wafer. Likewise, the terms chip and die may be used interchangeably.

[0024] Silicon-on-insulator (SOI) technology refers to the use of layered silicon-insulator-silicon substrates instead of traditional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and improve performance. Integrated circuits built using SOI devices can process approximately thirty percent (30%) faster than comparable bulk-based integrated circuits and consume up to eighty percent (80%) less power, making them ideal for mobile devices. SOI chips also reduce soft error rates, which are data corruption caused by cosmic rays and natural radioactive background signals. SOI transistors offer a unique opportunity to make CMOS architectures more scalable.

[0025] In some examples, a layer transfer process transfers the top active device portion of the SOI wafer to a handle wafer. In this process, the top of the SOI wafer is bonded to the handle wafer, and the bulk substrate layer (sacrificial substrate) of the SOI wafer is removed. In addition to the front-side connection system, the process can also form a back-side connection system. For example, the back insulating layer can be thinned. Openings can be formed in the back insulating layer so that back-side contacts can be formed to connect to devices, such as the source, drain, and / or body of a metal oxide semiconductor field effect transistor (MOSFET). In addition, one or more metal layers and vias can be formed on the back insulating layer to route power, ground, and / or signals to the device. Compared to the front-side contacts and metal layers and vias in the front-side connection system, the back-side contacts and one or more metal layers and vias form a back-side connection system. Source silicide and drain silicide are typically specified to facilitate good connection between the front-side connection system or the back-side connection system and the device.

[0026] RF switching devices for mobile RF transceivers can be fabricated using CMOS transistors on SOI wafers. Unfortunately, successfully fabricating CMOS transistors using SOI technology is complicated by parasitic capacitance. For example, parasitic capacitance in the form of contact / interconnect-to-gate capacitance can arise from the proximity between back-end-of-line (BEOL) interconnects / middle-of-line (MOL) contacts and the transistor gate. This parasitic capacitance can adversely affect the performance of CMOS devices, leading to circuit delays and losses. This parasitic capacitance is particularly problematic for RF switching devices.

[0027] Aspects of the present disclosure provide techniques for balancing capacitance in a double-sided contact switch (eg, an RF switch).The semiconductor manufacturing process flow for a double-sided contact switch may include front-end-of-line (FEOL) processes, MOL processes, and BEOL processes.

[0028] The MOL process is a collection of process steps that enable the connection of transistors to back-end-of-line (BEOL) interconnects (e.g., M1, M2, etc.) using MOL contacts. For example, parasitic capacitance in the form of contact / interconnect-to-gate capacitance is caused by the proximity of the BEOL interconnect / MOL contact to the transistor gate, drain, and source regions. The asymmetry of parasitic capacitance adversely affects CMOS transistors, resulting in circuit delays and losses, which is particularly problematic for RF switching devices. The layer transfer process can reduce the added capacitance by moving some wiring from the front side of the RF integrated circuit to the back side. However, moving some wiring may not be enough to address the asymmetry of parasitic capacitance and series resistance.

[0029] To improve the quality factor of the switch, the source and drain of the switch can have contacts on different or opposite sides of the switch (e.g., front and back). Having contacts on opposite sides of the switch reduces coupling capacitance, thereby improving (e.g., reducing) the quality factor of the switch. When turned off, the total capacitance of the transistor between the source and drain is the contribution of the source-to-gate capacitance, the drain-to-gate capacitance, the source-to-channel capacitance, and the drain-to-channel capacitance. The product of the stack's ON mode resistance (Ron) and OFF mode capacitance (Coff) in the RF domain yields a quality factor (Ron*Coff), which represents the RF performance of the switch.

[0030] Having one contact on the drain of the switch / on a first side of the switch and another contact on the source of the switch on the opposite side introduces asymmetry. The parasitic environment introduced when the source is coupled to the gate is different from the parasitic environment introduced when the drain is coupled to the gate. For example, the asymmetry may be due to a difference in the sum of the parasitic capacitances on the front side of the switch and the sum of the parasitic capacitances on the back side of the switch.

[0031] While asymmetry improves the switch's quality factor in this case, there is a trade-off with the switch's linear performance. For example, a switch operating in an asymmetric environment exhibits undesirable nonlinear characteristics that adversely affect the switch's performance. Undesirable nonlinear characteristics may include harmonic distortion, such as second harmonic distortion. Therefore, while an asymmetric implementation improves the quality factor, the switch's performance is degraded due to second harmonic distortion.

[0032] Other implementations achieve symmetry by having contacts for the source and drain on the same side of the switch. While these implementations reduce nonlinearity, the quality factor of these implementations is reduced. Therefore, it is desirable to introduce switches with improved quality factor and improved linearity.

[0033] Various aspects of the present disclosure relate to an integrated circuit (e.g., a double-sided radio frequency switch) with improved quality factor and improved linearity. The double-sided radio frequency switch balances capacitance and / or series resistance between conductive (metal) layers of the integrated circuit. The double-sided radio frequency switch is a multi-gate active device.

[0034] In one aspect, a double-sided RF switch includes a multi-gate active device comprising a first non-shared / independent drain / source region, a first shared drain / source region, a second independent drain / source region, a second shared drain / source region, a third independent drain / source region, and a third shared drain / source region. The shared drain / source regions and the independent drain / source regions are arranged in a checkerboard pattern. For example, the shared drain / source regions and the independent drain / source regions are alternately arranged to form a checkerboard pattern.

[0035] The first shared drain / source region is located between the first independent drain / source region and the second independent drain / source region and can be associated with the first active device and the second active device. For example, the first shared drain / source region is shared between the first active device and the second active device. Thus, the first independent drain / source region and at least a portion of the first shared drain / source region can be used to form the first active device. The second independent drain / source region and at least another portion of the first shared drain / source region can be used to form the second active device.

[0036] The third independent drain / source region is located between the second shared drain / source region and the third shared drain / source region. For example, the second shared drain / source region is shared between the third active device and another active device. Therefore, the third independent drain / source region and at least a portion of the second shared drain / source region can form a third active device. Similarly, the third shared drain / source region is shared between a fourth active device and yet another active device. Therefore, the third independent drain / source region and at least a portion of the third shared drain / source region can be used to form a fourth active device.

[0037] The double-sided RF switch also includes a first front-side conductive contact or interconnect located on the first independent drain / source region and a second front-side contact located on the second independent drain / source region. The double-sided RF switch also includes a first back-side contact located on the first shared drain / source region. Thus, the first back-side contact is a shared source / drain contact. For example, the first back-side contact is shared between the first active device and the second active device. In one aspect of the present disclosure, the double-sided RF switch includes a conductive bridge that connects the first front-side conductive contact or interconnect to the second front-side conductive contact.

[0038] The double-sided RF switch also includes a third front-side conductive contact located on the third independent drain / source region. The double-sided RF switch also includes a second back-side contact located on the second shared drain / source region and a third back-side contact located on the third shared drain / source region. Thus, the second back-side contact is a shared source / drain contact shared between the third active device and another active device. The third back-side contact is also a shared source / drain contact shared between the fourth active device and yet another active device. Similar to the shared drain / source region and the independent drain / source regions, the front-side and back-side contacts are arranged in a checkerboard pattern.

[0039] Figure 1 1 is a schematic diagram of a wireless device 100 (e.g., a cellular phone or smartphone) including a dual-sided RF switch implemented according to aspects of the present disclosure. Thus, the wireless device 100 benefits from the advantages of a dual-sided RF switch. The wireless device 100 may include a wireless local area network (WLAN) (e.g., WiFi) module 150 and an RF front-end module 170 for a chipset 110. The WiFi module 150 includes a first duplexer 160 that communicatively couples an antenna 162 to the wireless local area network module (e.g., WLAN module 152). The RF front-end module 170 includes a second duplexer 190 that communicatively couples an antenna 192 to a wireless transceiver 120 (WTR) via a duplexer 180 (DUP).

[0040] The wireless transceiver 120 and WLAN module 152 of the WiFi module 150 are coupled to a modem 130 (MSM, e.g., a baseband modem), which is powered by the power supply 102 through a power management integrated circuit (PMIC) 140. The chipset 110 also includes capacitors 112 and 114, and inductor(s) 116 to provide signal integrity. The PMIC 140, modem 130, wireless transceiver 120, and WLAN module 152 each include capacitors (e.g., 142, 132, 122, and 154) and operate based on a clock 118. The geometry and arrangement of the various inductor and capacitor components in the chipset 110 can reduce electromagnetic coupling between the components.

[0041] The wireless transceiver 120 of the wireless device typically includes a mobile radio frequency (RF) transceiver to transmit and receive data for bidirectional communication. The mobile RF transceiver may include a transmit section for data transmission and a receive section for data reception. For data transmission, the transmit section may modulate an RF carrier signal with data to obtain a modulated RF signal, amplify the modulated RF signal using a power amplifier (PA) to obtain an amplified RF signal with an appropriate output power level, and then transmit the amplified RF signal to the base station via antenna 192. For data reception, the receive section may obtain a received RF signal via antenna 192, amplify the received RF signal using a low noise amplifier (LNA), and process the received RF signal to recover the data sent by the base station in the communication signal.

[0042] The wireless transceiver 120 may include one or more circuits for amplifying these communication signals. The amplifier circuit (e.g., LNA / PA) may include one or more amplifier stages, which may have one or more driver stages and one or more amplifier output stages. Each of the amplifier stages includes one or more transistors configured in various ways to amplify the communication signals. There are various options for manufacturing transistors configured to amplify the communication signals transmitted and received by the wireless transceiver 120.

[0043] The wireless transceiver 120 and the RF front-end module 170 may be implemented using a layer transfer process to further separate the active devices from the substrate, such as Figures 2A to 2D shown.

[0044] Figures 2A to 2D 1 shows a cross-sectional view of a radio frequency (RF) integrated circuit 200 during a layer transfer process according to aspects of the present disclosure. Figure 2A As shown, an RF device includes an active device 210 located on an insulator layer 220 supported by a sacrificial substrate 201 (e.g., a bulk wafer). The RF device also includes an interconnect 250 coupled to the active device 210 within a first dielectric layer 204. Figure 2B As shown, a handle substrate 202 is bonded to the first dielectric layer 204 of the RF device. Additionally, the sacrificial substrate 201 is removed. Removing the sacrificial substrate 201 using a layer transfer process enables the realization of a high-performance, low-parasitic RF device by increasing the dielectric thickness. In other words, the parasitic capacitance of an RF device is proportional to the dielectric thickness, which determines the distance between the active device 210 and the handle substrate 202.

[0045] like Figure 2C As shown, once the handling substrate 202 is fixed and the sacrificial substrate 201 is removed, the RF device is flipped over. Figure 2DAs shown, the post-layer transfer metallization process is performed using, for example, a regular complementary metal oxide semiconductor (CMOS) process.

[0046] The active device 210 on the insulator layer 220 (eg, BOX layer) may be a complementary metal oxide semiconductor (CMOS) transistor. The RF front end module 170 ( Figure 1 ) can rely on these high-performance CMOS RF switch technologies for successful operation.

[0047] Figure 3A A cross-section of a double-sided RF switch 300 according to aspects of the present disclosure is shown. The double-sided RF switch 300 can be manufactured using a layer transfer process. The double-sided RF switch 300 has a first side 337 (e.g., a front side) and a second side 339 (e.g., a back side) opposite the first side 337.

[0048] The double-sided RF switch 300 includes a first active device 331 (e.g., a transistor) and a second active device 333. Each active device has a gate region and a source / drain region. Therefore, the double-sided RF switch 300 is a multi-gate active device. The double-sided RF switch 300 also includes a first independent drain / source region 372, a first shared drain / source region 374, and a second independent drain / source region 376. The first shared drain / source region 374 is located between the first independent drain / source region 372 and the second independent drain / source region 376.

[0049] The first active device 331 of the double-sided RF switch 300 includes a first gate 356, a first independent drain / source region 372, at least a first portion of a first shared drain / source region 374, and a first channel 382 formed on the isolation layer 307. The first gate 356 has spacers 344a and 344b.

[0050] The second active device 333 of the double-sided RF switch 300 includes a second gate 358, a second independent drain / source region 376, at least a second portion of the first shared drain / source region 374, and a second channel 384 formed on the isolation layer 307. The second gate 358 has spacers 346a and 346b.

[0051] In an SOI implementation, the isolation layer 307 is a buried oxide (BOX) layer, and the body (e.g., including the first channel 382 and the second channel 384) and the source / drain regions (e.g., the first independent drain / source region 372, the first shared drain / source region 374, and the second independent drain / source region 376) are formed by an SOI layer (e.g., silicon) including a shallow trench isolation (STI) region.

[0052] One aspect of the present disclosure uses a silicidation process with layer transfer (e.g., a backside / frontside silicidation process) to form frontside / backside source / drain contacts. For example, a first frontside contact 364, a backside contact 366, and a second frontside contact 368 are formed on the first independent drain / source region 372, the first shared drain / source region 374, and the second independent drain / source region 376, respectively. A first gate contact 336 and a second gate contact 338 are formed on the first gate 356 and the second gate 358 of the double-sided RF switch 300, respectively. The first gate contact 336, the second gate contact 338, the first frontside contact 364, the backside contact 366, and the second frontside contact 368 can be silicide contacts.

[0053] In one aspect of the present disclosure, the backside contact 366 is a backside shared source / drain contact. For example, the backside contact 366 is shared between the first active device 331 and the second active device 333. This is because the first shared drain / source region 374 is a shared source / drain region for the first active device 331 and the second active device 333.

[0054] Double-sided RF switch 300 also includes a first front-side conductive contact or interconnect 324a coupled to first independent drain / source region 372 / first front-side contact 364, and a second front-side contact 326 located on second independent drain / source region 376 / second front-side contact 368. Double-sided RF switch 300 also includes a back-side contact 394a located on first shared drain / source region 374. As noted, first shared drain / source region 374 is a shared source / drain region, while first back-side contact 394a is a shared source / drain contact for first active device 331 and second active device 333.

[0055] The interconnects of the double-sided RF switch 300 may also include trench interconnects and vias for coupling active devices formed during the FEOL process to the metallization layers formed during the BEOL process. The front-side metallization layer is formed in the front-side dielectric layer 348, while the back-side metallization layer is formed in the back-side dielectric layer 378.

[0056] For example, a first front side conductive contact or interconnect 324a is connected or coupled to a first front side contact 364 formed on a first independent drain / source region 372. A second front side conductive contact 326 is connected or coupled to a second front side contact 368 formed on a second independent drain / source region 376. The first front side conductive contact 324a and the second front side conductive contact 326 couple the first active device 331 and the second active device 333, respectively, to metallization in the BEOL layer.

[0057] The double-sided RF switch 300 includes backside trench interconnects and / or vias 396a to couple the first active device 331 and the second active device 333 to backside metallization (e.g., a second conductive bridge 397). In one aspect, the backside trench interconnects and / or vias 396a are coupled to backside contacts 394a, which are shared between the first active device 331 and the second active device 333.

[0058] In addition, the double-sided RF switch 300 includes a first front-side trench interconnect and / or via 328a, a second front-side trench interconnect and / or via 329a, a third front-side trench interconnect and / or via 334a, and a fourth front-side trench interconnect and / or via 335a. The first front-side trench interconnect and / or via 328a couples the first front-side metallization M1 associated with the first active device 331 to the second front-side metallization M2 associated with the first active device 331. The second front-side trench interconnect and / or via 329a couples the second front-side metallization M2 associated with the first active device 331 to the third front-side metallization M3.

[0059] A third front-side trench interconnect and / or via 334a couples the first front-side metallization M1 associated with the second active device 333 to the second front-side metallization M2 associated with the second active device 333. A fourth front-side trench interconnect and / or via 335a couples the second front-side metallization M2 associated with the second active device 333 to the third front-side metallization M3. In one aspect of the present disclosure, the third front-side metallization M3 includes a first conductive bridge 388 shared by the first active device 331 and the second active device 333. For example, the first conductive bridge 388 couples the first active device 331 to the second active device 333 located on the front side 337 of the double-sided RF switch 300.

[0060] Figure 3B Another cross-section of a double-sided radio frequency switch 300 according to aspects of the present disclosure is illustrated. Figure 3B The cross section spans Figure 3A The cross section of the axis AA' is perpendicular to the axis BB', as shown Figure 3C For example, Figure 3B The cross section of FIG. 3 includes a plurality of first front side conductive contacts 324a, 324b, 324c, and 324d associated with a plurality of gates of the multi-gate active device. Each of the first front side conductive contacts 324a, 324b, 324c, and 324d is coupled to the first front side metallization M1.

[0061] Figure 3BThe cross-section of includes a plurality of first front side trench interconnects and / or vias 328a, 328b, and 328c. Each of the first front side trench interconnects and / or vias 328a, 328b, and 328c couples the first front side metallization M1 to the second front side metallization M2. Figure 3B The cross section of FIG4 also shows a plurality of second front side trench interconnects and / or vias 329a and 329b. Each of the second front side trench interconnects and / or vias 329a and 329b couples the second front side metallization M2 to the third front side metallization M3.

[0062] Figure 3B The cross-section of FIG. 1 also includes a plurality of backside contacts (e.g., a first backside contact 394a and a second backside contact 394b). A plurality of backside trench interconnects and / or vias 396a and 396b couple the first backside contact 394a and the second backside contact 394b, respectively, to backside metallization including a second conductive bridge 397. In one aspect, the second backside contact 394b is fabricated on a fourth drain / source region (not shown).

[0063] Figure 3C A top view of a double-sided RF switch having front-side contacts and back-side contacts arranged in a checkerboard layout is illustrated in accordance with aspects of the present disclosure. As noted, Figure 3B The cross section spans Figure 3A The cross-section is taken orthogonally to the axis BB' by the axis AA'.

[0064] The double-sided RF switch 300 includes a first set of front-side conductive contacts 325 in a first independent drain / source region 372, a second set of front-side conductive contacts 327 in a second independent drain / source region 376, and a third set of front-side conductive contacts 355 in a third independent drain / source region 365. The independent drain / source regions 372, 376, 365 are arranged in a checkerboard pattern or an alternative configuration. That is, the first set of front-side contacts, the second set of front-side contacts, and the third set of front-side contacts (and the independent drain / source regions) are offset from each other, as shown in FIG. Figure 3C The offset helps balance the capacitance and series resistance.

[0065] The double-sided RF switch 300 further includes a plurality of spacers 344a, 344b, 346a, and 346b. A first set of front-side conductive contacts 325 includes a plurality of first front-side conductive contacts for coupling a plurality of active devices to different metallization layers. A second set of front-side conductive contacts 327 and a third set of front-side conductive contacts 355 also include the same or different number of front-side conductive contacts as the first set of front-side conductive contacts 325.

[0066] In one aspect, a first set of front side conductive contacts 325 is associated with first independent drain / source region 372 and first front side contact 364. A second set of front side conductive contacts 327 is associated with second independent drain / source region 376 and second front side contact 368. A third set of front side conductive contacts 355 is associated with third independent drain / source region 365.

[0067] The double-sided RF switch 300 includes a first set of backside conductive contacts 357 located in a first shared drain / source region 374, a second set of backside conductive contacts 359 located in a second shared drain / source region 363, and a third set of backside conductive contacts 361 located in a third shared drain / source region 367. The first shared drain / source region 374 is connected to the third drain / source region 365 to form a continuous drain / source region. The first independent drain / source region 372 is connected to the second shared drain / source region 363 to form a continuous drain / source region. The second independent drain / source region 376 is connected to the third shared drain / source region 367 to form a continuous drain / source region. The backside contacts 394a and 394b of the first set of backside conductive contacts 357 are larger than the front side conductive contacts 324a, 324b, 324c and 324(b) of the first set of front side conductive contacts 325. Figure 3A and Figure 3B ), thereby facilitating asymmetric parasitics. The first set of backside conductive contacts, the second set of backside conductive contacts and the third set of backside conductive contacts (and the shared drain / source region) are arranged in a checkerboard or alternative layout, such as Figure 3C shown to help balance parasitics, such as capacitance and series resistance.

[0068] The first set of backside conductive contacts 357 includes a plurality of backside contacts 394a and 394b for coupling a plurality of active devices to different metallization layers. The second set of backside conductive contacts 359 and the third set of backside conductive contacts 361 also include a number of backside conductive contacts that is the same as or different from the number of the first set of backside conductive contacts 357.

[0069] A first gate contact 336 in the first gate region is located between the first independent drain / source region 372 and the first shared drain / source region 374. The first gate contact 336 is also located between the third independent drain / source region 365 and the second shared drain / source region 363. A second gate contact 338 in the second gate region is located between the second independent drain / source region 376 and the first shared drain / source region 374. The second gate contact 338 is also located between the third drain / source region 365 and the third shared drain / source region 367.

[0070] Figure 4is a process flow diagram illustrating a method 400 for manufacturing a double-sided contact switch according to one aspect of the present disclosure. In box 402, a first independent drain / source region of a multi-gate active device is formed. In box 404, a first shared drain / source region of the multi-gate active device is formed. In box 406, a second independent drain / source region of the multi-gate active device is formed, the second independent drain / source region being adjacent to the first shared drain / source region. In box 408, a second shared drain / source region of the multi-gate active device is formed, the second shared drain / source region being adjacent to the first independent drain / source region. In box 410, a gate region is formed between the first independent drain / source region and the first shared drain / source region. The gate region is also formed between the second independent drain / source region and the second shared drain / source region.

[0071] According to another aspect of the present disclosure, a double-sided contact switch is described. The double-sided contact switch includes a component for forming a portion of a first transistor and a portion of a second transistor. The transistor forming component may be a first shared drain / source region 374, such as Figure 3A 、 Figure 3B and Figure 3C In another aspect, the aforementioned components may be any module or any device configured to perform the functions recited by the aforementioned components.

[0072] Figure 5 is a block diagram illustrating an exemplary wireless communication system 500 in which aspects of the present disclosure may be advantageously employed. For illustrative purposes, Figure 5 Three remote units 520, 530, and 550 and two base stations 540 are shown. It should be appreciated that a wireless communication system can have many more remote units and base stations. Remote units 520, 530, and 550 include IC devices 525A, 525C, and 525B that include the disclosed double-sided contact switches. It should be appreciated that other devices can also include the disclosed double-sided contact switches, such as base stations, switching equipment, and network equipment. Figure 5 Forward link signals 580 from base station 540 to remote units 520, 530, and 550 and reverse link signals 590 from remote units 520, 530, and 550 to base station 540 are shown.

[0073] exist Figure 5, remote unit 520 is shown as a mobile phone, remote unit 530 is shown as a portable computer, and remote unit 550 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote unit may be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit such as a personal digital assistant (PDA), a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed location data unit such as a meter reading device, or other communication device that stores or retrieves data or computer instructions, or a combination thereof. Although Figure 5 Remote units according to aspects of the present disclosure are illustrated, but the present disclosure is not limited to these exemplary illustrated units.Aspects of the present disclosure may be applicable to many devices that include the disclosed double-sided contact switches.

[0074] Figure 6 6 is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components, such as the RF devices disclosed above. Design workstation 600 includes a hard disk 601 containing operating system software, support files, and design software such as Cadence or OrCAD. Design workstation 600 also includes a display 602 that facilitates a circuit design 610 or a double-sided contact switch design 612. A storage medium 604 is provided for tangibly storing circuit design 610 or double-sided contact switch design 612. Circuit design 610 or double-sided contact switch design 612 can be stored on storage medium 604 in a file format such as GDSII or GERBER. Storage medium 604 can be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. Further, design workstation 600 includes a drive 603 for receiving input from storage medium 604 or writing output to storage medium 604.

[0075] The data recorded on storage medium 604 may specify a logic circuit configuration, pattern data for a photolithography mask, or mask pattern data for a serial write tool such as electron beam lithography. The data may also include logic verification data, such as timing diagrams or network circuits associated with logic simulations. Providing data on storage medium 604 facilitates circuit design 610 or double-sided contact switch design 612 by reducing the number of processes used to design semiconductor wafers.

[0076] For firmware and / or software implementations, the method can be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described herein. A machine-readable medium tangibly embodying instructions can be used to implement the methods described herein. For example, software code can be stored in a memory and executed by a processor unit. The memory can be implemented within the processor unit or external to the processor unit. As used herein, the term "memory" refers to long-term, short-term, volatile, non-volatile, or other types of memory, and is not limited to a particular type of memory or the number of memories or the type of medium on which the memory is stored.

[0077] If implemented in firmware and / or software, the functions may be stored as one or more instructions or codes on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media include physical computer storage media. A storage medium may be a usable medium that is accessible to a computer. By way of example and not limitation, such computer-readable media encompasses RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other media that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; as used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0078] In addition to being stored on a computer-readable medium, the instructions and / or data may be provided as signals on a transmission medium included in a communication device. For example, the communication device may include a transceiver that carries signals indicating the instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

[0079] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made herein without departing from the technology of the present disclosure as defined by the appended claims. For example, relative terms such as "above" and "below" are used with respect to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, the above becomes the below, and vice versa. Additionally, if positioned laterally, the above and below can refer to the sides of the substrate or electronic device. Moreover, the scope of this application is not intended to be limited to the specific configurations of the processes, machines, manufactures and material compositions, means, methods and steps described in the specification. As should be readily understood by those skilled in the art based on this disclosure, processes, machines, manufactures, material compositions, means, methods or steps that currently exist or are developed in the future to perform substantially the same functions or achieve substantially the same results as the corresponding configurations described herein can be utilized according to this disclosure. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, means, methods or steps within their scope.

Claims

1. A double-sided contact switch, comprising: a first independent drain / source region of a multi-gate active device; a first shared drain / source region of the multi-gate active device; a second independent drain / source region of the multi-gate active device, the second independent drain / source region being adjacent to the first shared drain / source region; a second shared drain / source region of the multi-gate active device, the second shared drain / source region being adjacent to the first independent drain / source region; a gate region located between the first independent drain / source region and the first shared drain / source region, and between the second independent drain / source region and the second shared drain / source region; a first front-side contact coupled to the first independent drain / source region; a first backside contact coupled to the first shared drain / source region; a second front-side contact coupled to the second independent drain / source region; as well as A second backside contact is coupled to the second shared drain / source region. 2 . The double-sided contact switch of claim 1 , wherein the first front-side contact, the first back-side contact, the second front-side contact, and the second back-side contact comprise silicide.

3. The double-sided contact switch according to claim 1 , further comprising: a third independent drain / source region of the multi-gate active device, the third independent drain / source region coupled to a third front-side contact; as well as A first conductive bridge couples the first front side contact and the third front side contact. 4 . The double-sided contact switch of claim 1 , wherein the first transistor includes the first independent drain / source region, at least a portion of the first shared drain / source region, and a first gate between the first independent drain / source region and the first shared drain / source region. 5 . The double-sided contact switch of claim 1 , wherein the double-sided contact switch comprises a radio frequency (RF) double-sided contact switch.

6. A method for manufacturing a double-sided contact switch, comprising: forming a first independent drain / source region of a multi-gate active device; forming a first shared drain / source region of the multi-gate active device; forming a second independent drain / source region of the multi-gate active device, the second independent drain / source region being adjacent to the first shared drain / source region; forming a second shared drain / source region of the multi-gate active device, the second shared drain / source region being adjacent to the first independent drain / source region; forming a gate region between the first independent drain / source region and the first shared drain / source region, and between the second independent drain / source region and the second shared drain / source region; fabricating a first front side contact, the first front side contact coupled to the first independent drain / source region; fabricating a first backside contact, the first backside contact coupled to the first shared drain / source region; forming a second front-side contact coupled to the second independent drain / source region; as well as A second backside contact is fabricated, the second backside contact being coupled to the second shared drain / source region.

7. The method according to claim 6, further comprising: forming a third independent drain / source region of the multi-gate active device, the third independent drain / source region being coupled to a third front-side contact; as well as A first conductive bridge is fabricated to couple the first front side contact and the third front side contact.

8. A double-sided contact switch comprising: a first independent drain / source region of a multi-gate active device; a transistor forming part for forming a portion of the first transistor and the second transistor; The multi-gate active device includes the first transistor and the second transistor; a second independent drain / source region of the multi-gate active device, the second independent drain / source region being adjacent to the transistor forming feature; a shared drain / source region of the multi-gate active device, the shared drain / source region being adjacent to the first independent drain / source region; a gate region between the first independent drain / source region and the transistor forming part, and between the second independent drain / source region and the shared drain / source region; a first front-side contact coupled to the first independent drain / source region; a first backside contact coupled to the transistor-forming feature; a second front-side contact coupled to the second independent drain / source region; as well as A second backside contact is coupled to the shared drain / source region. 9 . The double-sided contact switch of claim 8 , wherein the first front side contact, the first back side contact, the second front side contact, and the second back side contact comprise silicide.

10. The double-sided contact switch according to claim 8, further comprising: a third independent drain / source region of the multi-gate active device, the third independent drain / source region coupled to a third front-side contact; as well as A first conductive bridge couples the first front side contact and the third front side contact. 11 . The double-sided contact switch according to claim 8 , wherein the first transistor includes the first independent drain / source region, at least a portion of the transistor forming part, and a first gate between the first independent drain / source region and the transistor forming part.

12. The double-sided contact switch of claim 8, wherein the double-sided contact switch comprises a radio frequency (RF) double-sided contact switch.

13. A radio frequency front-end module, comprising: A double-sided contact switch having a first independent drain / source region of a multi-gate active device, a first shared drain / source region of the multi-gate active device, a second independent drain / source region of the multi-gate active device adjacent to the first shared drain / source region, a second shared drain / source region of the multi-gate active device adjacent to the first independent drain / source region, and gate regions between the first independent drain / source region and the first shared drain / source region and between the second independent drain / source region and the second shared drain / source region; a first front-side contact coupled to the first independent drain / source region; a first backside contact coupled to the first shared drain / source region; a second front-side contact coupled to the second independent drain / source region; as well as a second backside contact coupled to the second shared drain / source region An antenna is coupled to the double-sided contact switch. 14 . The RF front-end module of claim 13 , wherein the first front-side contact, the first back-side contact, the second front-side contact, and the second back-side contact comprise silicide.

15. The RF front-end module according to claim 13, wherein the double-sided contact switch further comprises: a third independent drain / source region of the multi-gate active device, the third independent drain / source region coupled to a third front-side contact; as well as A first conductive bridge couples the first front side contact and the third front side contact.

16. The RF front-end module according to claim 13, wherein the first transistor includes the first independent drain / source region, at least a portion of the first shared drain / source region, and a first gate between the first independent drain / source region and the first shared drain / source region.

Images