Detection and gating module, battery management system and battery management chip

Abstract

The present disclosure provides a detection and gating module in a battery management system for selecting and detecting the voltage of each battery in a battery pack of N serially connected batteries, where N≥1, including: N gating switches, where the i-th gating switch is respectively connected to the positive terminal of the i-th battery among the N batteries, and when the i-th gating switch is turned on, the voltage of the i-th battery is detected, where 1≤i≤N; N protection circuits, where the i-th protection circuit is used to protect the i-th gating switch among the N gating switches; and N voltage generation circuits, where the i-th voltage generation circuit is used to generate a conduction voltage that turns on the i-th gating switch among the N gating switches and a turn-off voltage that turns off the i-th gating switch. The present disclosure also provides a battery management system and a battery management chip.

Description

Technical Field

[0001] The present disclosure relates to a detection gating module, a battery management system, and a battery management chip. Background Art

[0002] In a battery management system, it is necessary to measure the voltage of each battery cell. Usually, a gating circuit is used to select the battery cell to be measured, and then an analog-to-digital converter converts the collected voltage into a digital signal and provides it to a controller. The controller manages the battery based on the collected voltage signal, for example, can control the charge and discharge switches, etc.

[0003] In the present disclosure, technical solutions are proposed to solve the technical problem of how to accurately control the gating circuit so as to reliably measure the voltage of each battery cell. Summary of the Invention

[0004] To solve one of the above technical problems, the present disclosure provides a detection gating module, a battery management system, and a battery management chip.

[0005] According to one aspect of the present disclosure, a detection gating module in a battery management system, the detection gating module is used to select and detect the voltage of each battery cell in a battery pack of N series-connected battery cells, where N≥1, and includes:

[0006] N gating switches, the i-th gating switch among the N gating switches is respectively connected to the positive terminal of the i-th battery among the N battery cells. When the i-th gating switch is turned on, the voltage of the i-th battery is detected, where 1≤i≤N;

[0007] N protection circuits, the i-th protection circuit among the N protection circuits is used to protect the i-th gating switch among the N gating switches; and

[0008] N voltage generation circuits, the i-th voltage generation circuit among the N voltage generation circuits is used to generate a conduction voltage that turns on the i-th gating switch among the N gating switches and a turn-off voltage that turns off the i-th gating switch.

[0009] According to the detection gating module of at least one embodiment of the present disclosure, when detecting the battery voltage of the i-th battery cell, the voltage across the two ends of the i-th battery cell is detected by turning on the i-th gating switch and the (i - 1)-th gating switch.

[0010] The detection gating module according to at least one embodiment of the present disclosure, wherein the i-th gating switch includes a first transistor and a second transistor, wherein the drain of the first transistor is connected to the battery voltage of the positive terminal of the i-th battery, and the source of the first transistor is connected to the source of the second transistor, the gates of the first transistor and the second transistor are connected, and the drain of the second transistor outputs the sampled battery voltage.

[0011] The detection gating module according to at least one embodiment of the present disclosure, wherein the i-th protection circuit is a protection diode, the cathode of the i-th protection diode is connected to the sources of the first transistor and the second transistor of the i-th gating switch, and the anode of the i-th protection diode is connected to the gates of the first transistor and the second transistor of the i-th gating switch.

[0012] The detection gating module according to at least one embodiment of the present disclosure, when detecting the voltage of the i-th battery, a control voltage higher than the battery voltage of the positive terminal of the i-th battery by a predetermined voltage value is generated by the i-th voltage generation circuit to turn on the first transistor and the second transistor of the i-th gating switch, and a control voltage higher than the battery voltage of the positive terminal of the (i - 1)-th battery by a predetermined voltage value is generated by the (i - 1)-th voltage generation circuit to turn on the first transistor and the second transistor of the (i - 1)-th gating switch;

[0013] When not detecting the voltage of the i-th battery, a control voltage lower than the battery voltage of the positive terminal of the i-th battery is generated by the i-th voltage generation circuit to turn off the first transistor and the second transistor of the i-th gating switch, and a control voltage lower than the battery voltage of the positive terminal of the (i - 1)-th battery is generated by the (i - 1)-th voltage generation circuit to turn off the first transistor and the second transistor of the (i - 1)-th gating switch.

[0014] The detection gating module according to at least one embodiment of the present disclosure, when detecting the voltage of the i-th battery, a conduction voltage that turns on the first transistor and the second transistor of the i-th gating switch is generated by the i-th voltage generation circuit, and a conduction voltage that turns on the first transistor and the second transistor of the (i - 1)-th gating switch is generated by the (i - 1)-th voltage generation circuit;

[0015] When not detecting the voltage of the i-th battery, a turn-off voltage that turns off the first transistor and the second transistor of the i-th gating switch is generated by the i-th voltage generation circuit, and a turn-off voltage that turns off the first transistor and the second transistor of the (i - 1)-th gating switch is generated by the (i - 1)-th voltage generation circuit.

[0016] The detection gating module according to at least one embodiment of the present disclosure, wherein the i-th voltage generation circuit includes a capacitor, and the control voltage is provided by charging and discharging the capacitor, so that the first transistor and the second transistor of the i-th gating switch are turned on or off.

[0017] The detection gating module according to at least one embodiment of the present disclosure, wherein the i-th voltage generation circuit includes:

[0018] The drain of the first NMOS transistor is connected to the highest voltage of the battery pack, the gate of the first NMOS transistor is connected to the battery voltage of the positive terminal of the i-th battery, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the source of the first NMOS transistor is connected to the cathode of the second diode, the gate of the first NMOS transistor is connected to the anode of the second diode, the source of the second NMOS transistor is grounded, the drain of the third NMOS transistor is connected to a constant current source, the drain and the gate of the third NMOS transistor are connected, the gate of the third NMOS transistor is connected to one end of the first switch, the other end of the first switch is connected to the gate of the second NMOS transistor, the gate of the second NMOS transistor is connected to one end of the second switch, the other end of the second switch is grounded, the drain of the third NMOS transistor is connected to one end of the third switch, the other end of the third switch is connected to the gate of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the gate of the fourth NMOS transistor is connected to one end of the fourth switch, and the other end of the fourth switch is grounded, the gate of the first PMOS transistor is connected to the source of the first NMOS transistor, the source of the first PMOS transistor is connected to the battery voltage of the positive terminal of the i-th battery, the drain of the first PMOS transistor is connected to the drain of the fourth NMOS transistor, and the drain of the fourth NMOS transistor is connected to the lower plate of the capacitor, the upper plate of the capacitor is connected to the anode of the first diode, the cathode of the first diode is connected to the supply voltage, and the upper plate of the capacitor is connected to the anode of the protection diode.

[0019] The detection gating module according to at least one embodiment of the present disclosure, wherein the i-th voltage generation circuit includes:

[0020] The drain of the first NMOS transistor is connected to the highest voltage of the battery pack. The gate of the first NMOS transistor is connected to the battery voltage at the positive terminal of the i-th battery cell. The source of the first NMOS transistor is connected to the cathode of the first diode. The gate of the first NMOS transistor is connected to the anode of the first diode. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The source of the second NMOS transistor is grounded. The drain of the third NMOS transistor is connected to a constant current source. The drain and the gate of the third NMOS transistor are connected. The gate of the third NMOS transistor is connected to one end of the first switch. The other end of the first switch is connected to the gate of the second NMOS transistor. The gate of the second NMOS transistor is connected to one end of the second switch. The other end of the second switch is grounded. The drain of the third NMOS transistor is connected to one end of the third switch. The other end of the third switch is connected to the gate of the fourth NMOS transistor. The source of the fourth NMOS transistor is grounded. The gate of the fourth NMOS transistor is connected to one end of the fourth switch. And the other end of the fourth switch is grounded. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor. And the gate of the first PMOS transistor is connected to the drain of the first PMOS transistor. The source of the first PMOS transistor and the source of the second PMOS transistor are connected to the highest voltage of the battery pack. The drain of the first PMOS transistor is connected to the drain of the fourth NMOS transistor. The drain of the second PMOS transistor is connected to the source of the third PMOS transistor. The gate of the third PMOS transistor is connected to the battery voltage at the positive terminal of the i-th battery cell. The drain of the third PMOS transistor is grounded. The drain of the second NMOS transistor is connected to the anode of the protection diode. The source of the third PMOS transistor is connected to the anode of the protection diode.

[0021] According to the detection gating module of at least one embodiment of the present disclosure, the i-th voltage generation circuit includes a fifth NMOS transistor. The drain of the fifth NMOS transistor is connected to the gates of the first transistor and the second transistor. The source of the fifth NMOS transistor is connected to the sources of the first transistor and the second transistor. The gate and the drain of the fifth NMOS transistor are connected. By turning on or off the fifth NMOS transistor, the control voltage is provided to turn on or off the first transistor and the second transistor of the i-th gating switch.

[0022] According to the detection gating module of at least one embodiment of the present disclosure, the i-th voltage generation circuit includes:

[0023] The sources of the first PMOS transistor and the second PMOS transistor are connected to the highest voltage of the battery pack. The gate and the drain of the first PMOS transistor are connected, and the gates of the first PMOS transistor and the second PMOS transistor are connected to form a mirror circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is connected to a constant current source, and the drain and the gate of the second NMOS transistor are connected. The source of the second NMOS transistor is grounded. The gate of the second NMOS transistor is connected to one end of a first switch, and the other end of the first switch is connected to the gate of the first NMOS transistor. One end of a second switch is connected to the gate of the first NMOS transistor, and the other end of the second switch is grounded. The drain of the second NMOS transistor is connected to one end of a third switch, and the other end of the third switch is connected to the gate of a third NMOS transistor. One end of a fourth switch is connected to the gate of the third NMOS transistor, and the other end of the fourth switch is grounded. The drain of the second NMOS transistor is connected to one end of a fifth switch, and the other end of the fifth switch is connected to the gate of a fourth NMOS transistor. One end of a sixth switch is connected to the gate of the fourth NMOS transistor, and the other end of the sixth switch is grounded. The drain of the third NMOS transistor is connected to the source of a fifth NMOS transistor and is connected to the sources of the first transistor and the second transistor. The drain of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor and is connected to the gates of the first transistor and the second transistor. The drain of the second PMOS transistor is connected to the drain of the fifth NMOS transistor, and the gate and the drain of the fifth NMOS transistor are connected.

[0024] For the detection gating module according to at least one embodiment of the present disclosure, the i-th voltage generation circuit includes a third PMOS transistor. The source of the third PMOS transistor is connected to the gates of the first transistor and the second transistor. The drain of the fifth NMOS transistor is connected to the sources of the first transistor and the second transistor. The gate and the drain of the third PMOS transistor are connected. The control voltage is provided by turning on or off the third PMOS transistor, so that the first transistor and the second transistor of the i-th gating switch are turned on or off.

[0025] For the detection gating module according to at least one embodiment of the present disclosure, the i-th voltage generation circuit includes:

[0026] The sources of the first PMOS transistor and the second PMOS transistor are connected to the highest voltage of the battery pack. The gate and drain of the first PMOS transistor are connected, and the gates of the first PMOS transistor and the second PMOS transistor are connected to form a mirror circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is connected to a constant current source, and the drain and gate of the second NMOS transistor are connected. The source of the second NMOS transistor is grounded. The gate of the second NMOS transistor is connected to one end of the first switch, and the other end of the first switch is connected to the gate of the first NMOS transistor. One end of the second switch is connected to the gate of the first NMOS transistor, and the other end of the second switch is grounded. The drain of the second NMOS transistor is connected to one end of the third switch, and the other end of the third switch is connected to the gate of the third NMOS transistor. One end of the fourth switch is connected to the gate of the third NMOS transistor, and the other end of the fourth switch is grounded. The drain of the second NMOS transistor is connected to one end of the fifth switch, and the other end of the fifth switch is connected to the gate of the fourth NMOS transistor. One end of the sixth switch is connected to the gate of the fourth NMOS transistor, and the other end of the sixth switch is grounded. The drain of the third NMOS transistor is connected to the drain of the third PMOS transistor and to the sources of the first transistor and the second transistor. The drain of the fourth NMOS transistor is connected to the source of the third PMOS transistor and to the gates of the first transistor and the second transistor. The drain of the second PMOS transistor is connected to the source of the third PMOS transistor. The gate and drain of the third PMOS transistor are connected.

[0027] According to the detection gating module of at least one embodiment of the present disclosure, the i-th voltage generation circuit is the protection diode. When the protection diode is reversely broken down, the control voltage is provided through the reverse breakdown voltage, so that the first transistor and the second transistor of the i-th gating switch are turned on or off.

[0028] According to the detection gating module of at least one embodiment of the present disclosure, the i-th voltage generation circuit includes:

[0029] The sources of the first PMOS transistor and the second PMOS transistor are connected to the highest voltage of the battery pack. The gate and drain of the first PMOS transistor are connected, and the gates of the first PMOS transistor and the second PMOS transistor are connected to form a mirror circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is connected to a constant current source, and the drain and gate of the second NMOS transistor are connected. The source of the second NMOS transistor is grounded. The gate of the second NMOS transistor is connected to one end of a first switch, and the other end of the first switch is connected to the gate of the first NMOS transistor. One end of a second switch is connected to the gate of the first NMOS transistor, and the other end of the second switch is grounded. The drain of the second NMOS transistor is connected to one end of a third switch, and the other end of the third switch is connected to the gate of a third NMOS transistor. One end of a fourth switch is connected to the gate of the third NMOS transistor, and the other end of the fourth switch is grounded. The drain of the second NMOS transistor is connected to one end of a fifth switch, and the other end of the fifth switch is connected to the gate of a fourth NMOS transistor. One end of a sixth switch is connected to the gate of the fourth NMOS transistor, and the other end of the sixth switch is grounded. The drain of the third NMOS transistor is connected to the sources of a first transistor and a second transistor. The drain of the fourth NMOS transistor is connected to the gates of the first transistor and the second transistor. The drain of the second PMOS transistor is connected to the gates of the first transistor and the second transistor.

[0030] According to another aspect of the present disclosure, a battery management system includes:

[0031] The detection gating module as described above, where the detection is used to select and detect the voltage of each battery in a battery pack of N series-connected batteries; and

[0032] A voltage amplification module, which is used to receive the voltage of each battery output by the detection gating module, so as to amplify and output the voltage of each battery.

[0033] The battery management system according to at least one embodiment of the present disclosure further includes:

[0034] An analog-to-digital conversion module, which is used to perform analog-to-digital conversion on the voltage of each battery from the voltage amplification module;

[0035] A control logic module, which is used to receive the battery voltage converted by the analog-to-digital conversion module, and at least provide a control signal to the switch driving module according to the converted battery voltage, so as to control the conduction or cutoff of the discharge switch and the charging switch through the switch driving module.

[0036] According to another aspect of the present disclosure, a battery management chip integrates the battery management system as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, are used to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in this specification and form a part of this specification.

[0038] Figure 1 FIG. shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

[0039] Figure 2 FIG. shows a schematic diagram of a gating detection module according to an embodiment of the present disclosure.

[0040] Figure 3 FIG. shows a schematic diagram of a gating detection switch and control according to an embodiment of the present disclosure.

[0041] Figure 4 FIG. shows a circuit diagram of an example of a gating detection switch and control according to an embodiment of the present disclosure.

[0042] Figure 5 FIG. shows a circuit diagram of an example of a gating detection switch and control according to an embodiment of the present disclosure.

[0043] Figure 6 FIG. shows a circuit diagram of an example of a gating detection switch and control according to an embodiment of the present disclosure.

[0044] Figure 7 FIG. shows a circuit diagram of an example of a gating detection switch and control according to an embodiment of the present disclosure.

[0045] Figure 8 FIG. shows a circuit diagram of an example of a gating detection switch and control according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] The present disclosure will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only for explaining the relevant content and not for limiting the present disclosure. Additionally, it should be noted that for the convenience of description, only parts related to the present disclosure are shown in the drawings.

[0047] It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. The technical solutions of the present disclosure will be described in detail below with reference to the drawings and embodiments.

[0048] Unless otherwise specified, the illustrated exemplary embodiments are to be understood as providing exemplary features of various details of some ways in which the technical conceptions of the present disclosure can be implemented in practice. Accordingly, unless otherwise specified, the features of the various embodiments can be additionally combined, separated, interchanged, and / or rearranged without departing from the technical conceptions of the present disclosure.

[0049] In the drawings, cross-hatching and / or shading are generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement regarding the specific materials, material properties, dimensions, proportions, commonalities between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. Additionally, in the drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process orders may be performed in an order different from that described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to that described. Further, like reference numerals denote like components.

[0050] When a component is referred to as being “on” or “above” another component, “connected to” or “coupled to” another component, the component can be directly on, directly connected to, or directly coupled to the other component, or there can be intervening components. However, when a component is referred to as being “directly on” another component, “directly connected to” or “directly coupled to” another component, there are no intervening components. To this end, the term “connected” can refer to a physical connection, an electrical connection, etc., and can have or not have intervening components.

[0051] For descriptive purposes, the present disclosure may use spatial relative terms such as “under,” “below,” “beneath,” “underneath,” “above,” “on,” “over,” “upper,” and “side (e.g., as in “sidewall”)” etc. to describe the relationship of one component to another (other) component as illustrated in the drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacturing. For example, if the device in the drawings is flipped, a component described as “under” or “beneath” another component or feature will then be positioned “above” the other component or feature. Thus, the exemplary term “under” can encompass both orientations of “above” and “under.” Additionally, the device can be positioned otherwise (e.g., rotated 90 degrees or at other orientations), and accordingly, the spatial relative descriptors used herein are to be interpreted.

[0052] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are also intended to include the plural forms. In addition, when the terms "comprise" and / or "include" and their variants are used in this specification, it is stated that there are the stated features, integers, steps, operations, components, assemblies and / or groups thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, components, assemblies and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as terms of degree, and thus they are used to explain the inherent deviations of measured values, calculated values and / or provided values that would be recognized by a person of ordinary skill in the art.

[0053] Figure 1 FIG. shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

[0054] As Figure 1 shown, the battery management system 100 can be used to perform high-precision voltage acquisition on the battery and manage it. The battery can be a lithium battery pack, including multiple lithium batteries connected in series.

[0055] The battery management system 100 may include a gating detection module 110, a voltage amplification module 120, an analog-to-digital conversion module 130, a control logic module 140, a switch driving module 150, a discharge switch MD, and a charging switch MC.

[0056] The gating detection module 110 gates and detects the voltage of each battery by gating the voltage of each battery. Among them, the gating detection module 110 can be used to detect the filtered battery voltage, and the filtering can be achieved by an RC filter composed of filtering resistors R n ~R f1 ~R fn and filtering capacitors C1~C n constituted.

[0057] The voltage amplification module 120 can amplify the voltage of each battery from the gating detection module 110.

[0058] The analog-to-digital conversion module 130 is used to perform analog-to-digital conversion on the voltage of each battery from the voltage amplification module 120, and provide the converted digital signal to the control logic module 140.

[0059] The control logic module 140 can provide a control signal to the switch driving module 150 at least according to the detected battery voltage, so as to control the discharge switch MD and the charging switch MC through the switch driving module 150, thereby realizing the charge and discharge control of the battery. When the battery is charged, it is charged through an external charger. When discharging, the battery management system is externally connected to a load to discharge.

[0060] In addition, the battery management system 100 may further include a battery converter 160. The battery converter 160 is used to convert the highest battery voltage VCC of the battery, such as, into various different required supply voltages VDD. For example, VDD can be 5V, etc.

[0061] As Figure 1 shown, the battery management system 100 can obtain the positive terminal voltage of the first battery B1 through the PIN1 pin, obtain the positive terminal voltage of the first battery B2 through the PIN2 pin,..., obtain the positive terminal voltage of the first battery B n-1 through the PIN n-1 pin, and obtain the positive terminal voltage of the first battery B n through the PIN n pin.

[0062] Figure 2 The figure shows a schematic diagram of the strobe detection module 110 according to an embodiment of the present disclosure. When sampling the voltage of the i-th battery (1 ≤ i ≤ n), by making the switch connected to the positive terminal voltage input pin PIN i of the i-th battery conduct, and making the switch connected to the negative terminal voltage input pin PIN i-1 (that is, the positive terminal voltage input pin of the (i - 1)-th battery) conduct. The two obtained voltages VPIN i and VPIN i-1 are respectively input to the positive input terminal + and the negative input terminal — of the operational amplifier OP of the voltage amplification module 120.

[0063] For example, when measuring the voltage of the first battery B1, the switch 110 - 11 is made to conduct and 110 - 02 is made to conduct, and the two obtained voltages are respectively input to the positive input terminal + and the negative input terminal — of the operational amplifier OP; when measuring the voltage of the second battery B2, the switch 110 - 21 is made to conduct and 110 - 12 is made to conduct, and the two obtained voltages are respectively input to the positive input terminal + and the negative input terminal — of the operational amplifier OP;...; when measuring the voltage of the i-th battery B i the switch 110 - i1 is made to conduct and 110 - i - 12 is made to conduct, and the two obtained voltages are respectively input to the positive input terminal + and the negative input terminal — of the operational amplifier OP; when measuring the voltage of the (n - 1)-th battery Bn-1 When measuring the voltage of the battery, the switches 110-n-11 and 110-n-22 are turned on, and the two resulting voltages are respectively input to the positive input terminal + and the negative input terminal - of the operational amplifier OP; when measuring the voltage of the second battery B n When measuring the voltage of the battery, the switches 110-n1 and 110-n-12 are turned on, and the two resulting voltages are respectively input to the positive input terminal + and the negative input terminal - of the operational amplifier OP.

[0064] According to an embodiment of the present disclosure, an on-voltage generation circuit and a gate protection circuit are provided. As Figure 3 shown, the gates of the first transistor and the second transistor (the left transistor 110i and the right transistor 110i) are applied with an on-voltage or an off-voltage by the on-voltage generation circuit and the gate protection circuit 111, so that the first transistor and the second transistor are turned on or off. When turned on, the voltage VB i is equal to the voltage VPIN i . When turned off, voltage sampling is not performed.

[0065] The following embodiments are provided in the present disclosure to illustrate the specific forms of the on-voltage generation circuit and the gate protection circuit.

[0066] In the following first to fifth embodiments, the two transistors 110i shown constitute Figure 3 the ith switch (e.g., 110-11,...) in the shown circuit. The drain of the left transistor 110i receives the voltage VPIN i of the pin PIN i , the source of the left transistor 110i is connected to the source of the right transistor 110i. When the two transistors are turned on, the drain of the right transistor 110i outputs the battery voltage VB i (equal to VPIN i ), and the gate of the left transistor 110i is connected to the gate of the right transistor 110i.

[0067] <First Embodiment>

[0068] Figure 4 Shows the on-voltage generation circuit and the gate protection circuit according to the first embodiment of the present disclosure.

[0069] In this embodiment, the protection diode 401 serves as the gate protection circuit, where the cathode of the protection diode 401 is connected to the source of the first transistor 110i (left transistor) and the source of the second transistor 110i (right transistor), and the anode of the diode 401 is connected to the gate of the first transistor 110i and the gate of the second transistor 110i. The gate protection function of the first transistor 110i and the second transistor 110i is realized through the diode 401.

[0070] In this embodiment, a voltage higher than the battery voltage VPIN of the i-th battery input to the drain of the first transistor is generated by the turn-on voltage generation circuit i by a predetermined voltage value, so that the first transistor and the second transistor are turned on, and the turn-on voltage generation circuit generates a voltage lower than the battery voltage VPIN of the i-th battery input to the drain of the first transistor i to turn off the first transistor and the second transistor.

[0071] The specific settings of the turn-on voltage generation circuit are as follows.

[0072] The drain of the first NMOS transistor 411 is connected to the battery maximum voltage VCC, the gate of the first NMOS transistor 411 is connected to the battery voltage VPIN of the i-th battery i , the source of the first NMOS transistor 411 is connected to the drain of the second NMOS transistor 412, the source of the first NMOS transistor 411 is connected to the cathode of the second diode 462, the gate of the first NMOS transistor 411 is connected to the anode of the second diode 462, the source of the second NMOS transistor 412 is grounded, the drain of the third NMOS transistor 413 is connected to the constant current source 471, the drain and the gate of the third NMOS transistor 413 are connected, the gate of the third NMOS transistor 413 is connected to one end of the first switch 431, the other end of the first switch 431 is connected to the gate of the second NMOS transistor 412, the gate of the second NMOS transistor 412 is connected to one end of the second switch 432, the other end of the second switch 432 is grounded, the drain of the third NMOS transistor 413 is connected to one end of the third switch 433, the other end of the third switch 433 is connected to the gate of the fourth NMOS transistor 414, the source of the fourth NMOS transistor 414 is grounded, the gate of the fourth NMOS transistor 414 is connected to one end of the fourth switch 434, and the other end of the fourth switch 434 is grounded, the gate of the first PMOS transistor 421 is connected to the source of the first NMOS transistor 411, the source of the first PMOS transistor 421 is connected to the battery voltage VPIN of the i-th battery i , the drain of the first PMOS transistor 421 is connected to the drain of the fourth NMOS transistor 414, and the drain of the fourth NMOS transistor 414 is connected to the lower plate of the capacitor 451, the upper plate of the capacitor 451 is connected to the anode of the first diode 461, the cathode of the first diode 461 is connected to the supply voltage VDD, and the upper plate of the capacitor 451 is connected to the anode of the protection diode 401. The turn-on voltage Vi is generated by the turn-on voltage generation circuit to control the conduction and disconnection of the first transistor and the second transistor 110i.

[0073] When the turn-on voltage Vi is higher than the battery voltage VPIN of the i-th batteryi When the predetermined voltage value is high, the first transistor and the second transistor are turned on, and thus the output battery voltage VB i is equal to the battery voltage VPIN of the i-th battery cell i . It is equivalent to Figure 3 a certain gating switch in

[0074] According to the structure of the turn-on voltage generation circuit of this embodiment, the first transistor and the second transistor can be stably turned on or off, avoiding error situations

[0075] When the third switch 433 is turned on and the fourth switch 434 is turned off, the fourth NMOS transistor 414 is turned on, so that the lower plate of the capacitor 451 is grounded, and the voltage of the upper plate of the capacitor 451 will be equal to the supply voltage VDD minus the voltage of the first diode 461. For example, when the supply voltage is 5V and the voltage of the first diode 461 is 0.7V, the voltage of the upper plate of the capacitor 451 is 4.3V. Thus, the voltage Vi is equal to 4.3V, which will be less than the battery voltage VPIN of the i-th battery cell i , so that the first transistor and the second transistor will not be turned on

[0076] When the third switch 433 is turned off and the fourth switch 434 is turned on, the fourth NMOS transistor 414 is turned off. And when the first switch 431 is turned on and the second switch 432 is turned off, the second NMOS transistor 412 is turned on, so that the current of the first NMOS transistor 411 can flow through the second NMOS transistor 412. At this time, the voltage of the gate of the first PMOS transistor 421 will be equal to i VPIN minus the gate-source voltage of the first NMOS transistor 411, approximately equal to the battery voltage VPIN of the i-th battery cell i . After the first PMOS transistor 421 is turned on, the voltage of the lower plate of the capacitor 451 will be approximately equal to the battery voltage VPIN of the i-th battery cell i . Thus, the voltage of the upper plate of the capacitor 451 will be equal to the battery voltage VPIN of the i-th battery cell i plus the supply voltage VDD minus the voltage of the first diode 461. In this way, the voltage Vi is also equal to this voltage, so that Vi is higher than the battery voltage VPIN of the i-th battery cell by a predetermined voltage value. In this way, the first transistor and the second transistor will be turned on, so that the battery voltage VPIN of the i-th battery cell i can be collected, and the output voltage VB i is equal to the battery voltage VPIN of the i-th battery cell i i .

[0077] <Second Embodiment>

[0078] Figure 5 ​Shows an on - voltage generation circuit and a gate protection circuit according to a second embodiment of the present disclosure.

[0079] In this embodiment, the protection diode 501 serves as the gate protection circuit. The cathode of the protection diode 501 is connected to the sources of the first transistor 110i (left - hand transistor) and the second transistor 110i (right - hand transistor), and the anode of the protection diode 501 is connected to the gates of the first transistor 110i and the second transistor 110i. The gate protection function of the first transistor 110i and the second transistor 110i is achieved through the diode 501.

[0080] In this embodiment, the on - voltage generation circuit generates a voltage that is higher than the battery voltage VPIN of the i - th battery input to the drain of the first transistor i by a predetermined voltage value, so that the first transistor and the second transistor are turned on, and the on - voltage generation circuit generates a voltage i lower than the battery voltage VPIN of the i - th battery input to the drain of the first transistor, so that the first transistor and the second transistor are turned off.

[0081] The specific setting of the on - voltage generation circuit is as follows.

[0082] The drain of the first NMOS transistor 511 is connected to the battery maximum voltage VCC, and the gate of the first NMOS transistor 511 is connected to the battery voltage VPIN of the i - th battery. i, the source of the first NMOS transistor 511 is connected to the cathode of the first diode 561, the gate of the first NMOS transistor 511 is connected to the anode of the first diode 561, the source of the first NMOS transistor 511 is connected to the drain of the second NMOS transistor 512, the source of the second NMOS transistor 512 is grounded, the drain of the third NMOS transistor 513 is connected to the constant current source 571, the drain and gate of the third NMOS transistor 513 are connected, the gate of the third NMOS transistor 513 is connected to one end of the first switch 531, the other end of the first switch 531 is connected to the gate of the second NMOS transistor 512, the gate of the second NMOS transistor 512 is connected to one end of the second switch 532, the other end of the second switch 532 is grounded, the drain of the third NMOS transistor 513 is connected to one end of the third switch 533, the other end of the third switch 533 is connected to the gate of the fourth NMOS transistor 514, the source of the fourth NMOS transistor 514 is grounded, the gate of the fourth NMOS transistor 514 is connected to one end of the fourth switch 534, and the other end of the fourth switch 534 is grounded. The gate of the first PMOS transistor 521 is connected to the gate of the second PMOS transistor 522, and the gate of the first PMOS transistor 521 is connected to the drain of the first PMOS transistor 521. The source of the first PMOS transistor 521 and the source of the second PMOS transistor 522 are connected to the battery maximum voltage VCC. The drain of the first PMOS transistor 521 is connected to the drain of the fourth NMOS transistor 514. The drain of the second PMOS transistor 522 is connected to the source of the third PMOS transistor 523. The gate of the third PMOS transistor 523 is connected to the battery voltage VPIN of the i-th battery i , the drain of the third PMOS transistor 523 is grounded. The drain of the second NMOS transistor 512 is connected to the anode of the protection diode 501. The source of the third PMOS transistor 523 is connected to the anode of the protection diode 501. The voltage Vi is generated by the turn-on voltage generation circuit to control the conduction and disconnection of the first transistor and the second transistor 110i.

[0083] When the turn-on voltage Vi is higher than the battery voltage VPIN of the i-th battery by a predetermined voltage value i , the first transistor and the second transistor are turned on, and thus the output battery voltage VB i is equal to the battery voltage VPIN of the i-th battery i . It is equivalent to Figure 3 that a certain select switch in

[0084] is turned on. According to the structure of the turn-on voltage generation circuit of this embodiment, the first transistor and the second transistor can be stably turned on or off, avoiding error situations.

[0085] AndFigure 4 has the same principle. In Figure 5 , by controlling the first switch to the fourth switch, a battery voltage VPIN higher than that of the i-th battery cell is generated i a voltage Vi of a predetermined voltage value so that the first transistor and the second transistor are turned on, or a voltage Vi lower than the battery voltage VPIN of the i-th battery cell is generated i to turn off the first transistor and the second transistor.

[0086] <Third Embodiment>

[0087] Figure 6 shows an on-voltage generation circuit and a gate protection circuit according to a third embodiment of the present disclosure.

[0088] In this embodiment, the protection diode 601 serves as a gate protection circuit, where the cathode of the protection diode 601 is connected to the source of the first transistor 110i (left transistor) and the source of the second transistor 110i (right transistor), and the anode of the protection diode 601 is connected to the gate of the first transistor 110i and the gate of the second transistor 110i. The gate protection function of the first transistor 110i and the second transistor 110i is achieved through the diode 601.

[0089] In this embodiment, an on-voltage generation circuit generates a voltage higher than the battery voltage VPIN of the i-th battery cell input to the drain of the first transistor i by a predetermined voltage value, so that the first transistor and the second transistor are turned on, and the on-voltage generation circuit generates a voltage lower than the battery voltage VPIN of the i-th battery cell input to the drain of the first transistor i to turn off the first transistor and the second transistor.

[0090] The specific setting of the on-voltage generation circuit in this embodiment is as follows.

[0091] The sources of the first PMOS transistor 621 and the second PMOS transistor 622 are connected to the battery maximum voltage VCC. The gate and drain of the first PMOS transistor 621 are connected, and the gates of the first PMOS transistor 621 and the second PMOS transistor 622 are connected to form a mirror circuit. The drain of the first PMOS transistor 621 is connected to the drain of the first NMOS transistor 611. The source of the first NMOS transistor 611 is grounded. The drain of the second NMOS transistor 612 is connected to the constant current source 671, and the drain and gate of the second NMOS transistor 612 are connected. The source of the second NMOS transistor 612 is grounded. The gate of the second NMOS transistor 612 is connected to one end of the first switch 631, and the other end of the first switch 631 is connected to the gate of the first NMOS transistor 611. One end of the second switch 632 is connected to the gate of the first NMOS transistor 611, and the other end of the second switch 632 is grounded. One end of the second NMOS transistor 612 is connected to one end of the third switch 633, and the other end of the third switch 633 is connected to the gate of the third NMOS transistor 613. One end of the fourth switch 634 is connected to the gate of the third NMOS transistor 613, and the other end of the fourth switch 634 is grounded. One end of the second NMOS transistor 612 is connected to one end of the fifth switch 635, and the other end of the fifth switch 635 is connected to the gate of the fourth NMOS transistor 614. One end of the sixth switch 636 is connected to the gate of the fourth NMOS transistor 614, and the other end of the sixth switch 636 is grounded. The drain of the third NMOS transistor 613 is connected to the source of the fifth NMOS transistor 615 and is connected to the sources of the first transistor and the second transistor. The drain of the fourth NMOS transistor 614 is connected to the drain of the fifth NMOS transistor 615 and is connected to the gates of the first transistor and the second transistor. The drain of the second PMOS transistor 622 is connected to the drain of the fifth NMOS transistor 615, and the gate and drain of the fifth NMOS transistor 615 are connected.

[0092] The voltage Vi is generated by the turn-on voltage generation circuit to control the conduction and disconnection of the first transistor and the second transistor 110i.

[0093] When the turn-on voltage Vi is higher than the battery voltage VPIN of the ith battery i by a predetermined voltage value, the first transistor and the second transistor are turned on, and thus the output battery voltage VB i is equal to the battery voltage VPIN of the ith battery i . It is equivalent to Figure 3 that a certain gating switch in

[0094] is turned on. According to the structure of the turn-on voltage generation circuit of this embodiment, the first transistor and the second transistor can be stably turned on or off, avoiding error situations.

[0095] In this embodiment, when the first switch 631 and the third switch 633 are turned on while the fifth switch 635 is turned off, the first NMOS transistor 611 is turned on and the third NMOS transistor 613 is turned on. Thus, a current is formed in the branch of the first PMOS transistor and the first NMOS transistor 611. Due to the mirror circuit, the same current is also formed in the branch of the turned-on third NOMOS transistor 613, the fifth NMOS transistor 615, and the second PMOS transistor 622. In this way, the gate-source voltage of the fifth NMOS transistor 615 will be equal to the gate-source voltage of the first transistor and the second transistor 110i, so that the first transistor and the second transistor 110i will be turned on, and thus the voltage VB i will be equal to the battery voltage VPIN of the ith battery cell i .

[0096] When the first switch 631 and the third switch 633 are turned off while the fifth switch 635 is turned on, the first NMOS transistor 611 is turned off, the third NMOS transistor 613 is turned off, and the fifth NMOS transistor 615 is turned off and no current will flow through. And since the fifth switch 635 is turned on, the fourth NMOS transistor 614 is turned on. In this way, the gate voltage of the first transistor and the second transistor 110i will be approximately equal to zero, so that the first transistor and the second transistor 110i will be turned off, thus playing the role of turning off Figure 3 the switch in

[0097] <Fourth Embodiment>

[0098] Figure 7 shows an on-voltage generation circuit and a gate protection circuit according to the fourth embodiment of the present disclosure

[0099] In this embodiment, the protection diode 701 serves as a gate protection circuit. The cathode of the protection diode 701 is connected to the source of the first transistor 110i (left transistor) and the source of the second transistor 110i (right transistor), and the anode of the protection diode 701 is connected to the gate of the first transistor 110i and the gate of the second transistor 110i. The gate protection function of the first transistor 110i and the second transistor 110i is realized through the diode 701

[0100] In this embodiment, an on-voltage that turns on the first transistor and the second transistor is generated by the on-voltage generation circuit, and an off-voltage that turns off the drain of the first transistor is generated by the on-voltage generation circuit, so that the first transistor and the second transistor are turned off

[0101] The specific setting of the on-voltage generation circuit in this embodiment is as follows

[0102] The sources of the first PMOS transistor 721 and the second PMOS transistor 722 are connected to the highest battery voltage VCC. The gate and the drain of the first PMOS transistor 721 are connected, and the gates of the first PMOS transistor 721 and the second PMOS transistor 722 are connected to form a mirror circuit. The drain of the first PMOS transistor 721 is connected to the drain of the first NMOS transistor 711. The source of the first NMOS transistor 711 is grounded. The drain of the second NMOS transistor 712 is connected to the constant current source 771, and the drain and the gate of the second NMOS transistor 712 are connected. The source of the second NMOS transistor 712 is grounded. The gate of the second NMOS transistor 712 is connected to one end of the first switch 731, and the other end of the first switch 731 is connected to the gate of the first NMOS transistor 711. One end of the second switch 732 is connected to the gate of the first NMOS transistor 711, and the other end of the second switch 732 is grounded. The drain of the second NMOS transistor 712 is connected to one end of the third switch 733, and the other end of the third switch 733 is connected to the gate of the third NMOS transistor 713. One end of the fourth switch 734 is connected to the gate of the third NMOS transistor 713, and the other end of the fourth switch 734 is grounded. The drain of the second NMOS transistor 712 is connected to one end of the fifth switch 735, and the other end of the fifth switch 735 is connected to the gate of the fourth NMOS transistor 714. One end of the sixth switch 736 is connected to the gate of the fourth NMOS transistor 714, and the other end of the sixth switch 736 is grounded. The drain of the third NMOS transistor 713 is connected to the drain of the third PMOS transistor 723 and is connected to the sources of the first transistor and the second transistor. The drain of the fourth NMOS transistor 714 is connected to the source of the third PMOS transistor 723 and is connected to the gates of the first transistor and the second transistor. The drain of the second PMOS transistor 722 is connected to the source of the third PMOS transistor 723. The gate and the drain of the third PMOS transistor 723 are connected.

[0103] The voltage Vi is generated by the turn-on voltage generation circuit to control the conduction and disconnection of the first transistor and the second transistor 110i.

[0104] According to the structure of the turn-on voltage generation circuit of this embodiment, the first transistor and the second transistor can be stably turned on or off, avoiding error situations.

[0105] In this embodiment, when the first switch 731 and the third switch 733 are turned on while the fifth switch 735 is turned off, the first NMOS transistor 711 is turned on and the third NMOS transistor 713 is turned on. Thus, a current is formed in the branch of the first PMOS transistor and the first NMOS transistor 711. Due to the mirror circuit, the same current is also formed in the branch of the turned-on third NOMOS transistor 713, the third PMOS transistor 723, and the second PMOS transistor 722. In this way, the gate-source voltage of the third PMOS transistor 723 will be equal to the gate-source voltage of the first transistor and the second transistor 110i. Thus, the first transistor and the second transistor 110i will be turned on, and thus the voltage VB i will be equal to the battery voltage VPIN of the ith battery cell i .

[0106] When the first switch 731 and the third switch 733 are turned off while the fifth switch 735 is turned on, the first NMOS transistor 711 is turned off, the third NMOS transistor 713 is turned off, the third PMOS transistor 723 is turned off and no current will flow through. And since the fifth switch 735 is turned on, the fourth NMOS transistor 714 is turned on. In this way, the gate voltage of the first transistor and the second transistor 110i will be approximately equal to zero. Thus, the first transistor and the second transistor 110i will be turned off, and this will serve to turn off Figure 3 the switch in

[0107] <Fifth Embodiment>

[0108] Figure 8 shows an on-voltage generation circuit and a gate protection circuit according to the fifth embodiment of the present disclosure

[0109] In this embodiment, the protection diode 801 serves as the gate protection circuit. The cathode of the protection diode 801 is connected to the source of the first transistor 110i (left transistor) and the source of the second transistor 110i (right transistor), and the anode of the protection diode 801 is connected to the gate of the first transistor 110i and the gate of the second transistor 110i. The gate protection function of the first transistor 110i and the second transistor 110i is realized through the diode 801

[0110] In this embodiment, an on-voltage that turns on the first transistor and the second transistor is generated by the on-voltage generation circuit, and an off-voltage that turns off the drain of the first transistor is generated by the on-voltage generation circuit, so that the first transistor and the second transistor are turned off

[0111] The specific setting of the on-voltage generation circuit in this embodiment is as follows

[0112] The sources of the first PMOS transistor 821 and the second PMOS transistor 822 are connected to the highest battery voltage VCC. The gate and the drain of the first PMOS transistor 821 are connected, and the gates of the first PMOS transistor 821 and the second PMOS transistor 822 are connected to form a mirror circuit. The drain of the first PMOS transistor 821 is connected to the drain of the first NMOS transistor 811. The source of the first NMOS transistor 811 is grounded. The drain of the second NMOS transistor 812 is connected to the constant current source 871, and the drain and the gate of the second NMOS transistor 812 are connected. The source of the second NMOS transistor 812 is grounded. The gate of the second NMOS transistor 812 is connected to one end of the first switch 831, and the other end of the first switch 831 is connected to the gate of the first NMOS transistor 811. One end of the second switch 832 is connected to the gate of the first NMOS transistor 811, and the other end of the second switch 832 is grounded. One end of the second NMOS transistor 812 is connected to one end of the third switch 833, and the other end of the third switch 833 is connected to the gate of the third NMOS transistor 813. One end of the fourth switch 834 is connected to the gate of the third NMOS transistor 813, and the other end of the fourth switch 834 is grounded. One end of the second NMOS transistor 812 is connected to one end of the fifth switch 835, and the other end of the fifth switch 835 is connected to the gate of the fourth NMOS transistor 814. One end of the sixth switch 836 is connected to the gate of the fourth NMOS transistor 814, and the other end of the sixth switch 836 is grounded. The drain of the third NMOS transistor 813 is connected to the sources of the first transistor and the second transistor. The drain of the fourth NMOS transistor 814 is connected to the gates of the first transistor and the second transistor. The drain of the second PMOS transistor 822 is connected to the gates of the first transistor and the second transistor.

[0113] The voltage Vi is generated by the turn-on voltage generation circuit to control the conduction and disconnection of the first transistor and the second transistor 110i.

[0114] According to the structure of the turn-on voltage generation circuit of this embodiment, the first transistor and the second transistor can be stably turned on or off, avoiding error conditions.

[0115] In this embodiment, when the first switch 831 and the third switch 833 are turned on while the fifth switch 835 is turned off, the first NMOS transistor 811 is turned on and the third NMOS transistor 813 is turned on. Thus, a current is formed in the branch of the first PMOS transistor and the first NMOS transistor 811. Due to the mirror circuit, the same current is also formed in the branch of the turned-on third NOMOS transistor 813, the protection diode 801, and the second PMOS transistor 822. This will cause reverse breakdown, thereby generating a breakdown voltage, which will be equal to the gate-source voltage of the first transistor and the second transistor 110i. In this way, the first transistor and the second transistor 110i will be turned on, and thus the voltage VB i will be equal to the battery voltage VPIN of the ith battery cell i .

[0116] When the first switch 831 and the third switch 833 are turned off while the fifth switch 835 is turned on, the first NMOS transistor 811 is turned off, the third NMOS transistor 813 is turned off, and since the fifth switch 835 is turned on, the fourth NMOS transistor 814 is turned on, and the protection diode 801 conducts a forward current. This will cause the gate voltage of the first transistor and the second transistor 110i to be very small and unable to form a large enough turn-on voltage. Thus, the first transistor and the second transistor 110i will be turned off, which will serve to turn off Figure 3 the switch in

[0117] In summary, at least the following technical solutions are proposed in this disclosure.

[0118] Technical solution 1. A detection and gating module in a battery management system, where the detection and gating module is used to select and detect the voltage of each battery cell in a series-connected battery pack of N battery cells, where N≥1, and includes: N gating switches, where the ith gating switch among the N gating switches is respectively connected to the positive terminal of the ith battery among the N battery cells. When the ith gating switch is turned on, the voltage of the ith battery is detected, where 1≤i≤N; N protection circuits, where the ith protection circuit among the N protection circuits is used to protect the ith gating switch among the N gating switches; and N voltage generation circuits, where the ith voltage generation circuit among the N voltage generation circuits is used to generate a turn-on voltage that turns on the ith gating switch among the N gating switches and a turn-off voltage that turns off the ith gating switch.

[0119] Technical solution 2. The detection and gating module according to technical solution 1, when detecting the battery voltage of the ith battery cell, the voltage across the two ends of the ith battery cell is detected by turning on the ith gating switch and the (i - 1)th gating switch.

[0120] Technical solution 3. For the detection and gating module as described in technical solution 2, the i-th gating switch includes a first transistor and a second transistor, where the drain of the first transistor is connected to the battery voltage of the positive terminal of the i-th battery, and the source of the first transistor is connected to the source of the second transistor. The gates of the first transistor and the second transistor are connected, and the drain of the second transistor outputs the sampled battery voltage.

[0121] Technical solution 4. For the detection and gating module as described in technical solution 3, the i-th protection circuit is a protection diode. The cathode of the i-th protection diode is connected to the sources of the first transistor and the second transistor of the i-th gating switch, and the anode of the i-th protection diode is connected to the gates of the first transistor and the second transistor of the i-th gating switch.

[0122] Technical solution 5. For the detection and gating module as described in technical solution 4,

[0123] When detecting the voltage of the i-th battery, a control voltage higher than the battery voltage of the positive terminal of the i-th battery by a predetermined voltage value is generated through the i-th voltage generation circuit to turn on the first transistor and the second transistor of the i-th gating switch, and a control voltage higher than the battery voltage of the positive terminal of the (i - 1)-th battery by a predetermined voltage value is generated through the (i - 1)-th voltage generation circuit to turn on the first transistor and the second transistor of the (i - 1)-th gating switch;

[0124] When not detecting the voltage of the i-th battery, a control voltage lower than the battery voltage of the positive terminal of the i-th battery is generated through the i-th voltage generation circuit to turn off the first transistor and the second transistor of the i-th gating switch, and a control voltage lower than the battery voltage of the positive terminal of the (i - 1)-th battery is generated through the (i - 1)-th voltage generation circuit to turn off the first transistor and the second transistor of the (i - 1)-th gating switch.

[0125] Technical solution 6. For the detection and gating module as described in technical solution 4,

[0126] When detecting the voltage of the i-th battery, a conduction voltage that turns on the first transistor and the second transistor of the i-th gating switch is generated through the i-th voltage generation circuit, and a conduction voltage that turns on the first transistor and the second transistor of the (i - 1)-th gating switch is generated through the (i - 1)-th voltage generation circuit;

[0127] When not detecting the voltage of the i-th battery, a turn-off voltage that turns off the first transistor and the second transistor of the i-th gating switch is generated through the i-th voltage generation circuit, and a turn-off voltage that turns off the first transistor and the second transistor of the (i - 1)-th gating switch is generated through the (i - 1)-th voltage generation circuit.

[0128] Technical solution 7. The detection and gating module as described in technical solution 5, wherein the ith voltage generation circuit includes a capacitor, and the control voltage is provided through the charging and discharging of the capacitor, so that the first transistor and the second transistor of the ith gating switch are turned on or off.

[0129] Technical solution 8. The detection and gating module as described in technical solution 7, wherein the ith voltage generation circuit includes:

[0130] The drain of the first NMOS transistor is connected to the highest voltage of the battery pack, the gate of the first NMOS transistor is connected to the battery voltage at the positive terminal of the ith battery, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the source of the first NMOS transistor is connected to the cathode of the second diode, the gate of the first NMOS transistor is connected to the anode of the second diode, the source of the second NMOS transistor is grounded, the drain of the third NMOS transistor is connected to a constant current source, the drain and the gate of the third NMOS transistor are connected, the gate of the third NMOS transistor is connected to one end of the first switch, the other end of the first switch is connected to the gate of the second NMOS transistor, the gate of the second NMOS transistor is connected to one end of the second switch, the other end of the second switch is grounded, the drain of the third NMOS transistor is connected to one end of the third switch, the other end of the third switch is connected to the gate of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the gate of the fourth NMOS transistor is connected to one end of the fourth switch, and the other end of the fourth switch is grounded, the gate of the first PMOS transistor is connected to the source of the first NMOS transistor, the source of the first PMOS transistor is connected to the battery voltage at the positive terminal of the ith battery, the drain of the first PMOS transistor is connected to the drain of the fourth NMOS transistor, and the drain of the fourth NMOS transistor is connected to the lower plate of the capacitor, the upper plate of the capacitor is connected to the anode of the first diode, the cathode of the first diode is connected to the supply voltage, and the upper plate of the capacitor is connected to the anode of the protection diode.

[0131] Technical solution 9. The detection and gating module as described in technical solution 5, wherein the ith voltage generation circuit includes:

[0132] The drain of the first NMOS transistor is connected to the highest voltage of the battery pack. The gate of the first NMOS transistor is connected to the battery voltage at the positive terminal of the i-th battery. The source of the first NMOS transistor is connected to the cathode of the first diode. The gate of the first NMOS transistor is connected to the anode of the first diode. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The source of the second NMOS transistor is grounded. The drain of the third NMOS transistor is connected to a constant current source. The drain and the gate of the third NMOS transistor are connected. The gate of the third NMOS transistor is connected to one end of the first switch. The other end of the first switch is connected to the gate of the second NMOS transistor. The gate of the second NMOS transistor is connected to one end of the second switch. The other end of the second switch is grounded. The drain of the third NMOS transistor is connected to one end of the third switch. The other end of the third switch is connected to the gate of the fourth NMOS transistor. The source of the fourth NMOS transistor is grounded. The gate of the fourth NMOS transistor is connected to one end of the fourth switch, and the other end of the fourth switch is grounded. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, and the gate of the first PMOS transistor is connected to the drain of the first PMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are connected to the highest voltage of the battery pack. The drain of the first PMOS transistor is connected to the drain of the fourth NMOS transistor. The drain of the second PMOS transistor is connected to the source of the third PMOS transistor. The gate of the third PMOS transistor is connected to the battery voltage at the positive terminal of the i-th battery. The drain of the third PMOS transistor is grounded. The drain of the second NMOS transistor is connected to the anode of the protection diode. The source of the third PMOS transistor is connected to the anode of the protection diode.

[0133] Technical solution 10. The detection gating module according to technical solution 6, wherein the i-th voltage generation circuit includes a fifth NMOS transistor. The drain of the fifth NMOS transistor is connected to the gates of the first transistor and the second transistor. The source of the fifth NMOS transistor is connected to the sources of the first transistor and the second transistor. The gate and the drain of the fifth NMOS transistor are connected. The control voltage is provided by the conduction or disconnection of the fifth NMOS transistor, so that the first transistor and the second transistor of the i-th gating switch are conducted or disconnected.

[0134] Technical solution 11. The detection gating module according to technical solution 10, wherein the i-th voltage generation circuit includes:

[0135] The sources of the first PMOS transistor and the second PMOS transistor are connected to the highest voltage of the battery pack. The gate and drain of the first PMOS transistor are connected, and the gates of the first PMOS transistor and the second PMOS transistor are connected to form a mirror circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is connected to a constant current source, and the drain and gate of the second NMOS transistor are connected. The source of the second NMOS transistor is grounded. The gate of the second NMOS transistor is connected to one end of the first switch, and the other end of the first switch is connected to the gate of the first NMOS transistor. One end of the second switch is connected to the gate of the first NMOS transistor, and the other end of the second switch is grounded. The drain of the second NMOS transistor is connected to one end of the third switch, and the other end of the third switch is connected to the gate of the third NMOS transistor. One end of the fourth switch is connected to the gate of the third NMOS transistor, and the other end of the fourth switch is grounded. The drain of the second NMOS transistor is connected to one end of the fifth switch, and the other end of the fifth switch is connected to the gate of the fourth NMOS transistor. One end of the sixth switch is connected to the gate of the fourth NMOS transistor, and the other end of the sixth switch is grounded. The drain of the third NMOS transistor is connected to the source of the fifth NMOS transistor and is connected to the sources of the first transistor and the second transistor. The drain of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor and is connected to the gates of the first transistor and the second transistor. The drain of the second PMOS transistor is connected to the drain of the fifth NMOS transistor. The gate and drain of the fifth NMOS transistor are connected.

[0136] Technical solution 12. The detection and gating module according to technical solution 6, wherein the i-th voltage generation circuit includes a third PMOS transistor. The source of the third PMOS transistor is connected to the gates of the first transistor and the second transistor. The drain of the fifth NMOS transistor is connected to the sources of the first transistor and the second transistor. The gate and drain of the third PMOS transistor are connected. The control voltage is provided by the conduction or disconnection of the third PMOS transistor, so that the first transistor and the second transistor of the i-th gating switch are conducted or disconnected.

[0137] Technical solution 13. The detection and gating module according to technical solution 12, wherein the i-th voltage generation circuit includes:

[0138] The sources of the first PMOS transistor and the second PMOS transistor are connected to the highest voltage of the battery pack. The gate and the drain of the first PMOS transistor are connected, and the gates of the first PMOS transistor and the second PMOS transistor are connected to form a mirror circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is connected to a constant current source, and the drain and the gate of the second NMOS transistor are connected. The source of the second NMOS transistor is grounded. The gate of the second NMOS transistor is connected to one end of the first switch, and the other end of the first switch is connected to the gate of the first NMOS transistor. One end of the second switch is connected to the gate of the first NMOS transistor, and the other end of the second switch is grounded. The drain of the second NMOS transistor is connected to one end of the third switch, and the other end of the third switch is connected to the gate of the third NMOS transistor. One end of the fourth switch is connected to the gate of the third NMOS transistor, and the other end of the fourth switch is grounded. The drain of the second NMOS transistor is connected to one end of the fifth switch, and the other end of the fifth switch is connected to the gate of the fourth NMOS transistor. One end of the sixth switch is connected to the gate of the fourth NMOS transistor, and the other end of the sixth switch is grounded. The drain of the third NMOS transistor is connected to the drain of the third PMOS transistor and to the sources of the first transistor and the second transistor. The drain of the fourth NMOS transistor is connected to the source of the third PMOS transistor and to the gates of the first transistor and the second transistor. The drain of the second PMOS transistor is connected to the source of the third PMOS transistor. The gate and the drain of the third PMOS transistor are connected.

[0139] Technical solution 14. The detection and gating module according to technical solution 6, wherein the i-th voltage generation circuit is the protection diode. When the protection diode is reversely broken down, the control voltage is provided by the reverse breakdown voltage, so that the first transistor and the second transistor of the i-th gating switch are turned on or off.

[0140] Technical solution 15. The detection and gating module according to technical solution 14, wherein the i-th voltage generation circuit includes:

[0141] The sources of the first PMOS transistor and the second PMOS transistor are connected to the highest voltage of the battery pack. The gate and the drain of the first PMOS transistor are connected, and the gates of the first PMOS transistor and the second PMOS transistor are connected to form a mirror circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is connected to a constant current source, and the drain and the gate of the second NMOS transistor are connected. The source of the second NMOS transistor is grounded. The gate of the second NMOS transistor is connected to one end of a first switch, and the other end of the first switch is connected to the gate of the first NMOS transistor. One end of a second switch is connected to the gate of the first NMOS transistor, and the other end of the second switch is grounded. The drain of the second NMOS transistor is connected to one end of a third switch, and the other end of the third switch is connected to the gate of a third NMOS transistor. One end of a fourth switch is connected to the gate of the third NMOS transistor, and the other end of the fourth switch is grounded. The drain of the second NMOS transistor is connected to one end of a fifth switch, and the other end of the fifth switch is connected to the gate of a fourth NMOS transistor. One end of a sixth switch is connected to the gate of the fourth NMOS transistor, and the other end of the sixth switch is grounded. The drain of the third NMOS transistor is connected to the sources of a first transistor and a second transistor. The drain of the fourth NMOS transistor is connected to the gates of the first transistor and the second transistor. The drain of the second PMOS transistor is connected to the gates of the first transistor and the second transistor.

[0142] Technical solution 16. A battery management system, comprising:

[0143] The detection and gating module according to any one of technical solutions 1 to 15, wherein the detection is used to select and detect the voltage of each battery in a battery pack of N series-connected batteries; and

[0144] A voltage amplification module, which is used to receive the voltage of each battery output by the detection and gating module, so as to amplify and output the voltage of each battery.

[0145] Technical solution 17. The battery management system according to technical solution 16, further comprising:

[0146] An analog-to-digital conversion module, which is used to perform analog-to-digital conversion on the voltage of each battery from the voltage amplification module;

[0147] A control logic module, which is used to receive the battery voltage converted by the analog-to-digital conversion module and provide a control signal to the switch driving module at least according to the converted battery voltage, so as to control the conduction or cut-off of the discharge switch and the charging switch through the switch driving module.

[0148] Technical solution 18. A battery management chip integrates the battery management system described in Technical solution 16 or 17.

[0149] In the description of this specification, the description with reference to the terms "one embodiment / way", "some embodiments / ways", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment / way or example are included in at least one embodiment / way or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment / way or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments / ways or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments / ways or examples described in this specification and the features of different embodiments / ways or examples.

[0150] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0151] Those skilled in the art should understand that the above embodiments are only for clearly explaining the present disclosure and not for limiting the scope of the present disclosure. For those skilled in the art, other changes or modifications can be made on the basis of the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A detection and gating module in a battery management system, which is used to select and detect the voltage of each battery in a battery pack composed of N series-connected batteries, where N ≥ 1, and is characterized in that, Including: N strobe switches, wherein the i-th strobe switch is respectively connected to the positive terminal of the i-th battery among the N batteries. When the i-th strobe switch is turned on, the voltage of the i-th battery is detected, where 1 ≤ i ≤ N; N protection circuits, wherein the i-th protection circuit is used to protect the i-th strobe switch among the N strobe switches; And N voltage generation circuits, wherein the i-th voltage generation circuit is used to generate a turn-on voltage for turning on the i-th strobe switch among the N strobe switches and a turn-off voltage for turning off the i-th strobe switch; The i-th voltage generation circuit includes: The drain of the first NMOS transistor is connected to the highest voltage of the battery pack, the gate is connected to the battery voltage at the positive terminal of the i-th battery, and the source is connected to the cathode of the first diode; The gate of the first NMOS transistor is connected to the anode of the first diode, and the source is connected to the drain of the second NMOS transistor; The source of the second NMOS transistor is grounded; The drain of the third NMOS transistor is connected to a constant current source, and the drain is connected to the gate, and the gate is connected to one end of the first switch. The other end of the first switch is connected to the gate of the second NMOS transistor. The gate of the second NMOS transistor is connected to one end of the second switch, and the other end of the second switch is grounded. The drain of the third NMOS transistor is connected to one end of the third switch, and the other end of the third switch is connected to the gate of the fourth NMOS transistor. The source of the fourth NMOS transistor is grounded. The gate of the fourth NMOS transistor is connected to one end of the fourth switch, and the other end of the fourth switch is grounded. The gates of the first PMOS transistor and the second PMOS transistor are connected, and the gate of the first PMOS transistor is connected to its drain. The sources of the first PMOS transistor and the second PMOS transistor are connected to the highest voltage of the battery pack. The drain of the first PMOS transistor is connected to the drain of the fourth NMOS transistor. The drain of the second PMOS transistor is connected to the source of the third PMOS transistor. The gate of the third PMOS transistor is connected to the battery voltage at the positive terminal of the i-th battery. The drain of the third PMOS transistor is grounded. The drain of the second NMOS transistor is connected to the anode of the protection diode. The source of the third PMOS transistor is connected to the anode of the protection diode.

2. The detection and gating module according to claim 1, wherein The i-th strobe switch includes a first transistor and a second transistor, wherein the drain of the first transistor is connected to the battery voltage at the positive terminal of the i-th battery, and the source of the first transistor is connected to the source of the second transistor. The gates of the first transistor and the second transistor are connected, and the drain of the second transistor outputs the sampled battery voltage.

3. The detection gating module according to claim 2, wherein The i-th protection circuit is the i-th protection diode. The cathode of the i-th protection diode is connected to the sources of the first transistor and the second transistor of the i-th strobe switch, and the anode of the i-th protection diode is connected to the gates of the first transistor and the second transistor of the i-th strobe switch.

4. The detection strobe module according to claim 3, wherein When detecting the voltage of the i-th battery cell, a control voltage higher than the battery voltage at the positive terminal of the i-th battery cell by a predetermined voltage value is generated through the i-th voltage generation circuit, so as to turn on the first transistor and the second transistor of the i-th strobe switch, and a control voltage higher than the battery voltage at the positive terminal of the (i - 1)-th battery cell by a predetermined voltage value is generated through the (i - 1)-th voltage generation circuit, so as to turn on the first transistor and the second transistor of the (i - 1)-th strobe switch; When not detecting the voltage of the i-th battery cell, a control voltage lower than the battery voltage at the positive terminal of the i-th battery cell is generated through the i-th voltage generation circuit, so as to turn off the first transistor and the second transistor of the i-th strobe switch, and a control voltage lower than the battery voltage at the positive terminal of the (i - 1)-th battery cell is generated through the (i - 1)-th voltage generation circuit, so as to turn off the first transistor and the second transistor of the (i - 1)-th strobe switch.

5. The detection strobe module according to claim 3, wherein When detecting the voltage of the i-th battery cell, a conduction voltage that turns on the first transistor and the second transistor of the i-th strobe switch is generated through the i-th voltage generation circuit, and a conduction voltage that turns on the first transistor and the second transistor of the (i - 1)-th strobe switch is generated through the (i - 1)-th voltage generation circuit; When not detecting the voltage of the i-th battery cell, a turn-off voltage that turns off the first transistor and the second transistor of the i-th strobe switch is generated through the i-th voltage generation circuit, and a turn-off voltage that turns off the first transistor and the second transistor of the (i - 1)-th strobe switch is generated through the (i - 1)-th voltage generation circuit.

6. The detection gating module according to claim 4, wherein The i-th voltage generation circuit includes a capacitor, and the control voltage is provided through the charging and discharging of the capacitor, so that the first transistor and the second transistor of the i-th strobe switch are turned on or off.

7. The detection gating module according to claim 6, wherein The i-th voltage generation circuit includes: The drain of the first NMOS transistor is connected to the highest voltage of the battery pack. The gate of the first NMOS transistor is connected to the battery voltage at the positive terminal of the i-th battery cell. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The source of the first NMOS transistor is connected to the cathode of the second diode. The gate of the first NMOS transistor is connected to the anode of the second diode. The source of the second NMOS transistor is grounded. The drain of the third NMOS transistor is connected to a constant current source. The drain and the gate of the third NMOS transistor are connected. The gate of the third NMOS transistor is connected to one end of the first switch. The other end of the first switch is connected to the gate of the second NMOS transistor. The gate of the second NMOS transistor is connected to one end of the second switch. The other end of the second switch is grounded. The drain of the third NMOS transistor is connected to one end of the third switch. The other end of the third switch is connected to the gate of the fourth NMOS transistor. The source of the fourth NMOS transistor is grounded. The gate of the fourth NMOS transistor is connected to one end of the fourth switch, and the other end of the fourth switch is grounded. The gate of the first PMOS transistor is connected to the source of the first NMOS transistor. The source of the first PMOS transistor is connected to the battery voltage at the positive terminal of the i-th battery cell. The drain of the first PMOS transistor is connected to the drain of the fourth NMOS transistor, and the drain of the fourth NMOS transistor is connected to the lower plate of the capacitor. The upper plate of the capacitor is connected to the anode of the first diode. The cathode of the first diode is connected to the supply voltage. The upper plate of the capacitor is connected to the anode of the protection diode.

8. The detection and gating module according to claim 4, wherein The i-th voltage generating circuit includes a fifth NMOS transistor. The drain of the fifth NMOS transistor is connected to the gates of the first transistor and the second transistor. The source of the fifth NMOS transistor is connected to the sources of the first transistor and the second transistor. The gate and the drain of the fifth NMOS transistor are connected. The control voltage is provided by turning on or off the fifth NMOS transistor, so that the first transistor and the second transistor of the i-th strobe switch are turned on or off.

9. The detection and gating module according to claim 8, wherein, The i-th voltage generating circuit includes: The sources of the first PMOS transistor and the second PMOS transistor are connected to the highest voltage of the battery pack. The gate and the drain of the first PMOS transistor are connected, and the gates of the first PMOS transistor and the second PMOS transistor are connected to form a mirror circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is connected to a constant current source, and the drain and the gate of the second NMOS transistor are connected. The source of the second NMOS transistor is grounded. The gate of the second NMOS transistor is connected to one end of the first switch, and the other end of the first switch is connected to the gate of the first NMOS transistor. One end of the second switch is connected to the gate of the first NMOS transistor, and the other end of the second switch is grounded. The drain of the second NMOS transistor is connected to one end of the third switch, and the other end of the third switch is connected to the gate of the third NMOS transistor. One end of the fourth switch is connected to the gate of the third NMOS transistor, and the other end of the fourth switch is grounded. The drain of the second NMOS transistor is connected to one end of the fifth switch, and the other end of the fifth switch is connected to the gate of the fourth NMOS transistor. One end of the sixth switch is connected to the gate of the fourth NMOS transistor, and the other end of the sixth switch is grounded. The drain of the third NMOS transistor is connected to the source of the fifth NMOS transistor and is also connected to the sources of the first transistor and the second transistor. The drain of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor and is also connected to the gates of the first transistor and the second transistor. The drain of the second PMOS transistor is connected to the drain of the fifth NMOS transistor, and the gate and the drain of the fifth NMOS transistor are connected.

10. The detection and gating module according to claim 8, characterized in that The i-th voltage generating circuit includes a third PMOS transistor. The source of the third PMOS transistor is connected to the gates of the first transistor and the second transistor. The drain of the fifth NMOS transistor is connected to the sources of the first transistor and the second transistor. The gate and the drain of the third PMOS transistor are connected. The control voltage is provided by the conduction or disconnection of the third PMOS transistor, so that the first transistor and the second transistor of the i-th strobe switch are conducted or disconnected.

11. The detection gating module according to claim 10, characterized in that, The i-th voltage generating circuit includes: The sources of the first PMOS transistor and the second PMOS transistor are connected to the highest voltage of the battery pack. The gate and the drain of the first PMOS transistor are connected, and the gates of the first PMOS transistor and the second PMOS transistor are connected to form a mirror circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is connected to a constant current source, and the drain and the gate of the second NMOS transistor are connected. The source of the second NMOS transistor is grounded. The gate of the second NMOS transistor is connected to one end of the first switch, and the other end of the first switch is connected to the gate of the first NMOS transistor. One end of the second switch is connected to the gate of the first NMOS transistor, and the other end of the second switch is grounded. The drain of the second NMOS transistor is connected to one end of the third switch, and the other end of the third switch is connected to the gate of the third NMOS transistor. One end of the fourth switch is connected to the gate of the third NMOS transistor, and the other end of the fourth switch is grounded. The drain of the second NMOS transistor is connected to one end of the fifth switch, and the other end of the fifth switch is connected to the gate of the fourth NMOS transistor. One end of the sixth switch is connected to the gate of the fourth NMOS transistor, and the other end of the sixth switch is grounded. The drain of the third NMOS transistor is connected to the drain of the third PMOS transistor and to the sources of the first transistor and the second transistor. The drain of the fourth NMOS transistor is connected to the source of the third PMOS transistor and to the gates of the first transistor and the second transistor. The drain of the second PMOS transistor is connected to the source of the third PMOS transistor. The gate and the drain of the third PMOS transistor are connected.

12. The detection and gating module according to claim 4, wherein, The i-th voltage generation circuit is the protection diode. When the protection diode is reversely broken down, the control voltage is provided through the reverse breakdown voltage, so that the first transistor and the second transistor of the i-th selection switch are turned on or off.

13. The detection gating module according to claim 12, characterized in that, The i-th voltage generation circuit includes: The sources of the first PMOS transistor and the second PMOS transistor are connected to the highest voltage of the battery pack. The gate and drain of the first PMOS transistor are connected, and the gates of the first PMOS transistor and the second PMOS transistor are connected to form a mirror circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is connected to a constant current source, and the drain and gate of the second NMOS transistor are connected. The source of the second NMOS transistor is grounded. The gate of the second NMOS transistor is connected to one end of the first switch, and the other end of the first switch is connected to the gate of the first NMOS transistor. One end of the second switch is connected to the gate of the first NMOS transistor, and the other end of the second switch is grounded. The drain of the second NMOS transistor is connected to one end of the third switch, and the other end of the third switch is connected to the gate of the third NMOS transistor. One end of the fourth switch is connected to the gate of the third NMOS transistor, and the other end of the fourth switch is grounded. The drain of the second NMOS transistor is connected to one end of the fifth switch, and the other end of the fifth switch is connected to the gate of the fourth NMOS transistor. One end of the sixth switch is connected to the gate of the fourth NMOS transistor, and the other end of the sixth switch is grounded. The drain of the third NMOS transistor is connected to the sources of the first transistor and the second transistor. The drain of the fourth NMOS transistor is connected to the gates of the first transistor and the second transistor. The drain of the second PMOS transistor is connected to the gates of the first transistor and the second transistor.

14. A battery management system, characterized in that, Comprising: The detection and gating module according to any one of claims 1 to 13, configured to select and detect the voltage of each battery in a battery pack of N series-connected batteries; and A voltage amplification module, configured to receive the voltage of each battery output by the detection and gating module, so as to amplify and output the voltage of each battery.

15. The battery management system according to claim 14, characterized in that, Further comprising: An analog-to-digital conversion module, configured to perform analog-to-digital conversion on the voltage of each battery from the voltage amplification module; A control logic module, configured to receive the battery voltage converted by the analog-to-digital conversion module, and provide a control signal to the switch driving module at least according to the converted battery voltage, so as to control the conduction or cutoff of the discharge switch and the charge switch through the switch driving module.

16. A battery management chip, characterized in that, Integrating the battery management system according to claim 14 or 15.

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