Photolithography mask with amorphous cap layer

Abstract

The present disclosure relates to a photolithography mask having an amorphous capping layer. A multilayer reflective structure is disposed on a substrate. The amorphous capping layer is disposed on the multilayer reflective structure. The amorphous capping layer may include ruthenium, oxygen, niobium, nitrogen, tantalum or zirconium. An amorphous layer may also be disposed between the multilayer reflective structure and the amorphous capping layer. The amorphous layer includes amorphous silicon, amorphous silicon oxide or amorphous silicon nitride.

Description

Technical Field

[0001] The present disclosure relates to a photolithography mask having an amorphous capping layer. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller, more complex circuits than the previous generation. However, these advances have increased the complexity of IC processing and manufacturing, and for these advances to be realized, similar developments in IC processing and manufacturing are required. Over the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased.

[0003] As semiconductor device dimensions continue to shrink, for example, below the 20 nanometer (nm) node, conventional lithography techniques have optical limitations that can cause resolution issues and may not achieve the desired lithography performance. In contrast, extreme ultraviolet (EUV) lithography can achieve smaller device dimensions. However, existing EUV lithography may still face certain challenges. For example, the capping layer of existing EUV masks may be easily damaged, which may reduce lithography performance and / or shorten the life of EUV masks.

[0004] Thus, while existing EUV lithography systems and methods have generally been adequate for their intended purposes, they have not been completely satisfactory in every respect. Summary of the invention

[0005] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate; a multilayer reflective structure disposed on the substrate; and an amorphous cap layer disposed on the multilayer reflective structure.

[0006] According to a second aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a multilayer reflective structure on a substrate; depositing or growing an amorphous layer on the multilayer reflective structure; and depositing or growing a cap layer on the amorphous layer.

[0007] According to a third aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a multilayer reflective structure on a substrate; treating the multilayer reflective structure using plasma; and after the treatment, forming an amorphous cap layer on the multilayer reflective structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 is a schematic diagram of a lithography system constructed according to some embodiments of the present disclosure.

[0010] Figure 2-Figure 13 Cross-sectional views of a photolithography mask at various stages of fabrication are shown according to an embodiment of the present disclosure.

[0011] Fig.14 is a flow chart illustrating a method of making and using a photolithography mask according to some embodiments of the present disclosure.

[0012] Fig.15 is a flow chart illustrating a method of making and using a photolithography mask according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0015] Furthermore, when "about", "approximately", etc. are used to describe a number or a numerical range, the term is intended to encompass numbers within a reasonable range including the described number, for example, within + / -10% of the described number (or other values ​​understood by those skilled in the art). For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0016] Extreme ultraviolet (EUV) lithography technology has been widely used because it can achieve smaller semiconductor device sizes. However, traditional systems and methods for performing EUV lithography may still face various challenges. For example, traditional EUV systems use lithography masks configured to perform EUV lithography. Among other components, the EUV lithography mask includes a cap layer configured to protect some other components of the EUV lithography mask (e.g., a multilayer reflective structure). Traditional EUV lithography masks can use polycrystalline materials to implement the cap layer. Unfortunately, in various EUV lithography processes, such polycrystalline materials may be easily damaged.

[0017] For example, a material with a polycrystalline structure has multiple crystallites (also referred to as "grains") of varying sizes and orientations. A grain boundary may refer to the interface between two such grains or crystallites. During lithography processes, for example, during (or as a result of) dry etching and cleaning processes, the grain boundaries of the polycrystalline capping layer may crack or become rough (as opposed to having a smooth, flat surface). Such damage to the capping layer may adversely affect lithography performance, such as with respect to critical dimension (CD) during wafer printing. Damage to the capping layer may also shorten the life of the EUV lithography mask, as an EUV lithography mask with capping layer damage is less able to withstand particle removal by cleaning or electron beam repair. If the EUV lithography mask has to be replaced frequently due to excessive damage, the cost of semiconductor manufacturing may increase.

[0018] To alleviate the problems discussed above, the present disclosure forms an EUV lithography mask having a capping layer with an amorphous structure rather than a polycrystalline structure. The amorphous structure allows the capping layer to better withstand various EUV lithography processes without being damaged, thereby improving EUV lithography performance and extending the service life of the EUV lithography mask. Figures 1 to 15 Various aspects of the present disclosure are discussed in more detail. First, reference is made to Figure 1 The EUV lithography system according to the embodiment of the present disclosure is discussed. Next, reference is made to Figure 2-Figure 15 Details of an EUV mask as part of an EUV lithography system according to embodiments of the present disclosure are discussed.

[0019] Figure 1is a schematic diagram of an EUV lithography system 10 constructed according to some embodiments. The EUV lithography system 10 may also be collectively referred to as a scanner, which is configured to perform a lithography exposure process using a corresponding radiation source and an exposure mode. The EUV lithography system 10 is designed to expose a photoresist layer by EUV light or EUV radiation. The photoresist layer is a material that is sensitive to EUV light. The EUV lithography system 10 uses a radiation source 12 to generate EUV light, for example, EUV light having a wavelength ranging from about 1 nm to about 100 nm. In a specific example, the radiation source 12 generates EUV light having a wavelength centered at about 13.5 nm. Therefore, the radiation source 12 is also referred to as an EUV radiation source 12.

[0020] The lithography system 10 also employs an illuminator 14. In various embodiments, the illuminator 14 includes various refractive optical components (e.g., a single lens, or a lens system with multiple lenses (zone plates)) or alternatively reflective optical devices (for EUV lithography systems) (e.g., a single mirror, or a mirror system with multiple mirrors) to direct light from the radiation source 12 onto the mask stage 16, and in particular onto the EUV lithography mask 18 fixed on the mask stage 16. The radiation source 12 generates light in the EUV wavelength range, and the illuminator 14 employs reflective optical devices. In some embodiments, the illuminator 14 includes a dipole illumination assembly.

[0021] In some embodiments, the illuminator 14 is operable to configure a reflector to provide appropriate illumination to the EUV lithography mask 18. In one example, the reflector of the illuminator 14 is switchable to reflect the EUV light to different illumination positions. In some embodiments, the stage before the illuminator 14 may additionally include other switchable reflectors, which can be controlled to guide the EUV light to different illumination positions together with the reflector of the illuminator 14. In some embodiments, the illuminator 14 is configured to provide on-axis illumination (ONI) to the EUV lithography mask 18. In an example, a disk illuminator 14 with a partial coherence σ of at most 0.3 is used. In some other embodiments, the illuminator 14 is configured to provide off-axis illumination (OAI) to the EUV lithography mask 18. In an example, the illuminator 14 is a dipole illuminator. In some embodiments, the dipole illuminator has a partial coherence σ of at most 0.3.

[0022] The lithography system 10 also includes a mask stage 16 configured to hold an EUV lithography mask 18. In some embodiments, the mask stage 16 includes an electrostatic chuck (e-cuck) for holding the EUV lithography mask 18. Because gas molecules absorb EUV light, the lithography system for EUV lithography patterning is maintained in a vacuum environment to avoid EUV intensity loss. In the present disclosure, the terms mask, photomask, and intermediate mask are used interchangeably to refer to the same item.

[0023] In the present embodiment, the lithography system 10 is an EUV lithography system and the EUV lithography mask 18 is a reflective mask. An exemplary structure of the EUV lithography mask 18 is provided for illustration. The EUV lithography mask 18 includes a substrate having a suitable material, for example, a low thermal expansion material (LTEM) or fused silica. In various examples, the LTEM includes SiO2 doped with TiO2, or other suitable materials with low thermal expansion. In some embodiments, the LTEM includes 5% to 20% TiO2 by weight and has a thickness of less than about 1.0×10 -6 / °C thermal expansion coefficient. For example, in some embodiments, the SiO2 material doped with TiO2 of the LTEM has a thermal expansion coefficient such that it changes by less than 60 parts per billion for every 1 degree Celsius temperature change. Of course, other suitable materials having a thermal expansion coefficient equal to or less than that of SiO2 doped with TiO2 may also be used.

[0024] The EUV lithography mask 18 also includes a multilayer reflective structure deposited on the substrate. The multilayer reflective structure includes a plurality of film pairs, for example, molybdenum-silicon (Mo / Si) film pairs (e.g., a molybdenum layer is above or below a silicon layer in each film pair). Alternatively, the multilayer reflective structure may include a molybdenum-beryllium (Mo / Be) film pair, or other suitable materials that may be configured to be highly reflective of EUV light.

[0025] The EUV lithography mask 18 may also include a cap layer disposed on the multilayer reflective structure for protecting the multilayer reflective structure and / or layers therebelow. Conventional EUV masks may implement a cap layer having a polycrystalline structure. As described above, the polycrystalline structure used for the cap layer may be susceptible to damage, for example, as a result of lithography processes such as etching and cleaning, the grain boundaries of the polycrystalline cap layer may become rough or cracked. Damage to the polycrystalline cap layer may cause manufacturing problems, such as poor critical dimension (CD). Due to damage to the polycrystalline cap layer, the EUV lithography mask itself may also suffer from reduced lifetime.

[0026] According to an embodiment of the present disclosure, the cap layer of the EUV lithography mask 18 has an amorphous structure, rather than a polycrystalline structure. In this regard, amorphous structures are non-crystalline and may lack a well-defined geometry because their components are not arranged in an ordered manner. In this way, the amorphous structure may not have grain boundaries that exist in a polycrystalline structure. Because manufacturing-induced damage typically occurs at grain boundaries, the lack of grain boundaries in the amorphous cap layer substantially prevents or at least reduces damage that may occur thereon. Therefore, lithography performance can be improved and the life of the EUV lithography mask 18 can be extended, which reduces the cost of semiconductor manufacturing.

[0027] In some embodiments, the amorphous capping layer includes an amorphous ruthenium (Ru) material. In some embodiments, the amorphous capping layer may further include one or more of the following elements: oxygen, niobium, nitrogen, tantalum, or zirconium. In some embodiments, the amorphous capping layer may be formed by first forming an amorphous layer on the multilayer reflective structure, and then forming the amorphous capping layer on the amorphous layer. In other embodiments, the amorphous capping layer may be formed by first treating the upper surface of the multilayer reflective structure (e.g., by treating the upper surface with plasma), and then forming the amorphous capping layer on the treated surface of the multilayer reflective structure. The formation of the amorphous capping layer will refer to Figure 2-Figure 5 Discuss in more detail.

[0028] The EUV lithography mask 18 also includes an absorber layer (also referred to as an absorber layer) deposited on the amorphous cap layer. The absorber layer is patterned to define an integrated circuit (IC) layer. Alternatively, another reflective layer may be deposited on top of the multilayer reflective structure and patterned to define an integrated circuit layer, thereby forming an EUV phase shift mask.

[0029] The lithography system 10 also includes a projection optical module (or projection optical box (POB) 20) for imaging the pattern of the EUV lithography mask 18 onto a target 26 (e.g., a semiconductor substrate) fixed on a substrate stage 28 of the lithography system 10. In various embodiments, the POB 20 has refractive optics (e.g., for UV lithography systems) or alternatively reflective optics (e.g., for EUV lithography systems). Light emitted from the EUV lithography mask 18 (which is diffracted into various diffraction orders and carries an image of the pattern defined on the mask) is collected by the POB 20. The POB 20 can include a magnification of less than one (thus, the size of the "image" on the target (e.g., target 26 discussed below) is smaller than the size of the corresponding "object" on the mask). The illuminator 14 and the POB 20 are collectively referred to as an optical module of the lithography system 10.

[0030] The lithography system 10 also includes a pupil phase modulator 22 for modulating the optical phase of light emitted from the EUV lithography mask 18 so that the light has a phase distribution on a projection pupil plane 24. In the optical module, there is a plane with a field distribution corresponding to the Fourier transform of the object (in the present case, the EUV lithography mask 18). This plane is called the projection pupil plane. The pupil phase modulator 22 provides a mechanism for modulating the optical phase of light on the projection pupil plane 24. In some embodiments, the pupil phase modulator 22 includes a mechanism for adjusting the mirrors of the POB 20 for phase modulation. For example, the mirrors of the POB 20 are switchable and controlled to reflect EUV light, thereby modulating the phase of the light through the POB 20.

[0031] In some embodiments, pupil phase modulator 22 utilizes a pupil filter placed on projection pupil plane 24. The pupil filter filters out specific spatial frequency components of EUV light from EUV lithography mask 18. Specifically, the pupil filter is a phase pupil filter that is used to modulate the phase distribution of light guided through POB 20. However, because all materials absorb EUV light, the use of phase pupil filters in certain lithography systems (e.g., EUV lithography systems) is limited.

[0032] As described above, the lithography system 10 also includes a substrate stage 28 for fixing a target 26 to be patterned, for example, a semiconductor substrate. In the present embodiment, the semiconductor substrate is a semiconductor wafer, for example, a silicon wafer or other types of wafers. A resist layer sensitive to a radiation beam (for example, EUV light in the present embodiment) is coated on the target 26. Various components including those described above are integrated together and are operable to perform a lithography exposure process. The lithography system 10 may further include other modules, or be integrated (or coupled) with other modules.

[0033] According to some embodiments, the EUV lithography mask 18 and its manufacturing method are further described. In some embodiments, the mask manufacturing process includes two operations: a blank mask manufacturing process and a mask patterning process. During the blank mask manufacturing process, a blank mask is formed by depositing a suitable layer (e.g., a reflective multilayer) on a suitable substrate. The blank mask is then patterned during the mask patterning process to achieve the desired design of the integrated circuit (IC) layer. The patterned mask is then used to transfer the circuit pattern (e.g., the design of the IC layer) to a semiconductor wafer. The pattern can be transferred over and over to multiple wafers through various lithography processes. A set of masks is used to build a complete IC.

[0034] In various embodiments, the EUV lithography mask 18 includes suitable structures, such as a binary intensity mask (BIM) and a phase shift mask (PSM). An exemplary BIM includes an absorptive region (also referred to as an opaque region) and a reflective region, which is patterned to define an IC pattern to be transferred to a target. In the opaque region, an absorber is present and the incident light is almost completely absorbed by the absorber. In the reflective region, the absorber is removed and the incident light is diffracted by multiple layers (multilayer reflective structure). The PSM may be an attenuated PSM (AttPSM) or an alternating PSM (AltPSM). An exemplary PSM includes a first reflective layer (e.g., a reflective multilayer reflective structure) and a second reflective layer patterned according to the IC pattern. In some examples, the AttPSM typically has a reflectivity of 2%-15% reflected from its absorber, while the AltPSM typically has a reflectivity of greater than 50% reflected from its absorber.

[0035] Figure 2-Figure 13 is a schematic partial cross-sectional side view of a photolithography mask at various stages of manufacture according to one embodiment of the present disclosure. Figure 2 , showing in more detail Figure 1 EUV lithography mask 18 in. EUV lithography mask 18 includes a substrate 30 made of LTEM. LTEM may include SiO2 doped with TiO2 and / or other low thermal expansion materials known in the art. In some embodiments, for the purpose of an electrostatic chuck, a conductive layer 32 is additionally disposed below a side 42 (also referred to as a back side) of LTEM substrate 30. In one example, conductive layer 32 includes chromium nitride (CrN). In other embodiments, other suitable compositions are also possible, such as materials containing tantalum.

[0036] The EUV lithography mask 18 includes a multilayer reflective structure 34 disposed on a side 44 (also referred to as a front side) of the LTEM substrate 30. The multilayer reflective structure 34 may be selected so that it provides high reflectivity for a selected radiation type / wavelength. The multilayer reflective structure 34 includes a plurality of film pairs, for example, a Mo / Si film pair (e.g., a molybdenum layer is above or below a silicon layer in each film pair). Alternatively, the multilayer reflective structure 34 may include a Mo / Be film pair, or any material with a refractive index difference that is highly reflective at EUV wavelengths.

[0037] Still reference Figure 2, an amorphous layer 50 is formed on the upper surface of the uppermost layer of the multilayer reflective structure 34. The amorphous layer 50 helps the layer formed thereon (i.e., the amorphous cap layer) to achieve an amorphous structure. This is because the lattice arrangement of the thin layer (the cap layer will be the thin layer) (e.g., whether it is a single crystal structure, a polycrystalline structure, or an amorphous structure) is greatly affected by the lattice arrangement of the underlying layer. In other words, if the layer 50 is formed to have an amorphous structure, the layer formed thereon (i.e., the cap layer) may also have an amorphous structure. This can be referred to as "substrate tuning" because the amorphous layer 50 can be considered as an "amorphous substrate" on which the amorphous cap layer is to be formed.

[0038] The amorphous layer 50 may be formed using an amorphous layer forming process 60. In some embodiments, the amorphous layer forming process 60 may include an epitaxial growth process. In some other embodiments, the amorphous layer forming process 60 may include a deposition process. The deposition process may include an atomic layer deposition (ALD) process, for example, an ALD process performed at a low temperature in a range between about 26 degrees Celsius and about 60 degrees Celsius. The deposition process may also include a chemical vapor deposition (CVD) process, for example, an atmospheric pressure CVD (APCVD) process, a low pressure CVD (LPCVD) process, a laser enhanced CVD (LECVD) process, and / or a plasma enhanced CVD (PECVD) process. The deposition process may also include a physical vapor deposition (PVD) process, for example, an electrically heated evaporation (thermal evaporation) process, a pulsed laser deposition process, an electron beam evaporation process, a molecular beam epitaxy process, an ion beam assisted evaporation process, and / or a discharge-based deposition process (e.g., sputtering or arc evaporation).

[0039] The amorphous layer 50 is formed to have a thickness 70. The value of the thickness 70 can be adjusted by adjusting various parameters of the amorphous layer forming process 60 (e.g., deposition time, etc.). In some embodiments, the thickness 70 is adjusted to be within a range between about 0.1 nanometers (nm) and about 4 nm, for example, within a range between about 2 nm and about 4 nm. This thickness range of the amorphous layer 50 helps ensure that the amorphous layer 50 is thick enough to help the cap layer to be formed thereon achieve an amorphous structure, but is not too thick so as not to significantly affect the reflectivity of the multilayer reflective structure 34.

[0040] In some embodiments, the uppermost layer of the multilayer reflective structure 34 is a silicon layer, and the amorphous layer 50 is directly formed on the uppermost surface of the uppermost silicon layer of the multilayer reflective structure 34. In some embodiments, the amorphous layer 50 may include, but is not limited to, amorphous silicon, amorphous silicon oxide (SiO2), or amorphous silicon nitride (SiN).

[0041] Reference now Figure 3, the cap layer 100 is formed on the amorphous layer 50, for example, directly on the upper surface of the amorphous layer 50. The cap layer 100 may be formed by a cap layer forming process 110. In some embodiments, the cap layer forming process 110 may include an epitaxial growth process, a CVD process (e.g., APCVD, LPCVD, LECVD, or PECVD), or a PVD process (e.g., electric heating evaporation, pulsed laser deposition, electron beam evaporation, molecular beam epitaxy, ion beam assisted evaporation, sputtering, or arc evaporation).

[0042] As described above, the presence of the amorphous layer 50 below the cap layer 100 makes it easier for the cap layer 100 to achieve an amorphous structure. In some embodiments, the cap layer 100 includes an amorphous material having amorphous ruthenium. In other embodiments, the cap layer 100 includes an amorphous material having a ruthenium-based compound in an amorphous state. For example, the ruthenium-based compound may include elements such as oxygen (O), niobium (Nb), nitrogen (N), tantalum (Ta), or zirconium (Zr). In some embodiments, the ruthenium-based compound may include: RuO2, RuNb, RuNbO, RuON, RuN, RuNbON, RuTaON, RuZr, or RuZrO. In an embodiment where the ruthenium-based compound is RuNb, the atomic weight of Nb in RuNb is less than or equal to about 50%, for example, about 10%, about 20%, about 30%, about 40%, or about 50%. In embodiments where the ruthenium-based compound is RuNbO, the atomic weight of Nb in RuNbO is less than or equal to about 50%, for example, about 10%, about 20%, about 30%, about 40%, or about 50%.

[0043] These ranges of atomic weights discussed above are specifically adjusted to optimize the performance of the cap layer. In this regard, ruthenium is an ideal candidate for the cap layer because it does not react with hydrogen (hydrogen present in the EUV scanner). However, ruthenium itself may not have the etching resistance that the cap layer 100 should have so that it is not damaged during the various etching processes used to make the EUV lithography mask 18. Niobium is more corrosion resistant than ruthenium. Thus, adding niobium to the ruthenium-based compound will help increase the etching resistance of the cap layer 100. However, if there is too much niobium, such a compound may become more reactive with hydrogen, which is undesirable. Here, the atomic weight of niobium in the ruthenium-based compound is less than 50%, which will help the cap layer 100 to achieve the following goals at the same time: not reacting with the hydrogen present in the EUV scanner, and having sufficient etching resistance to withstand the various etching processes performed herein.

[0044] The cap layer 100 is formed to have a thickness 120. The value of the thickness 120 can be adjusted by adjusting various parameters (e.g., deposition time, etc.) of the cap layer formation process 110. In some embodiments, the thickness 120 is adjusted to be within a range between about 2.5 nm and about 6 nm, for example, within a range between about 2 nm and about 4 nm. This thickness range of the cap layer 100 helps ensure that the cap layer 100 is thick enough to adequately protect the underlying multilayer reflective structure 34, but not too thick so as not to significantly affect the reflectivity of the multilayer reflective structure 34.

[0045] Understandably, Figure 2-Figure 3 Only one embodiment of forming the amorphous capping layer 100 is shown. Figure 4-Figure 5 Another embodiment of forming the amorphous cap layer 100 is shown in FIG. Figure 4 , a multilayer reflective structure 34 is formed on top of the LTEM substrate 30. The treatment process 200 is performed to process the upper surface of the uppermost layer (e.g., the silicon layer of the uppermost Si / Mo film pair) of the multilayer reflective structure 34. The treatment of the uppermost layer of the multilayer reflective structure 34 is conducive to the formation of an amorphous cap layer. In other words, if the uppermost layer of the multilayer reflective structure 34 is not processed by the treatment process 200, the cap layer to be formed thereon is more likely to have a polycrystalline structure, which is undesirable as described above. Here, the treatment of the uppermost layer of the multilayer reflective structure 34 means that the cap layer to be formed thereon can more easily achieve an amorphous structure. As described above, an amorphous cap layer is desirable because it reduces defects in the EUV mask 18, improves lithography performance, and extends the life of the EUV mask 18.

[0046] One reason why the processing of the multilayer reflective structure 34 helps to form an amorphous structure thereon involves free energy. When a film is formed on a substrate, there is a surface free energy of the substrate, a free energy of the film, and a free energy of the interface between the substrate and the film. The delta free energy can be defined as: free energy of the film + free energy of the interface - surface free energy of the substrate. A delta free energy less than 0 is associated with an island growth (Volmer-Weber) mode of film formation, in which "islands" appear first, and then these islands coalesce into a continuous film. This is undesirable because films formed in this manner are more likely to achieve a polycrystalline structure and may therefore be susceptible to damage. On the other hand, a delta free energy greater than 0 is associated with a layered growth (Frank-Van der Merwe) mode of film formation, in which the film grows layer by layer, with each layer mimicking the structure of the layer below. This is more desirable because the (one or more) layers formed in this manner can more easily obtain an amorphous structure. Here, the treatment process 200 performs a dewetting treatment on the uppermost surface of the multi-layer reflective structure 34 and makes the delta free energy greater than 0, which is beneficial to the layer-by-layer amorphous film formation of the cap layer 100 .

[0047] In some embodiments, the treatment process 200 involves applying a plasma to the uppermost layer (e.g., the silicon layer of the Si / Mo film pair) of the multilayer reflective structure 34. For example, the plasma may include an argon (Ar) plasma, an oxygen (O2) plasma, or a nitrogen (N2) plasma. The plasma treatment of the upper surface of the multilayer reflective structure 34 removes stains or grease or other contaminants from the upper surface, and thus improves the uniformity of the upper surface. In some embodiments, the plasma process is performed with a temperature range between about 28 degrees Celsius and about 35 degrees Celsius and a duration range between about 5 seconds and about 60 seconds. Such a temperature range and duration range are not randomly selected, but are actually specifically configured to optimize the effect of the plasma treatment of the uppermost layer of the multilayer reflective structure 34. For example, if the temperature range and / or the duration range are too long or too short, the formation of an amorphous cap layer on the treated surface of the multilayer reflective structure 34 may be destroyed.

[0048] Reference now Figure 5, a cap layer 100 is formed on the uppermost layer of the multilayer reflective structure 34. Likewise, the cap layer 100 may be formed using the cap layer forming process 110 described above, and the cap layer forming process 110 may include an epitaxial growth process, a CVD process, or a PVD process. As described above, the cap layer 100 has an amorphous structure and may include Ru, RuO2, RuNb, RuNbO, RuON, RuN, RuNbON, RuTaON, RuZr, or RuZrO. Also as described above, the process parameters of the cap layer forming process 110 may be configured so that the cap layer 100 has a thickness 120, which may be in a range between about 2.5 nm and about 6 nm.

[0049] It should be understood that the above reference Figure 2-Figure 3 The embodiments discussed and the above references Figure 4-Figure 5 The discussed embodiments may be combined to facilitate the formation of the cap layer 100. For example, in some embodiments, the treatment process 200 may be performed to treat the multilayer reflective structure 34. Thereafter, an amorphous layer 50 (e.g., an amorphous Si layer, an amorphous SiN layer, or an amorphous SiO2 layer) may be formed on the treated surface of the multilayer reflective structure 34. The treated surface of the multilayer reflective structure 34 may also facilitate the formation of an amorphous structure of the amorphous layer 50. Then, the cap layer 100 may be formed on the amorphous layer 50.

[0050] Regardless of how the capping layer 100 is formed to achieve the amorphous structure, further manufacturing processes may be performed to complete the formation of the EUV mask 18. For example, referring now to Figure 6 , an absorber layer 240 (also referred to as an absorber layer) is formed on the cap layer 100. In some embodiments, the absorber layer 240 absorbs EUV radiation directed onto the EUV lithography mask 18. In various embodiments, the absorber layer can be made of tantalum nitride (TaBN), tantalum boron oxide (TaBO), or chromium (Cr), radium (Ra), or a suitable oxide or nitride (or alloy) of one or more of the following materials: actinium, radium, tellurium, zinc, copper, aluminum, nickel, and nickel alloys.

[0051] It should be understood that in some embodiments, a buffer layer may be optionally formed between the cap layer 100 and the absorber layer 240. The buffer layer may be used as an etch stop layer in a patterning or repair process of the absorber layer 240. The buffer layer may have different etching characteristics than the absorber layer disposed thereon. In some embodiments, the buffer layer may include ruthenium, a Ru compound (e.g., RuB or RuSi), chromium, chromium oxide, or chromium nitride.

[0052] Reference now Figure 7, a photoresist layer 260 is formed over the absorber layer 240 from the side 44 using a photoresist forming process 270. In some embodiments, the photoresist forming process 270 may include a spin coating process. The photoresist layer 260 may be an EUV photoresist (e.g., sensitive to radiation in the EUV range). The photoresist layer 260 is patterned into a plurality of portions separated by a plurality of openings (e.g., openings 280, 281, and 282). In some embodiments, the patterning of the photoresist layer 260 may include an electron beam (E-beam) exposure process, a post-exposure bake process, and a photoresist development process.

[0053] Reference now Figure 8 , the absorber layer 240 is etched using an etching process 300, wherein the patterned photoresist layer 260 is used as an etching mask. In other words, the openings 280-282 extend vertically through the absorber layer 240 until a portion of the cap layer 100 is exposed by the openings 280-282. In some embodiments, the etching process 300 may include a dry etching process. The cap layer 100 is effectively used as an etching stop layer for the etching process 300. For a conventional EUV lithography mask in which the cap layer has a polycrystalline structure, the etching process 300 may damage the cap layer due to the polycrystalline structure having grain boundaries. For example, tiny cracks may appear at the exposed upper surface of the polycrystalline cap layer, or the exposed portion of the polycrystalline cap layer may have an overly rough upper surface. These defects may adversely affect the lithography performance and / or shorten the life of the EUV lithography mask. In contrast, the cap layer 100 of the present invention is formed to have an amorphous structure, which allows it to withstand the etching process 300 without causing significant damage. For example, even after performing the etching process 300 , the upper surface of the exposed portion of the capping layer 100 may be substantially flatter and smoother (compared to a polycrystalline capping layer used for conventional EUV lithography masks).

[0054] Reference now Fig. 9 , a photoresist removal process 320 is performed to remove the patterned photoresist layer 260. In some embodiments, the photoresist removal process 320 includes a photoresist stripping or ashing process. The photoresist removal process 320 may also damage the polycrystalline capping layer implemented in a conventional EUV lithography mask. However, because the EUV lithography mask 18 herein instead implements an amorphous capping layer, the photoresist removal process 320 can be performed without substantially damaging the capping layer 100.

[0055] Reference now Fig.10, a photoresist formation process 350 is performed to form another patterned photoresist layer 360 on top of the EUV lithography mask 18. In some embodiments, the photoresist formation process 350 may include a spin coating process. The photoresist layer 360 may be an EUV photoresist (e.g., sensitive to radiation in the EUV range). The photoresist layer 360 is patterned into a plurality of portions separated by a plurality of openings (e.g., openings 380 and 381). The openings 380-381 expose portions of the absorber layer 240. The patterned photoresist layer 360 is also filled in the openings 280-282. In some embodiments, the patterning of the photoresist layer 260 may include an electron beam (E-beam) exposure process or a laser beam exposure, a post-exposure bake process, and a photoresist development process.

[0056] Reference now Fig.11 , an etching process 400 is performed on the EUV lithography mask 18 from the side 44. The patterned photoresist layer 360 is used as a protective layer during the etching process 400 to protect the layers located below from being etched away. At the same time, the etching process 400 etches away portions of the absorber layer 240, the cap layer 100, the amorphous layer 50 (in an embodiment where the amorphous layer 50 is formed), and the multilayer reflective structure 34. The openings 380-381 extend downward (from the side 44 toward the side 42) and pass through the absorber layer 240, the cap layer 100, the amorphous layer 50, and the multilayer reflective structure 34. When reaching the LTEM substrate 30, the etching process 400 stops, and thus portions of the LTEM substrate 30 are exposed by the openings 380-381.

[0057] Reference now Fig.12 , a photoresist removal process 420 is performed to remove the patterned photoresist layer 360. In some embodiments, the photoresist removal process 420 includes a photoresist stripping or ashing process. The photoresist removal process 420 may also damage the polycrystalline capping layer implemented in a conventional EUV lithography mask. However, because the EUV lithography mask 18 herein instead implements an amorphous capping layer, the photoresist removal process 420 can be performed without substantially damaging the capping layer 100.

[0058] After performing the photoresist removal process 420, one or more cleaning processes may also be performed to clean the EUV lithography mask 18, for example, to remove contaminant particles disposed on the EUV lithography mask 18. Because portions of the cap layer 100 are still exposed by the openings 280-282, if the cap layer is implemented using a polycrystalline material, the chemicals used in the one or more cleaning processes (e.g., a solution containing oxygen and / or hydrogen) may penetrate into the cracked or rough surface of the cap layer and thus further damage the cap layer. However, because the cap layer 100 herein is implemented using an amorphous material, according to an embodiment of the present disclosure, the cleaning process will not damage the cap layer 100.

[0059] Reference now Fig.13 , one or more wafer printing processes 470 can be performed using the EUV lithography mask 18. In other words, the EUV lithography mask 18 can be used as a lithography mask in one or more EUV lithography processes to define or pattern various features on a semiconductor wafer. The wafer printing process 470 can generate outgassing products, for example, outgassing products containing carbon, hydrogen, oxygen, etc. These outgassing products can contact various components of the EUV lithography mask 18, including the exposed surface of the cap layer 100. If the cap layer 100 is implemented using a polycrystalline material (for example, in a conventional EUV lithography mask), such exposed surfaces may have suffered extensive damage (for example, excessive roughness or cracks) when the wafer printing process 470 is performed. Outgassing products are more likely to adhere to the exposed (and damaged) surface of the cap layer because the rough surface of such a cap layer will capture the outgassing products. The presence of outgassing products on the damaged cap layer surface will contaminate the EUV lithography mask and further reduce the performance of the lithography process. For example, due to the adhesion of outgassing products on the cap layer surface, the reflectivity of the multilayer reflective structure 34 will be undesirably changed. Again, the EUV lithography mask 18 of the present disclosure does not suffer from this problem because the amorphous cap layer 100 is substantially undamaged, and thus the outgassing products generated by the wafer printing process 470 will not adhere to the exposed surface of the cap layer 100. Therefore, the present disclosure avoids undesirable contamination of the EUV lithography mask 18.

[0060] Fig.14 is a flow chart of a method 600 of performing a semiconductor manufacturing process according to various aspects of the present disclosure.

[0061] The method 600 includes a step 610 of forming a multilayer reflective structure over a substrate. In some embodiments, the reflective structure includes a multilayer structure configured to provide high reflectivity, eg, a reflectivity above a predetermined threshold, for a predetermined radiation wavelength.

[0062] The method 600 includes depositing or growing an amorphous layer over the multilayer reflective structure 620. In some embodiments, depositing or growing the amorphous layer includes depositing or growing an amorphous silicon layer, an amorphous silicon oxide layer, or an amorphous silicon nitride layer.

[0063] Method 600 includes step 630 of depositing or growing a capping layer on the amorphous layer. In some embodiments, depositing or growing the capping layer includes depositing or growing an amorphous material containing ruthenium as the capping layer. The amorphous material may further contain: oxygen, niobium, nitrogen, tantalum or zirconium.

[0064] The method 600 includes a step 640 of performing an EUV lithography process. For example, the substrate, the multilayer reflective structure, the amorphous layer, and the capping layer may be part of an extreme ultraviolet (EUV) lithography mask. The EUV lithography process may be performed using the EUV lithography mask.

[0065] It should be understood that additional processes may be performed before, during, or after steps 610-640 of method 600 to complete the fabrication of the photolithography mask. For example, before depositing or growing the amorphous layer, method 600 may include the step of performing a plasma treatment process on the multilayer reflective structure. In some embodiments, the plasma treatment process includes applying Ar plasma, O2 plasma, or N2 plasma to the multilayer reflective structure. For simplicity, the other steps are not discussed in detail herein.

[0066] Fig.15 is a flow chart of a method 700 of performing a semiconductor manufacturing process according to various aspects of the present disclosure.

[0067] Method 700 includes step 710 of forming a multilayer reflective structure over a substrate. In some embodiments, the reflective structure includes a multilayer structure configured to provide high reflectivity, eg, a reflectivity above a predetermined threshold, for a predetermined radiation wavelength.

[0068] The method 700 includes a step 720 of treating the multilayer reflective structure with plasma. In some embodiments, the step 720 includes treating the multilayer reflective structure with Ar plasma, O2 plasma, or N2 plasma.

[0069] The method 700 includes a step 730 of forming an amorphous capping layer over the multilayer reflective structure. The step 730 may be performed after the multilayer reflective structure has been processed.

[0070] The method 700 includes a step 740 of performing an EUV lithography process. For example, the substrate, the multilayer reflective structure, and the cap layer may be part of an extreme ultraviolet (EUV) lithography mask. The EUV lithography process may be performed using the EUV lithography mask.

[0071] It should be understood that additional processes may be performed before, during, or after steps 710-740 of method 700 to complete the fabrication of the photolithographic mask. For example, after the processing of step 720 but before the formation of the amorphous capping layer of step 730, method 700 may include the step of forming a first layer over the multilayer reflective structure. The amorphous capping layer is formed over the first layer. In some embodiments, the first layer is formed to have a different type of amorphous material than the amorphous capping layer. For simplicity, the other steps are not discussed in detail herein.

[0072] In summary, the present disclosure forms an amorphous capping layer for EUV lithography masks. The amorphous capping layer can be formed by substrate tuning, which can include first forming a thin amorphous layer on a multilayer reflective structure, and then forming an amorphous capping layer on the thin amorphous layer using an epitaxial process or a CVD or PVD process. The amorphous capping layer can also be formed by processing a multilayer reflective structure, and then forming an amorphous capping layer on the processed surface of the multilayer reflective structure using an epitaxial process or a CVD or PVD process.

[0073] Based on the above discussion, it can be seen that the EUV mask of the present disclosure provides advantages over conventional EUV masks. However, it should be understood that other embodiments may provide additional advantages, and it is not necessary to disclose all advantages herein, and no specific advantages are required for all embodiments. One advantage is that the EUV lithography mask of the present disclosure can achieve better film quality for the cap layer compared to conventional EUV lithography masks. As described above, conventional EUV lithography masks form a polycrystalline cap layer, and the grain boundaries of the polycrystalline cap layer are easily damaged due to the performance of various etching and / or cleaning processes. A damaged polycrystalline cap layer may result in a decrease in lithography performance (e.g., poor critical dimensions). In contrast, the EUV lithography mask of this article forms an amorphous cap layer, which can better withstand the damage effects of various etching and / or cleaning processes compared to the polycrystalline cap layer. Therefore, the amorphous cap layer has an improved film quality, and thus the EUV lithography mask of this article has improved lithography performance compared to conventional EUV lithography masks.

[0074] In addition, because EUV lithography masks are used in wafer printing, outgassing products may be generated. These outgassing products are more likely to adhere to the exposed surface of the damaged polycrystalline cap layer of the conventional EUV lithography mask, which may reduce the lithography performance. Here, since the amorphous cap layer basically has no damaged surface, the outgassing products are less likely to adhere to the EUV lithography mask of the present disclosure. Therefore, the lithography performance is improved.

[0075] In addition, a damaged polycrystalline cap layer of a conventional EUV lithography mask may cause the conventional EUV mask to fail more quickly, or at least degrade the EUV lithography mask to the point where it no longer has satisfactory performance and should be replaced. In other words, the tendency of the polycrystalline cap layer to be easily damaged may shorten the life of a conventional EUV lithography mask. In contrast, the amorphous cap layer of the present invention can substantially extend the life of the EUV lithography mask. Since replacing or repairing an EUV lithography mask can be expensive, the present disclosure can substantially reduce manufacturing costs.

[0076] One aspect of the present disclosure relates to a device. The device includes a substrate. The device includes a multilayer reflective structure disposed on the substrate. The device includes an amorphous cap layer disposed on the multilayer reflective structure.

[0077] Another aspect of the present disclosure relates to a method. The method includes forming a multilayer reflective structure on a substrate. The method includes depositing or growing an amorphous layer on the multilayer reflective structure. The method includes depositing or growing a cap layer on the amorphous layer.

[0078] Another aspect of the present disclosure relates to a method. The method includes forming a multilayer reflective structure on a substrate. The method includes treating the multilayer reflective structure using plasma. The method includes: after the treatment, forming an amorphous cap layer on the multilayer reflective structure.

[0079] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0080] Example 1. A semiconductor device comprising:

[0081] substrate;

[0082] a multi-layer reflective structure disposed on the substrate; and

[0083] The amorphous cap layer is arranged on the multi-layer reflective structure.

[0084] Example 2. The device of Example 1, wherein the amorphous capping layer comprises ruthenium.

[0085] Example 3. The device of Example 2, wherein the amorphous cap layer further comprises: oxygen, niobium, nitrogen, tantalum, or zirconium.

[0086] Example 4. The device of Example 2, wherein the amorphous cap layer comprises Ru, RuO2, RuNb, RuNbO, RuON, RuN, RuNbON, RuTaON, RuZr, or RuZrO.

[0087] Example 5. The device of Example 4, wherein the amorphous cap layer comprises:

[0088] RuNb, wherein the atomic weight of Nb in RuNb is less than 50%; or

[0089] RuNbO, wherein the atomic weight of Nb in RuNbO is less than 50%.

[0090] Example 6. The device according to Example 1 further includes: an amorphous layer disposed between the multilayer reflective structure and the amorphous cap layer.

[0091] Example 7. The device of Example 6, wherein the amorphous layer comprises amorphous silicon, amorphous silicon oxide, or amorphous silicon nitride.

[0092] Example 8. The device of Example 1, wherein the multilayer reflective structure includes a plurality of pairs of silicon films and molybdenum films.

[0093] Example 9. The device of Example 1, wherein the device is an extreme ultraviolet (EUV) lithography mask.

[0094] Example 10. A method for forming a semiconductor device, comprising:

[0095] forming a multi-layer reflective structure on the substrate;

[0096] depositing or growing an amorphous layer on the multilayer reflective structure; and

[0097] A capping layer is deposited or grown over the amorphous layer.

[0098] Example 11. A method according to Example 10, wherein the substrate, the multilayer reflective structure, the amorphous layer and the cap layer are part of an extreme ultraviolet (EUV) lithography mask, and wherein the method further comprises: providing the EUV lithography mask to an entity performing an EUV lithography process.

[0099] Example 12. The method according to Example 10, wherein depositing or growing the amorphous layer comprises: depositing or growing an amorphous silicon layer, an amorphous silicon oxide layer, or an amorphous silicon nitride layer.

[0100] Example 13. The method of Example 10, wherein depositing or growing the cap layer comprises depositing or growing an amorphous material comprising ruthenium as the cap layer.

[0101] Example 14. The method of Example 13, wherein the amorphous material further comprises: oxygen, niobium, nitrogen, tantalum or zirconium.

[0102] Example 15. The method according to Example 10 further includes: performing a plasma treatment process on the multilayer reflective structure before depositing or growing the amorphous layer.

[0103] Example 16. The method of Example 15, wherein the plasma treatment process includes applying Ar plasma, O2 plasma, or N2 plasma.

[0104] Example 17. A method for forming a semiconductor device, comprising:

[0105] forming a multi-layer reflective structure on the substrate;

[0106] treating the multilayer reflective structure using plasma; and

[0107] After the processing, an amorphous capping layer is formed over the multilayer reflective structure.

[0108] Example 18. The method of Example 17, further comprising: forming a first layer over the multilayer reflective structure after the processing but before forming the amorphous capping layer, wherein the amorphous capping layer is formed over the first layer.

[0109] Example 19. The method of Example 18, wherein the first layer is formed to have an amorphous layer of a different type than the amorphous cap layer.

[0110] Example 20. The method of Example 17, wherein the treatment includes treating the multilayer reflective structure using Ar plasma, O2 plasma, or N2 plasma.

Claims

1. A semiconductor device, comprising: substrate; A multi-layer reflective structure is disposed on the substrate; An amorphous cap layer, disposed on the multi-layer reflective structure; as well as An amorphous layer is disposed between the multilayer reflective structure and the amorphous capping layer, wherein the amorphous layer is formed on an upper surface of an uppermost layer of the multilayer reflective structure, wherein the amorphous layer has an amorphous material different from that of the amorphous capping layer.

2. The device according to claim 1, wherein The amorphous capping layer includes ruthenium.

3. The device according to claim 2, wherein The amorphous cap layer further includes oxygen, niobium, nitrogen, tantalum or zirconium.

4. The device according to claim 2, wherein The amorphous capping layer includes Ru, RuO2, RuNb, RuNbO, RuON, RuN, RuNbON, RuTaON, RuZr or RuZrO.

5. The device according to claim 4, wherein The amorphous cap layer comprises: RuNb, wherein the atomic weight of Nb in RuNb is less than 50%; or RuNbO, wherein the atomic weight of Nb in RuNbO is less than 50%.

6. The device according to claim 1, wherein The amorphous layer includes amorphous silicon, amorphous silicon oxide or amorphous silicon nitride.

7. The device according to claim 1, wherein The multilayer reflective structure includes a plurality of pairs of silicon films and molybdenum films.

8. The device according to claim 1, wherein The device is an extreme ultraviolet (EUV) lithography mask.

9. A method for forming a semiconductor device, comprising: forming a multi-layer reflective structure on the substrate; depositing or growing an amorphous layer on the multilayer reflective structure, wherein the amorphous layer is formed on an upper surface of an uppermost layer of the multilayer reflective structure; as well as A capping layer is deposited or grown over the amorphous layer.

10. The method according to claim 9, wherein: The substrate, the multilayer reflective structure, the amorphous layer, and the capping layer are part of an extreme ultraviolet (EUV) lithography mask, and wherein the method further comprises providing the EUV lithography mask to an entity that performs an EUV lithography process.

11. The method according to claim 9, wherein: Depositing or growing the amorphous layer includes: depositing or growing an amorphous silicon layer, an amorphous silicon oxide layer or an amorphous silicon nitride layer.

12. The method according to claim 9, wherein: Depositing or growing the capping layer includes depositing or growing an amorphous material including ruthenium as the capping layer.

13. The method according to claim 12, wherein: The amorphous material further includes oxygen, niobium, nitrogen, tantalum or zirconium.

14. The method according to claim 9, further comprising: Before depositing or growing the amorphous layer, a plasma treatment process is performed on the multilayer reflective structure.

15. The method according to claim 14, wherein: The plasma treatment process includes applying Ar plasma, O2 plasma or N2 plasma.

16. A method for forming a semiconductor device, comprising: forming a multi-layer reflective structure on the substrate; Treating the multilayer reflective structure using plasma; forming an amorphous layer on the multi-layer reflective structure, wherein the amorphous layer is formed on an upper surface of an uppermost layer of the multi-layer reflective structure; as well as An amorphous capping layer is formed on the amorphous layer.

17. The method according to claim 16, wherein: The amorphous layer is formed to have a different type of amorphous material than the amorphous capping layer.

18. The method according to claim 16, wherein: The treating includes treating the multilayer reflective structure using Ar plasma, O2 plasma or N2 plasma.

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