Latency and throughput centric reconfigurable storage device

Abstract

A storage device includes a storage controller that receives data from a host device and stores the data in a storage memory, a reconfigurable integrated circuit that is communicatively connected to the storage controller and accelerates logical operations performed on the data stored in the storage memory, the reconfigurable integrated circuit including a first logic block that performs static logical operations among the logical operations, a second logic block that performs one or more dynamic logical operations among the logical operations, and a plurality of memory buffers configured to store inputs and outputs of the first logic block and the second logic block.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and interest in U.S. Provisional Application No. 62 / 966,443, filed January 27, 2020, entitled “LATENCY AND THROUGHPUT CENTRCIRECONFIGURABLE STORAGE DEVICES,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of one or more exemplary embodiments of this disclosure relate to storage devices, and more specifically, to storage devices for near-memory acceleration of latency-critical and throughput-oriented data-intensive operations. Background Technology

[0004] A storage system typically includes a host device and one or more storage devices. Such storage devices include, for example, magnetic storage devices (e.g., hard disk drives (HDDs), optical storage devices (e.g., Blu-ray disc drives, optical disc (CD) drives, digital versatile discs (DVDs), etc.), and flash memory devices (e.g., USB flash drives, solid-state drives (SSDs), etc.). Generally, to process data stored in a storage device, the host device first reads the data from the storage device, transferring the data from the storage device to the host device's main memory. The host device (e.g., a host device including a host processor, such as a central processing unit (CPU)) can then process the data transferred from the storage device to the host device's main memory.

[0005] For example, in the context of a database management system, a host device can output a response to an input database query by performing various data-intensive operations on data stored in a storage device. As an illustrative example, the host device can perform various operations (e.g., filtering, sorting, grouping, aggregation, etc.) on a table of data elements stored in a storage device by first reading data elements from the storage device and then processing those data elements to identify and output a subset of the data elements corresponding to the input database query. Such operations can be data-intensive because they may require a large amount of data (e.g., the data element table) to be transferred from the storage device to the host device for processing. When data-intensive operations are handled by the host device, resulting in a large amount of data being transferred between the storage device and the host device for processing, the host device's resources (e.g., CPU utilization, bandwidth, and / or the like) may be overused, latency may be introduced, and the performance of the storage system may degrade.

[0006] Therefore, storage devices may be desired for accelerating data-intensive operations that are closer to the storage.

[0007] The above information disclosed in this Background section is only for enhancing the understanding of the background of the present disclosure, and therefore, it can contain information that does not constitute prior art. SUMMARY

[0008] One or more example embodiments of the present disclosure are directed to a storage device for latency-critical and throughput-oriented near-memory acceleration of data-intensive operations and a method thereof.

[0009] According to one or more example embodiments of the present disclosure, a storage device includes a storage controller configured to receive data from a host device and store the data in a storage memory, and a reconfigurable integrated circuit communicably connected to the storage controller and configured to accelerate a logical operation performed on the data stored in the storage memory, the reconfigurable integrated circuit including a first logic block configured to perform a static logical operation among the logical operation, a second logic block configured to perform one or more dynamic logical operations among the logical operation, and a plurality of memory buffers configured to store inputs and outputs of the first and second logic blocks.

[0010] In an example embodiment, the logical operation can correspond to a pipelined workflow, the first logic block can be configured to be statically configured with a static logical operation for the pipelined workflow, and the second logic block can be configured to be dynamically reconfigured with one or more dynamic logical operations for at least one stage of the pipelined workflow.

[0011] In an example embodiment, the one or more dynamic logical operations can include a first dynamic logical operation and a second dynamic logical operation, the second logic block can be configured with the first dynamic logical operation during a first stage of the pipelined workflow, and the second logic block can be dynamically reconfigured with the second dynamic logical operation during a second stage of the pipelined workflow.

[0012] In an example embodiment, the plurality of memory buffers can include an input / output (I / O) buffer configured to store inputs and outputs of the first and second logic blocks, an intermediate I / O buffer configured to store intermediate outputs of the second logic block when the second logic block is reconfigured, and a configuration buffer configured to store a configuration file to reconfigure the second logic block.

[0013] In an example embodiment, the second logic block can be dynamically reconfigured by loading a configuration file in the configuration file stored in the configuration buffer to the second logic block.

[0014] In an example embodiment, during the first phase, the output of the second logic block can be stored in the intermediate I / O buffer, the second logic block can be reconfigured with different dynamic logic instructions for the second phase, and during the second phase, the intermediate I / O buffer can be designated as an input buffer for the second logic block.

[0015] In an example embodiment, the static logic operation can correspond to a latency- critical operation, and the one or more dynamic logic operations can correspond to throughput- oriented operations.

[0016] In an example embodiment, the latency-critical operation can be an operation with a completion time less than a reconfiguration time of the second logic block.

[0017] In an example embodiment, the storage device can be a solid state drive.

[0018] In an example embodiment, the reconfigurable integrated circuit can be a field programmable gate array (FPGA).

[0019] According to one or more example embodiments of the present disclosure, a method for accelerating operations in a storage device, the storage device including a storage controller, a storage memory, and a reconfigurable integrated circuit including a first logic block, a second logic block, and a buffer, the method comprising: performing, by the first logic block, a first logic operation on input data stored in the storage memory; storing, by the first logic block, an output of the first logic operation in an intermediate output buffer of the buffer; configuring, by the reconfigurable integrated circuit, a second logic operation in the second logic block; designating, by the reconfigurable integrated circuit, the intermediate output buffer as an input buffer for the second logic operation; performing, by the second logic block, the second logic operation on the output of the first logic operation stored in the intermediate output buffer.

[0020] In an example embodiment, the second logic operation can be configured in the second logic block while the first logic operation is performed in the first logic block.

[0021] In an example embodiment, configuring the second logic operation in the second logic block can include monitoring a value of the intermediate output buffer, determining that the value exceeds a threshold, and in response to the value exceeding the threshold, configuring the second logic operation in the second logic block.

[0022] In an example embodiment, the threshold can be a high water mark of the intermediate output buffer.

[0023] In an example embodiment, the buffer can include a configuration buffer configured to store a configuration file for configuring the second logic block.

[0024] In example embodiments, configuring the second logical operation in the second logic block can include loading a bitfile corresponding to the second logical operation in the configuration file stored in the configuration buffer into the second logic block.

[0025] In example embodiments, designating the intermediate output buffer as an input buffer for the second logical operation can include determining whether the first logical operation is stalled, designating the intermediate output buffer as an input buffer for the second logical operation in response to determining that the first logical operation is stalled, and designating an input buffer of the first logical operation as an output buffer for the second logical operation.

[0026] In example embodiments, determining whether the first logical operation is stalled can include determining whether an end of the intermediate output buffer is reached.

[0027] In example embodiments, the method can further include determining that the second logic block has processed all outputs of the first logical operation stored in the intermediate output buffer, and designating an output buffer of the second logical operation as a final output buffer.

[0028] In example embodiments, the storage device can be a solid state drive, and the reconfigurable integrated circuit can be a field programmable gate array (FPGA). BRIEF DESCRIPTION OF DRAWINGS

[0029] The above and other aspects and features of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, by the way of examples of embodiments thereof.

[0030] Figure 1 is a system diagram of a storage system in accordance with one or more example embodiments of the present disclosure.

[0031] Figure 2 is a block diagram illustrating a reconfigurable processing device of a storage device in accordance with one or more example embodiments of the present disclosure.

[0032] Figure 3 is a block diagram illustrating an extended memory of a reconfigurable processing device of a storage device in accordance with one or more example embodiments of the present disclosure.

[0033] Figure 4 is an illustrative example of a pipelined workflow in accordance with one or more example embodiments of the present disclosure.

[0034] Figure 5A illustrates a comparison example in which a storage device is statically configured with operations associated with a pipelined workflow of Figure 4

[0035] Figure 5B is utilized with operations associated with a pipelined workflow of​Figure 4 An illustrative example of a storage device according to one or more embodiments of the present disclosure associated with an operation configuration of a pipeline workflow.

[0036] Figure 6A and Figure 6B A method of accelerating data-intensive operations by a storage device according to one or more example embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0037] Hereinafter, example embodiments will be described in greater detail with reference to the accompanying drawings, in which like reference numerals refer to like elements throughout. The present disclosure may, however, be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques not necessary to an understanding of the aspects and features of the present disclosure can not be described. Like reference numerals refer to like elements throughout the accompanying drawings and the written description, so that the description will not be redundant and will not be repeated.

[0038] One or more example embodiments of the present disclosure are directed to a storage device for accelerating data-intensive operations of a host device closer to storage (e.g., near storage or in-storage). For example, a host device can offload data-intensive operations to a storage device such that the storage device processes data stored therein according to the data-intensive operations. In this case, in some embodiments, the storage device can process raw data stored therein to output a reduced amount of data and can pass the reduced amount of data to the host device instead of passing raw data (e.g., the entire raw data) to be processed by the host device. Thus, rather than reading data from the storage device by the host device and processing the freshly acquired data, a large amount of operations that would otherwise be performed by the host device on the freshly acquired data is offloaded into the storage device such that resources (e.g., CPU usage, bandwidth, etc.) of the host device can be used for, for example, cross-device operations (e.g., such as joint information from tables stored in multiple storage devices). Thus, performance of a storage system can be boosted, for example, by reducing the amount of traffic between the host device and the storage device.

[0039] In some embodiments, when data-intensive operations are offloaded to storage devices, the storage devices can improve scalability, e.g., by reducing resources of a host device that would otherwise be used to process data fetched from storage devices. For example, when a host device processes data-intensive operations, the host device can become a bottleneck for effective scalability. As an illustrative example, horizontally scaled clusters used in modern data processing systems can typically use servers that include one or two low-to-moderate core count CPUs that can process data for 4 to 8 SSDs before reaching the maximum limit of their interfaces. In such cases, to scale the storage of such data processing systems, additional servers can typically be added to the scaled cluster in order to process additional processing of data from additional SSDs, rather than scaling the number of SSDs that the core CPUs of the existing servers in the scaled cluster can process. On the other hand, according to one or more example embodiments, storage devices can accelerate data-intensive operations of host devices so that each server can process more data. For example, if data is first filtered by a storage device so that a minimal filtered table is sent to a host device to be joined with information of other tables (e.g., stored on the same or other storage devices within the server), the overall performance of a given decision support benchmark can be improved without requiring additional servers in the cluster.

[0040] In some embodiments, storage devices can be at least partially dynamically (e.g., in real-time or near real-time) reconfigurable (e.g., reprogrammable) to process data stored therein. For example, in some embodiments, a storage device can include a plurality of logical blocks configured to perform data-intensive operations offloaded to the storage device. In some embodiments, the logical blocks can include static logical blocks and dynamic logical blocks. Static logical blocks can correspond to logical blocks that are statically configured in the storage device for at least an entire pipeline workflow. Dynamic logical blocks can correspond to logical blocks that can be dynamically reconfigured when needed or desired at one or more stages of a pipeline workflow. As used herein, a pipeline workflow refers to a series of operations (e.g., processing) performed on data in stages (e.g., concurrently and / or sequentially) such that data read from a storage device can be an input to a first operation of a first stage of a pipeline workflow, an output of the first operation of the first stage can be an input to a second operation of a second stage of the pipeline workflow, and so on until an output of a final operation of a final stage of the pipeline workflow is a final result of the series of operations.

[0041] In some embodiments, operations corresponding to a given pipeline workflow can include one or more operations that are latency-critical operations and / or one or more operations that are throughput-oriented operations. As used herein, a latency-critical operation can refer to an operation that seeks to optimize or reduce the time taken from the start of a read operation on data to the end of an operation performed on the read data, while a throughput-oriented operation can refer to an operation that seeks to optimize or increase a rate parameter, such as, for example, the number of operations performed per unit time or the amount of data processed per unit time, but not necessarily the latency of any one operation. In this case, latency-critical operations (which can not be able to tolerate the time taken to reconfigure a storage device) can correspond to static logic blocks, and throughput-oriented operations (which can be able to tolerate the time taken to reconfigure a storage device) can correspond to dynamic logic blocks.

[0042] For example, in some embodiments, reconfiguring a dynamic logic block can take a reconfiguration time (e.g., approximately 1 millisecond (ms)), whereas user requirements (e.g., a service level agreement (SLA)) can require certain latency-critical operations to be performed in a shorter time (e.g., approximately 25 microseconds (ps)) than the reconfiguration time. In this case, the latency-critical operations can not be able to tolerate the time taken to reconfigure the dynamic logic block (e.g., can be operations with a completion time less than the reconfiguration time), and thus, the latency-critical operations can be configured in static logic blocks. On the other hand, when a storage device includes only static logic blocks, the operations that can be offloaded to the storage device can be limited according to the fixed resources of the storage device. For example, in this case, data-intensive operations can be configured on the storage device simultaneously (e.g., synchronously or at the same time), and thus, the amount of data processed and / or the types of operations that can be configured on the storage device simultaneously can be limited by the fixed resources of the storage device.

[0043] In some embodiments, the storage device can be configured (e.g., reconfigured or reprogrammed) at start time and / or run time (e.g., in real-time or near real-time) as needed or desired according to various user requirements (e.g., service level agreements (SLAs), etc.), available resources of the storage device (e.g., available memory, available number of lookup tables (LUTs), etc.), pipelined workflows, acceleration performance, data size, selectivity of data reduction operations, etc. For example, in some embodiments, delay critical operations and / or throughput centric operations can be configured in static logic blocks and dynamic logic blocks as needed or desired in view of SLAs (e.g., operations deemed to be delay critical), reconfiguration time of the logic blocks, available resources of the storage device (e.g., its reconfigurable integrated circuits), pipelined workflows, etc. In another embodiment, the storage device can operate in various modes according to acceleration performance and / or selectivity of its data reduction operations. For example, in some embodiments, if data intensive operations offloaded to the storage device do not actually reduce the data size that is ultimately returned to the host device, the data intensive operations offloaded to the storage device can be performed by the host device instead, such that the storage device can be dynamically reconfigured to operate in a normal mode (e.g., a mode in which data is read and processed by the host device instead of being offloaded to the storage device).

[0044] These and other aspects and features of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0045] Figure 1 is a system diagram of a storage system according to one or more example embodiments of the present disclosure.

[0046] Briefly summarized, a storage system 100 according to one or more embodiments of the present disclosure can include a host device (e.g., host computer) 102 and a storage device 104. The host device 102 can offload various data-intensive operations to the storage device 104 such that the storage device 104 accelerates the data-intensive operations of the host device 102. For example, the host device 102 can be communicably connected to the storage device 104 and can pass data to the storage device 104 to store the data in the storage device 104. The host device 102 can send various commands to the storage device 104 such that the storage device 104 processes data stored therein according to the commands, rather than sending the entire data to a host memory (e.g., main memory) 108 to be processed by a host processor (e.g., CPU) 106. For example, instead of sending a large amount of raw data stored in the storage device 104 to the host memory 108 to be mostly filtered out by the host processor 106, the storage device 104 can process the raw data stored therein in response to the commands to output a reduced amount of processed data (e.g., a subset of the raw data) to the host device 102. Thus, a large amount of operations performed on freshly acquired data can be offloaded to the storage device 104 to be performed closer to the storage (e.g., near storage or in storage) such that resources (e.g., CPU usage, I / O bus bandwidth, CPU cache capacity, cache-to-memory bandwidth, memory capacity, etc.) of the host device 102 can be used for other operations, such as in-memory operations and cross-device operations (e.g., joint data stored on multiple storage devices)

[0047] In more detail, referring to Figure 1 , the host device 102 can include a host processor 106 and a host memory 108. The host processor 106 can be a general-purpose processor, such as a CPU core of the host device 102, for example. The host memory 108 can be considered a high-performance main memory (e.g., primary memory) of the host device 102. For example, in some embodiments, the host memory 108 can include (or can be) a volatile memory, such as a dynamic random access memory (DRAM), for example. However, the present disclosure is not so limited, and the host memory 108 can include (or can be) any suitable alternative to a high-performance main memory (e.g., primary memory) of the host device 102, as known to those skilled in the art. For example, in other embodiments, the host memory 108 can be a relatively high-performance non-volatile memory, such as a NAND flash memory, a phase change memory (PCM), a resistive RAM, a spin-torque transfer RAM (STTRAM), any suitable memory based on PCM technology, a memristor technology, and / or a resistive random access memory (ReRAM), for example, and can include, for example, a chalcogenide, etc.

[0048] Storage device 104 can be considered a secondary storage that can permanently store data accessible to host device 102. In this context, storage device 104 can include (or can be) a relatively slower memory as compared to the high performance memory of host memory 108. For example, in some embodiments, storage device 104 can be a secondary storage of host device 102, such as an SSD. However, the present disclosure is not so limited, and in other embodiments, storage device 104 can include (or can be) any suitable storage device, such as, for example, an HDD, a USB flash drive, a Blu-ray disc drive, etc. In some embodiments, storage device 104 can conform to a large form factor technology standard (e.g., a 3.5-inch hard drive form factor technology), a small form factor technology standard (e.g., a 2.5-inch hard drive form factor technology), an M.2 form factor technology, etc. In other embodiments, storage device 104 can conform to any suitable or desired derivative of these form factor technologies.

[0049] In some embodiments, storage device 104 can include storage interface 110, storage controller 112, storage memory 114, reprogrammable integrated circuit (RIC) device 116, a direct (or dedicated) interconnect 118 between storage controller 112 and RIC device 116, and RIC expansion memory 120. Storage interface 110 can facilitate communication between host device 102 and storage device 104 (e.g., using a connector and a protocol). For example, in some embodiments, storage interface 110 can be faced with data communication to and from storage controller 112 and / or RIC device 116 of host device 102. In some embodiments, storage interface 110 can facilitate the exchange of storage requests and responses between host device 102 and storage device 104. In some embodiments, storage interface 110 can facilitate data transfer to and from host memory 108 of host device 102 to and from storage device 104. For example, in some embodiments, storage interface 110 (e.g., a connector and its protocol) can include (or can conform to) Peripheral Component Interconnect Express (PCIe), Ethernet-based Remote Direct Memory Access (RDMA), Serial Advanced Technology Attachment (SATA), Fibre Channel, Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), etc. In other embodiments, storage interface 110 (e.g., a connector and its protocol) can include (or can conform to) various general-purpose interfaces, such as, for example, Ethernet, Universal Serial Bus (USB), etc. In other embodiments, storage interface 110 can support additional acceleration or coherency protocols on top of its own connector and related protocol, such as CCIX, CAPI, OpenCAPI, nvLink, or CXL.

[0050] The storage controller 112 is connected to the storage interface 110 and is responsive to input / output (I / O) requests received from the host device 102 through the storage interface 110. The storage controller 112 can provide an interface to control the storage memory 114 and provide access to and from the storage memory 114. For example, the storage controller 112 can include at least one processing circuitry embedded thereon for interfacing with the host device 102 and the storage memory 114. The processing circuitry can include, for example, a digital circuitry (e.g., a microcontroller, a microprocessor, a digital signal processor, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.) that is capable of executing data access instructions to provide access to and from data stored in the storage memory 114 in accordance with the data access instructions. For example, the data access instructions can include any suitable data storage and retrieval algorithm (e.g., read / write) instructions, encryption / decryption algorithm instructions, compression algorithm instructions, etc. The storage memory 114 can store data received from the host device 102 permanently. For example, in the context of a database management system, the storage memory 114 can store data in any suitable self-describing columnar format, such as, for example, AVRO, ORC, PARQUET, etc. However, the present disclosure is not limited thereto, and the storage memory 114 can store data in any suitable format depending on the application of the storage system 100. For example, in the context of a media system, the storage memory 114 can store data in any suitable media format, such as, for example, H.264, H.265, MPEG, AVI, etc. In some embodiments, the storage memory 114 can store data received from the host device 102 in an encrypted and / or compressed format. The storage memory 114 can include a non-volatile memory, such as, for example, NAND flash. However, the present disclosure is not limited thereto, and depending on the type of storage device 104, the storage memory 114 can include any suitable memory, such as, for example, phase change memory, magnetic memory, ferroelectric memory, etc.

[0051] The RIC device 116 can process data stored in the storage memory 114 according to commands from the host device 102. For example, in some embodiments, the RIC device 116 can be communicably connected to the storage controller 112 (e.g., via the direct interconnect 118) to access (e.g., read) data stored in the storage memory 114, and can process (e.g., can reduce, filter, sort, group, aggregate, deduplicate, etc.) the read data such that a reduced amount of processed data (e.g., a subset of the retrieved data stored in the storage memory 114) is sent to the host device 102. In this case, the RIC device 116 can include a plurality of logic blocks having various suitable configurations to process data stored in the storage memory 114 according to commands from the host device 102. As used herein, a logic block can include a logical component of the RIC device 116, and can include gates and flip-flops with their connections configured (e.g., as defined in a lookup table (LUT) in the case of certain field programmable gate arrays (FPGAs)) to perform various logical operations (e.g., filtering, sorting, aggregating, deduplicating, etc.). Because the RIC device 116 can include logic blocks to perform various operations on freshly acquired data in place of the host device 102, resource utilization (e.g., CPU usage, PCI bandwidth, etc.) of the host device 102 can be reduced.

[0052] Accordingly, the RIC device 116 can be considered a separate and distinct processor from the processor(s) of the host device 102 (e.g., from the host processor(s) 106). For example, in some embodiments, the RIC device 116 can be implemented as an integrated circuit (IC). In some embodiments, the RIC device 116 can be implemented on the storage device 104 (e.g., can be embedded on the same board or the same circuit board as the storage device 104). For example, the RIC device 116 can be implemented on (e.g., can be attached to or mounted on) the storage device 104 as a system on a chip (SOC). In this case, because the RIC device 116 can be implemented on the storage device 104, data stored in the storage device 104 can be processed closer to the storage memory 114. Accordingly, latency that can be incurred when transferring data stored in the storage memory 114 over a long distance and / or over an external interface can be reduced or minimized. The storage system 100 can additionally benefit from the additional internal data transfer bandwidth between the RIC device 116 and the storage controller 112 introduced by each additional storage device 104. Accordingly, the net data transfer throughput of the storage system 100 is no longer limited by the host-to-storage interface. However, the present disclosure is not so limited, and in other embodiments, the RIC device 116 can be implemented on a board separate from the board of the storage device 104 (e.g., a separate circuit board) and can be communicably connected to the storage device 104. In some embodiments, the RIC device 116 can comprise (or can be) a field programmable gate array (FPGA) configured to support dynamic partial reconfiguration (DPR) such that at least a portion thereof is dynamically reconfigurable when needed or desired, although the present disclosure is not so limited. For example, in other embodiments, the RIC device can comprise (or can be) an application specific integrated circuit (ASIC), a graphics processing unit (GPU), a complex programmable logic device (CPLD), a coarse-grained reconfigurable array (CGRA), or the like.

[0053] In some embodiments, the RIC device 116 can be considered a supplemental processor to the storage device 104 that is separate and distinct from the storage controller 112. For example, in some embodiments, unlike the storage controller 112, which can not be readily reprogrammable, the RIC device 116 can support DPR, where the RIC device 116 can be at least partially dynamically reconfigurable when needed or desired depending on commands from the host device 102. However, the present disclosure is not so limited, and in other embodiments, the RIC device 116 can be implemented as part of the storage controller 112, for example, when all or a portion of the storage controller 112 is reprogrammable (e.g., configured to support DPR). As will be described below with reference to FIG. 2, in some embodiments, the RIC device 116 can be implemented as part of the storage controller 112, for example, when the storage controller 112 is implemented as a system on a chip (SOC). Figure 2In some embodiments, the RIC device 116 can include static logic blocks and dynamically reconfigurable logic blocks (e.g., dynamic logic blocks) to perform various operations on data stored in the storage memory 114 according to commands from the host device 102, described in more detail below.

[0054] Still referring to Figure 1 In some embodiments, the RIC device 116 can be communicatively connected to the storage controller 112 via a direct (or dedicated) interconnect 118. For example, in some embodiments, the RIC device 116 can read data stored in the storage memory 114 by directly communicating with the storage controller 112 via the direct interconnect 118 using peer-to-peer (P2P) communication without involving the host device 102. For example, instead of first loading data from the storage memory 114 to the host memory 108 and then transferring the data to the RIC device 116 for further processing, the RIC device 116 can directly communicate with the storage controller 112 to access or receive data from the storage memory 114 without involving the host device 102. The P2P communication between the RIC device 116 and the storage controller 112 via the direct interconnect 118 can further reduce or eliminate the overhead from host memory 118 read / write and can reduce operational latency that can be caused when communicating data via the host device 102. Even if additional storage devices 104 are placed in the storage system 100, the data transfer bandwidth of each direct interconnect 118 increases proportionally to the amount of data in the storage memory 114 to the overall data transfer throughput of the storage system 100. This scalability benefit of the present disclosure allows the storage system 100 to scale to hold more data without losing performance per unit of storage memory capacity compared to a comparative system. After the RIC device 116 processes the data, the processed data can be provided to the host device 102. For example, because the processed data is smaller through filtering operations performed by the RIC device 116 or more easily processed by the host through reformatting operations performed by the RIC device 116 or more suitable for viewing by a client of the storage system 100 through transcoding operations performed by the RIC device 116, the consumer of the functionality implemented by the storage system 100 gains additional performance and utility benefits due to the processing power of the RIC device 116 incorporated within the storage device 104, although the present disclosure is not limited thereto.

[0055] The RIC extended memory 120 can be communicably connected to the RIC device 116 and can be implemented on the storage device 104 as a memory chip (e.g., as a dynamic random access memory (DRAM) chip) connected to a channel (e.g., a double data rate (DDR) memory interface) of the RIC device 116. For example, in some embodiments, the RIC extended memory 120 can be embedded on the storage device 104 as a plurality of memory devices (e.g., a plurality of DRAM memory chips) connected to a DDR port of the RIC device 116. As used herein, a “memory device” refers to the smallest functionally replaceable unit of memory that can store data. For example, a DRAM memory device can contain three hundred sixty billion bits of data, each bit implemented by a capacitor for storing an electrical charge and a transistor for selectively charging the capacitor using one bit of data. However, the present disclosure is not so limited, and the RIC extended memory 120 can include any suitable type of memory to extend the main memory (e.g., internal memory) of the RIC device 116. For example, in other embodiments, the RIC extended memory 120 can include (or can be) any suitable volatile or non-volatile memory known to those skilled in the art, such as SRAM, MRAM, NAND, tightly coupled memory (TCM), PCM, resistive RAM, STTRAM, any suitable memory based on PCM technology, memristor technology, and / or resistive random-access memory (ReRAM), and can include, for example, chalcogenide or the like.

[0056] In some embodiments, the RIC extended memory 120 can be a relatively slower memory when compared to the main memory (e.g., internal memory) of the RIC device 116 (e.g., see Figure 2 ) but can have a larger capacity (e.g., more storage space) than the main on-chip memory of the RIC device 116, such as any Block RAM or Unified RAM in example embodiments where the RIC device 116 is a Xilinx UltraScale+ FPGA. In this case, as described below with reference to Figure 3In more detail, off-chip RIC expansion memory 120 can be used as staging memory, where RIC expansion memory 120 is partitioned to store intermediate input / output, as well as to store configuration files to dynamically reconfigure the dynamic logic blocks when needed or desired. For example, in some embodiments, RIC device 116 can include gates and flip-flops (e.g., logic blocks), and can be configured by loading configuration data (e.g., object files, or bit files in the case of FPGAs) into RIC device 116 to configure the functionality and / or connections between the gates and / or flip-flops (e.g., LUTs in the case of FPGAs), which will be referred to as configuration files hereinafter, which are stored in RIC expansion memory 120 to be quickly retrieved when needed or desired. However, the present disclosure is not limited as such, and in other embodiments, RIC expansion memory 120 can be omitted, for example, when the main memory of RIC device 116 has sufficient capacity to perform the functions of RIC expansion memory 120 described herein (e.g., sufficient capacity partitioned for intermediate staging memory).

[0057] Figure 2 is a block diagram illustrating RIC device 116 in more detail, in accordance with one or more example embodiments of the present disclosure. Figure 1 Figure 3 is a block diagram illustrating RIC expansion memory 120 in more detail, in accordance with one or more example embodiments of the present disclosure. Hereinafter, RIC device 116 will be described in more detail in the context of FPGAs for convenience, but the present disclosure is not limited as such. Figure 1

[0058] Reference is made to Figures 1 to 3 ​​RIC device 116 can process data stored on storage memory 114 according to commands from host device 102. For example, in some embodiments, RIC device 116 can include a RIC accelerator 202 and a RIC memory (e.g., main memory or internal memory) 204. In brief overview, RIC device 116 can receive data from storage memory 114 over direct interconnect 118 and can process the read data according to a configuration of RIC accelerator 202. Input / output of data processed by RIC accelerator 202 can be stored in RIC memory 204 (and / or RIC expansion memory 120). Once data is fully processed (e.g., by RIC accelerator 202), the processed data can be passed to host device 202. In some embodiments, RIC accelerator 202 can be dynamically reconfigured (e.g., in real-time or near real-time) at least partially according to available resources of RIC device 116, user requirements (e.g., service level agreements (SLAs)), pipelined workflows, size of data passed between stages, acceleration performance, selectivity of data reduction operations, etc.

[0059] For example, RIC accelerator 202 can include static logic blocks 206 and dynamic logic blocks 208. Static logic blocks 206 can correspond to logic blocks configured in RIC accelerator 202 for at least an entire pipelined workflow, and dynamic logic blocks can correspond to logic blocks that are dynamically reconfigured when needed or desired for one or more stages of the pipelined workflow. For example, a pipelined workflow can be divided into multiple stages, and each stage can include one or more operations performed on data (e.g., data read from storage memory 114 or data output from a previous stage) (e.g., at maximum throughput or minimum latency, or maximum throughput for each RIC accelerator resource in turn). For each stage of the pipelined workflow, RIC accelerator 202 can maintain static logic blocks 206 configured therein, but for any particular one or more stages, RIC accelerator 202 can dynamically reconfigure dynamic logic blocks 208 when needed or desired. For example, as will be discussed in more detail below, RIC accelerator 202 can include a plurality of static logic blocks 206 and a plurality of dynamic logic blocks 208, and each static logic block 206 can be configured to perform a particular operation (e.g., a particular data reduction operation) on data read from storage memory 114. Each dynamic logic block 208 can be configured to perform a particular operation (e.g., a particular data reduction operation) on data read from storage memory 114, and each dynamic logic block 208 can be dynamically reconfigured to perform a different operation (e.g., a different data reduction operation) on data read from storage memory 114. Figures 4 to 5B As discussed in more detail below, static logic blocks 206 and dynamic logic blocks 208 can be configured in RIC accelerator 202 according to (e.g., depending on) critical latency requirements of the operations and / or an amount of available resources on RIC accelerator 202 that can be configured simultaneously (e.g., synchronously or at the same time) to process the operations.

[0060] The RIC memory 204 can be considered a main memory (e.g., can be an internal memory) of the RIC device 116. The RIC memory 204 can include an I / O buffer 210, a first memory 212, and a second memory 214. The I / O buffer can be partitioned between the first memory 212 and the second memory 214, and can serve as a buffer for inputs and outputs of logical blocks (e.g., static logical blocks and / or dynamic logical blocks) executing in the RIC accelerator 202. The RIC expansion memory 120 can be an expansion memory (e.g., can be an external memory or a secondary memory) of the RIC device 116. In some embodiments, the RIC expansion memory 120 can serve as a hierarchical memory of the RIC device 116. As shown in FIG. 3, in some embodiments, the RIC expansion memory 120 can include a read / write buffer 302, an intermediate I / O buffer 304, a config buffer 306, and a third memory 308. The read / write buffer 302, the intermediate I / O buffer 304, and the config buffer 306 can be partitioned on the third memory 308. Figure 3

[0061] The read / write buffer 302 can store data read from and written to the storage memory 114. The intermediate I / O buffer 304 can serve as an intermediate buffer for inputs and outputs of logical blocks between stages of a pipelined workflow. For example, when a dynamic logical block is reconfigured between stages of a pipelined workflow, the output of the dynamic logical block of the previous stage can be stored in the intermediate I / O buffer 304 so that the dynamic logical block can be reconfigured for the current stage, and then the intermediate I / O buffer 304 can be designated as an input buffer for the reconfigured dynamic logical block of the current stage.

[0062] The config buffer 306 can store configuration files (e.g., object files, or bit files in the context of FPGAs) for various different configurations of the dynamic logical block. In this case, the dynamic logical block can be configured by loading a configuration file (e.g., corresponding to a desired operation) from the config buffer 306 to the RIC accelerator 202 when needed or desired. When the configuration files are stored in the config buffer 306 of the RIC expansion memory 120, the reconfiguration time of the dynamic logical block can be reduced (e.g., to approximately 1 millisecond) compared to other cases where the configuration files are stored externally and / or provided from another device (e.g., a host device). However, the present disclosure is not limited thereto, and in another embodiment, the config buffer 306 can be omitted. In this case, the configuration files can be stored in, for example, the storage memory 104 or the RIC memory 204, or can be provided from an external device (e.g., a host device, etc.).

[0063] ​In some embodiments, the first memory 212 can be the fastest available memory of the RIC device 116, but can have a low capacity (e.g., low storage space). The second memory 214 can have a higher capacity compared to the first memory 212, but can be slower than the first memory 212. The third memory 308 can have the largest capacity (e.g., largest storage space), but can be the slowest available memory of the RIC device 116. For example, in the context of an FPGA, the first memory 212 can include block random access memory (BRAM), the second memory 214 can include uniform random access memory (URAM), and the third memory 308 can include DRAM. However, the present disclosure is not so limited, and in another embodiment, one of the first memory 212 and the second memory 214 can be omitted, or the first memory 212 and the second memory 214 can include any suitable type of memory, depending on the type of RIC device 116. For example, in another embodiment, in the context of an FPGA, the second memory 214 (e.g., URAM) can be omitted. In some embodiments, the third memory 308 can include (e.g., can be) a 4 GB DRAM chip or an 8 GB DRAM chip, although the present disclosure is not so limited.

[0064] According to embodiments, the RIC accelerator 202 can store the input / output of the static logic blocks 206 and the dynamic logic blocks 208 in the first memory 212, the second memory 214, and / or the third memory 308 depending on the size of the data passed between stages and / or the desired speed of the data. For example, if the amount of data passed between stages is relatively small, and / or the operations performed by the logic blocks (e.g., static logic blocks 206) of the RIC accelerator 202 are latency critical, the input / output of such logic blocks can be stored in the first memory 212 or the second memory 214. On the other hand, if the data passed between stages is relatively large, and / or the operations performed by the logic blocks (e.g., dynamic logic blocks 208) are throughput oriented, the input / output of such logic blocks can be stored in the third memory 308.

[0065] In an embodiment, when the data passed between stages is relatively large, the output of the operations performed by the logic blocks (e.g., dynamic logic blocks 208) can be initially stored in the first memory 212 or the second memory 214, and when the dynamic logic blocks 208 are reconfigured (e.g., between stages), the output can be passed to the third memory 308 (e.g., intermediate I / O buffer 304) so that the dynamic logic blocks 208 can be reconfigured. The output stored in the third memory 308 can then be designated as the input buffer for the reconfigured dynamic logic blocks 208. In this case, the output of the reconfigured dynamic logic blocks 208 can be stored in any suitable one of the first memory 212, the second memory 214, and the third memory 308 (e.g., depending on speed, data size, etc.). In another embodiment, when the data passed between stages is relatively large, the output of the operations performed by the logic blocks (e.g., dynamic logic blocks 208) can be initially stored in the third memory 308 (e.g., intermediate I / O buffer 304), and when the dynamic logic blocks 208 are reconfigured, the output stored in the third memory 308 from the previous stage can be designated as the input for the reconfigured dynamic logic blocks 208 for the current stage. However, the present disclosure is not limited to these examples, and any suitable combination of static logic blocks 206 and dynamic logic blocks 208 can consume any suitable one of the first memory 212, the second memory 214, and the third memory 308 resources when needed or desired, depending on the amount of data passed between stages, the desired speed of data, etc.

[0066] Figure 4 is an illustrative example of a pipelined workflow in accordance with one or more example embodiments of the present disclosure. Figure 5A illustrates a comparative example of statically configuring storage devices with operations associated with a pipelined workflow of Figure 4 Figure 5B is an illustrative example of configuring storage devices in accordance with one or more embodiments of the present disclosure with operations associated with a pipelined workflow of Figure 4 For convenience, the pipelined workflow will be described in the context of illustrative database queries in a database application, but the present disclosure is not limited thereto.

[0067] Reference is made to Figures 1 to 5B ​A typical pipelined workflow 400 responding to a database query may include multiple stages 402 to 412. For example, these stages may include a first stage 402, a second stage 404, a third stage 406, a fourth stage 408, a fifth stage 410, and a sixth stage 412. Each stage 402 to 412 may include one or more operations performed (e.g., simultaneously or sequentially), starting with an operation in the first stage 402, as a first step in processing the database query, processing data stored in storage memory 114 and received from storage controller 112; subsequently, as a second step in processing the database query, an operation in the second stage 404 processes the output of the first stage 402, and so on. According to one or more embodiments of this disclosure, operations associated with any combination of stages 402 to 412 may be offloaded to storage device 104 instead of being performed by host device 102. Thus, in this case, as indicated by arrows with openings of different widths between each stage 402 to 412, data of different sizes may be transferred between different components of storage device 104 to perform the operations associated with the stages. For example, the operations associated with the first stage 402 may be performed by the storage controller 112, and the operations associated with the second stage 404 through the sixth stage 412 may be performed by the RIC device 116, but this disclosure is not limited thereto. For example, in other embodiments, all operations associated with the first stage 402 through the sixth stage 412 may be performed by the RIC device 116, or some operations associated with the first stage 402 through the sixth stage 412 (e.g., delay-critical operations) may be performed by the storage controller 112.

[0068] like Figure 4 As shown, in the context of database applications, data tables can typically be stored in storage device 104 (e.g., storage memory 114) in a compressed or encrypted format. Therefore, one or more operations associated with the first stage 402 may include the operation of decrypting data. According to embodiments of this disclosure, for example, one or more operations associated with the first stage 402 may be performed by storage controller 112. As a result, the compressed data can be decrypted by storage controller 112, and the decrypted compressed data can be sent to RIC device 116 (e.g., via direct interconnect 118) for further processing. For example, as... Figure 4 As shown, the decrypted compressed data can be sent from the storage controller 112 to the RIC device 116 at a rate of approximately 3.2 GB / s to approximately 6.4 GB / s, but this disclosure is not limited thereto.

[0069] The decrypted data can then be parsed, for example, to identify the desired compressed columns of the data table, and the desired compressed columns of the data table can be decompressed during the second stage 404. As an illustrative example, the database query can correspond to an operation to "identify all male smokers in zip code 95134 sorted by age group" in one or more data tables stored in the storage device 104, such that one column of the data table can correspond to zip code, one column can correspond to gender, one column can correspond to age, one column can correspond to smoker / non-smoker, etc. Thus, the one or more operations associated with the second stage 404 can include an operation to parse the stored data format (e.g., which can be a self-describing multi-column format in the context of a database application), and an operation to first decompress the parsed data using the inverse algorithm of the algorithm used to compress the stored data (e.g., decompressing the compressed columns corresponding to zip code, gender, age, smoker / non-smoker, etc.). Thus, for example, if the stored data was compressed using the gzip algorithm, then after reading the compressed data, the second stage 404 would thus include an operation to decompress the parsed data using the corresponding gunzip decompression algorithm. As a result, as shown by the increasing width of the arrow between the second stage 404 and the third stage 406 in Figure 4

[0070] The decompressed data can then be filtered according to one or more conditions defined in the database query. Thus, the one or more operations associated with the third stage 406 can include an operation to filter the decompressed data according to the conditions defined in the database query. For example, the conditions corresponding to the illustrative database query above can include zip code 95134, gender male, and smoker, but not non-smoker. In this case, for example, the RIC device 116 can select all rows corresponding to 95134 from the column corresponding to zip code, and can then obtain the remaining data for the other columns (e.g., gender, smoker, age, etc.) of those matching rows. The RIC device 116 can then select all rows corresponding to male from the column corresponding to gender of the matching rows, and can then obtain the remaining data for the other columns (e.g., smoker / non-smoker, age, etc.) of those rows matching zip code 95134 and male. Similarly, the RIC device 116 can select all rows corresponding to smoker, but not non-smoker, from the column corresponding to smoker / non-smoker in those matching rows, until all of the filtering conditions are applied.

[0071] As a result, as shown by the increasing width of the arrow between the second stage 404 and the third stage 406 in Figure 4 ​As indicated by the decreasing width arrows between stages 406 and 408, the size of the data can be reduced from the size of the decompressed data to the size of the filtered data. The size of the filtered data can depend on the selectivity of the conditions used for filtering. For example, if the conditions result in only a small number of entries matching out of millions of entries in the decompressed data, the size of the resulting filtered data may be significantly smaller than the size of the decompressed data. As a result, traffic to host device 102 can be significantly reduced. On the other hand, if the conditions are not very selective, such that most of the decompressed data is retained (e.g., not filtered out), the size of the filtered data can be substantially the same as the size of the decompressed data. In this case, the acceleration of storage device 104 may be ineffective because the amount of filtered data is the same as or substantially the same as the decompressed data.

[0072] Therefore, in some embodiments, depending on the data reduction operation (e.g., Figure 4 The selectivity of the data reduction operation (e.g., filtering operation) in the diagram can be monitored. When the conditions used to reduce data (e.g., filter data) are not highly selective, control can be turned back to the host device to perform the remaining operations. For example, in some embodiments, the selectivity of the data reduction operation (e.g., filtering operation) for a given pipeline workflow may not be known in advance (e.g., during the planning phase). In this case, during execution time (e.g., during runtime), the selectivity of the data reduction operation performed in one or more logical blocks can be monitored (e.g., by host device 102 or by other devices or systems communicatively connected to host device 102, such as runtime services), and if the reduction in data size is less than a threshold reduction size, control can be turned back to host device 102 (e.g., along with the reduced data) so that host device 102 can perform the remaining operations on the data.

[0073] After filtering the data, the filtered data can be sorted at a fourth stage 408, grouped at a fifth stage 410, and aggregated at a sixth stage 412 in the context of the illustrative database query. For example, the filtered data can be sorted by age at the fourth stage 408, grouped into different age groups at the fifth stage 410, and the grouped data can be aggregated at the sixth stage 412. Thus, the one or more operations associated with the fourth stage 408 can include an operation to sort the filtered data, the one or more operations associated with the fifth stage 410 can include an operation to group the sorted data, and the one or more operations associated with the sixth stage 412 can be to aggregate the grouped data. As indicated by the constant width arrows between the fourth stage 408 through the sixth stage 412, the sorting and grouping operations do not affect the size of the data, but the aggregation can potentially reduce the size. The aggregated data can then be sent to the host device 102 as indicated by the last arrow. Thus, the reduction in size of the data processed by the RIC device 116 can depend on the selectivity of the filtering conditions during the filtering stage 406, the number of different groups formed during the grouping stage 410, and / or the extent to which the aggregation stage 412 aggregates the data in each group.

[0074] As Figure 5A indicated, the resources required to statically configure the RIC accelerator 202 with all of the operations associated with the pipelined workflow 400 in the Figure 4 may exceed the amount of available resources on the RIC device 116. For example, in the context of an FPGA, the connections between the gates and flip-flops of a logic block (e.g., the static logic block 206 and the dynamic logic block 208) that implement the operations of a stage can be defined in a lookup table (LUT) as, for example, a truth table. However, the number of LUTs that can be configured in an FPGA at any given time can be limited by the maximum number of LUTs of the FPGA. For example, a small FPGA can be limited to a total maximum number of LUTs of 300K. In this case, the total number of LUTs used by the implementation of the operations of each of the stages 404-412 can exceed the total maximum number of LUTs of the FPGA.

[0075] For example, as Figure 5AAs shown, the number of LUTs used to parse the stored data format (e.g., in stage 404) can be approximately 25K, the number of LUTs used to decompress the parsed data (e.g., in stage 404) can be approximately 12K, and assuming a compression factor of 2, the number of LUTs used to filter decompressed data flowing at twice the rate of the stored data (e.g., in stage 406) could be even larger (e.g., 90K), the number of LUTs used to sort the reduced data (e.g., in stage 408, for illustration, assuming 90% of the data is filtered out) can be approximately 100K, and the number of LUTs used to group and aggregate the data (e.g., in stages 410 and 412) can be approximately 100K (e.g., for illustration, assuming the data is divided into 10 groups). In this comparative example, according to Figure 4 The pipeline workflow 400 uses a total of 327K LUTs to process data, exceeding the maximum total number of LUTs on the FPGA (e.g., 300K in this illustrative example). Therefore, all operations associated with the pipeline workflow 400 may not be adapted to FPGA resources simultaneously (e.g., synchronously or at the same time), and thus may not all be statically configured on the FPGA at once. In this case, the number of operations associated with the pipeline workflow 400 that can be offloaded to the FPGA can be reduced or limited based on the available resources on the FPGA.

[0076] On the other hand, such as Figure 5B As shown, when at least some operations of the pipeline workflow 400 are dynamically configured as needed or desired, the operations associated with the pipeline workflow 400 can be offloaded to the FPGA. For example, if operation 502 associated with the parsing, decompression, and filtering stages (e.g., second stage 404 and third stage 406) is statically configured, and the remaining operations 504 and 506 associated with the sorting, grouping, and aggregation stages (e.g., fourth stage 408, fifth stage 410, and sixth stage 412) are dynamically reconfigured as needed and desired, then the maximum number of LUTs used at any given time can be 227K (e.g., 127K for statically configured logic blocks and 100K for dynamically configured logic blocks). Therefore, when at least some operations are dynamically configured as needed or desired, the number of operations that can be offloaded to the FPGA can be increased.

[0077] In some embodiments, the reconfiguration time of the dynamic logic block can be reduced (e.g., reduced to approximately 1 ms) because the configuration file can be stored in the configuration buffer 306 (e.g., see...). Figure 3The configuration buffer 306 can be used to quickly retrieve information when needed or desired. In this case, when a different operation is to be performed by one of the dynamic logic blocks 208, the corresponding configuration file can be loaded into it, allowing the dynamic logic block to be reconfigured within 1 ms. However, even in this case, there may be delay-critical operations that may not tolerate the time spent reconfiguring the dynamic logic block. Therefore, in some embodiments, operations corresponding to delay-critical operations in the pipeline workflow can be configured in a static logic block, so that the reconfiguration time is not added to those operations, and the dynamic logic block can be configured with other operations in the pipeline workflow (e.g., throughput-oriented operations) that can tolerate the time spent reconfiguring the dynamic logic block, thereby improving the resource utilization of the RIC device 116. However, this disclosure is not limited thereto. For example, as referenced Figure 6A and Figure 6B As discussed, in some embodiments, dynamic logic blocks can be reconfigured while other logical operations are being performed, so that the reconfiguration time of dynamic logic blocks can be hidden.

[0078] Figure 6A and Figure 6B A method 600 for accelerating data-intensive operations using a storage device according to one or more example embodiments of the present disclosure is illustrated. However, the present disclosure is not limited to this. Figure 6A and Figure 6B The order or number of operations of the method 600 shown can be altered to any desired order or number of operations as recognized by one of ordinary skill in the art. For example, in some embodiments, the order may be varied, or the method may include fewer or additional operations.

[0079] refer to Figure 6A and Figure 6B When storage device 104 receives one or more commands from host device 102 to process data stored in storage memory 114 (e.g., see...), Figure 1 When data is accessed in the RIC device 116, the method begins. Commands can be associated with specific pipeline workflows, allowing the pipeline workflow to be divided into multiple stages, each corresponding to one or more data-intensive operations associated with the command. For each stage, data can be accessed in the RIC device 116 (e.g., see [link to RIC device]). Figure 2 One or more logical operations can be dynamically configured in dynamic logic block 208 to perform operations. For example, a first logical operation can be configured in a logic block (e.g., a dynamic logic block), and input data (e.g., stored in memory 114) at operation 605 can be sent to the logic block that actively performs the first logical operation. At operation 610, the logic block can be configured to store its output in an intermediate output buffer (e.g., ...). Figure 3in the intermediate I / O buffer 304) in the intermediate output buffer 304.

[0080] As the output of the logic block fills the intermediate output buffer, at operation 615, the intermediate output buffer is monitored to determine if a threshold (e.g., a high water mark (HWM)) is reached. If the HWM is not reached at operation 615 (e.g., no), at operation 620 it is determined if the first logic operation has completed. If the first logic operation has not completed at operation 620 (e.g., no), the first logic operation continues to be executed until the HWM is reached at operation 615 or the first logic operation is completed at operation 620. If, on the other hand, the first logic operation has completed at operation 620 (e.g., yes), processing continues at operation 625 (A), which will be discussed below with reference to FIG. 6B. Figure 6B

[0081] If the HWM is reached at operation 615 (e.g., yes), a second logic operation is configured (e.g., in a second dynamic logic block) while the first logic operation continues to be executed at operation 630. In this case, for example, the reconfiguration time of the second logic operation in the second logic block can be hidden (e.g., can be insignificant) since the first logic operation continues to be executed while the second logic operation is configured. In this case, in some embodiments, the second logic operation can be an extension of the first logic operation. The method 600 can work best when the first logic operation and the second logic operation form a throughput-oriented pipeline (e.g., a minimal version of the pipelined workflow 400), although the present disclosure is not limited as such.

[0082] Continuing to execute the first logic operation until the end of the intermediate output is reached (e.g., the intermediate output buffer is full), in which case the operation is stalled, or the first logic operation runs out of input data, in which case the operation is considered complete. Thus, at operation 635 it is determined if the first logic operation is stalled. If the first logic operation is not stalled at operation 635 (e.g., no), the first logic operation runs to completion, in which case the intermediate output buffer of the first logic operation is designated as the final output buffer at operation 640. The data stored in the final output buffer can be sent to the host device 102.

[0083] ​On the other hand, if the first logical operation is pending (e.g., Yes) at operation 635, the intermediate output buffer of the first logical operation is designated as the input buffer for the second logical operation at operation 645, and the input buffer of the first logical operation is designated as the output buffer for the second logical operation at operation 650. At operation 655, the data in the intermediate output buffer (now designated as the input buffer for the second logical operation) is processed according to the second logical operation. The method 600 can be repeated until there are no remaining inputs, and the entire pipelined workflow of operations is performed on all inputs.

[0084] Reference Figure 6B If the first logical operation has completed (e.g., Yes) at operation 620, the process continues at operation 625 (A), where it is determined whether there are any other logical operations to configure in the pipelined workflow. If there are no additional logical operations to configure for the pipelined workflow (e.g., No) at operation 625, the intermediate output buffer of the first logical operation is designated as the final output buffer at operation 660. The data stored in the final output buffer can be sent to the host device 102.

[0085] On the other hand, if there are additional logical operations to configure for the pipelined workflow (e.g., Yes) at operation 625, the next logical operation is configured (e.g., in a second logic block) at operation 665. The intermediate output buffer of the first logical operation is designated as the input buffer for the next logical operation at operation 670, and the input buffer of the first logical operation is designated as the output buffer for the next logical operation at operation 675. At operation 680, the data in the intermediate output buffer (now designated as the input buffer for the next logical operation) is processed according to the next logical operation, the method 600 can be repeated until there are no remaining inputs, and the entire pipelined workflow of operations is performed on all inputs.

[0086] While some example embodiments have been described with reference to the attached figures, it is to be understood that the disclosure can be embodied in various different forms and should not be construed as limited to the embodiments set forth in this disclosure. Rather, these embodiments were provided so that this disclosure will be thorough and complete, and fully convey the aspect and features of the disclosure to those skilled in the art. Therefore, unless otherwise specified, aspects and features of each example embodiment within the description should not be construed as being limited to other similar aspects and features in other example embodiments.

[0087] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“a first element, component, region, layer or section described below” could be“a second element, component, region, layer or section” without departing from the spirit and scope of the present disclosure.

[0088] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms“a,”“an” and“the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms“comprises,”“comprising,”“includes” and“including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term“and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as“at least one of,” when preceding the

[0089] As used herein, the terms“substantially,”“approximately” and like terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent variations in measuring or calculating values that would be recognized by those of ordinary skill in the art. Further, use of“may” when describing embodiments of the present disclosure is intended to mean that one or more embodiments of the present disclosure. As used herein, the term“use” can be considered synonymous with the term“utilize,” respectively.

[0090] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the

[0091] Although Figures 1-3 An exemplary package is shown, but it will be apparent to those skilled in the art that various functions and components can also be arranged in other suitable ways by application of semiconductor packaging, printed circuit board design, integrated circuit design, system design, and design of racks or clusters of systems, depending on the number of components used or necessary for large-scale data processing use.

[0092] Furthermore, Figures 1-3 Any interconnect shown in the figures can be replaced by any suitable wired or wireless connection, ranging from simple as conductive or optical connections within an integrated circuit, to through-silicon or other non-silicon optical, inductive, conductive or capacitive connections between dies, packages or chiplets, to traces, wires, switches or direct cables or wires between chips, packages and / or systems, to complex as entire data center scale or rack scale structures.

[0093] Figures 1-3 The inventive concepts of the application can be applied to systems of any suitable scale, ranging from a single core host processor to multi-core host processors, from a single channel of host memory to multiple channels of host memory, each channel containing multiple devices such as DIMMs, from a single host to hundreds of thousands or more hosts, from a single storage device to multiple storage devices in each host or storage devices on optical fibers connected to multiple hosts, from a device with one storage controller to a device containing multiple controllers, from a device containing one RIC device to a device that can contain multiple different kinds of devices.

[0094] Thus, although several example embodiments have been described, it will be apparent to those skilled in the art that various modifications can be made within the spirit and scope of the disclosure. It will be understood that the description of features or aspects in each embodiment is generally applicable to other similar features or aspects in other embodiments unless otherwise described. Accordingly, it is to be understood that the foregoing description is directed to various example embodiments and that it is not to be taken in a limiting sense, but is made merely for the purpose of providing a thorough and complete description of the application. Accordingly, the disclosure is intended to embrace all alternatives, modifications and variations of the example embodiments disclosed herein, including these falling within the scope of the appended claims, and their equivalents.

Claims

1. A storage device comprising; The storage controller is configured to receive data from the host device and store the data in the storage memory; as well as A reconfigurable integrated circuit, communicatively connected to a memory controller and configured to accelerate logical operations performed on data stored in a memory, the reconfigurable integrated circuit comprising: The first logic block is configured to perform static logic operations in the logical operations; The second logic block is configured to perform one or more dynamic logic operations in the logical operations; and Multiple memory buffers are configured to store the inputs and outputs of the first and second logic blocks. The plurality of memory buffers includes an intermediate output buffer configured to store intermediate outputs of the second logic block, and The reconfigurable integrated circuit is configured as follows: Monitor the value of the intermediate output buffer; Determine that the value exceeds the threshold; and In response to the value exceeding the threshold, the logical operation in the second logic block is configured.

2. The storage device according to claim 1, wherein, The logical operations correspond to a pipelined workflow. The first logical block is configured to be statically configured using static logical operations for the pipelined workflow, and the second logical block is configured to be dynamically reconfigured using one or more dynamic logical operations for at least one stage of the pipelined workflow.

3. The storage device according to claim 2, wherein, The one or more dynamic logic operations include a first dynamic logic operation and a second dynamic logic operation. During the first stage of the pipeline workflow, the second logic block is configured using the first dynamic logic operation, and during the second stage of the pipeline workflow, the second logic block is dynamically reconfigured using the second dynamic logic operation.

4. The storage device according to claim 1, wherein, The plurality of memory buffers include: Input / output I / O buffers are configured to store the inputs and outputs of the first and second logic blocks; and The configuration buffer is configured to store configuration files for reconfiguring the second logical block, and The intermediate output buffer is configured to store the intermediate output of the second logic block when the second logic block is being reconfigured.

5. The storage device according to claim 4, wherein, The second logical block is dynamically reconfigured by loading the configuration file stored in the configuration buffer into the second logical block.

6. The storage device according to claim 4, wherein, During the first phase, the output of the second logic block is stored in an intermediate I / O buffer. The second logic block is reconfigured using different dynamic logic instructions for the second phase, and during the second phase, the intermediate I / O buffer is designated as the I / O buffer for the second logic block.

7. The storage device according to claim 1, wherein, The static logic operations correspond to delay-critical operations, and the one or more dynamic logic operations correspond to throughput-oriented operations.

8. The storage device according to claim 7, wherein, The delayed critical operation is an operation with a completion time less than the reconfiguration time of the second logic block.

9. The storage device according to claim 1, wherein, The storage device is a solid-state drive.

10. The storage device according to claim 9, wherein, The reconfigurable integrated circuit is a field-programmable gate array (FPGA).

11. A method for accelerating operation in a storage device, the storage device comprising a storage controller, a storage memory, and a reconfigurable integrated circuit including a first logic block, a second logic block, and a buffer, the method comprising: The first logic block performs a first logical operation on the input data stored in the memory. The first logic block stores the output of the first logic operation in the intermediate output buffer of the buffer. The second logic operation in the second logic block is configured by the reconfigurable integrated circuit; The intermediate output buffer is designated as an input buffer for a second logic operation by the reconfigurable integrated circuit; as well as The second logic block performs a second logic operation on the output of the first logic operation stored in the intermediate output buffer. The second logical operation in the configuration second logical block includes: Monitor the value of the intermediate output buffer; Determine that the value exceeds the threshold; and In response to the value exceeding the threshold, the second logical operation in the second logical block is configured.

12. The method according to claim 11, wherein, While the first logical operation is being executed in the first logical block, the second logical operation in the second logical block is configured.

13. The method according to claim 11, wherein, The threshold is the high water level of the intermediate output buffer.

14. The method according to claim 12, wherein, The buffer includes a configuration buffer configured to store a configuration file for configuring the second logical block.

15. The method according to claim 14, wherein, The second logical operation in the configuration second logical block includes: The bit file corresponding to the second logical operation is loaded into the second logical block from the configuration file stored in the configuration buffer.

16. The method according to claim 11, wherein, Specifying the intermediate output buffer as an input buffer for the second logic operation includes: Determine whether the first logical operation is suspended; In response to determining that the first logical operation is suspended, the intermediate output buffer is designated as the input buffer for the second logical operation; as well as Designate the input buffer for the first logical operation as the output buffer for the second logical operation.

17. The method according to claim 16, wherein, Determining whether the first logical operation is suspended includes: Determine if the end of the intermediate output buffer has been reached.

18. The method of claim 11, further comprising: It is determined that the second logic block has processed all the outputs of the first logic operation stored in the intermediate output buffer; and Specify the output buffer of the second logical operation as the final output buffer.

19. The method according to claim 11, wherein, The storage device is a solid-state drive, and the reconfigurable integrated circuit is a field-programmable gate array (FPGA).

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