Devices and methods for verifying components of storage devices

Abstract

A storage device configured for hardware verification is disclosed. The storage device includes a first hardware component comprising a connector and first verification logic. The first verification logic is configured to detect a criterion and generate a first signal via the connector in response to detection of the criterion. The storage device further includes a second hardware component coupled to the first hardware component via the connector. The second hardware component includes second verification logic, wherein the second verification logic is configured to monitor and receive the first signal via the connector. In response to receiving the first signal, the second verification logic is configured to compare the received first signal with an expected signal and generate a result. The storage device is configured to take action in response to the result.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority and benefit to U.S. Provisional Application No. 62 / 975,616, filed February 12, 2020, entitled “SYSTEMS, METHODS, AND APPARATUS FOR PROVIDING LOCK-IN FEATURES FOR MODULAR STORAGE DEVICES”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more aspects of embodiments of this disclosure relate to storage devices, and more specifically, to verifying whether components of a storage device are authorized and / or verified components. Background Technology

[0004] It may be desirable to use compute storage devices (e.g., solid-state drives (SSDs) or field-programmable gate arrays (FPGAs) with embedded processors) for various data processing tasks, as such storage devices can help provide efficient and cost-effective data processing solutions. For example, compute storage devices can provide a platform within the storage device itself for performing at least some of the data processing functions that would otherwise be performed by the host CPU processor.

[0005] Therefore, there is a need for a system and method for quickly determining whether one or more components of a computing storage device are verified components. Summary of the Invention

[0006] Embodiments of this disclosure relate to a storage device configured for hardware verification. The storage device includes a first hardware component comprising a connector and first verification logic. The first verification logic is configured to detect a criterion and generate a first signal via the connector in response to detection of the criterion. The storage device further includes a second hardware component coupled to the first hardware component via the connector. The second hardware component includes second verification logic, wherein the second verification logic is configured to monitor and receive the first signal via the connector. In response to receiving the first signal, the second verification logic is configured to compare the received first signal with an expected signal and generate a result. The storage device is configured to take action in response to the result.

[0007] According to one embodiment, the first hardware component includes at least one of a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), and the second hardware component includes non-volatile memory.

[0008] According to one embodiment, the intended signal is associated with an identifier stored in the memory of a second hardware component.

[0009] According to one embodiment, the connector is a connector that supports the Fast Peripheral Component Interconnect (PCIe) protocol.

[0010] According to one embodiment, the standard is to detect the start of the reset period.

[0011] According to one embodiment, the first signal is provided via a preset pin of the connector.

[0012] According to one embodiment, the result includes an indication that the received first signal matches the expected signal, and the action includes enabling the acceleration features of the storage device.

[0013] According to one embodiment, the result includes an indication that the received first signal does not match the expected signal, and the action includes disabling the acceleration features of the storage device.

[0014] According to one embodiment, the result includes an indication that the received first signal does not match the expected signal, and the action includes displaying a notification on a display device.

[0015] According to one embodiment, the second hardware component is coupled to the host via a second connector.

[0016] Embodiments of this disclosure relate to a method for hardware verification via a storage device. The method includes: detecting a criterion via first verification logic in a first hardware component; generating a first signal via a connector in the first hardware component in response to detecting the criterion; monitoring and receiving the first signal via second verification logic in a second hardware component, the second hardware component being coupled to the first hardware component via the connector; and comparing the received first signal with the desired signal via the second verification logic in response to receiving the first signal, and generating a result, wherein the storage device is configured to take action in response to the result.

[0017] As those skilled in the art will recognize, embodiments of this disclosure provide a mechanism for quickly determining whether one or more components of a computing storage device are verified components. For example, this can help avoid unpredictable device behavior or failures due to the use of unverified components. Attached Figure Description

[0018] The following figures illustrate non-limiting and non-exhaustive embodiments of this example, wherein, unless otherwise specified, the same reference numerals refer to the same parts throughout the various views.

[0019] Figures 1A-1C This is a block diagram of an exemplary computing storage device with modular components according to an exemplary embodiment;

[0020] Figure 2This is a block diagram of a verification module for performing hardware verification of modular components of a computing storage device, according to an exemplary embodiment.

[0021] Figure 3 The configuration is based on the exemplary embodiment. Figure 2 Figure 1 is a block diagram of an exemplary computing storage device for the verification module;

[0022] Figure 4 This is an exemplary signaling diagram according to an exemplary embodiment; and

[0023] Figure 5 This is a flowchart of a hardware verification process according to an exemplary embodiment. Detailed Implementation

[0024] In the following description, exemplary embodiments will be presented in more detail with reference to the accompanying drawings, wherein similar reference numerals refer to similar elements throughout. However, the invention may be embodied in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art various aspects and features of this disclosure. Therefore, processes, elements, and techniques that are unnecessary for a full understanding of the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and thus, descriptions of the same reference numerals may not be repeated. Furthermore, in the drawings, the relative dimensions of elements, layers, and regions may be enlarged and / or simplified for clarity.

[0025] Computational storage devices can sometimes be modular in design or construction. In this case, the computing storage device can consist of different movable components, such as storage components (e.g., solid-state memory) and processing components (e.g., field-programmable gate arrays (FPGAs)). Modular components of computing storage devices can be obtained from different vendors. Thus, it is possible to attempt to construct computing storage devices from unauthorized / unqualified vendors, which may compromise the quality of the constructed computing storage device.

[0026] In summary, embodiments of this disclosure relate to a system and method for hardware-based detection of whether a storage device (e.g., an SSD) or processor device (e.g., an FPGA), which forms part of a computing storage device, is a licensed component. For example, the verification process may be performed during a complete or partial reset of the computing storage device. For example, the verification process may be performed to verify whether the device has a licensed component before the FPGA has downloaded images and / or bit files configuring the FPGA to operate in a predetermined manner.

[0027] In one embodiment, verification can be performed via hardware verification logic included in both the processor device and the storage device. The hardware verification logic can be configured to utilize reserved pins on a connector (e.g., a U.2 connector) that connects the storage device to the processor device. In one embodiment, the reserved pins may include pin E6 of the U.2 connector.

[0028] According to one embodiment, hardware verification performed by the initiator of the target occurs during a reset period. The initiator can be an initiator as described in the NVMe standard, although embodiments of this disclosure are not limited thereto. The initiator can be a processor device, and the target can be a storage device, or vice versa. For example, a reset period may occur when a device is inserted into a slot in a computer system without stopping or shutting down the system, or when the entire computer system is rebooted. During the reset period, the initiator can be configured to monitor a reserved pin to determine if activity is detected through that pin. In one embodiment, an authorized target uses an authentication ID (also referred to as an authentication signal) to drive the reserved pin, which informs the initiator that the target is an authorized device. For example, the authentication ID may include a predetermined waveform pattern / signal. In response to verifying that the target is an authorized device, the initiator can enable certain functions of the device that would not be enabled without such verification. For example, functions may include downloading proprietary bitfiles and / or enabling specific acceleration features.

[0029] Figures 1A-1C This is a block diagram of an exemplary computing storage device 100a-100c (collectively referred to as 100) having modular hardware components according to an exemplary embodiment. The various modular components described herein may also be referred to as hardware components.

[0030] Figure 1A The computing storage device 100a includes a modular storage component 102 that can be removably coupled to one or more processor components 104a, 104b. For example, the modular storage component 102 may be an SSD including a storage controller 106 and various flash drives 108. For example, the SSD may be a non-volatile fast memory (NVMe) SSD, an NVMe Over Fabrics (NVMe-oF) compatible Ethernet SSD (eSSD), or any other suitable persistent (non-volatile) memory device.

[0031] For example, one or more processor components 104a, 104b may include one or more FPGAs 110a, 110b. In some embodiments, graphics processing units (GPUs), tensor processing units (TPUs), and / or other application-specific integrated circuits (ASICs) conventional in the art may be used additionally or instead of FPGAs.

[0032] exist Figure 1A In the example, modular storage component 102 is connected to the host device via connector 111a, which may be a small-form-factor-technology-affiliate-100x (SFF-TA-100X) connector (where X is an integer value equal to 2, 6, 7, 8, etc.). Users can create selected computing storage devices by adding one or more processor components 104a, 104b to storage component 102 as needed.

[0033] In one embodiment, the modular storage component 102 is connected to one or more processor components 104a, 104b via connectors 112a, 112b. Connectors 112a, 112b can be standard connectors, such as U.2, M.2, Next Generation Small Form Factor (NF1), or Enterprise and Data Center SSD Form Factor (EDSFF) connectors. For example, communication between the storage component 102 and one or more processor components 104a, 104b can occur via connectors 112a, 112b on PCIe links 114a, 114b.

[0034] Figure 1B The example computing storage device 100b includes a modular processor assembly 120, which can be removably coupled to one or more modular storage components 122a-122d (collectively referred to as 122) via connectors 124a-124d. For example, the processor device in the modular processor assembly 120 may be an FPGA, and, for example, the one or more modular storage components 122 may be an SSD. Figure 1B In the example, processor component 120 is connected to the host device via connector 111b. Users can create selected computing storage devices by adding one or more modular storage components 122 to processor component 120 as needed.

[0035] In addition to the dual-processor components 130a and 130b being coupled to the storage component 132 via a connector 134 with a dual-port configuration, Figure 1C The computing storage device 100c can be similar to (but not necessarily the same as) Figure 1A The computing storage device 100a. For example, the connector can be a U.2 connector or a PCIe interface. Figure 1C In the example, processor components 130a and 130b are connected to the host device via connector 111c. Users can design selected computing storage devices by adding selected modular storage components 132 to processor components 130a and 130b as needed.

[0036] exist Figures 1A-1C In the example of the modular configuration of the compute storage device 100, it is possible that certain modular components could be obtained from unauthorized / unqualified vendors, which could, for example, compromise the quality (e.g., performance) of the compute storage device. Therefore, a system and method for determining whether one or more components of the compute storage device are verified components may be desired. Once an added modular component is verified as a verified component, certain acceleration features can be enabled, such as compression and / or encryption functions of the compute storage device.

[0037] In one embodiment, if the added modular components cannot be verified, the compute storage device can be configured to download, or otherwise receive, a standard FPGA bitfile without downloading a proprietary FPGA bitfile. For example, this could allow the compute storage device to operate as it normally would, but without acceleration capabilities. The device could also send a message to the user or application notifying them that the added device is unauthorized.

[0038] Figure 2 This is a block diagram of verification modules 200a and 200b (collectively referred to as 200) for performing hardware verification of modular components of a computing storage device, according to an exemplary embodiment. In one embodiment, verification module 200 is installed in an initiating component and a target component. The verification module may include hardware verification logic 202a and 202b (collectively referred to as 202), which, for example, may be described as a state machine.

[0039] In one embodiment, the verification module 200 further includes multiplexers 204a and 204b (collectively referred to as 204). Input to a particular one of the multiplexers 204 can be provided by corresponding hardware verification logic 202 and reserved pin 208. In one embodiment, reserved pin 208 is a reserved pin of connector 210 (similar to connectors 112, 124, 134). When the connector is implemented as a U.2 connector, pin 208 can be pin "E6" which is defined as a reserved (RSVD) pin (or any other suitable pin). Although the U.2 connector is used as an example of a connector for connecting a processor module to a memory module, those skilled in the art will recognize that the connector can also be an M.2 or NF1 connector with one or more reserved pins.

[0040] The outputs of multiplexers 204a and 204b are coupled to reserved pin 208 of connector 210. Reset pin 206 controls multiplexers 204a and 204b, thereby selecting the output of hardware verification logic 202 during the reset period when reset pin 206 is asserted (e.g., asserted low). When reset pin 206 is de-asserted, the multiplexer sends a signal indicating the chassis type via reserved pin 208.

[0041] In one embodiment, hardware verification logic 202 in the initiating and target devices initializes the verification cycle in response to a host processor reset. In one embodiment, the reset drive reset pin 206 is asserted low, causing multiplexer 204 to select hardware verification logic 202 to communicate via reserved pin 208 of connector 210 during reset.

[0042] In one embodiment, the initiator is a device initially installed on the host to seek authentication of the target; this device can be a modular component added later. One of the processor or storage components can be the initiator or the target. In one example, the initiator is... Figure 1B , Figure 1C The processor components 120 and 130, and the target is... Figure 1B , Figure 1C Storage components 122 and 132. In another example, the initiator is... Figure 1A The storage component 102, and the target is Figure 1A The processor component 110.

[0043] For illustrative purposes, assuming the initiator is an FPGA and the target is an SSD, the initiator can execute hardware verification logic 202a from a non-volatile memory device upon a reset, including, for example, a verification identifier (ID). The non-volatile memory device could be an electrically erasable programmable read-only memory (EEPROM). The reason for the download might be that a reset clears all programmed logic in the FPGA.

[0044] In one embodiment, the initiator's hardware verification logic 202a monitors reserved pin 208 during a reset period to monitor activity on pin 208. Monitoring may continue until the reserved pin is no longer asserted as low.

[0045] Turning to the target, similar to the initiator, multiplexer 204b selects hardware verification logic 202b in the SSD to communicate with the FPGA via connector 208 in response to reset pin 206 being asserted low. In one embodiment, assuming the target is the device to be verified, hardware verification logic 202b uses a verification ID to drive reserved pin 208 of connector 208 during the reset period. In one embodiment, the target's hardware verification logic 202b receives the verification ID to be sent via reserved pin 208 from the FPGA or host processor, etc.

[0046] The FPGA's hardware verification logic 202a detects the verification ID on the monitored reserved pin 208 and compares the received verification ID with the expected verification ID downloaded from the memory device. If the verification IDs do not match, verification of the target SSD fails. The FPGA's hardware verification logic 202a can write the result of the failed verification process to a defined register location. For example, an "unverified" result can be written to the defined register location. However, if verification is successful, the FPGA's hardware verification logic 202a can be configured to write a "verified" status to the defined register location.

[0047] In one embodiment, the FPGA may check the verification results in a defined register location before taking certain actions. For example, such actions might include whether to download a proprietary bitfile in addition to the standard bitfile during the boot sequence, and / or enable or disable certain acceleration features of the FPGA, including compression, encryption, etc. Other acceleration features that may be enabled or disabled depending on the verification results may include, for example, enabling / disabling a double data rate fourth-generation synchronous dynamic random access (DDR4) channel (if supported), enabling / disabling high-bandwidth memory (HBM) (if present), etc.

[0048] Figure 3 The configuration is based on the exemplary embodiment. Figure 2 The verification modules 200a and 200b Figure 1A A block diagram of an exemplary computing storage device. Hardware verification logic 202a executed by storage component 102 can be incorporated into initialization logic run by the storage controller during a cold restart. Hardware verification logic 202a executed by processor component 104 can be stored in a non-volatile memory such as EEPROM and loaded into FPGA 110 upon reset.

[0049] In one embodiment, multiplexers 204a and 204b are incorporated into storage component 102 and processor component 104, respectively. In some embodiments, multiplexers 204a and 204b may be located outside of storage component and / or processor component.

[0050] Figure 4 This is an exemplary signaling diagram of a verification module 200 according to an exemplary embodiment. During the rise of a specific clock cycle 400, the reset pin 206 is asserted as low 402, and a reset period begins. For example, the reset period may last for several seconds. In one embodiment, no activity occurs during the reset period of the restarted device, and the lack of activity is used by the initiator of the target device to perform verification. In one example, the hardware verification logic 202b in the target device drives the reserved pin 208 from low state 404 to high state 406 a required number of times based on a predetermined pattern indicated by the verification ID. In one embodiment, the minimum requirement may be driving the pin from low to high within at least one clock cycle and from high to low within at least another clock cycle.

[0051] During the reset period, the initiator monitors the reserved pin 208 for receiving verification IDs. In one embodiment, when a first signal is received on the reserved pin 208, the initiator invokes a fixed counter. When the fixed counter reaches a specific value corresponding to the size of the expected verification IDs, the initiator concludes that all verification IDs have been received. Alternatively, the initiator can drive the reserved pin 208 (not shown) low 408. For example, this can occur before the reset period expires. The initiator compares the received verification IDs with the expected verification IDs to determine if they match.

[0052] In one embodiment, when the reset pin 206 is no longer asserted as low 410 (e.g., at the end of a reset period), the reserved pin 208 is used to provide the rack type. For example, a reserved pin 208 in a low state may indicate the rack type of NVMe, while a reserved pin in a high state may indicate the rack type of NVMe-oF.

[0053] Figure 5 This is a flowchart of a hardware verification process according to an exemplary embodiment. It should be understood that the order of the steps in this process is not fixed, but can be changed to any desired order recognized by those skilled in the art.

[0054] In action 500, the reset is asserted by the host processor for a specific slot (e.g., in response to the host inserting a device into the slot) or for the entire system.

[0055] In action 502, in response to a reset, the hardware verification logic 202a, 202b in the initiator and target are initialized. In one embodiment, the determination of which modular component of the computing storage device is the initiator and which is the target may depend on the device first connected to the host device. In one embodiment, the module acting as the initiator or target may be configured via programmable pins.

[0056] In action 504, the initiator's hardware verification logic 202a monitors reserved pin 208 to determine whether the target is an authorized target. In one embodiment, the initiator's hardware verification logic 202a compares the signal received via reserved pin 208 with the initiator's expected verification ID. If the received signal matches the expected verification ID, the target can be considered authorized, and the "verified" status can be stored in a specific register location.

[0057] In Action 506, in response to the verification target, the initiator takes one or more actions permitted to be performed with the authorized target. For example, such actions might include downloading a proprietary FPGA bitfile (in addition to a standard FPGA bitfile) from the vendor providing the FPGA during the boot sequence and continuing the PCIe link training sequence to establish a high-speed I / O connection between the initiator and the target device. Other actions might include enabling acceleration features of processor components, enabling DDR4 channels, and / or enabling high-bandwidth memory.

[0058] Referring again to action 504, if the initiator's hardware verification logic 202a (e.g., because the received verification ID does not match the expected verification ID) cannot verify the target, then in action 508, the hardware verification logic 202a stores the "unverified" state in a specific register location.

[0059] In action 510, the initiator takes one or more actions in response to the failure of target component verification. For example, such actions might include performing a boot sequence by downloading a standard FPGA bitfile instead of a proprietary FPGA bitfile, disabling certain acceleration features of the FPGA (e.g., compression, encryption, etc.), disabling the DDR4 channel, and / or disabling HBM (if present). In this way, a compute storage device with an unverified target component can function, but with limited capabilities.

[0060] In one embodiment, a notification is sent in action 512 to inform the user that the target device is not an authorized device. For example, the notification may be displayed to the user as part of the functionality of the Basic Input / Output System (BIOS).

[0061] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the spirit and scope of the inventive concept, the first element, component, region, layer, or portion discussed herein may be referred to as the second element, component, region, layer, or portion.

[0062] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximate terms rather than terms of degree, and those skilled in the art will recognize that these terms are intended to account for inherent biases in measured or calculated values.

[0063] As used herein, the singular forms “a” and “an” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. When expressions such as “at least one” precede a list of elements, they modify the entire list of elements and not individual elements within the list. Furthermore, when describing embodiments of the inventive concept, the use of “may” refers to “one or more embodiments of this disclosure.” Additionally, the term “exemplary” is intended to indicate an example or illustration. As used herein, the terms “use” and “utilized” may be considered synonymous with the terms “exploited” and “taken advantage of,” respectively.

[0064] It will be understood that when a component or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another component or layer, the component or layer may be directly on, connected to, coupled to, or adjacent to the other component or layer, or one or more intermediate components or layers may exist. Conversely, when a component or layer is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another component or layer, no intermediate components or layers exist.

[0065] Any numerical range described herein is intended to include all subranges containing the same numerical precision within the stated range. For example, the range "1.0 to 10.0" is intended to include all subranges between the minimum value of 1.0 and the maximum value of 10.0 (i.e., the minimum value is equal to or greater than 1.0 and the maximum value is equal to or less than 10.0), such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein.

[0066] While exemplary embodiments of systems and methods for verifying components of modular computing storage devices have been specifically described and illustrated herein, various modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that systems and methods for verifying components of modular computing storage devices constructed in accordance with the principles of this disclosure can be embodied in addition to those specifically described herein. This disclosure is also defined in the appended claims and their equivalents.

Claims

1. A storage device configured for hardware verification, comprising: A first hardware component includes a connector and first verification logic, the first verification logic being configured to detect a criterion and generate a first signal in response to detecting the criterion via the connector, wherein the criterion is used to detect the start of a reset period when the device is inserted into a slot in a computer system without stopping or shutting down the system; and A second hardware component, coupled to the first hardware component via the connector, includes second verification logic configured to monitor and receive the first signal via the connector. In response to receiving the first signal, the second verification logic is configured to compare the received first signal with the expected signal and generate a result. The storage device is configured to take action in response to the result.

2. The device according to claim 1, wherein, The first hardware component includes at least one of a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), and the second hardware component includes non-volatile memory.

3. The device according to claim 1, wherein, The expected signal is associated with an identifier stored in the memory of the second hardware component.

4. The device according to claim 1, wherein, The connector is a connector that supports the PCIe (Peripheral Component Interconnect) protocol.

5. The device according to claim 1, wherein, The first signal is provided through a preset pin of the connector.

6. The device according to claim 1, wherein, The result includes an indication that the received first signal matches the expected signal, and the action includes enabling the acceleration features of the storage device.

7. The device according to claim 1, wherein, The result includes an indication that the received first signal does not match the expected signal, and the action includes disabling the acceleration features of the storage device.

8. The device according to claim 1, wherein, The result includes an indication that the received first signal does not match the expected signal, and the action includes displaying a notification on a display device.

9. The device according to claim 1, wherein, The second hardware component is coupled to the host via a second connector.

10. A method for hardware verification via a storage device, the method comprising: The first verification logic in the first hardware component is used to detect the standard. In response to the detection of the standard, a first signal is generated via a connector in the first hardware component, wherein the standard is the start of a reset period detected when the device is inserted into a slot in a computer system without stopping or shutting down the system; The first signal is monitored and received via a second verification logic in a second hardware component, the second hardware component being coupled to the first hardware component via the connector; and In response to receiving the first signal, the received first signal is compared with the expected signal by the second verification logic, and a result is generated, wherein the storage device is configured to take action in response to the result.

11. The method according to claim 10, wherein, The first hardware component includes at least one of a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), and the second hardware component includes non-volatile memory.

12. The method according to claim 10, wherein, The expected signal is associated with an identifier stored in memory.

13. The method according to claim 10, wherein, The connector is a connector that supports the PCIe (Peripheral Component Interconnect) protocol.

14. The method of claim 10, wherein, The first signal is provided through a preset pin of the connector.

15. The method according to claim 10, wherein, The result includes an indication that the received first signal matches the expected signal, and the action includes enabling the acceleration features of the storage device.

16. The method of claim 10, wherein, The result includes an indication that the received first signal does not match the expected signal, and the action includes disabling the acceleration features of the storage device.

17. The method according to claim 10, wherein, The result includes an indication that the received first signal does not match the expected signal, and the action includes displaying a notification on a display device.

18. The method according to claim 10, wherein, The second hardware component is coupled to the host via a second connector.

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