Method and system for providing a programmable microcontroller using a two-stage configuration process

Abstract

The present application relates to a method and system for providing a programmable microcontroller using a two-stage configuration process. One embodiment of the present invention discloses a two-stage configuration process, configuring a field programmable gate array to include a configurable microcontroller during a first stage configuration, and configuring the configurable microcontroller during a second stage configuration. In one aspect, the two-stage configuration process can receive first configuration data from a first external storage location via a communication bus. The first configuration data is stored in a first configuration memory for use in configuring the field programmable gate array to include a configurable microcontroller for the first stage configuration, and then obtaining second configuration data having microcontroller attributes from a second external storage location via the communication bus. Subsequently, the second configuration data is stored in a second configuration memory for use in programming the configurable microcontroller for the second stage configuration.

Description

Technical Field

[0001] Exemplary embodiments of the present invention relate to computer hardware and software. More specifically, exemplary embodiments of the present invention relate to on-chip processors and / or microcontrollers (MCUs). Background Art

[0002] With the increasing popularity of digital communications, artificial intelligence (AI), the Internet of Things (IoT), and / or robotic control, the demand for more and faster data is increasing. In order to handle large amounts of data between electronic systems or computers, high-speed interface components are usually required. In order to properly handle different types of interface standards or protocols, different types of MCUs are generally used.

[0003] A traditional MCU includes one or more processors integrated in a single integrated circuit (IC). A traditional MCU includes memory devices and logic circuits for embedded applications, such as input / output (IO) management.

[0004] In terms of applications, MCU can be used to manage products and equipment such as automotive control systems, computer network systems, medical systems, remote control, vehicle control, robotic applications, mechanical control, office machines, electrical appliances, power tools, toys, etc. Various types of peripherals require different types of MCUs to handle various digital computing and / or network industries. In different environments, different peripherals may require MCUs to sense and / or control electrical systems, industrial control, automobiles, network communications, etc.

[0005] A disadvantage of conventional MCUs is that, in general, a specific type of interface communication requires a specific MCU configuration. Summary of the invention

[0006] One embodiment of the present invention discloses a two-phase configuration process (TCP) that configures a field-programmable gate array (FPGA) to include a configurable microcontroller unit (CMU) during a first phase configuration and configures the CMU during a second phase configuration. On the one hand, the TCP can receive first configuration data from a first external storage location via a communication bus. The first configuration data is stored in a first configuration memory for configuring the FPGA to include the CMU for the first phase configuration, and then, second configuration data having MCU attributes is obtained from a second external storage location via the communication bus. Subsequently, the second configuration data is stored in a second configuration memory for programming the CMU for the second phase configuration.

[0007] In one aspect, the CMU includes a processor, an I / O port, and a programmable microcontroller (PM). The processor is configured to communicate with a host central processing unit (CPU) based on a set of predefined instruction codes. The I / O port is used to transmit information between the processor and external devices. The PM facilitates a communication interface between the I / O port and one or more external devices through one or more configurable communication standards selected by the PM according to an interface programming microcode.

[0008] Alternatively, one embodiment discloses a process for providing a CMU for identifying at least one embedded function. For example, after searching for a bitmap or software that enables the CMU to perform the embedded function through a communication network, once the bitmap is found, the bitmap is downloaded through the communication network. Once the CMU is programmed in response to the bitmap, the embedded function performed by the CMU is verified according to the downloaded bitmap.

[0009] Other features and advantages of exemplary embodiments of the invention will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Exemplary embodiments of the present invention will be more fully understood through the following detailed description and various drawings of embodiments of the present invention, however, these drawings should not be used to limit the present invention to specific embodiments but are only for explanation and understanding.

[0011] Figure 1 FIG. 1 is a diagram showing a CMU according to an embodiment of the present invention, wherein the CMU can provide a communication interface based on a programmable microcode.

[0012] Figure 2 FIG. 4 is a block diagram of a programmable processor used in a CMU according to an embodiment of the present invention.

[0013] Figure 3 FIG. 4 is a block diagram of a CMU with programmable ports according to an embodiment of the present invention.

[0014] Figure 4-6 FIG. 4 is a block diagram of a CMU including a PM according to an embodiment of the present invention.

[0015] Figure 7 FIG. 4 is a block diagram showing a memory structure used in a CMU according to an embodiment of the present invention.

[0016] Figure 8 FIG. 4 is a block diagram showing a configurable switch of a programming PM according to an embodiment of the present invention.

[0017] Figure 9-10 It is a process block diagram of cloud programming CMU according to one embodiment of the present invention.

[0018] Fig.11 FIG. 4 is a flowchart showing a process of programming a CMU using a downloaded bitmap according to an embodiment of the present invention.

[0019] Fig.12 FIG. 4 is a diagram of a computer network capable of providing embedded functions through a CMU according to an embodiment of the present invention.

[0020] Fig.13 is a block diagram illustrating a digital processing system or components capable of processing and / or executing instructions used in a CMU according to one embodiment of the present invention.

[0021] Fig.14 FIG. 1 is a block diagram of a programmable semiconductor device (PSD) or FPGA that can include a CMU through a TCP according to an embodiment of the present invention.

[0022] Fig.15 FIG. 4 is a block diagram showing a logical process of TCP according to an embodiment of the present invention.

[0023] Fig.16 FIG. 4 is a process flow diagram of a TCP for facilitating a configuration process of a CMU according to an embodiment of the present invention.

[0024] Fig.17 FIG. 4 is a flowchart showing a process of programming a CMU using TCP according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Embodiments of the present invention are described herein in the context of methods and / or apparatus for providing selectable interface management via one or more configurable MCUs.

[0026] The purpose of the following detailed description is to provide an understanding of one or more embodiments of the present invention. Those of ordinary skill in the art will appreciate that the following detailed description is merely illustrative and is not intended to be limiting in any way. Other embodiments will readily occur to those skilled in the art who benefit from this disclosure and / or description.

[0027] For the sake of clarity, not all of the routine functionality of the embodiments described herein is shown and described. Of course, it is understood that in the development of any such actual embodiment, many implementation-specific decisions may be made in order to achieve the developer's specific goals, such as complying with application-related and business-related constraints, and that these specific goals may vary from one embodiment to another and from one developer to another. Moreover, it is understood that such development work, while potentially complex and time-consuming, is a routine engineering effort for those of ordinary skill in the art who benefit from the embodiments disclosed herein.

[0028] The various embodiments of the present invention shown in the accompanying drawings are not drawn to scale. Instead, the sizes of various features may be enlarged or reduced for clarity. In addition, some drawings may be simplified for clarity. Therefore, not all components of a given device (e.g., apparatus) or method may be depicted in the accompanying drawings. The same reference numerals will be used throughout the drawings and the detailed description below to refer to the same or similar parts.

[0029] According to embodiments of the present invention, the components, process steps and / or data structures described herein may be implemented using various types of operating systems, computing platforms, computer programs and / or general-purpose machines. In addition, those skilled in the art will recognize that less general-purpose devices, such as hardware devices, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc., may also be used without departing from the scope and spirit of the inventive concepts disclosed herein. If the method including a series of process steps is implemented by a computer or machine, and these process steps can be stored as a series of instructions readable by the machine, they can be stored on a tangible medium such as a computer storage device, for example: Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash Memory, Jump Drive, magnetic storage media (e.g., magnetic tape, disk drive, etc.), optical storage media (e.g., CD-ROM, DVD-ROM, paper cards and paper tapes, etc.) and other known types of program memory.

[0030] The term "system" or "device" is used herein generally to describe any number of components, elements, subsystems, devices, packet switch elements, packet switches, access switches, routers, networks, computers and / or communication devices or mechanisms, or combinations of their components. The term "computer" includes a processor capable of executing instructions, a memory, and a bus, wherein a computer refers to a single or clustered computer, a personal computer, a workstation, a mainframe, or a combination of computers.

[0031] One embodiment of the present invention discloses a CMU capable of providing one or more programmable I / O interfaces. The CMU includes a processor, an I / O port, and a PM. The processor is configured to communicate with a host CPU based on a set of predefined instruction codes. The I / O port is used to transmit information between the processor and an external device. The PM facilitates a communication interface between the I / O port and one or more external devices through one or more configurable communication standards selected by the PM according to an interface programming microcode.

[0032] Alternatively, one embodiment discloses a process for providing a CMU for identifying at least one embedded function. For example, after searching for a bitmap or software that enables the CMU to perform the embedded function through a communication network, once the bitmap is found, the bitmap is downloaded through the communication network. Once the CMU is programmed in response to the bitmap, the embedded function performed by the CMU is verified according to the downloaded bitmap.

[0033] Figure 1 1 is a block diagram 100 of a CMU 102 that can provide a communication interface based on a programmable microcode according to one embodiment of the present invention. In one aspect, the CMU 102 includes a programmable processor 110, a programmable memory, a programmable I / O component 116, and a program code storage device 106. In one aspect, the programmable code storage device 106 stores a processor configuration code 120, a memory configuration code 122, and an I / O configuration code 126. It should be noted that the basic concept of the exemplary embodiment of the present invention will not change even if one or more blocks (circuits or components) are added or removed to / from the block diagram 100.

[0034] In one aspect, the processor 110 can be configured according to the application. For example, the processor 110 can be programmed by a programmable microcode stored in the programmable code storage device 106 to execute ARM-based instruction codes. For example, a programmable processor can be programmed or configured to execute instructions according to ARM, MIPS, X86 or PowerPC microcode. In another embodiment, the processor 110 is a conventional processor or a fixed processor (non-programmable) that can manage programmable I / O components 116 and / or programmable memory 112. The benefit of a programmable processor is that it can provide additional flexibility to the end user.

[0035] Depending on the application, the memory 112 can be a configurable or static memory device. In one embodiment, the memory 112 is a programmable memory that can be programmed according to the memory configuration code 122 stored in the programmable code storage device 106. Alternatively, the memory 112 can be programmed to a plurality of different storage capacities to handle different I / O ports. Alternatively, depending on the application and the user's preferences, the memory 112 can be programmed to use onboard flash memory, static random access memory (SRAM) and / or RAM. In another embodiment, the memory 112 can be a static or conventional memory device, which can be a conventional flash memory, SRAM, RAM, or a combination of flash memory, SRAM and RAM storage devices.

[0036] In one embodiment, the I / O assembly 116 includes a set of I / O ports and an interface microcontroller. In one aspect, the interface microcontroller is a PM based on the I / O configuration code 126 in the programmable code storage device 106. The function of the PM is to facilitate data communication or peripheral interfaces between external devices and the processor 110 through a set of I / O ports. For example, the peripheral interface includes, but is not limited to, an Inter-Integrated Circuit (IC) bus. 2 C), Serial Peripheral Interface (SPI), Universal Asynchronous Receiver / Transmitter (UART), etc. The benefit of using PM is that CMU can flexibly handle multiple interface standards.

[0037] In one example, I 2 C includes multi-master, multi-slave, single-ended, and serial computer buses. 2 A typical application of SPI is that it can be used to attach low-speed peripherals for short-distance and intra-board communication. The SPI bus is a synchronous serial communication interface specification used for short-distance communication such as in embedded systems. In one example, SPI devices communicate with a single master device in full-duplex mode using a master-slave architecture. The master device initiates frames for reading and writing. It should be noted that the SPI bus can also be called a four-wire serial bus instead of a three-wire, two-wire, or one-wire serial bus. UART is a computer hardware device for asynchronous serial communication in which the data format and transmission speed can be configured. In one example, some electrical signal levels and methods are handled by driver circuits external to the UART.

[0038] In one embodiment, the programmable code storage device 106 is used to store programming microcode to program programmable devices, such as the programmable processor 110, the programmable memory 112, and / or the programmable I / O component 116. In one aspect, the storage device 106 divides its storage space into three parts for storing processor configuration code 120, memory configuration code 122, and I / O configuration code 126. Alternatively, the storage device 106 includes a processor configuration memory for storing the processor configuration code 120, a memory configuration memory for storing the memory configuration code 122, and / or an I / O configuration memory for storing the I / O configuration code 1126.

[0039] It should be noted that configuration codes, such as codes 120 - 126 , may be obtained from a user, a cloud, and / or a provider.

[0040] In one embodiment, the function of CMU 102 is to provide a programmable I / O interface using processor 110, I / O port 118 and PM. The processor is configured to communicate with the host CPU based on a set of predefined instruction codes ( Figure 1 In one aspect, the processor 110 is a programmable processor that can include a hard macro or macro code that can selectively execute instruction sets based on Advanced RISC Machine (ARM), Million Instructions Per Second (MIPS), Argonaut RISC Core (ARC), X86, or Power according to the processor programmable code.

[0041] I / O port 118 is used to transmit information between the processor and external devices or peripheral devices. For example, one or more I / O ports are configured to be coupled to multiple external devices through one or more buses. Different buses operate under different bus or interface standards. For example, these standards include but are not limited to analog comparator protocol, analog-to-digital converter protocol, liquid crystal display (LCD) interface protocol, universal synchronous / asynchronous receiver-transmitter (USART) protocol, SPI protocol and / or two-wire serial interface (Two-wire Serial Interface, TWI) protocol.

[0042] The PM coupled to the processor facilitates a communication interface between the I / O port 118 and one or more external devices via at least one of several configurable communication standards selected by the PM according to an interface programming microcode, such as the I / O configuration code 126. In one embodiment, the PM includes a plurality of programmable interfaces configured to facilitate communication between the I / O port 118 and one or more external devices according to the interface programming microcode. In one example, the programmable interfaces are configured to utilize I / O ports 118 and one or more external devices. 2C, based on a set of predefined programming microcodes, promotes communication between I / O port 118 and external devices. The programmable interface can also be configured to adopt the SPI bus protocol to facilitate communication between I / O port 118 and external devices. In another example, the programmable interface is configured to utilize the UART interface protocol to facilitate communication between I / O port 118 and external devices. Alternatively, the programmable interface can be configured to utilize an integer (Integer, Int) interface protocol to facilitate communication between I / O port 118 and external devices based on a predefined programming microcode. In addition, the programmable interface is configured to utilize the TWI protocol to facilitate communication between I / O port 118 and one or more external devices based on a programming microcode. In addition, the programmable interface is also configured to utilize the timer interface protocol to facilitate communication between I / O port and external devices based on a set of predefined programming microcodes.

[0043] In one aspect, the CMU 102 includes a memory coupled to the processor and configured to store predefined programming microcode that can be downloaded from the cloud system. In one example, the memory includes flash memory for storing a bitmap downloaded from a remote location via a communication network. The memory may include an SRAM for storing data. For example, an SRAM is a configurable memory device that can set a programmable bandwidth according to a programmable code of the memory. In one aspect, some memories are configurable and can be configured as one of a single port and a dual port according to a programmable code of the memory.

[0044] Compared with traditional MCU, the advantage of using CMU is that it provides programmability, so CMU can implement a variety of different peripheral interface protocols based on microcode.

[0045] Figure 2 2 is a block diagram 200 of a programmable processor 202 used in a CMU according to an embodiment of the present invention. In one embodiment, the processor 202 includes a programmable processor 222, a selection logic 220, an ARM core 210, a MIPS core 212, an X86 core, a PowerPC core 216, and an FPGA core 218. It should be noted that the core refers to software or firmware microcode that can program the programmable processor 222 into one of ARM, MIPS, X86, PowerPC, or other FPGA logic according to one of the selected cores 210-218. It should be noted that the basic concept of the exemplary embodiment of the present invention will not change if one or more blocks (circuits or components) are added or removed to / from the block diagram 200.

[0046] Figure 3300 is a block diagram of a memory device 308 with programmable ports according to an embodiment of the present invention. In one embodiment, the memory device 308 can be a programmable memory or a static non-programmable memory, such as a conventional flash memory or SRAM. On the one hand, the memory device 308 includes a set of ports 302-304, a memory array 310 with n bits and m rows, and a configurable logic 306. In one embodiment, the configurable logic 306 manages or controls the storage capacity size of the single port and the dual port. It should be noted that the basic concept of the exemplary embodiment of the present invention will not change if one or more blocks (circuits or components) are added or removed to / from the block diagram 300.

[0047] It should be noted that memory 308 can be a hard-core SRAM, and in some cases, it can be configured. For example, memory 308 can be configured as a single port or a dual port. Alternatively, the data width can be programmed to be 8, 16, and / or 32 bits wide. In addition, the depth of the array can also be configured to be 1K, 2K, 16K, 32K, etc. Memory 308 can also be a hard-core flash memory that has the same access behavior as SRAM. In one example, the flash memory and / or SRAM can be accessed by the CPU with a memory addressing scheme that makes it just like the SRAM and / or flash memory scheme of a normal MCU.

[0048] Figure 4 4 is a block diagram 400 of a CMU including a PM according to one embodiment of the present invention. The block diagram 400 includes a processor or CPU 110, a memory 112, an I / O port 118, a programming code storage device 106, and a PM 402. The programmable code storage device 106, also referred to as a configuration component, stores processor configuration codes for programming the PM, the processor 110, and / or the memory 112. It should be noted that the basic concept of the exemplary embodiment of the present invention will not change even if one or more blocks (circuits or elements) are added or removed to / from the block diagram 400.

[0049] In one embodiment, PM 402 is configured to provide peripheral data communication between external devices or peripheral devices and a host using Software-defined Matrix and Logic (SDML). In one aspect, SDML is a programmable logic that can perform certain tasks based on microcode. An exemplary SDML is similar to an FPGA or Programmable Logic Device (PLD), where the logic or IC needs to be programmed before use. For example, PM 402 can be programmed to use I 2C standard programming to facilitate communication. In addition, PM 402 is programmed to allow some I / O ports to use the SPI bus standard and other I / O ports to use the UART interface protocol. On the one hand, PM 402 can be programmed to facilitate the use of I 2 C, SPI, UART, Int, TWI and / or timer interfaces for communication.

[0050] The advantage of using PM 402 is that PM 402 is flexible and can be programmed to handle various interfaces of MCU. Another advantage of using PM 402 is that it allows the user to update, delete and / or add interface protocols after installing CMU in the system.

[0051] Figure 5 FIG. 5 is a block diagram 500 of a CMU including a PM according to an embodiment of the present invention. The block diagram 500 is similar to Figure 4 The block diagram 400 shown includes a processor or CPU 110, a memory 112, an I / O port 118, a programming code storage device 106, and a PM 502. The programming code storage device 106 is also referred to as a configuration component, and stores processor configuration codes for programming the PM, the processor 110, and / or the memory 112. It should be noted that the basic concept of the exemplary embodiment of the present invention will not change even if one or more blocks (circuits or elements) are added or removed to / from the block diagram 500.

[0052] In one embodiment, PM 502 is a configurable device that can use I 2 One of C, SPI, UART and Int, provides peripheral data communication between external devices or peripheral devices and the host. PM 502 is composed of some fixed cores, such as I 2 C 506, plus some software defined logic or kernel. In one aspect, PM 502 can select the interface block for data communication. In one example, microcode can be provided by a user or provider through a remote location. For example, PM 502 can 2 C506 is programmed to handle communications between I / O port 508 and processor 110 .

[0053] The advantage of using PM 502 is that it reduces the complexity of the programmable logic while providing flexibility.

[0054] Figure 6 FIG. 6 is a block diagram 600 of a CMU including a PM according to an embodiment of the present invention. The block diagram 600 is similar to Figure 5The block diagram 500 shown includes a processor or CPU 110, a memory 112, an I / O port 118, a programming code storage device 106, and a PM 602. The programming code storage device 106 is also referred to as a configuration component, and stores processor configuration codes for programming the PM, the processor 110, and / or the memory 112. It should be noted that the basic concept of the exemplary embodiment of the present invention will not change even if one or more blocks (circuits or elements) are added or removed to / from the block diagram 600.

[0055] PM 602 is similar to Figure 5 The PM 502 shown is a configurable device that can use timers, TWI, I 2 C, a liquid crystal display and / or other logic to provide peripheral data communication between an external device or peripheral device and a host. PM 602 is composed of some fixed cores, such as timer 610, plus some software defined logic or cores. On the one hand, PM 602 can select the interface block for data communication. In one example, microcode can be provided by a user or provider through a remote location. For example, PM 602 can program block 610 to handle communication between I / O ports 606-608 and processor 110.

[0056] The advantage of using PM 602 is the flexibility provided by being able to use both hard core and programmable logic.

[0057] On the one hand, CMU essentially provides an MCU hardware platform with a mainstream CPU such as ARM, MIPS, X86, etc., where the components are defined by a downloadable configuration file. When the user selects certain configurations, such as different sizes of SRAM, flash memory, different peripherals, or different numbers of ports, the specific configuration file can be downloaded from the cloud. The benefit is that it allows users to make product decisions based on flexible hardware design. Another benefit is that CMU can be upgraded even after leaving the factory. In addition, by providing a common platform, hardware manufacturing and / or resources will be reduced.

[0058] For software-defined MCU components, the CMU may include a programmable CPU and a programmable I / O component. The CPU or processor may be a hard core, such as ARM, MIPS, ARC, X86, and Power PC. One reason for choosing a hard core is that the MCU architecture is convergent. The hard core is a cost-effective approach that provides the highest efficiency in terms of performance and power balance. The I / O component may also be a hard core to provide input and output of the CMU. In one example, the I / O standard can be configured to support different I / O standards, such as LVCMOS3.3, SSTL2.5, SST1.8, etc.

[0059] Figure 7700 is a block diagram of a memory structure used in a CMU according to an embodiment of the present invention. Block diagram 700 shows a configurable MCU or CMU that can receive programming code or configuration code from outside the CMU through port 730. After receiving the configuration code or microcode, the code is stored in memory cell group 732. It should be noted that the basic concept of the exemplary embodiment of the present invention will not change if one or more blocks (circuits or components) are added or removed to / from block diagram 700.

[0060] The block diagram 700 also includes a configuration engine 736 for programming the programmable device according to the received code. In one aspect, the configuration engine 736 is coupled to the memory cell group 732. The interface port 730 with an external programmer, a personal computer, or an automated test equipment (ATE) is connected to a data bus having one or more bus protocols, such as Joint Test Action Group (Jtag), I 2 C, SPI and / or data bus connected to the CPU. It should be noted that the configuration engine 736 receives data from the interface and transfers the data to the memory unit.

[0061] Schematic 702 shows a one-dimensional memory cell organized in a series, where data within the series is moved from one cell to the next based on a clock cycle. In one example, the memory cell can be a 6T SRAM cell or a non-volatile memory cell. Schematic 706 shows a two-dimensional memory cell as a normal SRAM array. In one example, each memory cell can send a control signal with a value of "0" or "1". Data is transferred from one to the next.

[0062] It should be noted that SDML refers to a matrix that can be composed of connections and logic. The output of the memory cells determines the connections and logic that are formed. The logic can be predefined in the hard core, and then the memory cells select the logic desired by the user. More advanced methods can use programmable logic such as general array logic (GAL), complex programmable logic device macros (CPLD'sMacro) or FPGA lookup tables and registers.

[0063] Figure 8800 is a block diagram of a configurable switch for programming a PM according to an embodiment of the present invention. Block diagram 800 includes three cells 802-808, three switches 812-818, three input lines A, B, C, and one output line 810. Switch 812 controls whether the data on input line A should pass through output line 810, and switch 816 controls whether the data on input line B should pass through output line 810. In addition, switch 818 controls whether the data on input line C should enter output line 810. To determine which data on the input lines should enter output line 810, the values ​​in cells 802-808 determine which switch should be turned on. For example, if cell 2 806 has an "on" logic value, switch 816 should be turned on and the data on input line B should pass through output line 810. In one aspect, cells such as cells 802-808 and switches 812-818 are used to form connections and logic in a PM.

[0064] For example, if the cell output is 1, the switch is on. Otherwise, the switch is off. Assume A is I 2 C is output, B is timer output, and C is SPI output. By setting the cell value to "0" or "1", the user can select which hard core will be used and output to O.

[0065] Fig. 9 900 is a process block diagram of cloud programming CMU according to one embodiment of the present invention. Block diagram 900 includes a laptop 902, a CMU 906, a cloud 908, and a server 910. In one embodiment, server 910 stores configuration files, wherein server 910 may be a supplier server. Laptop 902 controlled by a user can download configuration files from server 910 via cloud 908. Subsequently, the configuration files are used to program MCU 906 connected to laptop 902. On the one hand, laptop 902 can search for configuration files through online providers to configure CMU 906 according to user expectations.

[0066] The laptop 920 includes an ATE 922, a cloud 908, and a server 910, wherein the ATE accommodates a plurality of CMUs. The ATE 922 is used to facilitate mass production, and it can program a plurality of CMUs simultaneously. After downloading a configuration file or configuration microcode from the supplier server 910, the ATE can simultaneously program the CMUs according to the downloaded configuration file.

[0067] Fig.101000 is a process block diagram of cloud programming CMU according to one embodiment of the present invention. Block diagram 1000 includes laptop 902, cloud 908 and CMU 906, wherein laptop 902 is coupled to CMU 906 via cloud 908. In one aspect, laptop 902 can configure CMU 906 via cloud 908 via a remote configuration operation process. It should be noted that the basic concept of the exemplary embodiment of the present invention will not change even if one or more blocks (circuits or components) are added or removed to / from block diagram 1000.

[0068] The exemplary embodiment of the present invention includes various processing steps, which will be described below. The steps of this embodiment can be embodied in machine or computer executable instructions. The instructions can be used to cause a general or special purpose system programmed with the instructions to perform the steps of the exemplary embodiment of the present invention. Alternatively, the steps of the exemplary embodiment of the present invention can be performed by specific hardware elements containing hard-wired logic for performing the steps, or by any combination of programmed computer elements and customized hardware elements.

[0069] Fig.11 1100 is a flowchart of a process for programming a CMU using a downloaded bitmap according to an embodiment of the present invention. At block 1102, a process or method for providing a CMU identifies a first embedded function of a configurable MCU to facilitate a network interface between a host and an external device based on a first interface protocol. For example, determining I 2 The function of the C interface is used to communicate with at least one external device. Alternatively, the function of the UART interface is determined to be used to communicate with at least one external device.

[0070] At block 1104, a communication network is used to search for a first bitmap for programming a configurable MCU, and after executing a first embedded function, at block 1106, the first bitmap is Figure 1 Once located, it is downloaded from the cloud system via the communication network. It should be noted that the configurable MCU is the same or similar to the CMU.

[0071] At block 1108, after programming the configurable MCU in response to the first bitmap, the first embedded function of the CMU after programming is verified at block 1110. In one embodiment, the first bitmap is stored in a local memory. If the first bitmap fails to verify the first embedded function performed by the CMU, the process can search for a new bitmap associated with the first embedded function to program the CMU. In one aspect, after identifying a second embedded function of the CMU to facilitate a network interface between a host and an external device based on a second interface protocol, a second bitmap is downloaded from the cloud system via a communication network. The process programs or configures the configurable MCU in response to the second bitmap.

[0072] It should be noted that I2 C is a multi-master, multi-slave, single-ended, serial computer bus. It is commonly used to connect lower speed peripheral integrated circuits to processors and microcontrollers for short-distance intra-board communications.

[0073] Alternatively, the SPI bus is a synchronous serial communication interface specification for short-distance communication, mainly used in embedded systems. The SPI bus can be used for data cards and / or LCD displays. SPI devices can use a master-slave architecture to communicate with the master in dual mode. For example, the master device provides the frames for reading and writing, while multiple slave devices are supported by selecting a separate chip select signal (Slave Select, SS) line.

[0074] Fig.12 1 is a diagram of a computer network that can provide embedded functions through a configurable MCU according to an embodiment of the present invention. In this network environment, system 1201 is coupled to wide area network 1202, LAN 1206, network 1204, and server 1205. Wide area network 1202 includes the Internet or other dedicated networks, including America On-Line TM 、SBC TM 、MicrosoftNetwork TM and Prodigy TM Wide area network 1202 may also include network backbones, long-haul lines, Internet service providers, various levels of network routers, and other means of routing data between computers.

[0075] On one hand, the server 1204 is coupled to the WAN 1202 and routes data to the clients 1210-1212 via the LAN 1206. The server 1204 is coupled to the storage device 1222 to improve the overall storage efficiency.

[0076] The LAN connection allows the client systems 1210-1212 to communicate with each other via the LAN 1206. The USB portable system 1230 can communicate with the client computer systems 1210-1212, the provider system 1220, and the storage device 1222 via the wide area network 1202 using conventional network protocols. For example, the client system 1210 can be directly connected to the wide area network 1202, or directly connected to the wide area network 1202 by dialing a telephone or other network transmission line. Alternatively, the clients 1210-1212 use a modem pool to connect to the wide area network 1202.

[0077] After briefly describing an embodiment of a computer network in which an embodiment of the present invention operates, Fig.12 An example of a computer system is shown that uses one or more configurable MCUs and / or programmable MCUs.

[0078] Fig.13 1 is a block diagram of a digital processing system that can use a CMU according to an embodiment of the present invention. Computer system 500 may include a processing unit 1301, an interface bus 1312, and an I / O unit 1320. Processing unit 1301 includes a processor 1302, a main memory 1304, a system bus 1311, a static storage device 1306, a bus control unit 1305, an I / O element 1330, and a non-volatile memory 1385. It should be noted that the data to / from Fig.12 The basic concept of the exemplary embodiments of the present invention will not change even if one or more blocks (circuits or elements) are added or removed.

[0079] The bus 1311 is used to transmit information between various components and the processor 1302 for data processing. The processor 1302 can be any of a variety of general-purpose processors, embedded processors, or microprocessors, such as Embedded processors, Core TM Duo, Core TM Quad, Pentium TM Microprocessor, Motorola TM 68040, series processor or Power PC TM microprocessor.

[0080] The main memory 1304 may include multiple levels of cache memory to store frequently used data and instructions. The main memory 1304 may be a random access memory (RAM), a magnetic random access memory (MRAM), or a flash memory. The static memory 1306 may be a ROM, which is coupled to the bus 1311 and is used to store static information and / or instructions. The bus control unit 1305 is coupled to the buses 1311-1312 and controls components that can use the bus, such as the main memory 1304 or the processor 1302. The bus control unit 1305 manages the communication between the bus 1311 and the bus 1312. The large-capacity storage memory or solid-state drive 106, such as a magnetic disk, an optical disk, a hard disk drive, a floppy disk, a read-only optical disk memory, and / or a flash memory, is used to store a large amount of data.

[0081] In one embodiment, I / O unit 1320 includes display 1321, keyboard 1322, cursor control device 1323, and communication device 1325. Display device 1321 can be a liquid crystal device, a cathode ray tube (CRT), a touch screen display, or other suitable display device. Display 1321 projects or displays an image of a graphic planning board. Keyboard 1322 can be a conventional alphanumeric input device for communicating information between computer system 500 and a computer operator. Another type of user input device is cursor control device 1323, such as a conventional mouse, touch mouse, trackball, or other type of cursor, for communicating information between system 1300 and a user.

[0082] The communication device 1325 is coupled to the bus 1311 and is used to obtain information from a remote computer or server, such as the server 1004 or other computers, through the wide area network 1202. The communication device 1325 may include a modem or a network interface device, or other similar device to facilitate communication between the computer 1300 and the network. The computer system 1300 may be connected to the network infrastructure, such as Fig.12 The infrastructure shown in FIG. 1 is coupled to some servers 1204 .

[0083] In another embodiment, a TCP capable of configuring an FPGA as a CMU is disclosed. During the first phase configuration process, the FPGA is programmed to include one or more CMUs; during the second phase configuration process, the CMU is configured to include one or more user-defined MCU functions. On the one hand, the TCP can receive first configuration data from a first external storage location via a communication bus. The first configuration data is stored in a first configuration memory for use in obtaining second configuration data having MCU attributes from a second external storage location via a communication bus after configuring the FPGA to include a CMU for the first phase configuration. Subsequently, the second configuration data is stored in a second configuration memory for use in programming the CMU for the second phase configuration.

[0084] Fig.1414 is a block diagram 1400 of a PSD or FPGA that can include a CMU through TCP according to an embodiment of the present invention. To simplify the above discussion, the terms "PSD", "programmable integrated circuit (PIC)", "FPGA", and "PLD" all refer to the same or similar devices and can be used interchangeably below. Block diagram 1400 includes multiple programmable partition regions (PPRs) 1402-1408, a programmable interconnect array (PIA) 1450, and a regional I / O port 1466. The programmable partition regions 1402-1408 also include a control unit 1410, a memory 1412, and a logic block (LB) 1416. It should be noted that the control unit 1410 can be configured as a single control unit, and similarly, the memory 1412 can also be configured as a single memory to store the configuration. It should be noted that the basic concept of the exemplary embodiment of the present invention will not change even if one or more blocks (circuits or elements) are added or removed to / from block diagram 1400.

[0085] The logic block 1416 is also called a configurable function unit (CFU), and includes a plurality of logic array blocks (LABs) 1418, which are also called configurable logic units (CLUs). For example, each LAB 1416 can be further configured to include a group of programmable logic elements (LEs), configurable logic slices (CLSs), or macro cells ( Fig.14 (not shown) and other circuits. In one example, each LAB may include any number of programmable LEs from 32 to 512. I / O pins ( Fig.14 ), LABs and LEs are connected via programmable interconnect array 1450 and / or other buses (such as bus 1462 or 1414) to facilitate communication between programmable interconnect array 1450 and programmable partitioned regions 1402-1408.

[0086] Each LE includes programmable circuits, such as product term matrices, lookup tables, and / or registers. LEs are also called cells, Configurable Logic Blocks (CLBs), slices, CFUs, macrocells, etc. Each LE can be independently configured to perform sequential and / or combinatorial logic operations. It should be noted that the basic concept of the PSD does not change even if one or more blocks and / or circuits are added or removed to / from the PSD.

[0087] The control unit 1410, also referred to as configuration logic, may be a single control unit. For example, the control unit 1410 manages and / or configures a single LE in the LAB 1418 based on configuration information stored in the memory 1412. It should be noted that some I / O ports or I / O pins are configurable so that they can be configured as input pins and / or output pins. Some I / O pins are programmed as bidirectional I / O pins, while other I / O pins are programmed as unidirectional I / O pins. A control unit such as unit 1410 is used to process / or manage PSD operations based on a system clock signal.

[0088] The logic block 1416 includes a plurality of LABs that can be programmed by the end user. Each LAB contains a plurality of LEs, wherein each LE also includes one or more lookup tables (LUTs) and one or more registers (or D flip-flops or latches). Depending on the application, the LE can be configured to perform user-specific functions based on a predefined function library implemented by the configuration software. In some applications, the PSD also includes a set of fixed circuits for performing specific functions. For example, fixed circuits include but are not limited to processors, digital signal processing (DSP) units, wireless transceivers, etc.

[0089] Programmable interconnect array 1450 is coupled to logic block 1416 via various internal buses such as bus 1414 or bus 1462. In some embodiments, bus 1414 or bus 1462 is part of programmable interconnect array 1450. Each bus includes a channel or conductor for transmitting signals. It should be noted that the terms "channel", "wiring channel", "conductor", "bus", "connection" and "interconnection" all refer to the same or similar connections and are used interchangeably herein. Programmable interconnect array 1450 can also be used to receive and / or transmit data directly or indirectly from / to other devices through I / O pins and LABs.

[0090] The memory 1412 may include multiple memory cells located on a programmable partitioned area. Alternatively, the memory 1412 may be combined into a single memory cell in the PSD. In one embodiment, the memory 1412 is a non-volatile memory storage cell used for both configuration and user memory. The non-volatile memory storage cell may be, but is not limited to, MRAM, flash memory, ferroelectric RAM, and / or phase change memory (or chalcogenide RAM). Depending on the application, some of the memory 1412 may be designated, allocated, or configured as block RAM (Block RAM, BRAM) for storing large amounts of data in the PSD.

[0091] The PSD includes a large number of programmable logic blocks 1416 interconnected by a programmable interconnect array 1450, where each programmable logic block is further divided into a plurality of LABs 1418. Each LAB 1418 also includes a large number of LUTs, multiplexers, and / or registers. During the configuration process, the user programs a truth table for each LUT to implement the desired logic function. It should be noted that each LAB can be further organized to include a plurality of LEs, which can be viewed as Configurable Logic Cells (CLCs) or CLSs. For example, a four-input (16-bit) LUT receives LUT inputs ( Fig.14 (Not shown). Based on the truth table programmed into the LUT during configuration of the PSD, a combinational output is generated by the programmed truth table of the LUT according to the logic value of the LUT input. The combinational output is then latched or buffered into a register or flip-flop before the end of the clock cycle.

[0092] In one embodiment, the control unit 1410 includes a multi-boot (MBC) module 1420 with a backup default configuration function. It should be noted that the multi-boot module 1420 with a backup default configuration function can be placed at any location within the programmable integrated circuit or PSD to facilitate a multi-boot process with a backup default configuration function. The function of the multi-boot module 1420 with a backup default configuration function is to use user-defined configuration data or default configuration data (DCD) to control a configuration process or a restart process. The benefit of using a multi-boot process with a backup default configuration function is to restore or recover a programmable integrated circuit or PSD from damaged or erroneous configuration data.

[0093] Depending on the application, the FPGA can be programmed to include one or more CMUs by means of the first stage configuration data stored in the first configuration memory. The advantage of using TCP is that once the FPGA is configured by the hardware engineer to emulate a CMU, the software engineer can program the CMU, for example, to perform user-defined MCU functions.

[0094] Fig.15 15 is a block diagram 1500 showing the logical process of TCP according to one embodiment of the present invention. The block diagram 1500 includes a user 1502, a first stage configuration 1506, and a second stage configuration 1508. On the one hand, the user 1502, including an engineer or a customer, couples the first stage configuration 1506 and the second stage configuration 1508 through a bus or communication channel 1504. It should be noted that the basic concept of the exemplary embodiment of the present invention will not change even if one or more blocks (circuits or elements) are added or removed to / from the block diagram 1500.

[0095] The first stage configuration 1506 includes a PLD 1510 that is configured or programmed to include at least one CMU capable of processing and executing MCU functions. In one embodiment, the PLD 1510 includes an embedded processor 1530, a plurality of CLBs, an I / O block 1536, a communication block 1532, and a memory block 1520. In one aspect, the memory block 1520 is organized into two parts, wherein the first part M1 is designated as a first configuration memory 1522 and the second part M2 is designated as a second configuration memory 1526. In one example, the I / O block 1536 includes a plurality of I / O pins for communicating with external devices. The communication block 1532 can be a part of the I / O block 1536 for communicating with a remote device or system using one or more existing communication networks, such as a wireless network, a Bluetooth network, or other types of communication networks.

[0096] The embedded processor 1530 is used to perform logical functions based on the instruction set. The embedded processor 1530 can be a software processor, a hardware processor, or a combination of the two. For example, the embedded processor 1530 can be a hard core that selectively executes an instruction set based on an ARM, MIPS, ARC, X86, Ryzen processor, or Power PC according to the processor programmable code.

[0097] The CLB 1416 may be further divided into LUTs that may be programmed to perform user-defined logic functions. For example, the CLB 1416 is configured as a CMU device having multiple programmable interfaces for facilitating communication between an I / O port and one or more external devices via at least one configurable communication standard. It should be noted that the user-defined characteristics of the CMU are defined by a set of predefined programming microcodes stored in the second configuration memory 1526.

[0098] In one embodiment, the memory block 1520 is an embedded flash memory, wherein a portion M1 of the embedded flash memory is a first configuration memory 1522 for accommodating PLD configuration data, and a second portion M2 of the embedded flash memory is a second configuration memory 1526 for accommodating CMU configuration data. In one embodiment, the flash memory is configured as a random access memory referenced by an address. For example, the first configuration memory 1522 stores configuration data of the PLD for configuring the PLD 1510 to implement functions or simulations as a CMU. The second configurable memory 1526 stores configuration data of the CMU for programming the CMU. Alternatively, the memory block 1520 may be an SRAM, wherein a portion of the SRAM is configured as a first configuration memory 1522 for facilitating the PLD configuration process; and a second portion of the SRAM is configured as a second configuration memory 1526 for facilitating the CMU configuration process. In another embodiment, the memory block 1520 includes a combination of volatile memory and non-volatile memory for processing the first and second configuration memories 1522-1526.

[0099] The first phase configuration 1506 includes an FPGA configuration process using a hardware description language (HDL) that uses an HDL such as Verilog or VHDL to configure the FPGA to include at least one CMU. For example, after the first phase configuration process, the FPGA 1510 behaves as a CMU. In operation, the user 1502 sends configuration data encoded in the HDL to the first configuration memory 1522 via a communication channel 1516 that is part of the bus 1504. It should be noted that the communication channels 1516-1518 are all the same bus 1504 in different phases. It should be noted that during the first phase configuration process, the communication channel 1516 is the bus 1504; during the second phase configuration process, the communication channel 1518 is the bus 1504.

[0100] After the FPGA including the CMU is verified through a set of predefined verification processes, the process enters the second stage configuration 1508 (as shown by reference numeral 1528). In one embodiment, the second stage configuration 1508 indicates that the FPGA or PLD 1512 has been configured as a CMU. For example, the second stage configuration 1508 facilitates the use of a programming environment in an assembly language, such as but not limited to C language, Python, and JavaScript, for configuring an embedded MCU and / or an embedded system.

[0101] When the user 1502 provides the assembly language as the second configuration data for configuring the CMU through the communication channel 1518, the CMU such as the PLD 1512 is programmed to use I 2CMU is programmed to use the SPI bus protocol to facilitate communication between the I / O port and one or more external devices according to a set of predefined programming microcodes. Alternatively, according to the interface programming microcode, the CMU is programmed to use the SPI bus protocol to facilitate communication between the I / O port and one or more external devices. In another embodiment, the CMU is programmed to use the Improved Inter-Integrated Circuit (IIC) bus. 3 C) protocol to facilitate communication between the I / O port and one or more external devices according to the interface programming microcode. In addition, the CMU can also be programmed to use UART, Int, TWI or timer interface to facilitate communication between multiple I / O ports and one or more external devices according to the interface programming microcode

[0102] Fig.16 1600 is a flowchart of a block diagram according to an embodiment of the present invention, and the TCP is used to implement a configuration process of a CMU. At block 1602, the process reads first configuration data or FPGA configuration data for configuring an FPGA from a first configuration memory. At block 1604, the FPGA is configured to behave as or simulate as one or more configurable MCUs according to the first configuration data. At block 1604, the process activates a verification process to verify or confirm the functionality of the FPGA. For example, the verification process determines that the FPGA behaves as a CMU.

[0103] At block 1608, the process checks whether the verification process verifies the functionality of the FPGA, the FPGA simulates the CMU, and if the verification process fails, the process continues with the process shown in block 1602. Otherwise, after completing the first phase or FPGA configuration, the process continues with the process shown in block 1610. After receiving and storing the MCU configuration data provided by the user, the second configuration data is read from the second configuration memory. At block 1612, the CMU is configured to perform one or more user-defined MCU logic functions according to the second configuration data. At block 1614, the process verifies the functionality of the CMU. At block 1616, the process checks whether the second phase configuration is successful. If the second phase configuration fails, the process enters block 1610 to continue configuring the CMU. Otherwise, if the second phase or CMU configuration is successful, after verifying that the CMU performs the user-defined function, the process continues to enter the end block. For example, the process can also identify a first embedded function of the CMU, such as an interface protocol for facilitating communication between a host and an external device. For example, the embedded function includes but is not limited to an I for communicating with at least one external device. 2 C interface function or I 3 C interface function.

[0104] The advantage of using TCP is that it allows the first user to program the FPGA using hardware language to emulate the CMU; the second user to program the CMU using assembly language to execute the user-defined MCU functions.

[0105] Fig.17 1700 is a flowchart of programming a CMU using a TCP according to an embodiment of the present invention. At block 1702, a TCP capable of configuring an FPGA and a CMU receives first configuration data from a first external storage location via a communication bus. In one example, the first configuration data is FPGA configuration information encoded in an HDL, and is used to program the FPGA to simulate a CMU.

[0106] At block 1706, first configuration data is stored in a first configuration memory for configuring the FPGA to include at least one CMU. In one aspect, the FPGA includes a local flash memory, wherein a portion of the flash memory is allocated to the first configuration memory to store the FPGA configuration data, and another portion of the flash memory is allocated to the second configuration memory to store the CMU configuration data. For example, the local flash memory may store a first bitmap or a first bitstream provided by a first user for configuring the FPGA or CMU configuration data.

[0107] At block 1708, second configuration data including MCU attributes or functions is obtained or received from a second external storage location via the communication bus. In one example, the second configuration data may also be referred to as MCU configuration data. For example, the MCU configuration data may include information related to transmission bandwidth and speed, bidirectional or unidirectional transmission, communication protocol, etc.

[0108] At block 1710, second configuration data is stored in a second configuration memory for programming the CMU. In one aspect, the first stage configuration includes programming the FPGA as an MCU or a CMU via the FPGA configuration data stored in the first configuration memory. After the FPGA is configured as a CMU, the CMU may be further configured by a user. For example, the process may configure the CMU via the MCU configuration data stored in the second configuration memory to perform at least one user-defined MCU function. In one aspect, after identifying the function of the configurable MCU, the process may search or search online for a first bitmap or bitstream to program the CMU to perform the first embedded function using a network interface between a host and an external device based on a first interface protocol. In one embodiment, after downloading the first bitmap from the cloud system to the second configuration memory, programming is performed for the first bitmap.

[0109] It should be noted that the embedded functions include I 2The process can include a first embedded function that is implemented by the CMU and a second bitmap that is associated with the first embedded function to program the CMU. The process can include a first embedded function that is implemented by the CMU and / or a UART interface function to communicate with at least one external device. If the first bitmap fails to verify the first embedded function performed by the CMU, the process can search for a new bitmap associated with the first embedded function to program the CMU. A second function of the CMU is determined, and after using a network interface based on a second interface protocol, the second bitmap is downloaded from the cloud system to a second configuration memory via a communication network. In one aspect, the process continues to configure the CMU until the CMU can perform the user-defined MCU function.

[0110] Although specific embodiments of the present invention have been shown and described, it is apparent that, based on the teachings herein, those skilled in the art may make changes and modifications without departing from the exemplary embodiments of the present invention and its broader aspects. Therefore, the appended claims are intended to include within the scope of the claims all changes and modifications that are consistent with the true spirit and scope of the exemplary embodiments of the present invention.

Claims

1. A method of configuring a field programmable gate array to include a configurable microcontroller by a two-stage configuration process, the method comprising: receiving first configuration data from a first external storage location via the communication bus; storing the first configuration data in a first configuration memory for configuring a field programmable gate array to include a configurable microcontroller; Retrieve second configuration data with microcontroller attributes from a second external storage location via the communication bus; as well as storing the second configuration data in a second configuration memory for programming the configurable microcontroller, Wherein, the method further comprises: identifying a first embedded function of the configurable microcontroller to facilitate a network interface between a host and an external device based on a first interface protocol; and A first bitmap is searched over a communication network for programming the configurable microcontroller to perform the first embedded function.

2. The method according to claim 1, further comprising: The field programmable gate array is programmed by the field programmable gate array configuration data stored in the first configuration memory so that it behaves as a microcontroller, which can be further configured by a user.

3. The method according to claim 2, further comprising: The configurable microcontroller is configured by the microcontroller configuration data stored in the second configuration memory so as to perform at least one user-defined microcontroller function when the field programmable gate array is programmed.

4. The method of claim 1 , wherein the second configuration data comprises a set of predefined programmed microcodes, and the configurable microcontroller facilitates communication between a plurality of input / output ports and one or more external devices via at least one of a plurality of configurable communication standards according to the set of predefined programmed microcodes.

5. The method according to claim 1, further comprising: downloading the first bitmap from the cloud system to the second configuration memory via the communication network using the communication bus; as well as The configurable microcontroller is programmed in response to the first bitmap. The method of claim 5 , further comprising storing the first bitmap in local flash memory.

7. The method according to claim 1, wherein: Identifying the first embedded functionality includes determining an integrated circuit bus interface functionality for communicating with at least one external device.

8. The method according to claim 1, wherein: Identifying the first embedded function includes determining a universal asynchronous receiver-transmitter interface function for communicating with at least one external device.

9. The method according to claim 1, further comprising: If the first bitmap fails to verify the first embedded function executed by the configurable microcontroller, a new bitmap associated with the first embedded function is searched for to program the configurable microcontroller.

10. The method according to claim 5, further comprising: identifying a second embedded function of the configurable microcontroller to facilitate a network interface between the host and the external device based on a second interface protocol; downloading the second bitmap from the cloud system to the second configuration memory via the communication network using the communication bus; as well as The configurable microcontroller is programmed in response to the second bitmap.

11. A programmable logic device, which can be configured to include a configurable microcontroller for processing information, the programmable logic device comprising: Embedded processors that can perform logical functions based on an instruction set; a plurality of configurable logic blocks coupled to the embedded processor and organized by lookup tables that can be programmed to perform user-defined logic functions; a first configuration memory coupled to the plurality of configurable logic blocks and configured to store programmable logic device configuration data for configuring the programmable logic device to include the configurable microcontroller; as well as a second configuration memory coupled to the plurality of configurable logic blocks and configured to store configurable microcontroller configuration data for programming the configurable microcontroller, wherein the configurable microcontroller includes a first embedded function to facilitate a network interface between a host and an external device based on a first interface protocol, and wherein the configurable microcontroller is configured to be programmed to perform the first embedded function in response to a first bitmap searched through a communication network.

12. The programmable logic device according to claim 11, wherein: The plurality of configurable logic blocks are configured as a device of a configurable microcontroller having a plurality of programmable interfaces that facilitate communication between a plurality of input / output ports and one or more external devices via at least one of a plurality of configurable communication standards in accordance with a set of predefined programmed microcodes in the second configuration memory.

13. The programmable logic device according to claim 11 further includes an embedded flash memory, wherein a portion of the embedded flash memory accommodates the first configuration memory for configuring the programmable logic device; and a second portion of the embedded flash memory accommodates the second configuration memory for configuring the configurable microcontroller.

14. The programmable logic device according to claim 11 further includes a static random access memory, a portion of which is configured as the first configuration memory for programmable logic device configuration; and a second portion of the static random access memory is configured as the second configuration memory for configurable microcontroller configuration.

15. The programmable logic device according to claim 11, wherein: The embedded processor includes a hard core that selectively executes instruction sets based on advanced reduced instruction set computers, single-word fixed-point instruction average execution speed, Argonaut RISC core, X86 or Power PC according to processor programmable code.

16. The programmable logic device according to claim 12, wherein: The programmable interface is configured to facilitate communications between the plurality of input / output ports and one or more external devices according to the set of predefined programmed microcodes using an integrated circuit bus.

17. The programmable logic device according to claim 12, wherein: The programmable interface is configured to employ a serial peripheral interface bus protocol to facilitate communications between the plurality of input / output ports and one or more external devices according to an interface programming microcode.

18. The programmable logic device according to claim 12, wherein: The programmable interface is configured to facilitate communication between the plurality of input / output ports and one or more external devices according to an interface programming microcode using a modified integrated circuit bus protocol.

19. The programmable logic device according to claim 12, wherein: The programmable interface is configured to facilitate communication between the plurality of input / output ports and one or more external devices according to an interface programming microcode using one of a universal asynchronous receiver / transmitter, integer, two-wire serial interface, and timer interface protocol.

20. A method of configuring a field programmable gate array to include a configurable microcontroller via a two-stage configuration process, the method comprising: Reading first configuration data from a first configuration memory for configuring a field programmable gate array; configuring the field programmable gate array as one or more microcontrollers according to the first configuration data; After verifying the functionality of the field programmable gate array including the configurable microcontroller, the first stage of configuration is completed; as well as Retrieving second configuration data from a second configuration memory and configuring the configurable microcontroller according to the second configuration data to perform one or more user-defined microcontroller logic functions, Wherein, the method further comprises: identifying a first embedded function of the configurable microcontroller to facilitate a network interface between a host and an external device based on a first interface protocol; and A first bitmap is searched over a communication network for programming the configurable microcontroller to perform the first embedded function.

21. The method of claim 20, further comprising verifying functionality of the configurable microcontroller.

22. The method of claim 21, further comprising completing the second stage configuration after verifying one or more user-defined functions of the configurable microcontroller.

23. The method of claim 20, wherein the second configuration data comprises a set of predefined programmed microcodes, and the configurable microcontroller facilitates communication between a plurality of input / output ports and one or more external devices through at least one of a plurality of configurable communication standards according to the set of predefined programmed microcodes.

24. The method according to claim 20, wherein: Identifying the first embedded functionality includes determining an integrated circuit bus interface functionality for communicating with at least one external device.

25. The method according to claim 20, wherein: Identifying the first embedded functionality includes determining an improved integrated circuit bus interface functionality for communicating with at least one external device.

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