System and method for representing the layout of an integrated circuit

Abstract

The present application relates to systems and methods for representing the layout of an integrated circuit. An embodiment provides a method for representing the layout of an integrated circuit. In an example embodiment, a method includes determining a plurality of regions of an integrated circuit IC layout design based on one or more parameters. In an embodiment, at least one region of the plurality of regions has a certain characteristic. The example method further includes determining a plurality of regions associated with the plurality of regions. Each region of the plurality of regions has a characteristic of one region of the plurality of regions.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 976,245, filed on February 13, 2020, entitled “SYSTEMS AND METHODS FOR CONTINUOUS GLOBAL REPRESENTATION OF LOCAL DATA USING EFFECTIVE AREAS IN AN INTEGRATEDCIRCUIT LAYOUT,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates generally to integrated circuit fabrication, and more particularly to continuous global representation of local data using active areas in an integrated circuit layout. Background Art

[0004] In integrated circuit manufacturing technology, some parameters (e.g., the thickness of a planar dielectric) vary significantly across an integrated circuit layout. However, the rules used to generate parameter values ​​often depend on parameters that are not clearly defined throughout the integrated circuit layout. Even in the case where the parameters are clearly defined, the parameters may not necessarily be continuous across regions of the integrated circuit layout. Summary of the invention

[0005] In some embodiments, a method for representing a layout of an integrated circuit is provided. In some embodiments, the method includes determining a plurality of regions of an integrated circuit (IC) layout design based on one or more parameters, at least one region having a certain characteristic. In some embodiments, the method further includes determining a plurality of regions, wherein each region of the plurality of regions has a characteristic of one of the plurality of regions. In some embodiments, the method further includes assigning a first value to a location of the IC layout design outside the plurality of regions, and assigning a second value to a location of the IC layout design within the plurality of regions. In some embodiments, the method further includes; in response to determining that a location of the IC layout design is located in two or more overlapping regions of the plurality of regions, determining a generated value associated with the location based at least in part on the values ​​of the two or more overlapping regions of the plurality of regions. In some embodiments, the method further includes using a processor to generate an integrated circuit (IC) representation of the IC layout design based at least in part on the first value, the second value, and the generated value.

[0006] In some embodiments, the generated value determined based at least in part on the values ​​of the two or more overlapping regions of the plurality of regions comprises a weighted average of the values ​​of the two or more overlapping regions of the plurality of regions.

[0007] In some embodiments, the plurality of regions include one or more of a plurality of points of an integrated circuit (IC) representation, a plurality of line segments of an integrated circuit (IC) representation, or a plurality of contiguous regions of an integrated circuit (IC) representation.

[0008] In some embodiments, determining the plurality of regions comprises: for each adjacent region as a region, determining the adjacent region by sweeping the adjacent region in the x-direction and the y-direction, wherein the adjacent region has a first length and a first width. In some embodiments, determining the plurality of regions further comprises: for each line segment as a region, determining a rectangle by sweeping the line segment in the x-direction and the y-direction, wherein the rectangle has a second length and a second width. In some embodiments, determining the plurality of regions further comprises: for each point as a region, determining a line by sweeping the point in one of the x-direction or the y-direction, wherein the line has a third length.

[0009] In some embodiments, one or more of the first length, the second length, or the third length is determined based at least in part on a portion x1 of the length of the corresponding region, where x1>0.

[0010] In some embodiments, one or more of the first width or the second width is determined based at least in part on a portion x2 of the width of the corresponding region, where x2>0.

[0011] In some embodiments, one or more of the first length, the second length, the third length, the first width, or the second width is determined based at least in part on a maximum distance, wherein the maximum distance is a constant.

[0012] In some embodiments, one or more of the first length, the second length, the third length, the first width, or the second width is determined based at least in part on a portion x3 of the length of the corresponding region, where x3>0.

[0013] In some embodiments, one or more of the first length, the second length, the third length, the first width, or the second width is determined based at least in part on a portion x4 of the width of the corresponding region, where x4>0. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present disclosure will be more fully understood according to the detailed description given below and the drawings of the embodiments of the present disclosure. The drawings are used to provide an understanding and understanding of the embodiments of the present disclosure, and the scope of the present disclosure is not limited to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0015] Figure 1 is a flow chart illustrating an example for determining a continuous global representation of local data using valid regions in an integrated circuit layout according to some embodiments.

[0016] Figure 2 is a flow chart illustrating an example for determining a plurality of regions associated with the plurality of zones according to some embodiments.

[0017] Figure 3A , 3B 3C and 3C show example integrated circuit layouts according to some embodiments.

[0018] Figure 4A , 4B 4C illustrate example subsets of multiple regions according to some embodiments.

[0019] Figure 5A , 5B , 5C and 5D show example subsets and global representations of multiple regions according to some embodiments.

[0020] Figure 6 Flowcharts depicting various processes used during the design and fabrication of integrated circuits according to some embodiments of the present disclosure.

[0021] Figure 7 A diagram depicting an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0022] Aspects of the present disclosure relate to continuous global representation of local data using active areas in an integrated circuit layout.

[0023] Integrated circuit (IC) layout involves the representation (e.g., or modeling) of an integrated circuit in terms of the components that make up the IC, and the components depend on the properties of the metal, oxide, or semiconductor layers that make up the components. IC layout places and connects the components that make up the IC so that they meet specific criteria (e.g., performance, size, density, manufacturability, etc.), and the ability of the components to meet the specific criteria depends on parameters or local values ​​associated with the characteristics of the components (e.g., some of which may not be explicitly defined, measured, or understood).

[0024] In multi-dimensional (e.g., three-dimensional (3D)) integrated circuit modeling, some global effects may be characterized in terms of local parameters (e.g., local data). Local parameters may be explicitly defined only at specific points or regions within a given integrated circuit (IC) layout, and local parameters may not be explicitly defined at many locations of the IC layout. In this document, a parameter may be considered to be explicitly defined when it is clear, constant, or known (e.g., as may also be understood with reference to the figures described herein). For example, the width of a polygon may be explicitly defined at a point on its perimeter as the vertical distance inward from the edge until the perimeter is encountered again. In such an example, the width of the polygon may be considered to be explicitly defined at the point, but may be considered not to be explicitly defined at other points. Furthermore, local parameters may be discontinuous in that different values ​​may be associated with adjacent locations where the local parameter values ​​are actually explicitly defined.

[0025] As used herein, local parameters refer to parameters of a layout that are only clearly defined at specific points or regions within an IC layout and are not defined or poorly defined at the rest of the layout. Local data refers to local parameters and functions of local parameters. As used herein, a uniform local region may refer to a point, line segment, or contiguous region of an IC layout having uniform local parameters. In some embodiments, the local parameters may not be uniform, but an average value of the local parameters may be used.

[0026] As used herein, an area of ​​influence refers to an area associated with a uniform local region. In a tiled global representation according to embodiments herein, a global data value (e.g., such as the thickness of a dielectric layer) may be assigned to any region. A continuous global representation is defined at all locations and is continuous (e.g., smooth). A continuous global representation based on local data should represent the actual fabricated structure.

[0027] In multi-dimensional (e.g., 3D) integrated circuit modeling, it may be preferred that global effects (e.g., derived values, such as thickness) are well defined throughout the layout and that the global effects are smooth or continuous. In an embodiment, a global effect may be considered smooth or continuous when a value associated with a particular defined region gradually transitions (e.g., as opposed to abruptly transitioning) from a first region with a particular defined parameter adjacent to a second region with the particular defined parameter, where the particular defined parameter differs from the first region to the second region. In some embodiments, smooth or continuous may refer to the difference in value between two points approaching zero as the distance between the two points approaches zero.

[0028] In various examples, the thickness of a dielectric layer associated with a particular IC layout may be described in terms of a function of the width and spacing of lines in an interconnect layer. In such examples, the dielectric layer requires a thickness that is a smooth function of position, whereas the width and spacing of the interconnect layer may not be well defined throughout the IC layout.

[0029] Embodiments herein overcome the aforementioned disadvantages by implementing a method (e.g., sometimes referred to herein as an effective region method) by which a continuous global representation of values ​​across an IC layout that depends on local data (e.g., local parameters associated with various locations of the IC layout) is generated. In an embodiment, a tiled global representation is generated from an effective region associated with each region of the layout having uniform and well-defined parameter values. As mentioned herein, an effective region may include multiple locations of an IC layout to which values ​​(e.g., predefined values) may be applied (e.g., multiple locations of an IC layout may be considered to be within a defined effective region). That is, an effective region may include multiple locations of an IC layout to which a particular set of local parameters may be assigned (e.g., in place of actual parameters associated with the locations). In this way, a continuous global representation has uniform and defined parameter values.

[0030] Embodiments herein use regions of influence to establish a global representation of local data. That is, a tiled global representation of an IC layout. Regions of influence are generated to represent each uniform region of the tiled global representation. Nominal data values ​​for a particular parameter of interest are assigned to any location that is not in any region of influence. In an embodiment, the nominal value may be a value associated with a location of the IC layout that is not near a region of influence (e.g., a region for which the value associated with the particular parameter of interest does not exist or is not known). Any location in a single region of influence is assigned the data value of the region of influence (e.g., for a particular parameter of interest).

[0031] In various embodiments, areas common to multiple active regions (e.g., or one or more locations of an integrated circuit layout) may be assigned data values ​​determined based on overlapping active regions. In embodiments, areas not covered by any active region may be assigned nominal data values. In various embodiments, region-based averaging or other techniques may be used to create a smooth global representation.

[0032] Figure 11 is a flow chart illustrating an example 100 for determining a continuous global representation of local data using a valid area in an integrated circuit layout according to some embodiments. In some embodiments, the current system may determine multiple (e.g., a plurality of) regions of an IC layout design based on one or more parameters at 101, at least one of the regions having a certain characteristic. In some embodiments, the one or more parameters include parameters of the integrated circuit layout design that are well-defined and continuous within at least a certain region on the integrated circuit layout design. In some embodiments, the local data includes parameters and functions of parameters (e.g., thickness, which may be a function of parameter width W and parameter spacing S). In certain embodiments, where the local data is poorly defined, the local function is poorly defined. Furthermore, where the local data is discontinuous, the local function is discontinuous.

[0033] Figures 3A-3C is an example integrated circuit layout according to some embodiments. Figure 3C As shown, the spacing within the interconnect is not clearly defined. As an example, the width between two adjacent interconnects (e.g., within the spacing) is not clearly defined. As another example, where the interconnect is non-uniform along the height of the interconnect, the width of the interconnect is discontinuous. In some embodiments, local data and parameters are not clearly defined. In some embodiments, the parameters include parameters of the integrated circuit layout that are only clearly defined at specific points or regions within the integrated circuit layout. Therefore, in some embodiments, the parameters are not defined at the rest of the integrated circuit layout. Alternatively, in some embodiments, the parameters are poorly defined at the rest of the integrated circuit layout. In some embodiments, the parameters include the local width W and local spacing S of the interconnect layer. In some embodiments, the width and spacing are only clearly defined at points on the perimeter of the shape, where the vertical direction is clearly defined. It should be understood that Figures 3A-3C The shaded areas in represent regions of the IC layout for which width and spacing are not defined (eg, there are no W or S, and no active areas are applied to those regions).

[0034] like Figure 3B As shown, a segment of the perimeter (e.g., the edge of an interconnect) is uniform, wherein the segment of the perimeter has a uniform width and spacing. In some embodiments, a segment of the outline of a polygon (in the y direction) has uniform values ​​for width and spacing. In some embodiments, a uniform segment comprises the edge of a polygon, or a portion of the edge of a polygon that has the same width and spacing along the entire length of the polygon. In some embodiments, different portions of the perimeter of a polygon may have different width and spacing values. In some embodiments, a zone is defined as a point with uniform parameters. Alternatively, in some embodiments, a zone is defined as a line segment with uniform parameters. In some embodiments, a zone is defined as an adjacent area with uniform parameters.

[0035] Return to Figure 1 In some embodiments, at 102, the present system determines a plurality of regions (eg, influence regions as discussed above) associated with corresponding regions of the plurality of regions. Figures 4A-4C Examples of multiple regions according to some embodiments are shown. Multiple regions may be associated with a zone. As a non-limiting example, for a point, the multiple regions are zones containing the point. As another non-limiting example, for a line segment with a uniform parameter, the multiple regions are zones containing the line segment. As yet another non-limiting example, for an adjacent region with a uniform parameter, the multiple regions contain the adjacent region. The multiple regions associated with a zone have the same parameter value as the associated zone. The relationship between the zone and the multiple regions may depend on any one of a variety of factors. In some embodiments, the relationship between the zone and the multiple regions may be based on theoretical considerations comprising at least one of the following: a parameter, a function of a parameter, or a function of a position. Figure 4A Multiple regions of a point based on the density at the point are shown. Figure 4B Multiple regions of the segment based on distances, such as -W / 2 and +S / 2, are shown. Figure 4C Multiple regions based on the area of ​​the bounding box are shown.

[0036] Figure 3A is an example integrated circuit layout according to some embodiments. In some embodiments, a ratio of W to S (W / S) is used as a parameter. The W / S ratio is based on a uniform line segment (e.g., relative to width and spacing). In some embodiments, the W / S ratio is constructed based on the outline of a polygon. In addition, in some embodiments, a specific subset of multiple regions is determined. The specific subset of multiple regions may include a rectangle with a width that matches the line segment. It should be understood that a rectangle is only a non-limiting example for describing the embodiments herein, and any shape or size of the region is within the scope of the present disclosure. It should also be understood that the location of the integrated circuit design may also be referred to herein as (but not limited to) a point of the design.

[0037] In some embodiments, a subset of a plurality of regions is extended to include more contours than a uniform segment. In some embodiments, a subset of a plurality of regions is generated from a uniform region. In some embodiments, a subset of a plurality of regions has a different dimension than a uniform region (e.g., a point, a line segment, a region). A 3D physical representation of an integrated circuit layout requires a smooth function to achieve an accurate and self-consistent analysis. As a non-limiting example, the thickness of a dielectric layer should be defined at all locations throughout the integrated circuit layout. In addition, the thickness should be generally continuous (e.g., smooth) to avoid non-physical situations. Therefore, the function is defined as a continuous global representation.

[0038] like Figure 3AAs shown, the thickness of the dielectric (e.g., thk) is a function of W and S. In the case where the thickness thk of the dielectric layer is a function of the width W and the spacing S of the interconnect layer (e.g., the shaded area), the thickness thk is poorly defined at any location where W or S is poorly defined. For example, where the spacing S is zero (e.g., at one end of the integrated circuit layout), the thickness is undefined.

[0039] Return to Figure 3C , for a uniform line segment based on a polygonal outline, a subset of the plurality of regions may be a rectangle defined by sweeping the line segment. In some embodiments, a uniform edge parallel to the x-axis is swept in the y-direction, and a uniform edge parallel to the y-axis is swept in the x-direction. The distances swept in the x- and y-directions may depend on local factors such as the values ​​of W and S. As an example, for the W / S ratio, distances -W / 2 and +S / 2 may be used. The negative sign indicates a direction toward the interior of the polygon. The positive sign indicates a direction away from the polygon. In addition, in some embodiments, the maximum distance out may be reduced to a constant, or to a value that is a function of W or other parameters, to limit a subset of the plurality of regions to an edge toward the outside of the integrated circuit layout (e.g., where the spacing is infinite).

[0040] Figure 2200 is a flowchart showing an example of determining a plurality of regions associated with the plurality of regions according to some embodiments. In an embodiment, the current system determines a second adjacent region (e.g., region) by sweeping a first adjacent region in the x-direction and the y-direction at 201. The current system may determine the second adjacent region as a region for each adjacent region. In some embodiments, the second adjacent region has a first length and a first width. In an embodiment, the current system determines a rectangle (e.g., region) by sweeping a line segment in the x-direction and the y-direction at 202. The current system may determine the rectangle as a region for each line segment. In some embodiments, the rectangle has a first length and a first width. In an embodiment, the current system determines a line (e.g., region) by sweeping a point in one of the x-direction or the y-direction at 203. In some embodiments, the line has a third length. The current system may determine the line as a region for each point. In some embodiments, one or more of the first length, the second length, and the third length are determined based at least in part on a portion x1 of the length of the corresponding region, wherein x1>0. In some embodiments, one or more of the first width and the second width is determined based at least in part on a portion x2 of the width of the corresponding region, where x2>0. Alternatively, in some embodiments, one or more of the first length, the second length, the third length, the first width, and the second width is determined based at least in part on a maximum distance, where the maximum distance is a constant. In some embodiments, one or more of the first length, the second length, the third length, the first width, and the second width is determined based at least in part on a portion x3 of the length of the corresponding region, where x3>0. In some embodiments, one or more of the first length, the second length, the third length, the first width, and the second width is determined based at least in part on a portion x4 of the width of the corresponding region, where x4>0.

[0041] Return to Figure 1 In an embodiment, the current system assigns a nominal data value to each point of the integrated circuit layout in a location outside the plurality of regions at 103. In an embodiment, the current system assigns a data value associated with the plurality of regions to each point of the integrated circuit layout located in the plurality of regions at 104. In an embodiment, the current system, in response to determining that a point of the integrated circuit layout is located in two or more overlapping plurality of regions, assigns to the point a value determined at least in part based on a data value of each of the two or more overlapping plurality of regions at 105.

[0042] In an embodiment, the global effect is a derived value, such as thickness. The global effect is preferably clearly defined everywhere within the integrated circuit layout or design, and should be continuous (e.g., smooth). In an embodiment, in 3D integrated circuit modeling, some global effects are characterized by parameters (e.g., local data). The parameters are only clearly defined at specific points or regions within the integrated circuit layout. The parameters are not clearly defined at many locations of the integrated circuit layout. In some embodiments, the parameters may be discontinuous. For example, although the parameters are clearly defined in adjacent locations, the parameters may have different values ​​at the adjacent locations. For example, the thickness of a dielectric layer can be described as a function of the width and spacing of the lines in the associated interconnect layer. The dielectric layer requires thickness as a smooth function of position. However, because the width and spacing of the interconnect layer are not clearly defined everywhere, neither is a function of width and spacing.

[0043] Continue to refer Figure 1 In an embodiment, the current system generates an integrated circuit (IC) representation based at least in part on the aforementioned first plurality of values, the second plurality of values, and the generated values ​​at 106. That is, in some examples, a model of the integrated circuit design may be generated using parameters based on physical properties defined according to the first plurality of values, the second plurality of values, and the generated values. In an embodiment, generating an IC representation of an integrated circuit may include parasitic extraction, general IC layout analysis, physical modeling of IC layout, capacitance extraction, thermal modeling, lithography effect analysis, generation of compact device models, design rule generation, metal migration, interface resistance analysis, etc.

[0044] Figures 5A-5D An example subset and global representation of multiple regions according to some embodiments are shown. In some embodiments, the W / S ratio is restricted to a Manhattan shape. In a Manhattan shape, each edge is parallel to the x or y axis. In some embodiments, other angles may be handled by a step approach. For example, the step approach may include replacing diagonals by steps of horizontal and vertical lines. Alternatively, in some embodiments, a hybrid approach (e.g., a combination of step and Manhattan approaches; for example, or using non-Manhattan valid regions) may be used to handle other angles. In some embodiments, the W / S ratio has two categories of multiple regions: one category of multiple regions oriented along the x direction, and one category of multiple regions oriented along the y direction. Figure 5A Display cut to constant maximum value S MAX Multiple regions oriented along the x-direction (e.g., based on a uniform segment in the y-direction, and by using values ​​of -W / 2 (in) and +S / 2 (out)). Figure 5BMultiple regions oriented in the y direction are shown. In some embodiments where -W / 2 and +S / 2 are used, the current system generates a tiled description of all regions close to the polygon. The lateral direction of the integrated circuit design or layout along the x direction of any polygon in S MAX The region within is tiled by the union of subsets of the multiple regions oriented along the x-direction. No region is covered by multiple regions oriented along the x-direction. Similar behavior occurs for multiple regions oriented along the y-direction.

[0045] In some embodiments, intersection points of the plurality of regions have associated values ​​for the parameters and functions of the parameters. Figure 5C One such intersection point between a plurality of regions oriented in the x-direction (e.g., A_L2) and a plurality of regions oriented in the y-direction (e.g., A_T1) is shown. In some embodiments, any suitable method may be used to resolve the deviation created by the intersection point. In some embodiments, a weighted average method is used. In these embodiments, a weight of 1 / Δ is used, where Δ is the width of the plurality of regions from an associated uniform edge (e.g., a value of W / 2 or S / 2 for a uniform edge). For parameter P A_L2 and P A_T1 , the average value can be [P A_L2 / Δ A_L2 +P A_T1 / Δ A_T1 ] / [1 / Δ A_L2 +1 / Δ A_T1 In some embodiments, a weight of 1 / Δ is used. 2 Alternatively, in some embodiments, the value with the smallest value Δ is used.

[0046] Figure 5D An example tiled global representation is shown. In the tiled global representation, all regions are assigned global data values, such as the thickness of a dielectric layer. In some embodiments, the nominal region includes all regions that are not in any subset of the plurality of regions. In such embodiments, the nominal region is assigned a nominal value. Figure 5D In some embodiments, a region within a single subset of the plurality of regions is assigned a value associated with a local region. Figure 5D In some embodiments, uniform edges are shown as regions within a single subset of the plurality of regions. In some embodiments, regions that are intersections of the plurality of subsets of the plurality of regions are assigned analytical values ​​based on parameters or functions of those parameters. In some embodiments, the tiled global representation is a discontinuous global function.

[0047] The representation of the layout (e.g., a tiled global representation) is a function that is well defined everywhere, but may change abruptly across interfaces or intersections between zones. In some embodiments, a continuous global function is derived from a discontinuous global function by finding the zone-based average at any point. In some embodiments, the zone-based average at position (x, y) is found by considering each zone (e.g., zone i) within a square averaging window centered at (x, y). When the nominal value is 0, the zone-based average may be given by the following equation (1):

[0048]

[0049] Where Ai is the area of ​​the interaction region i within the window, Fi is the associated function value (e.g., a value assigned to a given point that may be a function of a parameter), and Awindow is the area of ​​the average window. In some embodiments, for a non-zero nominal value Fnom, the following equation (2) may be used.

[0050]

[0051] Multiple windows of different sizes may be used. In some embodiments, the final result is a weighted average with the same or different weights. For example,

[0052] F=50%*F window1 +30%*F window2 +20%*F window3 (3)

[0053] For example, the choice of weights associated with the weighted average depends on the associated function. As a non-limiting example, if the thickness depends on the closest edge, averaging two thickness values ​​may be stronger when the edges are closer. In an embodiment, the averaging function may be defined according to the following equation (4).

[0054]

[0055] In an embodiment, the averaging function may be defined according to the following equation (5).

[0056]

[0057] Where k is a certain number.

[0058] In some embodiments, a mapping is generated by finding the value of a continuous global function of a point on a grid. In order to evaluate the global function at a point between grid points, interpolation is performed in the x direction and in the y direction. In some embodiments, a global representation of local data is established using a subset of multiple regions. In these embodiments, a tiled global representation is first created. A subset of multiple regions is generated to represent each uniform region. A nominal data value is assigned to any position that is not in any subset of multiple regions, and a data value of the subset of multiple regions is assigned to any position in a single subset of multiple regions. Similarly, a data value is assigned to any position in multiple subsets of multiple regions based on the value of each overlapping subset of parsed multiple regions. Finally, a smooth global representation of local data can be created using any of a variety of region-based averaging techniques. In one embodiment, the local data includes a width and spacing defined on the perimeter of an interconnected layer shape. Each uniform line segment is represented by a rectangle extending from halfway inside the shape to halfway toward the nearest external shape.

[0059] Figure 6 A set of example processes 700 for transforming and verifying design data and instructions representing an integrated circuit used during the design, verification, and manufacture of an article such as an integrated circuit are shown. Each of these processes can be constructed and implemented as multiple modules or operations. The term "EDA" stands for the term "electronic design automation". These processes begin with creating a product concept 710 with information supplied by a designer, which is transformed to create an article using a set of EDA processes 712. When the design is complete, the design is taped out 734, at which time the work (e.g., geometric pattern) of the integrated circuit is sent to a manufacturing facility to manufacture a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor die are manufactured 736, and packaging and assembly processes 738 are performed to produce a finished integrated circuit 740.

[0060] The specification of a circuit or electronic structure can vary from a low-level transistor material layout to a high-level description language. The high-level representation can be used to design circuits and systems using a hardware description language ("HDL") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be transformed into a logic level register transfer level ("RTL") description, a gate level description, a layout level description, or a mask level description. Each lower level of representation as a more detailed description adds more useful details to the design description, such as more details of the modules that contain the description. The lower level representation as a more detailed description can be computer generated, derived from a design library, or created by another design automation process. An example of a specification language at a lower level representation language for specifying a more detailed description is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each representation level is enabled for use by the corresponding tools (e.g., formal verification tools) at that layer. The design process can use Figure 6 The sequence depicted in . The described process is enabled by an EDA product (or tool).

[0061] During system design 714, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or code line), and cost reduction. Partitioning the design into different types of modules or components can be done at this stage.

[0062] During logic design and functional verification 716, modules or components in a circuit are specified in one or more description languages ​​and the functional accuracy of the specifications is checked. For example, the components of the circuit can be checked to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification can use simulators and other programs, such as test bench generators, static HDL checkers, and formal checkers. In some embodiments, special systems of components called "emulators" or "prototyping systems" are used to accelerate functional verification.

[0063] During synthesis and test design 718, the HDL code is transformed into a netlist. In some embodiments, the netlist can be a curved structure where the edges of the curved structure represent components of the circuit and where the nodes of the curved structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that the integrated circuit works according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, the finished integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0064] During netlist verification 720, the netlist is checked for compatibility with timing constraints and correspondence with the HDL code. During design planning 722, the overall floor plan of the integrated circuit is constructed and analyzed for timing and top-level placement.

[0065] During layout or physical implementation 724, physical placement (e.g., positioning of circuit components such as transistors or capacitors) and layout (connection of circuit components by multiple conductors) are performed, and selection of cells from a library to enable specific logic functions may be performed. As used herein, the term "cell" may specify a group of transistors, other components, and interconnects that provide a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (e.g., a flip-flop or latch). As used herein, a circuit "block" may refer to two or more cells. Both cells and circuit blocks may be referred to as modules or components, and are enabled as both physical and analog structures. Parameters such as size are specified for the selected cell (based on a "standard cell"), and the parameters are made accessible in a database for use by the EDA product.

[0066] During analysis and extraction 726, circuit functionality is verified at the layout level, which permits improvements to the layout design. During physical verification 728, the layout design is checked to ensure that manufacturing constraints such as DRC constraints, electrical constraints, lithography constraints, etc. are correct and that the circuit system functionality matches the HDL design specifications. During resolution enhancement 730, the geometry of the layout is transformed to improve how the circuit design is manufactured.

[0067] During tape-out, data is created for use in producing lithography masks (after applying lithography enhancements where appropriate).During mask data preparation 732, the "tape-out" data is used to generate lithography masks for use in producing finished integrated circuits.

[0068] Computer systems (e.g. Figure 7 The storage subsystem of the computer system 900) may be used to store programs and data structures used by some or all of the EDA products described herein and products for developing libraries and units of physical and logical design that use the libraries.

[0069] Figure 7 An example machine of computer system 900 is shown within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment as a peer machine in a peer-to-peer (or distributed) network environment or as a server or a client machine in a cloud computing infrastructure or environment.

[0070] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0071] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 918, which communicate with each other via a bus 930.

[0072] The processing device 902 represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 902 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 902 may be configured to execute instructions 926 for performing the operations and steps described herein.

[0073] The computer system 900 may further include a network interface device 908 to communicate over a network 920. The computer system 900 may also include a video display unit 910 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), a graphics processing unit 922, a signal generating device 916 (e.g., a speaker), a graphics processing unit 922, a video processing unit 928, and an audio processing unit 932.

[0074] The data storage device 918 may include a machine-readable storage medium 924 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 926 or software embodying any one or more of the methods or functions described herein. The instructions 926 may also reside, completely or at least partially, within the main memory 904 and / or within the processing device 902 during execution thereof by the computer system 900, the main memory 904 and the processing device 902 also constituting machine-readable storage media.

[0075] In some embodiments, the instructions 926 include instructions that implement functionality corresponding to the present disclosure. Although the machine-readable storage medium 924 is shown as a single medium in the example embodiments, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing the one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding an instruction set for machine execution and causing the machine and processing device 902 to perform any one or more methods of the present disclosure. The term "machine-readable storage medium" should accordingly be considered to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0076] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations that produce a desired result. Operations are those that require physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0077] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specifically stated as apparent from the present disclosure, it should be understood that throughout the description, specific terms refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0078] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0079] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. In addition, the present disclosure is described without reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0080] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0081] In the above disclosure, the embodiments of the present disclosure have been described with reference to their specific example embodiments. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure set forth in the appended claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the drawings, and similar elements are marked with similar reference numerals. Therefore, the present disclosure and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method for representing a layout of an integrated circuit, the method comprising: determining a plurality of regions of the integrated circuit IC layout design based on one or more parameters, at least one region of the plurality of regions having a certain characteristic; determining a plurality of regions, each region of the plurality of regions having a characteristic of one of the plurality of regions; assigning a first plurality of values ​​to locations of the IC layout design outside of the plurality of regions; assigning a second plurality of values ​​to locations within the plurality of regions of the IC layout design; In response to determining that the location of the IC layout design is located in two or more overlapping regions of the plurality of regions, determining a value associated with the location based on the second plurality of values ​​in each of the two or more overlapping regions; as well as An integrated circuit (IC) representation of the IC layout design is generated, using a processor, based at least in part on the first plurality of values, the second plurality of values, and the value. 2 . The method of claim 1 , wherein the generated value determined based on the second plurality of values ​​of the two or more overlapping regions comprises a weighted average of each of the values ​​of the two or more overlapping regions. 3 . The method of claim 1 , wherein the plurality of regions comprises one or more of a plurality of points represented by the integrated circuit IC, a plurality of line segments represented by the integrated circuit IC, or a plurality of contiguous regions represented by the integrated circuit IC.

4. The method of claim 1, wherein the determining the plurality of regions comprises: For each adjacent area as a zone, determining a contiguous region by sweeping the contiguous region in an x-direction and a y-direction, wherein the contiguous region has a first length and a first width; For each line segment as a region, determining a rectangle by sweeping the line segment in the x-direction and the y-direction, wherein the rectangle has a second length and a second width; as well as For each point as a zone, A line is determined by sweeping the points in one of the x-direction or the y-direction, wherein the line has a third length. 5 . The method of claim 4 , wherein one or more of the first length, the second length, or the third length is determined based at least in part on a portion x1 of a length of a corresponding region, where x1>0. 6 . The method of claim 4 , wherein one or more of the first width or the second width is determined based at least in part on a portion x2 of a width of a corresponding region, where x2>0.

7. The method of claim 4, wherein one or more of the first length, the second length, the third length, the first width, or the second width is determined based at least in part on a maximum distance, wherein the maximum distance is a constant.

8. The method of claim 4, wherein one or more of the first length, the second length, the third length, the first width, or the second width is determined at least in part based on a portion x3 of the length of a corresponding region, wherein x3>0.

9. The method of claim 4, wherein one or more of the first length, the second length, the third length, the first width, or the second width is determined at least in part based on a portion x4 of a width of a corresponding region, wherein x4>0.

10. An electronic system comprising: a memory storing instructions; as well as a processor coupled to the memory and executing instructions that, when executed, cause the processor to: determining a plurality of regions of the integrated circuit IC layout design based on one or more parameters, at least one region of the plurality of regions having a certain characteristic; determining a plurality of regions, each region of the plurality of regions having a characteristic of one of the plurality of regions; assigning a first plurality of values ​​to locations of the IC layout design outside of the plurality of regions; assigning a second plurality of values ​​to locations within the plurality of regions of the IC layout design; In response to determining that the location of the IC layout design is located in two or more overlapping regions of the plurality of regions, determining a value associated with the location based on the second plurality of values ​​in each of the two or more overlapping regions; as well as An integrated circuit (IC) representation of the IC layout design is generated based at least in part on the first plurality of values, the second plurality of values, and the value.

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