Device with latching balancing mechanism and method of operating the same

Abstract

The present application relates to a device with a latch balancing mechanism and an operating method thereof. Methods, devices and systems related to a storage device are described. The storage device may include a local latch circuit, each of which has a holding circuit and a drive circuit. The holding circuit may be configured to provide local storage of broadcast information for downstream circuits. The drive circuit may be configured to connect a first voltage and a second voltage to the holding circuit at different times for broadcast and local storage.

Description

Technical Field

[0001] The disclosed embodiments relate to devices, and in particular, to semiconductor memory devices having a latch balancing mechanism and methods of operating the same. Background Art

[0002] An apparatus (e.g., a processor, a memory system, and / or other electronic device) may include one or more semiconductor circuits configured to store and / or process information. For example, the apparatus may include a storage device, such as a volatile storage device, a non-volatile storage device, or a combination. Storage devices such as dynamic random access memory (DRAM) utilize electromagnetic energy to store and access data.

[0003] Technological improvements are usually associated with reducing the physical size of the device and / or the circuit therein. However, reducing the physical size often brings new or other challenges. For example, some storage devices contain predetermined information (e.g., fault / repair information, device identifier, etc.), which is stored in a non-volatile memory (e.g., a fuse) and is broadcast to the circuit / part in the storage device after a specified event (e.g., a power-on or reset event). Various circuits / parts in the storage device include a set of fuse latches, which are configured to load and / or store the broadcasted information locally. Although it may be desirable to reduce the size / coverage of each latch, this reduction reduces the driving capability for loading and / or accessing information related to the latch. Therefore, the amount of charge required to change the state of the latch (e.g., latch voltage level) is reduced, which leads to an increase in data errors (e.g., a soft error rate (SER) caused by a change in latched data). Summary of the invention

[0004] The present invention relates to an apparatus having a latching balancing mechanism and a method of operating the same.

[0005] In some embodiments of the present invention, a device includes: a holding circuit configured to provide local storage of information for accessing a circuit; a load circuit coupled to the holding circuit and configured to load the information into the holding circuit during a fuse broadcast phase; and a drive portion coupled to the holding circuit and configured to connect a first voltage and a second voltage to the holding circuit at different times for the load and the local storage.

[0006] In some embodiments of the present invention, a method of operating a device includes: receiving broadcast information at a load circuit during a fuse broadcast phase; transmitting the broadcast information or a portion thereof from the load circuit to a holding circuit during a loading phase; storing the broadcast information or the portion thereof in the holding circuit for later access after the fuse broadcast phase; connecting the holding circuit to a first voltage during the fuse broadcast phase; and connecting the holding circuit to a second voltage after the fuse broadcast phase, wherein the second voltage is greater than the first voltage.

[0007] In some embodiments of the present invention, a method of manufacturing a device includes: providing a holding circuit, the holding circuit being configured to provide local storage of information for accessing a circuit; connecting a load circuit to the holding circuit, wherein the load circuit is configured to transmit the information to the holding circuit during a fuse broadcast phase; and forming a drive circuit, the drive circuit being coupled to the holding circuit and configured to connect a first voltage and a second voltage to the holding circuit at different times of the load and the local storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a device according to an embodiment of the present technology.

[0009] Figure 2 is a timing diagram of broadcasting according to an embodiment of the present technology.

[0010] Figure 3A is a schematic block diagram of a first example balancing mechanism according to an embodiment of the present technology.

[0011] Figure 3B is an example connection of the drive portion of the balancing mechanism according to an embodiment of the present technology.

[0012] Figure 4 is a timing diagram of a balancing mechanism according to an embodiment of the present technology.

[0013] Figure 5 is a schematic block diagram of a second example balancing mechanism according to an embodiment of the present technology.

[0014] Figure 6 is a schematic block diagram of a third example balancing mechanism according to an embodiment of the present technology.

[0015] Fig. 7A is a flow chart illustrating an example method of operating a device in accordance with embodiments of the present technology.

[0016] Figure 7B is a flow chart illustrating an example method of manufacturing a device according to embodiments of the present technology.

[0017] Figure 8is a schematic diagram of a system including devices according to embodiments of the present technology. DETAILED DESCRIPTION

[0018] As described in more detail below, the technology disclosed herein relates to an apparatus for locally latching received data, such as for use in a storage system, a system having a storage device, related methods, etc. The apparatus (e.g., a storage device and / or a system including the storage device) may include a latch circuit configured to locally store received or transmitted data.

[0019] Fuse latch circuits are often associated with soft errors that result in uncorrectable error correction code (UECC) errors corresponding to time failure (FIT) measurements. Soft errors associated with fuse latch circuits may be caused by insufficient drive capability (e.g., the ability to load data into a latch and / or access data from a latch) and / or unexpected changes in latch states due to external influences (e.g., neutron strikes and / or hammer effects on transistors). Therefore, the FIT measurement may be directly proportional to the N+ area associated with the transistor size and / or inversely proportional to the critical charge (Qcrit) associated with the latch. The critical charge may be a measure of drive capability that corresponds to the amount of charge required to change the state of the fuse latch. In other words, larger transistors in a fuse latch circuit are more likely to receive neutron strikes, while smaller transistors may have less drive capability.

[0020] As described in detail below, the device may include a latch circuit having a balancing mechanism configured to increase the ratio between the N+ region and the Qcrit measurement. In some embodiments, the balancing mechanism may include a drive circuit configured to control a bias voltage of one or more transistors in the storage portion. The drive circuit may set the bias voltage to a first level to latch a bit, initially float the bias voltage after latching the bit, and / or set the bias voltage to a second level greater than the first level. Therefore, by floating the bias voltage and / or driving the bias voltage to a second level, the drive circuit may increase the critical charge of the latch circuit without increasing the N+ region. The increase in critical charge may result in a reduced error rate.

[0021] Additionally or alternatively, the balancing mechanism may include a mirrored latch configuration that connects the first latch and the second latch in a mirrored configuration. One of the connected latches may be an unused latch that has been reconfigured via the mirrored latch configuration. Thus, a previously unused latch may latch the same information as the mirrored latch, which may effectively increase the N+ area. To access the information, the mirrored latch configuration may include an output selection circuit that selects a latched output from the master latch instead of an output from a previously unused latch. Thus, even if the N+ area is increased, the probability of error (e.g., the area susceptible to neutron strikes) is limited by the master latch.

[0022] Further additionally or optionally, the balancing mechanism may include a split latch configuration, which includes a first storage portion connected in parallel with a second storage portion. Both the first storage portion and the second storage portion may be implemented using half-size silicon coverage. Therefore, in other embodiments, the first storage portion and the second storage portion connected in parallel may be combined to the same N+ region as a single storage portion. However, the first storage portion and the second storage portion may be located at different locations. Therefore, the first storage portion and the second storage portion can reduce the error generated by a single neutron strike (e.g., at a single location) for, for example, a single / entire storage portion. In other words, by allocating the layout arrangement of the first storage portion and the second storage portion, the split latch configuration can maintain the N+ region while reducing the error rate. For two halves, the split latch configuration can provide increased robustness because the degradation caused by the neutron strike in one half may not cause the hit half to fail completely. Therefore, the remaining charge / state in the hit half and the remaining charge / state in the retained half can be combined to restore the original state.

[0023] Figure 1 is a block diagram of an apparatus 100 (e.g., a semiconductor die assembly including a three-dimensional integration (3DI) device or a die stack package) according to an embodiment of the present technology. For example, the apparatus 100 may include a DRAM or a portion thereof including one or more dies / chips.

[0024] The device 100 may include a memory cell array, such as the memory array 150. The memory array 150 may include a plurality of memory banks (e.g., memory banks 0 to 15), and each memory bank may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at the intersections of the word lines and the bit lines. The memory cells may include any of a plurality of different storage media types, including capacitive, magnetoresistive, ferroelectric, phase change, etc. The selection of the word lines WL may be performed by the row decoder 140, and the selection of the bit lines BL may be performed by the column decoder 145. A sense amplifier (SAMP) may be provided for the corresponding bit lines BL and connected to at least one corresponding local I / O line pair (LIOT / B), which in turn may be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG), which may be used as a switch. The sense amplifiers and transmission gates may operate based on control signals from a decoder circuit, which may include command decoder 115, row decoder 140, column decoder 145, any control circuitry of memory array 150, or any combination thereof. Memory array 150 may also include board lines and corresponding circuitry for managing their operation.

[0025] The device 100 may employ a plurality of external terminals, including a command terminal and an address terminal coupled to a command bus and an address bus to receive a command signal (CMD) and an address signal (ADDR), respectively. The device 100 may further include a chip select terminal for receiving a chip select signal (CS), a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI and DMI, and power supply terminals VDD, VSS and VDDQ.

[0026] Address signals and bank address signals can be provided to the command terminal and address terminal from the outside ( Figure 1 140). The address signal and the bank address signal provided to the address terminal may be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 may receive the address signal and provide the decoded row address signal (XADD) to the row decoder 140 and the decoded column address signal (YADD) to the column decoder 145. The address decoder 110 may also receive the bank address signal and provide the bank address signal to the row decoder 140 and the column decoder 145.

[0027] A command signal (CMD), an address signal (ADDR), and a chip select signal (CS) may be provided to the command terminal and the address terminal from a storage controller and / or a malicious chipset. The command signal may represent various storage commands (e.g., including access commands, which may include read commands and write commands) from a storage controller. The chip select signal may be used to select the device 100 in response to commands and addresses provided to the command terminal and the address terminal. When the active chip select signal is provided to the device 100, the command and address may be decoded, and a storage operation may be performed. The command signal may be provided to the command decoder 115 via the command / address input circuit 105 as an internal command signal ICMD. The command decoder 115 may include a circuit for decoding the internal command signal ICMD to generate various internal signals and commands for performing storage operations, such as a row command signal for selecting a word line and a column command signal for selecting a bit line. The command decoder 115 may further include one or more registers for tracking various counts or values ​​(e.g., a count of refresh commands received by the device 100 or a self-refresh operation performed by the device 100).

[0028] Read data may be read from a memory cell in the memory array 150 specified by a row address (e.g., an address provided with an active command) and a column address (e.g., an address provided with a read). The read command may be received by the command decoder 115, which may provide an internal command to the input / output circuit 160, so that the read data may be output from the data terminals DQ, RDQS, DBI, and DMI via the read / write amplifier 155 and the input / output circuit 160 according to the RDQS clock signal. The read data may be provided at a time defined by the read latency information RL, which may be programmed in the device 100, for example, in the mode register ( Figure 1 The read latency information RL may be defined according to a clock cycle of the CK clock signal. For example, when providing associated read data, the read latency information RL may be a number of clock cycles of the CK signal after the device 100 receives a read command.

[0029] The write data may be provided to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command may be received by the command decoder 115, which may provide an internal command to the input / output circuit 160, so that the write data may be received by the data receiver in the input / output circuit 160 and supplied to the storage array 150 via the input / output circuit 160 and the read / write amplifier 155. The write data may be written to the storage cell specified by the row address and the column address. The write data may be provided to the data terminal at a time defined by the write wait time WL information. The write wait time WL information may be programmed in the device 100 (e.g., in a mode register). The write wait time WL information may be defined according to the clock cycle of the CK clock signal. For example, when the associated write data is received, the write wait time information WL may be a plurality of clock cycles of the CK signal after the device 100 receives the write command.

[0030] The power supply terminal can be provided with a power supply potential V DD and V SS These power supply potentials V DD and V SS The internal voltage generator circuit 170 can be provided to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can be based on the power supply potential V DD and V SS Generates various internal potentials V PP 、V OD 、V ARY 、V PERI etc. Internal potential V PP Can be used for row decoder 140, internal potential V OD and V ARY can be used for the sense amplifier included in the memory array 150, and the internal potential V PERI Can be used in many other circuit blocks.

[0031] The power supply terminal can also be provided with a power supply potential V DDQ . Power supply potential V DDQ The power supply potential VSS may be supplied to the input / output circuit 160. In the embodiment of the present technology, the power supply potential V DDQ can be the power supply potential V SS In another embodiment of the present technology, the power supply potential V DDQ can be the power supply potential V DD However, the dedicated power supply potential V DDQ It can be used for the input / output circuit 160 so that the power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0032] An external clock signal and a complementary external clock signal can be provided to the clock terminal and the data clock terminal. External clock signals CK, CKF, WCK, and WCKF can be provided to the clock input circuit 120. The CK signal and the CKF signal can be complementary, and the WCK signal and the WCKF signal can also be complementary. Complementary clock signals can have opposite clock levels and simultaneously switch between opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. In addition, when the clock signal is switched from a low clock level to a high clock level, the complementary clock signal is switched from a high clock level to a low clock level, and when the clock signal is switched from a high clock level to a low clock level, the complementary clock signal is switched from a low clock level to a high clock level.

[0033] The input buffer included in the clock input circuit 120 can receive an external clock signal. For example, when enabled by a clock / enable signal from the command decoder 115, the input buffer can receive a clock / enable signal. The clock input circuit 120 can receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK can be provided to the internal clock circuit 130. The internal clock circuit 130 can generate an internal clock signal ICLK based on the internal clock signal ICLK received from the command / address input circuit 105 and the clock enable ( Figure 1 (not shown) to provide various phase and frequency controlled internal clock signals. For example, the internal clock circuit 130 may include a clock path ( ) that receives the internal clock signal ICLK and provides various clock signals to the command decoder 115. Figure 1 100). The internal clock circuit 130 may further provide an input / output (IO) clock signal. The IO clock signal may be provided to the input / output circuit 160 and may be used as a timing signal for determining the output timing of read data and / or the input timing of write data. The IO clock signal may be provided at a plurality of clock frequencies so that data may be output from and input to the device 100 at different data rates. When a high storage speed is required, a higher clock frequency may be required. When lower power consumption is required, a lower clock frequency may be required. The internal clock signal ICLK signal ICLK may be provided to the timing generator 135 so that various internal clock signals may be generated.

[0034] The device 100 may be connected to any of a number of electronic devices or components thereof that are capable of utilizing memory to temporarily or permanently store information. For example, the host device of the device 100 may be a computing device such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet, a digital reader, a digital media player), or some of its components (e.g., a central processing unit, a co-processor, a dedicated storage controller, etc.). The host device may be a networking device (e.g., a switch, a router, etc.) or a digital image, audio, and / or video recorder, a vehicle, an appliance, a toy, or any of a number of other products. In one embodiment, the host device may be directly connected to the device 100; although in other embodiments, the host device may be indirectly connected to the storage device (e.g., via a network connection or via an intermediate device).

[0035] In some embodiments, the device 100 may include a non-volatile memory, such as a fuse or anti-fuse, configured to store predetermined information. For example, the non-volatile memory may be used to store fault / repair information, device or circuit identifiers, and / or other operational information required across power cycles. Such non-volatile memory may be grouped, such as for fuse array 180, and may be located in a position removed from a device or circuit using the stored information / or away from a device or circuit using the stored information. Therefore, one or more of the above-mentioned circuits or devices may include a local latch 182, which is configured to load and store predetermined information at a closer and / or more accessible location. For illustrative purposes, the local latch 182 is shown as being close to the fuse array 180, but it should be understood that the local latch 182 may be placed away from the fuse array 180 and closer to other circuits such as comparison circuit 184, row decoder 140, column decoder 145, etc. Predetermined information in a non-volatile memory (e.g., fuse array 180) may be transmitted or broadcast at a specified time (e.g., after a power-up event), and the device / circuit may load the broadcasted information, or a corresponding portion thereof, into local latches 182 for local storage. The term "local" may refer to the proximity (e.g., within a threshold distance) between a latch and a downstream circuit configured to access the information stored in the latch.

[0036] Comparison circuit 184 may process information in local latch 182. As an example, local latch 182 may store repair information for exchanging defective rows / columns with redundant rows / columns. Comparison circuit 184 may receive an address (e.g., a row and / or column address) associated with an incoming command (e.g., a read and / or write command). Comparison circuit 184 may compare the received address with the latched address to detect when the incoming command is associated with a defective cell. Based on the detection, comparison circuit 184 and subsequent circuits (e.g., row decoder 140 and / or column decoder 145) may access redundant memory instead of the defective cell associated with the command.

[0037] As described in detail below, the local latch 182 may include a balancing mechanism configured to increase the N+ area and / or Qcrit measurement without negatively affecting the remaining drive capability and / or the neutron strike target area, respectively. In some embodiments, the balancing mechanism may include a drive circuit configured to control the bias voltage of one or more transistors within the storage portion. The balancing mechanism may adjust the bias voltage of one or more devices (e.g., transistors) in the latch to increase the drive capability without increasing the N+ area. Additionally or alternatively, the balancing mechanism may include a mirror latch configuration with a coupling circuit that connects one or more unused / unallocated latches to a used / allocated latch, thereby increasing the N+ area and the corresponding drive capability. The mirror latch configuration may include an output selection circuit that provides a selection of an output from a used / allocated latch, thereby eliminating / reducing the impact of neutron strikes on the unused / unallocated latch. Further additionally or alternatively, the balancing mechanism may include a split latch configuration including a first storage portion separated from and connected in parallel with a second storage portion. The combined size / capacity of the two storage portions may be combined into a single / entire latch, thereby maintaining the drive capability. However, by positioning the two halves at different locations, the split latch configuration may reduce / eliminate the negative effects caused by a single neutron strike.

[0038] Figure 2 is a timing diagram of a broadcast according to an embodiment of the present technology. In some embodiments, Figure 1 The device 100 may store persistent data in a non-volatile memory, such as a fuse, an anti-fuse, a flash memory, and / or other permanent storage device. The persistent data may include boot and / or set up the device (e.g., Figure 1 Some examples of stored persistent data may include device / circuit identifiers, repair information, and / or other device setting data.

[0039] The non-volatile memory may be grouped, for example, in a fuse bank, and located in one or more locations separate from other circuits that access the stored persistent data. Thus, device 100 may transmit the stored persistent data from the grouped locations, and circuits corresponding to the transmitted data may receive and locally latch the information.

[0040] As an illustrative example, device 100 may broadcast stored persistent data from one or more fuse banks to Figure 1 A set of circuits shown. Figure 1 One or more of the circuits shown may include a local latch (e.g., a volatile memory) configured to store a portion of the broadcast information. In some embodiments, the broadcast may be followed by a power reset signal indicating that the system power of the device 100 is transitioning from an off state to an on state. The power reset signal may be issued between time Ta and time Tb.

[0041] The device 100 may be configured to broadcast information stored in one or more fuse banks during a fuse broadcast phase 204. The fuse broadcast phase 204 may correspond to a duration after a power reset signal and end at time Tc. The device 100 (via, for example, a broadcast circuit) may read the data stored in the fuse array and broadcast the read data to the Figure 1 In addition, one or more circuits can receive the broadcast data and load corresponding portions into a local memory (eg, a local latch) according to one or more commands.

[0042] After a predetermined duration, the fuse broadcast phase 204 may end and the fuse load end phase 206 may begin (e.g., at time Tc). The fuse load end phase 206 may correspond to a training phase or an initial calibration phase. During the fuse load end phase 206, the device 100 may implement one or more predetermined processes to align timing signals, such as clock (CK) and / or data strobe (DQS), adjust read / write delays, and / or other setup processes. The device 100 may implement such setup processes to establish an operating state.

[0043] Figure 3A is a schematic block diagram of a first example balancing mechanism according to an embodiment of the present technology. As described above, Figure 1 The device 100 can Figure 1 The one or more circuits shown may broadcast information. Each of the one or more circuits may include a set of local latch circuits 300 configured to locally store the broadcast information or a portion thereof. Figure 3AAs shown, each local latch circuit 300 can store one bit in a storage portion 302 (e.g., a static random access memory (SRAM) circuit or a D-type latch (DLAT) circuit). The storage portion 302 can include a load circuit 312, a holding circuit 314, and / or a pull-down circuit 316. The load circuit 312 can include a circuit configured to receive the broadcast information and load it into the holding circuit 314. In some embodiments, the load circuit 312 can include a transistor (e.g., an NMOS device) that is connected to the broadcast line on one side / terminal and to the holding circuit 314 on the opposite side / terminal. The load circuit 312 can be connected to (e.g., at its gate) and controlled by a corresponding fuse load signal 332. The fuse load signal 332 can be used to identify when the relevant / target information of the local latch circuit 300 is in Figure 2 is broadcast during the fuse broadcast phase 204. Therefore, the fuse load signal 332 can operate the load circuit 312 to transfer the broadcast data to the holding circuit 314 at such a timing to load the relevant part of the broadcast data.

[0044] The holding circuit 314 may include a circuit configured to store the loaded data and provide a circuit for accessing the data during operation of the device 100. In other words, the holding circuit 314 may include a volatile memory configured to store a locally relevant portion of the broadcast data. In some embodiments, the holding circuit 314 may include a cross-coupled inverter. The cross-coupled inverter may include a first inverter and a second inverter. The input of the first inverter may be connected to a first load transistor and an output of the second inverter. The input of the second inverter may be connected to a second load transistor and an output of the first inverter. The output of the second inverter may be connected to an access node 318, where the latched data may be accessed or read.

[0045] In one or more embodiments, local latch circuit 300 may include a pull-down circuit 316 (e.g., a transistor, such as an NMOS device) connected between access node 318 and electrical ground. Pull-down circuit 316 may be configured to connect access node 318 to ground and ensure a low state for certain conditions. In other embodiments, local latch circuit 300 may be devoid of pull-down circuit 316. For example, storage portion 302 may correspond to an SRAM circuit devoid of pull-down circuit 316.

[0046] To improve the Qcrit measurement without negatively affecting the neutron strike target region, a first example balancing mechanism can include a driving portion 304 coupled to the storage portion 302. The driving portion 304 can include circuitry configured to control an operating state of the holding circuit 314, such as by adjusting a bias voltage of one or more transistors within the storage portion 302. Thus, the driving portion 304 can increase the driving capability without changing the N+ region (e.g., the coverage of the storage portion 302).

[0047] To explain the control of the operating state of the holding circuit 314, Figure 3B is an example connection for the drive portion of the balancing mechanism according to an embodiment of the present technology. Figure 3A and 3B , the driving portion 304 may be connected to the storage portion 302 at the power supply node 310, and the storage portion 302 is further connected to Figure 3B One or more of the inverters in the holding circuit 314 are shown.

[0048] As an illustrative example, an inverter 350 (e.g., one of the inverters in the cross-coupled inverter circuit) may include a first switch 352 and a second switch 354. In some embodiments, the first switch 352 (e.g., a PMOS device) and the second switch 354 (e.g., an NMOS device) may be complementary transistors. The first switch 352 of the inverter 350 may be connected to the power supply node 310. For example, the source terminal and / or the body terminal of the first switch 352 may be directly connected to the power supply node 310. The input of the inverter 350 may be connected to the gates of the first switch 352 and the second switch 354, and the output of the inverter 350 may be connected between the first switch 352 and the second switch 354. For example, the drain terminals of the PMOS device and the NMOS device may be connected to the output of the inverter 350. The second switch may be connected (at, for example, the source terminal) to a voltage potential (e.g., electrical ground) that is different from the voltage potential of the power supply node 310.

[0049] Return to reference Figure 3A, the driving portion 304 may include a first voltage controller 322 and a second voltage controller 326 configured to provide power to the power supply node 310. The first voltage controller 322 may be configured to connect the first voltage source 324 to the power supply node 310. The first voltage controller 322 may be configured to connect the first voltage source 324 to the power supply node 310 during the fuse broadcast phase 204 except when the broadcast information is loaded. In some embodiments, the first voltage controller 322 may include a logic device (e.g., an OR device) that activates a transistor (e.g., a PMOS device) based on the fuse load signal 332 and the load completion signal 334, the load completion signal 334 indicating the end of the fuse broadcast phase 204. Therefore, the first voltage controller 324 may connect the first voltage source 324 to the power supply node 310 (e.g., the OR device may activate the transistor) during the fuse broadcast phase 204, except when the fuse load signal 332 is active (e.g., when the broadcast information is loaded). In other words, the first voltage controller 324 can disconnect the first voltage source 324 from the power supply node 310 while the broadcast information is being loaded (e.g., when the fuse load signal 332 is active) and when the fuse broadcast phase 204 ends. For example, the OR device can activate the transistor before and / or after loading the incoming data (in / inF). The OR device can deactivate the transistor when the broadcast information is being loaded and after the fuse broadcast phase 204 ends. In this way, the first voltage controller 322 can provide a high impedance state for the holding circuit 314 during loading and provide an increased voltage for the holding circuit after fuse broadcasting, thereby improving the overall performance of the holding circuit 314.

[0050] The second voltage controller 326 may be configured to connect the second voltage source 328 to the power supply node 310. The second voltage source 328 may provide a second voltage level (V2) greater than the first voltage level (V1) of the first voltage source 324. The second voltage controller 326 may be configured to connect the second voltage source 328 to the power supply node 310 when the fuse broadcast phase 204 ends, thereby increasing the drive capability after loading the information and during operation (i.e., while maintaining the coverage of the retention circuit 314 without increasing the N+ area). In some embodiments, the second voltage controller 326 may include a transistor (e.g., a PMOS device) that connects the second voltage source 328 to the power supply node 310 according to the inverted completion signal 336 (i.e., the complement of the load completion signal 334). Therefore, the second voltage controller 326 may connect the second voltage source 328 to the power supply node 310 after the fuse broadcast phase 204.

[0051] In some embodiments, the driver portion 304 can be configured to set one or more devices (e.g., the inverter 350 in the holding circuit 314) to a third state during the loading phase. For example, when the fuse load signal 332 is active, both the first voltage controller 322 and the second voltage controller 326 can disconnect the respective power supplies from the power supply node 310. Therefore, the PMOS device in the inverter 350 within the holding circuit 314 can correspond to a floating or high impedance (HiZ) state. Therefore, the driver portion 304 can use the third state to improve the loading performance (e.g., loading time and / or efficiency) of the holding circuit 314.

[0052] Figure 4 3 is a timing diagram of a balancing mechanism (e.g., local latch circuit 300 of FIG. 3 ) according to an embodiment of the present technology. As described above, device 100 (via, for example, a broadcast circuit) can generate various fuse load signals (e.g., fuseload_0 to fuseload_x), each of which is configured to identify a loading stage of a corresponding local latch circuit. After a power reset signal (e.g., Figure 2 between Ta and Tb), the device 100 may (via e.g. Figure 1 The device 100 may broadcast information stored in the fuse array 180 according to a predetermined sequence. Figure 1 The latch 182 of the device 100 may be received at the latch 182 of the device 100. The latch 182 may load the broadcast information based on the corresponding position / timing in the predetermined sequence. The device 100 may transmit a fuse load signal (e.g., an enable signal) to the latch 182 indicating the corresponding position / timing in the predetermined sequence. For the target latch n (e.g., an instance of the local latch circuit 300 in the latch 182), fuseload_n (e.g., the corresponding fuse load signal 332) may determine the loading phase that occurs simultaneously with the broadcast of the information corresponding to the target latch n.

[0053] The timing diagram illustrates the operating state 402, e.g. Figure 3A The corresponding holding circuit 314 Figure 3B During the initial portion of fuse broadcast phase 204, for example until fuse load signal 332 is active, operating state 402 may correspond to the bias state / voltage of inverter 350. Figure 3A The operating state 402 may correspond to a floating state 414 (HiZ) during the loading phase of the target latch n and / or when the fuseload_n signal is active. For the floating state 414, the power supply node 310 may be connected to the first voltage 412 (V1) associated with the first voltage source 324. Figure 3A The first voltage source 324 and the second voltage source 328 are both disconnected. Therefore, Figure 3BThe first switch 352 may be isolated from the voltage source and / or in a high impedance state. The operating state 402 may return to the first voltage 412 after the floating state 414. When the fuse broadcast phase 204 ends, the operating state 402 may correspond to the Figure 3A The second voltage 416 (V2) associated with the second voltage source 328 may be greater than the first voltage 412. In other words, when the load completion signal 334 becomes active and the inverted completion signal 336 becomes inactive, Figure 3A The second voltage controller 326 may connect the power supply node 310 to a second voltage source 328 .

[0054] Figure 5 5 is a schematic block diagram of a second example balancing mechanism according to an embodiment of the present technology. The second example balancing mechanism can correspond to a mirrored latch configuration 500 that connects an active / used latch (e.g., a first latch 502) to an inactive / unused latch (a second latch 504). Figure 1 The device 100 can be manufactured with a predetermined number of fuses and / or fuse latches, which generally correspond to the worst case. Thus, during the testing and qualification process, a portion of the fuses and / or latches are generally utilized, for example, for repair information. As described in detail below, the mirrored latch configuration 500 can connect active / used latches to inactive / unused latches to increase drive capability while limiting latch information access to only active / used latches to maintain the N+ region.

[0055] The first latch 502 and the second latch 504 may each correspond to Figure 3A For example, the first latch 502 and the second latch 504 may each include a holding circuit 314 connected to the load circuit 312. Furthermore, the first latch 502 and the second latch 504 may each include Figure 3A In other words, the second example balancing mechanism may be implemented in addition to the first example balancing mechanism instead of the first example balancing mechanism.

[0056] The mirror latch configuration 500 may include a coupling circuit 506 configured to connect a set of latches. The coupling circuit 506 may include a control portion and a connection portion. As an illustrative example, the control portion may include a logic device (e.g., a NAND device and an AND device), and the connection portion may include a transmission gate (TG) connected between a first latch 502 and a second latch 504. The control portion may operate the connection portion according to the active / inactive state of the corresponding latch. For example, the control portion may receive a first enable 512 and a second enable 514, which respectively represent the active / inactive state of the first latch 502 and the second latch 504. The control portion (via, for example, a NAND device) may be configured to generate an active output when one latch is active and the other latch is inactive. The control portion may also receive a load completion signal 334 (e.g., at an AND device). When the load completion signal 334 is active and the active output indicates that one latch is active and the other latch is inactive, the control portion may activate the connection portion and connect the first latch 502 and the second latch 504. In other words, when only one of the set of latches has been activated, the coupling circuit 506 may be inactive. Figure 2 The first latch 502 and the second latch 504 are connected after the fuse broadcast stage 204. Unused latches can be connected in parallel to load and latch the same value, thereby increasing the drive capability.

[0057] The mirror latch configuration 500 may further include an output selection circuit 508 configured to selectively generate an access output (e.g., a read result of the latched information). The output selection circuit 508 may include a logic device (e.g., an AND device) configured to provide access only to the active latch without providing access to the inactive / coupled latch. As an illustrative example, the AND devices in the output selection circuit 508 may each receive one of the first enable and the second enable 512. The AND device may generate a corresponding match flag based on the first enable and the second enable 512, thereby accessing / utilizing the latched information from the active circuit without accessing / utilizing the latched information from the inactive circuit. Although the driving capability may be provided by a set of connected latches, the actual output corresponds to one circuit. Further, since the connected latches are separated, a neutron strike is less likely to affect the latched states of the two latches than a single latch with a larger (e.g., double) coverage. Therefore, the mirror latch configuration 500 may provide increased driving capability without increasing the error sensitivity caused by the increased N+ area. The mirrored latch configuration 500 may further increase robustness against latch state changes based on replicating the latch state at two different locations.

[0058] Figure 66 is a schematic block diagram of a third example balancing mechanism according to an embodiment of the present technology. The third example balancing mechanism may correspond to a split latch configuration 600, the split latch configuration 600 including a Figure 1 Separate fractional portions (eg, first storage portion 602 and second storage portion 604 ) of holding circuit 314 at different locations in device 100 .

[0059] The first storage portion 602 and the second storage portion 604 may have the same components and configuration, but each has a fractional size / capacity of the holding circuit 314. For example, the first storage portion 602 may include a set of cross-coupled inverters having a fractional (e.g., half) silicon coverage connected to the load circuit 312. The second storage portion 604 may include a different set of cross-coupled inverters having a fractional (e.g., half) silicon coverage connected to the load circuit 312 and connected in parallel to the first storage portion 602. Thus, the combination of storage portions may add up to the desired size / capacity of the load circuit 312, thereby maintaining drive capability.

[0060] Since the holding circuit 314 is implemented by the first storage portion 602 and the second storage portion 604 that are separately arranged, the latch state is saved at two different locations. Therefore, compared with a single complete latch at one location, a neutron strike is less likely to affect the latch state of both parts. In other words, the split latch configuration 600 can maintain the N+ region but reduce the SER. Therefore, the split latch configuration 600 can further increase the robustness against changes in the latch state based on duplicating the latch state at two different locations without reducing the driving capability.

[0061] The first storage portion 602 and the second storage portion 604 may correspond to Figure 3A For example, the first storage portion 602 and the second storage portion 604 may be connected to Figure 3A In other words, the third example balancing mechanism may be implemented in addition to or in place of the first example balancing mechanism. Further, the first storage portion 602 and the second storage portion 604 may be connected to a separate latch or a corresponding set of portions (e.g., via Figure 5 5. Coupling circuit 506 and output selection circuit 508 of mirrored latch configuration 500 are shown.) Thus, the third example balancing mechanism may be implemented in addition to or in place of the second example balancing mechanism.

[0062] Fig. 7A is a diagram illustrating an operating device (eg, Figure 1 The device 100, the local latch circuit 300 of FIG. 3, Figure 5 The mirror latch configuration 500, Figure 6 Flowchart of an example method 700 for operating the split latch configuration 600 and / or a portion thereof). For example, the method 700 can be used to operate the local latch circuit 300 and / or components thereof. The method 700 can be used to operate the device 100 according to one or more of the above-described balancing mechanisms.

[0063] At block 702, device 100 may detect a power reset condition. For example, device 100 (via, for example, Figure 1 The voltage generator 170) can detect Figure 2 A power reset sequence 202 may be provided, such as a power ramp condition and / or a reset condition.

[0064] At block 704, device 100 may broadcast persistent data to Figure 1 For example, the broadcast circuitry may access persistent data stored in a non-volatile memory (e.g., a fuse bank). The broadcast circuitry may be configured to receive a signal from a broadcast source and to receive a signal from a receiver. Figure 2 During the fuse broadcast phase 204 of the controller, the accessed persistent data is transmitted to one or more circuits. For the corresponding one or more circuits, the accessed persistent data can be transmitted to Figure 3A The local latch circuit 300 Figure 3A The load circuit 312 is provided.

[0065] At block 706, the device 100 may Figure 3A The holding circuit 314 is connected to Figure 4 For example, the device 100 may control the first voltage 412 (V1) according to the broadcast sequence. Figure 3A The fuse load signal 332 and Figure 3A The device 100 can operate according to the fuse load signal 332 and the load completion signal 334. Figure 3A The first voltage controller 322 is used to Figure 3A The power supply node 310 is connected to Figure 3A As described above, the device 100 may Figure 3B The power supply node 310 and the connected first switch 352 (eg, a PMOS device) are connected to a first voltage 412. The holding circuit 314 can be connected to the first voltage 412 before and / or after the corresponding loading phase and during the fuse broadcast phase 204.

[0066] At block 708, device 100 may store the broadcast data locally. Figure 4As shown, the local latch circuit 300 can sequentially receive and load the broadcast data during the fuse broadcast phase 204. Since the persistent data is broadcast, the load circuit 312 can receive the broadcast data throughout the fuse broadcast phase 204. To load the broadcast data, the device 100 can control the corresponding fuse load signal 332.

[0067] At block 712, the device 100 isolates the holding circuit 314 according to the corresponding fuse load signal 332. As described above, the driving portion 304 (e.g., the first voltage controller 322 and the second voltage controller 326) can remove the power supply node 310 from the first voltage source 324 and the second voltage source 328 and the corresponding first voltage 412 and the second voltage 416 based on the fuse load signal 332. Therefore, the first switch 352 (e.g., a PMOS device) in the holding circuit 314 can be in a state of being disconnected during the corresponding loading phase. Figure 4 of the floating state 414 (eg, when the load circuit 312 is activated via the corresponding fuse load signal 332).

[0068] At block 714, device 100 may load the broadcast data according to the corresponding fuse load signal 332. In some embodiments, device 100 may load the broadcast data simultaneously with or after isolating retention circuit 314. Load circuit 312 may load the target data based on transferring the broadcast data from load circuit 312 to connected retention circuit 314 according to the corresponding fuse load signal 332 and the loading phase.

[0069] At block 716, device 100 may load the broadcast data into the partitioned portions within each of holding circuits 314. In some embodiments, local latch circuit 300 may include Figure 6 The first storage part 602 and the second storage part 604. Figure 6 In the split latch configuration 600, each of the holding circuits 314 may correspond to a target drive capability. Each of the holding circuits 314 may include at least a first storage portion 602 and a second storage portion 604. The first storage portion 602 and the second storage portion 604 may be separate and located at different locations within the device 100. The first storage portion 602 and the second storage portion 604 may correspond to a portion of the drive capability. Based on the parallel connection between the first storage portion 602 and the second storage portion 604, the device 100 may load the broadcast data into the first storage portion 602 and the second storage portion 604 at the same time.

[0070] The fuse broadcast phase 204 may end after a predetermined duration and / or after all broadcast data has been loaded into the corresponding local latch circuits 300. The local latch circuits 300 may store the loaded broadcast data in the retention circuits 314 after the fuse broadcast phase 204 to be retrieved by downstream circuits (e.g., Figure 1 The device 100 may also control the fuse broadcast phase 204 based on the end of the fuse broadcast phase 204. Figure 3B The load completion signal 334 and / or the inverted completion signal 336 are also provided.

[0071] At block 710, the device 100 may connect the holding circuit 314 to the second voltage 416 (V2). The device 100 may operate the second voltage controller 326 to connect the power node 310 to the second voltage 416 (V2) according to the inverted completion signal 336. Figure 3A As described above, the apparatus 100 can connect the power supply node 310 and the connected first switch 352 (eg, a PMOS device) to the second voltage 416. After the fuse broadcast phase 204, the holding circuit 314 can be connected to the second voltage 416.

[0072] In some embodiments, as shown at block 712, the device 100 may connect the inactive latch to the active latch. The device 100 may include Figure 5 The coupling circuit 506 and Figure 5 The output selection circuit 508 is based on Figure 5 The mirrored latch configuration 500 of FIG. 100 connects a set of local latch circuits 300. The device 100 can transmit an enable signal (e.g., indicating that the corresponding latch is selected to store broadcast data for access during operation) or inactive / unused according to whether the corresponding latch is active during operation (e.g., indicating that the latch is selected to store broadcast data for access during operation) or inactive / unused. Figure 5 Based on the enable signal, the coupling circuit 506 can detect when one of the local latch circuits in the group is active and the other local latch circuits are inactive. As a result of the detection, the coupling circuit 506 can connect the holding circuits 314 of the group of local latch circuits 300 in parallel. The coupling circuit 506 can connect the holding circuits 314 after the fuse broadcast stage. Therefore, the coupled / inactive holding circuits 314 can store the same charge level (i.e., the same / duplicate data) as the active latch.

[0073] Also based on the enable signal, the output selection circuit 508 can provide access to the holding circuit 314 of the active local latch circuit. The output selection circuit 508 can isolate or prevent access to the inactive holding circuit during operation. Therefore, the device 100 can use the inactive holding circuit to increase the driving capability without increasing the failure rate.

[0074] Figure 7B is a diagram illustrating a manufacturing device (eg, Figure 1 The device 100, the local latch circuit 300 of FIG. 3, Figure 5 The mirror latch configuration 500, Figure 6 Flowchart of an example method 750 for manufacturing a split latch configuration 600 and / or a portion thereof. For example, the method 750 can be used to manufacture a device 100 including one or more of the above-described balancing mechanisms.

[0075] At block 752, a load circuit (e.g., Figure 3A In some embodiments, providing a load circuit may include forming a load circuit (e.g., a transistor, such as an NMOS device) on a semiconductor material. The transistor may be formed based on depositing oxide, applying photoresist and / or masking, etching one or more layers, doping semiconductor material, depositing / etching metal, and / or other semiconductor manufacturing processes.

[0076] At block 754, a holding circuit may be provided (e.g., Figure 3A The provided retention circuit may be configured as a local memory for accessing / providing information to downstream circuits. In some embodiments, providing the retention circuit may include providing an SRAM device. In other embodiments, as shown at block 762, providing the retention circuit may include forming the retention circuit (e.g., a cross-coupled inverter) on a semiconductor material. For example, forming the retention circuit may include forming a plurality of groups of semiconductor devices according to the semiconductor manufacturing process described above. Figure 3B The first switch 352 and the second switch 354. In some embodiments, providing a holding circuit may include cross-coupling inverters, for example, by connecting inputs and outputs of the inverters as described above.

[0077] As shown at block 764, providing a holding circuit may include providing a holding circuit according to Figure 6 The split latch configuration 600 provides a partial retention circuit. For example, providing / forming a partial retention circuit may include Figure 6 The first storage portion 602 and the second storage portion 604 are provided at different locations for each implementation of the retention circuit 314. The retention circuit 314 can correspond to a target drive capability, and the first storage portion 602 and the second storage portion 604 can correspond to a fraction / portion of the target drive capability. In some embodiments, providing the retention circuit can include connecting the first storage portion 602 and the second storage portion 604 in parallel.

[0078] At block 756, a Figure 3A The voltage controller of the driving portion 304 (eg, Figure 3A The first voltage controller 322 and the second voltage controller 326 of the embodiment of the present invention are provided. Providing the voltage controller may include providing a switch, a transistor and / or a logic device. In some embodiments, providing the voltage controller may include forming a transistor and / or a logic device on a semiconductor material according to one or more semiconductor processes described above.

[0079] At block 758, a coupling circuit (e.g., Figure 5 The coupling circuit 506) and the output selection circuit (eg, Figure 5 For example, the output selection circuit 508 can be Figure 5 The mirrored latch configuration 500 is used to provide or form the coupling circuit 506 and the output selection circuit 508. In some embodiments, the coupling circuit 506 and the output selection circuit 508 can be disposed between or coupled to a predetermined group of local latch circuits 300. Providing the coupling circuit 506 and the output selection circuit 508 can include providing transmission gates and / or logic devices and / or forming them in semiconductor materials.

[0080] At block 760, various circuits may be connected, such as load circuit 312, hold circuit 314, storage portion, voltage controller, coupling circuit 506, and / or output selection circuit 508. For example, connecting the circuits may include forming conductors (e.g., traces and / or metal layers), such as by masking, depositing metal materials, and / or etching processes. Thus, at block 766, the hold circuit and the load circuit may be electrically connected to each other. Additionally, at block 768, a drive circuit (e.g., drive portion 304) may be formed. For example, connecting the circuits may include connecting first switch 352 to Figure 3A The first and second voltage controllers 322 and 326 are connected to the power supply node 310, respectively connecting the first and second voltage controllers 324 and 326, and / or connecting the first and second voltage controllers 322 and 326 to the power supply node 310. Furthermore, connecting the circuit may include connecting the logic device to the switch as described above.

[0081] Figure 8 is a schematic diagram of a system including an apparatus according to an embodiment of the present technology. Figures 1 to 7B Any of the aforementioned devices (e.g., storage devices) described may be incorporated into any of a myriad of larger and / or more complex systems, a representative example of which is Figure 8 880 is schematically shown in FIG. 880. The system 880 may include a storage device 800, a power supply 882, a drive 884, a processor 886, and / or other subsystems or components 888. The storage device 800 may include a storage device 800 that is substantially similar to the storage device 800 described above. Figures 1 to 7BThe features of the device described herein and thus may include various features for performing direct read requests from a host device. The resulting system 880 may perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, a representative system 880 may include, but is not limited to, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of the system 880 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communications network). The components of the system 880 may also include any of a variety of remote devices and computer-readable media.

[0082] As can be understood from the above, specific embodiments of the present technology have been described herein for illustrative purposes, but various modifications may be made without departing from the present disclosure. In addition, certain aspects of the new technology described in the context of a specific embodiment may also be combined or eliminated in other embodiments. In addition, although the advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need to exhibit such advantages to fall within the scope of the present technology. Therefore, the present disclosure and associated technology may include other embodiments not explicitly shown or described herein.

[0083] In the embodiments shown above, the apparatus has been described in the context of DRAM devices. However, apparatus configured according to other embodiments of the present technology may include other types of suitable storage media in addition to or in place of DRAM devices, such as devices incorporating NAND-based or NOR-based non-volatile storage media (e.g., NAND flash memory), magnetic storage media, phase change storage media, ferroelectric storage media, etc.

[0084] The term "processing" as used herein includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, calculating results, executing instructions, assembling, transmitting and / or manipulating data structures. The term data structure includes information arranged as bits, words or codewords, blocks, files, input data, system-generated data (such as calculated or generated data) and program data. Further, the term "dynamic" as used herein describes the process, function, action or realization that occurs during the operation, use or deployment of the corresponding device, system or embodiment and after or while running the manufacturer or third-party firmware. The process, function, action or realization that occurs dynamically can occur after or after design, manufacture and initial testing, setting or configuration.

[0085] The above embodiments are described in sufficient detail to enable those skilled in the art to make and use these embodiments. However, those skilled in the relevant art will appreciate that the technology may have additional embodiments and that the technology may be used without the above reference. Figures 1 to 8 The described embodiments are implemented without the need for several details.

Claims

1. A device comprising: a holding circuit configured to locally store the broadcast information for access via the access circuit; a load circuit coupled to the holding circuit and configured to load the information into the holding circuit during a fuse broadcast phase; as well as a driving portion coupled to the holding circuit and configured to connect a first voltage and a second voltage to the holding circuit at different times for loading and the local storage, wherein the first voltage and the second voltage are different source voltages, configured to provide power for loading the information into the holding circuit and / or for providing access to the stored information. 2 . The device of claim 1 , wherein the driving section is configured to connect the first voltage to the holding circuit during the fuse broadcasting phase, and to connect the second voltage to the holding circuit after the fuse broadcasting phase. The apparatus of claim 2 , wherein the second voltage is greater than the first voltage. 4 . The apparatus according to claim 2 , wherein the driving section is configured to disconnect the holding circuit from both the first voltage and the second voltage when the load circuit loads broadcast information or a portion thereof into the holding circuit.

5. The apparatus of claim 1, wherein: The holding circuit includes a set of cross-coupled inverters, wherein inputs of the inverters are connected to the load circuit and one or more components of the inverters are connected to a power supply node; as well as The driving portion is connected to the power supply node and is configured to control an operating state of the one or more components in the inverter based on controlling a voltage supplied to the power supply node.

6. The apparatus of claim 5, wherein at least one inverter in the set of cross-coupled inverters comprises a first switch and a second switch connected in series, wherein the first switch and the second switch are complementary.

7. The apparatus of claim 6, wherein the first switch is a PMOS device having one or more terminals directly connected to the power supply node.

8. The apparatus of claim 1, wherein the drive portion comprises: a first voltage controller connected between a first voltage source and the holding circuit, wherein the first voltage source corresponds to the first voltage; and A second voltage controller is connected between a second voltage source and the holding circuit, wherein the second voltage source corresponds to the second voltage.

9. The apparatus of claim 8, wherein the first voltage controller is configured to connect the first voltage source to the holding circuit based on a fuse load signal and a load completion signal, wherein the fuse load signal corresponds to the fuse broadcast phase and the load completion signal corresponds to the end of the fuse broadcast phase.

10. The device of claim 9, wherein the first voltage controller is configured to connect the first voltage source to the holding circuit before the end of the fuse broadcast phase and / or outside of a loading duration, the loading duration corresponding to the duration for which the load circuit transmits broadcast information or a portion thereof to the holding circuit.

11. The apparatus of claim 8, wherein the second voltage controller is configured to connect the second voltage source to the holding circuit based on an inverted completion signal corresponding to an end of the fuse broadcast phase.

12. The apparatus of claim 11, wherein the second voltage controller is configured to connect the second voltage source to the holding circuit at and / or after the end of the fuse broadcast phase.

13. The apparatus of claim 1, wherein: The holding circuit, the load circuit and the driving section include a first local latch circuit; It further includes: a second local latch circuit configured to load and provide access to the separate information; a coupling circuit coupled to the first local latch circuit and the second local latch circuit and configured to selectively connect load circuits of the first local latch circuit and the second local latch circuit in parallel with each other; and An output selection circuit is coupled to the first local latch circuit and the second local latch circuit and is configured to selectively provide access to the load circuits of the first local latch circuit and the second local latch circuit.

14. The apparatus of claim 13, wherein: The coupling circuit is configured to: (1) when one of the first local latch circuit and the second local latch circuit is active and the other is inactive, wherein the active latch is selected to store the information for access during operation, and (2) after the fuse broadcast, connect the load circuits of the first local latch circuit and the second local latch circuit; as well as The output selection circuit is configured to provide access to the load circuit of the active latch.

15. The apparatus of claim 1, wherein the holding circuit corresponds to a drive capability and comprises: a first storage portion corresponding to a portion of the drive capacity and located at a first position; and A second storage portion, which is connected in parallel with the first storage portion, corresponds to a portion of the driving capacity and is located at a second position.

16. The apparatus of claim 1, wherein the retention circuit comprises a static random access memory.

17. The apparatus of claim 16, wherein the apparatus comprises a dynamic random access memory (DRAM) device.

18. A method of operating a device, the method comprising: receiving broadcast information at a load circuit during a fuse broadcast phase; transmitting the broadcast information or a portion thereof from the load circuit to the holding circuit during a loading phase; storing the broadcast information or the portion thereof in the retention circuit for later access after the fuse broadcast phase; connecting the holding circuit to a first voltage during the fuse broadcast phase; as well as The holding circuit is connected to a second voltage after the fuse broadcast phase, wherein the second voltage is greater than the first voltage.

19. The method of claim 18, further comprising isolating the holding circuit from both the first voltage and the second voltage during the loading phase.

20. The method of claim 18, wherein: The holding circuit and the load circuit include a first local latch circuit; It further includes: detecting that the first local latch circuit is active and a corresponding second local latch circuit is inactive, wherein an active setting of a latch indicates that the latch is selected to store the broadcast information or the portion thereof for access during operation; Based on the detecting, connecting the holding circuit in parallel to a second holding circuit in the second local latch circuit after the fuse broadcasting phase; and Access to the holding circuit of the first local latch circuit is provided while access to the second holding circuit is isolated during operation.

21. The method of claim 18, wherein: The holding circuit corresponds to the driving capability and comprises: a first storage portion corresponding to a portion of the drive capacity and located at a first position, and a second storage portion connected in parallel with the first storage portion, corresponding to a portion of the driving capacity, and located at a second position; as well as Transmitting the broadcast information or a portion thereof includes transmitting the broadcast information or a portion thereof to the first storage portion and the second storage portion.

22. A method of manufacturing a device, the method comprising: providing a holding circuit configured to locally store the broadcast information for access by the access circuit; connecting a load circuit to the holding circuit, wherein the load circuit is configured to transfer the information into the holding circuit during a fuse broadcast phase; as well as A driver circuit is formed, the driver circuit being coupled to the holding circuit and configured to connect a first voltage and a second voltage to the holding circuit at different times of the load and the local storage, wherein the first voltage and the second voltage are different source voltages, configured to provide power for loading the information into the holding circuit and / or for providing access to the stored information.

23. The method of claim 22, wherein: The holding circuit, the load circuit and the drive circuit include a first local latch circuit; It further includes: forming a second local latch circuit configured to load and provide access to the separate information; forming a coupling circuit coupled to the first local latch circuit and the second local latch circuit and configured to selectively connect load circuits of the first local latch circuit and the second local latch circuit in parallel with each other; and An output selection circuit is formed that is coupled to the first local latch circuit and the second local latch circuit and is configured to selectively provide access to the load circuits of the first local latch circuit and the second local latch circuit.

24. The method of claim 22, wherein the holding circuit corresponds to a drive capability and comprises: a first storage portion corresponding to a portion of the drive capacity and located at a first position; and A second storage portion, which is connected in parallel with the first storage portion, corresponds to a portion of the driving capacity and is located at a second position.

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