Three-dimensional memory device

Abstract

A three-dimensional (3D) memory device is provided. The three-dimensional (3D) memory device includes a memory cell array, a first sense amplifier, and a second sense amplifier. The memory cell array includes lower memory cells respectively arranged in regions where lower word lines and bit lines cross, and upper memory cells respectively arranged in regions where upper word lines and bit lines cross. The first sense amplifier is connected to a first lower word line and performs a data sensing operation on a first lower memory cell connected between a first bit line and the first lower word line. The second sense amplifier is connected to a first upper word line and performs a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line. Reading operations on the first sense amplifier and the second sense amplifier are performed in parallel.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2020-0010031, filed January 28, 2020, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The inventive concept relates to a memory device, and more particularly, to a three-dimensional (3D) memory device and a method of operating the 3D memory device. BACKGROUND

[0003] As a non-volatile memory device, a flash memory and a resistive memory device such as a phase change random access memory (PRAM), a nano floating gate memory (NFGM), a polymer RAM (PoRAM), a magnetic RAM (MRAM), a ferroelectric RAM (FeRAM), and a resistive RAM (RRAM) are known. The resistive memory device can have the speed of the DRAM and the non-volatility of the flash memory. The memory cell of the resistive memory device can have a resistance distribution according to programmed data. In an operation of reading data stored in the memory cell, the data can be sensed by applying a constant current or voltage to the memory cell and reading a voltage varied according to the resistance of the memory cell. As the demand for highly integrated memory devices has increased, it is necessary to reduce the power consumption of the memory device. SUMMARY

[0004] According to an aspect of the inventive concept, there is provided a three-dimensional (3D) memory device including: a memory cell array including a plurality of lower memory cells respectively arranged in regions where a plurality of lower word lines and a plurality of bit lines cross each other and a plurality of upper memory cells respectively arranged in regions where a plurality of upper word lines and the plurality of bit lines cross each other; a first sense amplifier connected to a first lower word line among the plurality of lower word lines, the first sense amplifier comparing a voltage of the first lower word line with a first reference voltage to perform a data sensing operation on a first lower memory cell connected between a first bit line among the plurality of bit lines and the first lower word line; and a second sense amplifier connected to a first upper word line among the plurality of upper word lines, the second sense amplifier comparing a voltage of the first upper word line with a second reference voltage to perform a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line, wherein the data sensing operation of the first sense amplifier and the data sensing operation of the second sense amplifier are performed in parallel.

[0005] According to another aspect of the inventive concept, there is provided a three-dimensional (3D) memory device including a first semiconductor layer and a second semiconductor layer stacked in a vertical direction, wherein the first semiconductor layer includes a memory cell array including a plurality of lower memory cells respectively arranged in regions where a plurality of lower word lines and a plurality of bit lines cross each other and a plurality of upper memory cells respectively arranged in regions where a plurality of upper word lines and the plurality of bit lines cross each other, and wherein the second semiconductor layer includes a first sense amplifier connected to a first lower word line among the plurality of lower word lines, the first sense amplifier performing a data sensing operation on a first lower memory cell connected between a first bit line among the plurality of bit lines and the first lower word line, and a second sense amplifier connected to a first upper word line among the plurality of upper word lines, the second sense amplifier performing a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line.

[0006] According to another aspect of the inventive concept, there is provided a three-dimensional (3D) memory device including a memory cell array including a plurality of lower memory cells respectively arranged in regions where a plurality of lower word lines and a plurality of bit lines cross each other and a plurality of upper memory cells respectively arranged in regions where a plurality of upper word lines and the plurality of bit lines cross each other, a first row decoder including a plurality of lower row switches respectively connected to corresponding ones of the plurality of lower word lines, the first row decoder performing a selection operation on the plurality of lower word lines, a second row decoder including a plurality of upper row switches respectively connected to corresponding ones of the plurality of upper word lines, the second row decoder performing a selection operation on the plurality of upper word lines, a first sense amplifier connected to a first lower word line among the plurality of lower word lines, the first sense amplifier performing a data sensing operation on a first lower memory cell connected between a first bit line among the plurality of bit lines and the first lower word line, and a second sense amplifier connected to a first upper word line among the plurality of upper word lines, the second sense amplifier performing a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line. BRIEF DESCRIPTION OF DRAWINGS

[0007] Embodiments of the inventive concept will become more fully understood from the detailed description given herein below, and the accompanying drawings, which are given by way of illustration only and thus are not limitative of the present inventive concept, and wherein:

[0008] Figure 1 is a block diagram of a memory system according to an embodiment of the inventive concept;

[0009] Figure 2 is a block diagram of a memory device according to an embodiment of the inventive concept; Figure 1

[0010] Figure 3 is shown in more detail according to an embodiment of the inventive concept;​Figure 2 part of a memory device according to an embodiment of the inventive concept;

[0011] Figure 4 a memory cell according to an embodiment of the inventive concept is shown;

[0012] Figure 5A a plot illustrating a set write and a reset write of a variable resistor element of a memory cell of Figure 4 Figure 5B a plot illustrating a distribution of a memory cell according to resistance when Figure 4 a plot illustrating a distribution of a memory cell according to resistance when the memory cell of

[0013] Figure 6A a circuit diagram of a memory cell array according to an embodiment of the inventive concept, Figure 6B a perspective view of a memory cell array of Figure 6A

[0014] Figure 7 a flow chart of a method of reading data from a memory device according to an embodiment of the inventive concept;

[0015] Figure 8 a circuit diagram illustrating components for performing a read operation of a memory device according to an embodiment of the inventive concept;

[0016] Figure 9 a plot illustrating a read operation of a memory device according to an embodiment of the inventive concept;

[0017] Figure 10 a timing diagram illustrating a read operation for a first memory cell and a second memory cell according to an embodiment of the inventive concept;

[0018] Figure 11 a timing diagram illustrating a read operation for a first memory cell and a second memory cell according to an embodiment of the inventive concept;

[0019] Figure 12 a memory device having a cell-on-periphery (COP) structure according to an embodiment of the inventive concept is shown;

[0020] Figure 13 a top surface of a second semiconductor layer according to an embodiment of the inventive concept is shown;

[0021] Figure 14 a cross-sectional view of the memory device taken along line XIV-XIV' in Figure 13 Figure 15 a cross-sectional view of the memory device taken along line XV-XV' in Figure 13

[0022] ​​​​Figure 16 illustrates a top surface of a second semiconductor layer according to an embodiment of the inventive concept;

[0023] Figure 17 It is along Figure 16 A cross-sectional view of the memory device taken along line XVII-XVII' in FIG. Figure 18 It is along Figure 16 A cross-sectional view of the memory device taken along line XVIII-XVIII′ in FIG. Figure 19 It is along Figure 16 A cross-sectional view of the memory device taken along line XIX-XIX' in FIG. Figure 20 It is along Figure 16 A cross-sectional view of the memory device taken along line XX-XX';

[0024] Figures 21-24 Memory devices according to some embodiments of the inventive concept are shown;

[0025] Figure 25 is a block diagram illustrating an example in which a memory device according to some embodiments of the inventive concept is applied to a solid state drive (SSD) system; and

[0026] Figure 26 A memory device having a chip-to-chip structure according to some embodiments of the inventive concept is shown. DETAILED DESCRIPTION

[0027] Hereinafter, some example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram of a memory system 10 according to an embodiment of the inventive concept.

[0029] Reference Figure 1 , a memory system 10 may include a memory device 100 and a memory controller 200. The memory device 100 may include a memory cell array 110, a first sense amplifier SA1, and a second sense amplifier SA2. In an embodiment, the memory cell array 110 may include a plurality of resistive memory cells, and the memory device 100 may be referred to as a "resistive memory device." However, the inventive concept is not limited thereto, and the memory cell array 110 may include various other types of memory cells.

[0030] The memory device 100 can be implemented in various forms. As an example, the memory device 100 can be a device implemented with one memory chip or one memory die. Alternatively, the memory device 100 can be defined as a device including a plurality of memory chips, and as an example, the memory device 100 can be a memory module in which a plurality of memory chips are mounted on a board. However, embodiments of the inventive concept are not limited thereto, and the memory device 100 can be implemented in various forms such as a semiconductor package including a memory die.

[0031] The memory controller 200 can control the memory device 100 to read data stored in the memory device 100 or write data to the memory device 100 in response to a write / read request from the host HOST. In particular, the memory controller 200 can provide an address ADDR, a command CMD, and a control signal CTRL to the memory device 100 to control a program (or write) operation, a read operation, and an erase operation, etc. of the memory device 100. Also, write data DATA and read data DATA can be transmitted and received between the memory controller 200 and the memory device 100.

[0032] The memory cell array 110 can include a plurality of memory cells arranged in regions where a plurality of first signal lines and a plurality of second signal lines cross, respectively. In an embodiment, the first signal lines can be one of bit lines and word lines, and the second signal lines can be the other of the bit lines and the word lines. Accordingly, the memory device 100 can be referred to as a "cross-point memory device".

[0033] Each of the plurality of memory cells can be a single-level cell storing one bit, or a multi-level cell capable of storing at least 2 bits or more of data. Also, the memory cells can have a plurality of resistance distributions according to the number of bits stored in each memory cell. For example, the memory cells can have two resistance distributions when one bit of data is stored in each memory cell, and the memory cells can have four resistance distributions when two bits of data are stored in each memory cell.

[0034] The memory cell array 110 can include resistive memory cells each including a variable resistor element (or referred to as a "variable resistance element"). For example, when the variable resistor element includes a phase change material and the resistance of the variable resistor element changes as a temperature, the resistive memory device can be a PRAM. As another example, when the variable resistor element includes an upper electrode, a lower electrode, and a composite metal oxide located between the upper electrode and the lower electrode, the resistive memory device can be a RRAM. As another example, when the variable resistor element includes an upper electrode of a magnetic material, a lower electrode of a magnetic material, and a dielectric material located between the upper electrode of the magnetic material and the lower electrode of the magnetic material, the resistive memory device can be a MRAM. Hereinafter, the term "memory cell" will be used to refer to a resistive memory cell.

[0035] The memory cell array 110 can include a plurality of layers each including a plurality of resistive memory cells, layers adjacent to each other can be configured to share a signal line (e.g., a bit line). Accordingly, the memory device 100 can be referred to as a "three-dimensional (3D) resistive memory device". Hereinafter, embodiments in which the memory device 100 is a 3D resistive memory device will be mainly described.

[0036] In embodiments, the memory cell array 110 can include a first layer (e.g., a first layer 310a in Figure 12 and a second layer (e.g., a second layer 310b in Figure 12 The first sense amplifier SA1 can be connected to the first layer, and the second sense amplifier SA2 can be connected to the second layer. The connection relationship between the memory cell array 110 and the first and second sense amplifiers SA1 and SA2 will be described in more detail with reference to Figure 3

[0037] Figure 2 is a block diagram of the memory device 100 according to an embodiment of the inventive concept. Figure 1

[0038] Referring to Figure 2 , the memory device 100 can include a memory cell array 110, a write / read circuit 120, control logic 130, a row decoder 140, a column decoder 150, and a voltage generator 160. The write / read circuit 120 can include a sense amplification block 121 and a write driver 122. The sense amplification block 121 can include at least a first sense amplifier SA1 and a second sense amplifier SA2.

[0039] ​​The memory cell array 110 can be connected to a plurality of first signal lines and a plurality of second signal lines. Also, the memory cell array 110 can include a plurality of memory cells arranged in regions where the plurality of first signal lines and the plurality of second signal lines cross each other, respectively. Hereinafter, a case where the plurality of first signal lines are word lines WL and the plurality of second signal lines are bit lines BL will be described as an example.

[0040] The write / read circuit 120 can supply a constant voltage or current to a selected memory cell (hereinafter, simply referred to as "selected memory cell") among the plurality of memory cells during a data write and read operation of the selected memory cell through a selected word line (hereinafter, simply referred to as "selected word line") or a selected bit line (hereinafter, simply referred to as "selected bit line") connected to the selected memory cell. For example, when a read operation is performed, the write / read circuit 120 can supply a pre-charge voltage to the selected word line and / or the selected bit line, and then can sense a voltage level of the selected word line or the selected bit line.

[0041] The sense amplification block 121 can be selectively connected to the bit line BL and / or the word line WL, and can read data written to the selected memory cell. For example, the sense amplification block 121 can detect a voltage from the word line WL connected to the selected memory cell, amplify the detected voltage, and output read data DATA. The write driver 122 can be selectively connected to the bit line BL and / or the word line WL, and can supply a write current to the selected memory cell. As a result, the write driver 122 can program data DATA to be stored in the memory cell array 110.

[0042] The control logic 130 can output various control signals required for writing data to or reading data from the memory cell array 110 based on a command CMD, an address ADDR, and a control signal CTRL received from the memory controller 200. Figure 1

[0043] ​In an embodiment, the control logic 130 can control the first sense amplifier SA1 and the second sense amplifier SA2 such that a data read operation performed on the first lower memory cell arranged in the first layer and a data read operation performed on the first upper memory cell arranged in the second layer are performed in parallel. In particular, the control logic 130 can control a pre-charge operation to be performed on the first lower word line and the first upper word line in a word line pre-charge period, and can control a pre-charge operation for the first bit line in a bit line pre-charge period after the word line pre-charge period. For example, the memory device can further include a first word line pre-charge circuit configured to apply a first word line pre-charge voltage to the first lower word line in the word line pre-charge period, a second word line pre-charge circuit configured to apply a second word line pre-charge voltage to the first upper word line in the word line pre-charge period, and a bit line pre-charge circuit configured to apply a bit line pre-charge voltage to the first bit line in the bit line pre-charge period, a voltage level of each of the first word line pre-charge voltage and the second word line pre-charge voltage being a negative voltage. Details thereof will be described later with reference to FIGS. 6 and 7. Figures 9-11 A read control operation of the control logic 130 is described.

[0044] The voltage generator 160 can generate various types of voltages required for performing a write operation, a read operation, and an erase operation on the memory cell array 110 based on a voltage control signal CTRL_vol. The row decoder 140 can be connected to the memory cell array 110 through a plurality of word lines WL and can activate a selected word line among the plurality of word lines WL in response to a row address X_ADDR. The column decoder 150 can be connected to the memory cell array 110 through a plurality of bit lines BL and can activate a selected bit line among the plurality of bit lines BL in response to a column address Y_ADDR.

[0045] Figure 3 A portion of the memory device 100 according to an embodiment of the inventive concept is shown in more detail. Figure 2

[0046] Referring to Figure 3 The memory cell array 110 can include lower memory cells or first memory cells MC1 arranged in regions where lower word lines WL11 to WL1n and bit lines BL1 to BLm cross each other, and upper memory cells or second memory cells MC2 arranged in regions where upper word lines WL21 to WL2n and the bit lines BL1 to BLm cross each other, respectively. Here, m and n can be an integer of 2 or more. In this case, the first memory cells MC1 can correspond to a first layer or a lower layer, and the second memory cells MC2 can correspond to a second layer or an upper layer. However, the inventive concept is not limited thereto, and the memory cell array 110 can have a structure in which three or more layers are vertically stacked.​

[0047] The row decoder 140 can be disposed between the memory cell array 110 and the sense amplification block 121, and can include row switches 141a, 141b, 142a, and 142b. In an embodiment, the first row switches 141a and 141b and the second row switches 142a and 142b can be turned on or off according to a word line selection signal LX0. For example, the word line selection signal LX0 can be generated from the row decoder 140 based on a row address X_ADDR. However, the inventive concept is not limited thereto. The row decoder 140 can include the first row switches 141a and 141b connected to and performing a selection operation on the corresponding lower word lines WL11 to WL1n, respectively, and the second row switches 142a and 142b connected to and performing a selection operation on the corresponding upper word lines WL21 to WL2n, respectively. According to an embodiment, the row decoder 140 can include a first row decoder including the first row switches 141a and 141b, and a second row decoder including the second row switches 142a and 142b.

[0048] The column decoder 150 can include column switches 151 and 152 connected to and performing a selection operation on the corresponding bit lines BL1 to BLm, respectively. The column switches 151 and 152 can be turned on or off according to bit line selection signals LY1 and LYm corresponding thereto, respectively, and thus the column decoder 150 can select one of the bit lines BL1 to BLm. For example, the bit line selection signals LY1 and LYm can be generated from the column decoder 150 based on a column address Y_ADDR.

[0049] The sense amplification block 121 can include at least two sense amplifiers (i.e., a first sense amplifier 121a and a second sense amplifier 121b) corresponding to lower and upper layers, respectively. The first sense amplifier 121a can be connected to a lower word line WL11 selected from among lower word lines WL11 to WL1n, and the second sense amplifier 121b can be connected to an upper word line WL21 selected from among upper word lines WL21 to WL2n. The first sense amplifier 121a can include a first sense amplifier SA1 and a pre-charge transistor TR1, and the second sense amplifier 121b can include a second sense amplifier SA2 and a pre-charge transistor TR2. The first sense amplifier 121a and the second sense amplifier 121b can have the same structure. The first sense amplifier 121a can be optimized for sensing data of memory cells connected to the lower word lines WL11 to WL1n, and the second sense amplifier 121b can be optimized for sensing data of memory cells connected to the upper word lines WL21 to WL2n. However, the inventive concept is not limited thereto, and the sense amplification block 121 can further include a third sense amplifier 121c and a fourth sense amplifier 121d. The third sense amplifier 121c can be connected to a lower word line WL1n selected from among the lower word lines WL11 to WL1n, and the fourth sense amplifier 121d can be connected to an upper word line WL2n selected from among the upper word lines WL21 to WL2n.

[0050] A group including memory cells connected to the first sense amplifier 121a and the second sense amplifier 121b can be referred to as a first sense amplifier group, and a group including memory cells connected to the third sense amplifier 121c and the fourth sense amplifier 121d can be referred to as a second sense amplifier group. In this case, the first sense amplifier group can be connected to a first global word line or a first data line DL1 and a second global word line or a second data line DL2, and the second sense amplifier group can be connected to a third global word line or a third data line DL3 and a fourth global word line or a fourth data line DL4. Accordingly, a lower word line included in the first sense amplifier group from among the lower word lines WL11 to WL1n can be selected through the first data line DL1, and a lower word line included in the second sense amplifier group from among the lower word lines WL11 to WL1n can be selected through the third data line DL3. Similarly, an upper word line included in the first sense amplifier group from among the upper word lines WL21 to WL2n can be selected through the second data line DL2, and an upper word line included in the second sense amplifier group from among the upper word lines WL21 to WL2n can be selected through the fourth data line DL4.

[0051] Figure 4 A memory cell MC according to an embodiment of the inventive concept is illustrated.

[0052] Reference is made to Figure 4, the memory cell MC may include a variable resistor element R and a switch element (or referred to as a "selection element") SW connected in series. The memory cell MC may be connected to Figure 3 The variable resistor element R may include a phase change layer (or variable resistance layer) 11, an upper electrode 12 formed on the phase change layer 11, and a lower electrode 13 formed below the bottom of the phase change layer 11. For example, the variable resistor element R may include a phase change material (e.g., Ge-Sb-Te (GST)), a transition metal oxide, or a magnetic material. The switching element SW may be implemented using various elements such as a bidirectional threshold switch (OTS) material, a transistor, and a diode.

[0053] The upper electrode 12 and the lower electrode 13 may include various metals, metal oxides, or metal nitrides. The phase change layer 11 may include a bipolar resistive memory material or a unipolar resistive memory material. The bipolar resistive memory material may be programmed to a set or reset state by the polarity of the current. Perovskite-type materials may be used for the bipolar resistive memory material. Even when the current has the same polarity, the unipolar resistive memory material may be programmed to a set or reset state. For example, NiO x or TiO x Transition metal oxides can be used as unipolar resistive memory materials.

[0054] Figure 5A It shows the Figure 4 Graphs of set writing and reset writing of the variable resistor element R of the memory cell MC, Figure 5B It shows that Figure 4 A graph showing distribution of memory cells according to resistance when the memory cell MC is a single-level cell.

[0055] Refer to it together Figure 4 and Figure 5A When the phase-change material constituting the variable resistor element R is heated to a temperature between the crystallization temperature Tx and the melting point Tm for a specific period of time and then gradually cooled, the phase-change material enters a crystalline state. This crystalline state is referred to as the "set state," storing data '0'. On the other hand, when the phase-change material is quenched after being heated to a temperature above the melting point Tm, the phase-change material enters an amorphous state. This amorphous state is referred to as the "reset state," storing data '1'. Therefore, current can be supplied to the variable resistor element R to store data, and the resistance value of the variable resistor element R can be measured to read the data.

[0056] Refer to it together Figure 4 and Figure 5B , Figure 5B The horizontal axis of the graph represents resistance, Figure 5BThe vertical axis of the graph indicates the number of memory cells MC. When the memory cells MC are single-level cells, the memory cells MC can be in one of a low resistance state LRS (i.e., a set state SET) and a high resistance state HRS (i.e., a reset state RESET). Accordingly, an operation of switching the memory cells MC from the low resistance state LRS to the high resistance state HRS can be referred to as a reset operation or a reset write operation. In addition, an operation of switching the memory cells MC from the high resistance state HRS to the low resistance state LRS can be referred to as a set operation or a set write operation.

[0057] Figure 6A is a circuit diagram of a memory cell array 110a according to an embodiment of the inventive concept.

[0058] Referring to Figure 6A The memory cell array 110a can include a first layer and a second layer stacked vertically, which can share signal lines (e.g., bit lines BL1 to BL4). The memory cell array 110a can include lower word lines WL11 and WL12 extending in a first direction (X direction) and spaced apart from each other in a second direction (Y direction) perpendicular to the first direction, and upper word lines WL21 and WL22 extending in the first direction and spaced apart from the lower word lines WL11 and WL12 in a third direction (Z direction) perpendicular to the first direction. In addition, the memory cell array 110a can include the bit lines BL1 to BL4 extending in the second direction separately from each of the upper word lines WL21 and WL22 and the lower word lines WL11 and WL12 in the third direction.

[0059] The first memory cells MC1 can be respectively arranged in regions where the bit lines BL1 to BL4 cross the lower word lines WL11 and WL12, and the second memory cells MC2 can be respectively arranged in regions where the bit lines BL1 to BL4 cross the upper word lines WL21 and WL22. The lower word lines WL11 and WL12, the first memory cells MC1, and the bit lines BL1 to BL4 can constitute the first layer, and the upper word lines WL21 and WL22, the second memory cells MC2, and the bit lines BL1 to BL4 can constitute the second layer. Any of the first memory cells MC1 and the second memory cells MC2 can be addressed by selectively activating the lower word lines WL11 and WL12, the upper word lines WL21 and WL22, and the bit lines BL1 to BL4. Each of the first memory cells MC1 and the second memory cells MC2 can include a variable resistor element R and a switching element SW.

[0060] In the case of the first layer, the variable resistor element R can be connected between one of the bit lines BL1 to BL4 and the switching element SW, and the switching element SW can be connected between the variable resistor element R and one of the lower word lines WL11 and WL12. In the case of the second layer, the variable resistor element R can be connected between one of the upper word lines WL21 and WL22 and the switching element SW, and the switching element SW can be connected between the variable resistor element R and one of the bit lines BL1 to BL4. However, the inventive concept is not limited thereto, and the arrangement order of the switching element SW and the variable resistor element R can be changed.

[0061] The switching element SW can control the current supplied to the variable resistor element R according to the voltage applied to the word line and the bit line connected with the switching element SW. For example, the switching element SW can be implemented with an ovonic threshold switch (OTS) material. However, the inventive concept is not limited thereto, and in another embodiment, the switching element SW can be changed to other switchable elements such as unidirectional diodes, bidirectional diodes, and transistors.

[0062] A voltage can be applied to the variable resistor element R of each of the first memory cell MC1 and the second memory cell MC2 through the lower word lines WL11 and WL12, the upper word lines WL21 and WL22, and the bit lines BL1 to BL4, and thus, the current can flow through the variable resistor element R. For example, the variable resistor element R can include a phase change material layer that can reversibly transition between a first state and a second state. However, the variable resistor element R is not limited thereto, but can include any variable resistor having a resistance value that varies according to the voltage applied. For example, in each of the first memory cell MC1 and the second memory cell MC2, the resistance of the variable resistor element R can reversibly transition between a first state and a second state according to the voltage applied to the variable resistor element R.

[0063] Figure 6B is a perspective view of a memory cell array 110a according to an embodiment. Figure 6A

[0064] Referring to Figure 6B ​The memory cell array 110a can include a lower word line WL1, an upper word line WL2, a bit line BL, a first memory cell MC1, and a second memory cell MC2. The lower word line WL1 can extend in a first direction X and can be arranged in parallel with each other in a second direction Y. In this case, the first direction X and the second direction Y can be substantially orthogonal to each other. The bit line BL can extend in the second direction Y and can be arranged in parallel with each other in the first direction X. The upper word line WL2 can extend in the first direction X and can be arranged in parallel with each other in the second direction Y. The first memory cell MC1 can be arranged in regions where the lower word line WL1 and the bit line BL cross each other, respectively, and the second memory cell MC2 can be arranged in regions where the upper word line WL2 and the bit line BL cross each other, respectively.

[0065] Figure 7 is a flowchart of a method of reading data by a memory device according to an embodiment of the inventive concept.

[0066] Referring to Figure 7 The method according to the present embodiment corresponds to an operation of reading data by a memory device according to a request from a host. For example, the method can include operations performed in the memory device 100 in a time sequence. For example, the memory controller 200 can provide a read command to the memory device 100 according to a request from a host. In operation S10, the memory device 100 receives the read command and decodes an address provided with the read command to determine selected memory cells. For example, the selected memory cells can be a first memory cell arranged in a first layer and a second memory cell arranged in a second layer. Figure 1

[0067] In operation S20, the memory device 100 pre-charges a lower word line connected to one end of the first memory cell and an upper word line connected to one end of the second memory cell. In operation S30, the memory device 100 pre-charges a bit line commonly connected to the other end of the first memory cell and the other end of the second memory cell. In an embodiment, in operation S30, the lower word line and the upper word line can be floated. For example, a particular word line can be floated when a word line selection transistor TRx connected to the particular word line is turned off. However, the inventive concept is not limited thereto. In some embodiments, in operation S30, at least one of row switches connected to the lower word line and the upper word line can be slightly turned on. Operations S20 and S30 will be described later with reference to Figure 8

[0068] ​​In operation S40, the memory device 100 can connect the lower word line to the first data line and the upper word line to the second data line. For example, when the lower word line and the first data line are electrically connected to each other, charge sharing can be performed between the lower word line and the first data line, and the voltage levels of the lower word line and the first data line can be equal to each other. Accordingly, when the first memory cell is in the set state, the voltage level of the first data line can be relatively high, and when the first memory cell is in the reset state, the voltage level of the first data line can be relatively low.

[0069] In operation S50, the memory device 100 can sense data (i.e., data stored in the first memory cell and the second memory cell, respectively) based on the voltage levels of the first data line and the second data line. The memory device 100 can compare the voltage level of the first data line with a reference voltage and output the comparison result as the first data. In this case, the reference voltage can be set to an intermediate level between the voltage level of the first data line when the first memory cell is in the set state and the voltage level of the first data line when the first memory cell is in the reset state. Accordingly, by comparing the voltage level of the first data line with the reference voltage, the comparison result can be output as 1-bit data (e.g., 0 or 1). Similarly, the memory device 100 can perform a similar operation on the voltage level of the second data line with a different reference voltage. However, the inventive concept is not limited thereto. For example, when the first memory cell and the second memory cell are multi-level cells, each of the first memory cell and the second memory cell can have a plurality of states, and in operation S50, the voltage levels of the first data line and the second data line according to the plurality of states of the first memory cell and the second memory cell can be determined. The memory device can read multi-bit data by comparing the voltage levels of the first data line and the second data line with a plurality of reference voltages, respectively.

[0070] Figure 8 is a circuit diagram illustrating components for performing a read operation of a memory device according to an embodiment of the inventive concept.

[0071] Referring to Figure 8 , a word line WL can be connected to one end of a memory cell MC, and a bit line BL can be connected to the other end of the memory cell MC. A row decoder 140 can be connected to the word line WL. For example, the row decoder 140 can include a plurality of row switches such as a word line selection transistor TRx and a discharge transistor TRd. In Figure 8 , for convenience of description, the row decoder 140 is illustrated as including one word line selection transistor TRx and one discharge transistor TRd. However, the row decoder 140 can include a plurality of word line selection transistors TRx and a plurality of discharge transistors TRd connected to a plurality of word lines. Furthermore, the row decoder 140 can further include other switches and / or control elements.

[0072] The word line selection transistor TRx can turn on or off in response to a word line selection signal LX. The word line selection signal LX can be generated from the row decoder 140 based on a row address X_ADDR. When the word line selection transistor TRx is turned on, the word line WL can be connected to the sense amplification block 121 through the data line DL. The sense amplification block 121 can correspond to one of, for example, a first sense amplifier 121a to a fourth sense amplifier 121d. When the word line selection transistor TRx is implemented as an NMOS transistor, the word line selection transistor TRx can turn on when the word line selection signal LX is at a high level, and can turn off when the word line selection signal LX is at a low level. Figure 3

[0073] The discharge transistor TRd can turn on or off in response to a discharge enable signal WDE. When the discharge transistor TRd is turned on, a discharge voltage Vd can be applied to the word line WL. For example, the discharge voltage Vd can be a ground voltage VSS. In an embodiment, the discharge transistor TRd can be implemented as an NMOS transistor. The NMOS transistor—discharge transistor TRd can turn on when the discharge enable signal WDE is at a high level, and can turn off when the discharge enable signal WDE is at a low level. In an embodiment, the discharge transistor TRd can be implemented as a PMOS transistor. The PMOS transistor—discharge transistor TRd can turn on when the discharge enable signal WDE is at a low level, and can turn off when the discharge enable signal WDE is at a high level. For example, in a read operation, when the word line selection transistor TRx connected to a selected word line is turned on, the discharge transistor TRd connected to the selected word line can be turned off. The discharge transistor TRd connected to an unselected word line can be turned on, and the word line selection transistor TRx connected to the unselected word line can be turned off.

[0074] The column decoder 150 can be connected to the bit line BL. For example, the column decoder 150 can include a plurality of column switches such as a bit line selection transistor TRy. In Figure 8 , for ease of description, the column decoder 150 is shown to include one bit line selection transistor TRy. However, the column decoder 150 can include a plurality of bit line selection transistors TRy connected to a plurality of bit lines BL, respectively. In addition, the column decoder 150 can further include a plurality of discharge transistors connected to the plurality of bit lines BL, respectively.

[0075] The bit line selection transistor TRy can be connected to a control switch, for example, a clamp transistor TR CMP and a bit line precharge transistor TRb. The bit line precharge transistor TRb and the clamp transistor TR CMP ​It can be understood as a component of the sense amplifier block 121. The bit line selection transistor TRy is turned on or off in response to the bit line selection signal LY. The bit line selection signal LY can be generated from the column decoder 150 based on the column address Y_ADDR. For example, when the bit line selection transistor TRy is implemented as a PMOS transistor, the bit line selection transistor TRy can be turned on when the bit line selection signal LY is at a low level, and turned off when the bit line selection signal LY is at a high level. The bit line precharge transistor TRb can be turned on or off in response to the bit line precharge enable signal BPE. For example, when the bit line precharge transistor TRb is implemented as a PMOS transistor, the bit line precharge transistor TRb can be turned on when the bit line precharge enable signal BPE is at a low level, and turned off when the bit line precharge enable signal BPE is at a high level. When the bit line precharge transistor TRb is turned on, a second precharge voltage Vp2 can be applied to the bit line BL. In this case, the second precharge voltage Vp2 can be applied to the bit line BL based on the clamping voltage V CMP To control the clamp transistor TR CMP To apply a specific voltage to the bit line BL. In an embodiment, the clamp transistor TR CMP It can be a PMOS transistor or an NMOS transistor. For example, an NMOS transistor—clamp transistor TR CMP The clamping voltage V CMP It is turned on when it is at a high level and is at the clamping voltage V CMP In this case, the clamping voltage V CMP The voltage level of φ may be greater than the voltage level of the bit line BL.

[0076] The sense amplification block 121 may include a word line precharge transistor TRa and a sense amplifier SA. The word line precharge transistor TRa may be turned on or off in response to a word line precharge enable signal WPE. In an example embodiment, the word line precharge transistor TRa may be implemented as a PMOS transistor. The word line precharge transistor TRa—a PMOS transistor—may be turned on when the word line precharge enable signal WPE is at a low level and turned off when the word line precharge enable signal WPE is at a high level. In an example embodiment, the word line precharge transistor TRa may be implemented as an NMOS transistor. The word line precharge transistor TRa—an NMOS transistor—may be turned on when the word line precharge enable signal WPE is at a high level and turned off when the word line precharge enable signal WPE is at a low level. When the word line select transistor TRx and the word line precharge transistor TRa are turned on, a first precharge voltage Vp1 may be applied to the word line WL. In an example embodiment, the voltage level of the precharge voltage applied to the lower word line may be different from the voltage level of the precharge voltage applied to the upper word line. However, the inventive concept is not limited thereto, and the voltage level of the precharge voltage applied to the lower word line may be the same as the voltage level of the precharge voltage applied to the upper word line.

[0077] The word line WL and the bit line BL can each include a parasitic capacitor, and the parasitic capacitor (e.g., word line capacitor C A ) of the word line WL can have a smaller capacitance than the parasitic capacitor (not shown) of the bit line BL. Accordingly, the sense amplifier SA can be connected to the word line WL, which is relatively less affected by the parasitic capacitor, and sense a voltage level of the word line WL, thereby reading data of the selected memory cell MC.

[0078] The sense amplifier SA can compare a sense voltage Vsen of the sense node SN (e.g., a voltage level of the data line DL, in which case the voltage level of the data line DL is the same as the voltage level of the word line WL) with a reference voltage Vref, and output a comparison result as data DATA. For example, the sense amplifier SA can operate as a comparator. When the memory cell MC is in the set state, the sense voltage Vsen can be higher than the reference voltage Vref, and the sense amplifier SA can output '1' as the data DATA. When the memory cell MC is in the reset state, the sense voltage Vsen can be lower than the reference voltage Vref, and the sense amplifier SA can output '0' as the data DATA.

[0079] Hereinafter, a read operation of a memory device will be described with reference to Figure 7 and Figure 8 In operation S20, the word line selection transistor TRx can be turned on to connect the word line WL to the data line DL, and the word line WL and the data line DL can be precharged through a precharge path connected to the data line DL. In operation S30, the bit line selection transistor TRy can be turned on, and thus the bit line BL can be precharged.

[0080] The second pre-charge voltage Vp2 can be higher than the first pre-charge voltage Vp1, and a difference between the first pre-charge voltage Vp1 and the second pre-charge voltage Vp2 can be higher than a threshold voltage of the memory cell MC (e.g., a threshold voltage of the switching element SW). Accordingly, a current (hereinafter, referred to as a "cell current") can flow through the memory cell MC and the cell current can charge the word line WL, and thus, a voltage level of the word line WL can increase. In this case, because an amount of the cell current varies according to a state of the memory cell MC (e.g., according to the set state or the reset state), the voltage level of the word line WL can change according to the state of the memory cell MC. For example, when the memory cell MC is in the set state, because a resistance value of the memory cell MC is relatively small and the amount of the cell current is relatively large, the voltage level of the word line WL can increase relatively large. On the other hand, when the memory cell MC is in the reset state, because the resistance value of the memory cell MC is relatively large and the amount of the cell current is relatively small, the voltage level of the word line WL can increase relatively small or not increase.

[0081] Figure 9 is a graph illustrating a read operation of a memory device according to an embodiment of the inventive concept.

[0082] Referring to Figure 8 and Figure 9 , Figure 9 a horizontal axis of the graph of Figure 9 a vertical axis of the graph of

[0083] The word line WL can be floated in the second pre-charge period T_P2 (e.g., the bit line pre-charge period BL_PRC), and the bit line BL can be pre-charged to a second pre-charge voltage Vp2. For example, the word line WL can be floated when the word line selection transistor TRx and the discharge transistor TRd, which are both connected to the word line WL, are turned off. The bit line selection transistor TRy and the bit line pre-charge transistor TRb can be turned on in the second pre-charge period T_P2, and thus, the second pre-charge voltage Vp2 can be applied to the bit line BL. In an embodiment, the power supply voltage can be applied through the bit line pre-charge transistor TRb, the clamp transistor TRc, and the bit line selection transistor TRy. The bit line pre-charge transistor TRb can be turned on in the second pre-charge period T_P2, and thus, the second pre-charge voltage Vp2 can be applied to the bit line BL. CMP The second pre-charge voltage Vp2 can be determined according to the clamp voltage Vc. CMP The voltage level of the bit line BL can be maintained as the second pre-charge voltage Vp2.

[0084] In the second pre-charge period T_P2, the voltage level of the bit line BL can increase to the second pre-charge voltage Vp2. In this case, when the difference between the voltage level of the bit line BL and the voltage level of the word line WL is equal to or greater than the threshold voltage Vth of the memory cell MC, a cell current can flow in the memory cell MC. When the memory cell MC is in the set state, the voltage level of the word line WL can increase, and the difference between the voltage level of the word line WL and the voltage level of the bit line BL can be maintained above the blocking voltage Vs (i.e., the voltage level at which the cell current of the memory cell MC is blocked). Thus, when the memory cell MC is in the set state, the voltage level of the word line WL can increase until the voltage level obtained by lowering the voltage level of the bit line BL by the blocking voltage Vs. On the other hand, when the memory cell MC is in the reset state, the voltage level of the word line WL can hardly increase or can increase very little.

[0085] In some embodiments, in the second pre-charge period T_P2, the second pre-charge voltage Vp2 can be pre-charged to the bit line BL while the word line selection transistor TRx is slightly turned on. In this case, the word line WL can be pseudo-floated as the word line selection transistor TRx is slightly turned on. For example, the word line selection transistor TRx can be slightly turned on when the word line selection signal LX has a certain voltage level between the voltage level of the high level and the voltage level of the low level. Thus, when the selected memory cell is in the set state, the data line DL is slightly charged in the second pre-charge period T_P2. As described above, the word line selection transistor TRx can be turned on when the word line selection signal LX is at the high level, and can be turned off when the word line selection signal LX is at the low level.

[0086] The word line selection transistor TRx can be turned on in a sensing time period T_S (e.g., a data sensing time period DL_Sensing), and thus, the word line WL and the data line DL can be electrically connected to each other and the charge sharing can be performed. In an embodiment, in a bit line discharge time period (not shown) between the second pre-charge time period T_P2 and the sensing time period T_S, the bit line BL can be discharged to a certain voltage (i.e., a ground voltage VSS). For example, a bit line discharge circuit connected to the bit line BL can discharge the voltage of the bit line BL during the bit line discharge time period. The charge sharing can be performed after the bit line discharge time period in the sensing time period T_S. The voltage level of the word line WL can be the same as that of the data line DL through the charge sharing, and the voltage level of the word line WL can be changed as shown in Figure 9 FIG. 2B. When the charge sharing is completed, the data can be sensed based on the voltage level of the data line DL (e.g., a sensing voltage Vsen). The sense amplifier SA can sense the data by comparing the reference voltage Vref with the sensing voltage Vsen.

[0087] In the course of the charge sharing, especially when the memory cell MC is in the set state, the voltage level of the word line WL can be lowered through the charge sharing. In this case, when the amount of lowering is large, the sensing margin of the sense amplifier SA can be reduced. However, because the word line selection transistor TRx is slightly turned on in the second pre-charge time period T_P2 and thus the drain current of the word line selection transistor TRx charges the data line DL, the effect such as the increase of the capacitance of the word line capacitor C A may occur. Accordingly, when the memory cell MC is in the set state, the amount of change of the voltage level of the word line WL can be reduced, thereby sufficiently securing the sensing margin SM.

[0088] Figure 10 is a timing diagram illustrating a read operation for the first memory cell MC1 and the second memory cell MC2 according to an embodiment of the inventive concept.

[0089] Referring to Figure 3 , Figure 6A and Figures 8-10 together, the first memory cell MC1 and the second memory cell MC2 can share the bit line BL1, which can be driven by a bit line selection signal LY. In addition, the first lower word line WL11 connected to the first memory cell MC1 and the first upper word line WL21 connected to the second memory cell MC2 can be driven by the same word line selection signal LX. Accordingly, the read operation for the first memory cell MC1 and the read operation for the second memory cell MC2 can be performed in parallel and can be performed substantially at the same time. Hereinafter, the word line selection transistor connected to the first lower word line WL11 is referred to as a lower word line selection transistor (e.g., TRx1), and the word line selection transistor connected to the first upper word line WL21 is referred to as an upper word line selection transistor (e.g., TRx2). Figure 22The word line selection transistor connected to the first upper word line WL21 is referred to as an upper word line selection transistor (eg, Figure 22 The second row of switches 721 in FIG.

[0090] In the standby period STB from time t0 to time t1, the word line selection signal LX may be at a low level and the bit line selection signal LY may be at a high level. Figure 22 The first row switch 711 in the upper word line select transistor (eg, Figure 22 The second row switch 721 in the bit line selection transistor TRy can be turned off. The first lower word line WL11 and the first upper word line WL21 can be floated or have a voltage level of the ground voltage VSS. For example, the first lower word line WL11 and the first upper word line WL21 can be turned off by Figure 8 The discharge transistor TRd is turned on and has the ground voltage VSS.

[0091] Thereafter, at time t1, the word line select signal LX may be transitioned to a high level, and the first lower word line WL11 and the first upper word line WL21 may be precharged based on the first precharge voltage Vp1. In this case, the time period from time t1 to time t2 may be defined as a word line precharge period WL_PRC. The first precharge voltage Vp1 may be a negative voltage. Therefore, the voltage level VWL11 of the first lower word line WL11 and the voltage level VWL21 of the first upper word line WL21 may decrease. In an embodiment, the voltage level of the precharge voltage applied to the first lower word line WL11 and the voltage level of the precharge voltage applied to the first upper word line WL21 may be different from each other. However, the inventive concept is not limited thereto, and the voltage level of the precharge voltage applied to the lower word line WL11 may be the same as the voltage level of the precharge voltage applied to the upper word line WL21.

[0092] At time t2, the bit line selection signal LY can transition to low, and the bit line BL1 can be pre-charged based on a second pre-charge voltage Vp2. In this case, a time period from time t2 to time t4 can be defined as a bit line pre-charge time period BL PRC. The second pre-charge voltage Vp2 can be higher than the first pre-charge voltage Vp2 and can be a positive voltage. In an embodiment, the word line selection signal LX can transition to low (i.e., an off level Voff), and thus, the first lower word line WL11 and the first upper word line WL21 can be floated. In an embodiment, the word line selection signal LX can transition to a weak on level Vwo, where the weak on level Vwo can be higher than the low level (i.e., the off level Voff) of the word line selection signal LX and can be lower than the high level (i.e., the on level Von) of the word line selection signal LX. The lower word line selection transistor and the upper word line selection transistor can be slightly turned on based on the word line selection signal LX having the weak on level Vwo, and thus, the first lower word line WL11 and the first upper word line WL21 can be pseudo-floated.

[0093] As described above, when the difference between the voltage level of the bit line BL1 and the voltage level of the first lower word line WL11 (e.g., at time t3) is equal to or greater than the threshold voltage of the first memory cell MC1, a cell current can flow through the first memory cell MC1. Similarly, when the difference between the voltage level of the bit line BL1 and the voltage level of the first upper word line WL21 (e.g., at time t3) is equal to or higher than the threshold voltage of the second memory cell MC2, a cell current can flow through the second memory cell MC2. For example, the first memory cell MC1 in the set state can have a larger amount of cell current than the amount of cell current of the second memory cell MC2 in the reset state, and as the cell current charges the parasitic capacitor C A of the first lower word line WL11, the voltage level VWL11 of the first lower word line WL11 can increase. In this case, when the lower word line selection transistor is slightly turned on, the voltage level of the data line DL can increase as the drain current of the lower word line selection transistor charges the capacitor C DL of the data line DL. In the case that the second memory cell MC2 is in the reset state, the voltage level VWL21 of the first upper word line WL21 can increase very little or can hardly increase.

[0094] At time t4, as the bit line selection signal LY and the word line selection signal LX transition to high levels, the bit line selection transistor TRy is turned off and the lower word line selection transistor is turned on, the first lower word line WL11 can be electrically connected to the first data line DL1 corresponding thereto, and thus, charge sharing can be performed between the first lower word line WL11 and the first data line DL1. Since the voltage level of the first data line DL1 is lower than that of the first lower word line WL11, the voltage level of the first lower word line WL11 decreases and the voltage level of the first data line DL1 increases, and thus, the voltage levels of the first lower word line WL11 and the first data line DL1 can be the same. Thereafter, data sensing for the first memory cell MC1 can be performed from time t5 to time t6, i.e., in a data sensing time period.

[0095] Similarly, at time t4, as the word line selection signal LX transitions to a high level and the upper word line selection transistor is turned on, the first upper word line WL21 can be electrically connected to the second data line DL2 corresponding thereto, and thus, charge sharing can be performed between the first upper word line WL21 and the second data line DL2. Since the voltage level of the second data line DL2 is the same as that of the first upper word line WL21, the voltage level of the first upper word line WL21 can be maintained. Thereafter, data sensing for the second memory cell MC2 can be performed from time t5 to time t6, i.e., in a data sensing time period.

[0096] As described above, according to the present embodiment, the data read operation for the first memory cell MC1 and the data read operation for the second memory cell MC2 can be performed in parallel based on one word line selection signal LX and one bit line selection signal LY. Thus, the read speed for the first memory cell MC1 and the second memory cell MC2 can be improved, and the read power consumption of the memory device including the first memory cell MC1 and the second memory cell MC2 can be reduced.

[0097] Figure 11 is a timing diagram illustrating a read operation for the first memory cell MC1 and the second memory cell MC2 according to an embodiment of the inventive concept. Referring to Figure 11 , the read operation for the first memory cell MC1 and the second memory cell MC2 according to the present embodiment corresponds to a variation of the read operation shown in Figure 10 . When the read operation according to the present embodiment is compared with the read operation of Figure 10 , the voltage level of the word line selection signal LX in the bit line pre-charge time period BL_PRC according to the present embodiment can be different from that in the bit line pre-charge time period BL_PRC of the read operation of Figure 10

[0098] ​At time t2, the bit line selection signal LY can transition to a low level, and the bit line BL1 can be pre-charged based on the second pre-charge voltage VP2. Also, at time t2, the word line selection signal LX can transition to a weakly on level Vwo, and at time t4, the word line selection signal LX can transition to a low level Voff. Accordingly, the lower word line selection transistor and the upper word line selection transistor can be slightly on in a part of the bit line pre-charge period BL_PRC, and be off in the remaining period. In this case, the period from time t2 to time t4 can be adjusted based on the capacitance of the word line capacitor C A . For example, as the capacitance of the word line capacitor C A increases, the period in which the word line selection transistor TRx is slightly on in the bit line pre-charge period BL_PRC can decrease.

[0099] Figure 12 A memory device 300 having a periphery over cell (COP) structure according to an embodiment of the inventive concept is illustrated.

[0100] Referring to Figure 12 , the memory device 300 can include a first semiconductor layer 310 and a second semiconductor layer 320 stacked in a vertical direction Z. The first semiconductor layer 310 can include a first layer 310a and a second layer 310b. In some embodiments, the first semiconductor layer 310 can further include one or more layers on the second layer 310b. The first layer 310a can include a lower word line WL1, the second layer 310b can include an upper word line WL2, and the first layer 310a and the second layer 310b can share a bit line BL.

[0101] The first layer 310a can further include first memory cells respectively arranged in regions where the lower word line WL1 and the bit line BL intersect, and the second layer 310b can further include second memory cells respectively arranged in regions where the upper word line WL2 and the bit line BL intersect. A peripheral region including a peripheral circuit can be arranged on and in the second semiconductor layer 320. For example, a write / read circuit (e.g., a write driver / sense amplifier WD / SA) 321 and a control logic 322 can be arranged on and in the second semiconductor layer 320. However, the inventive concept is not limited thereto, and various types of peripheral circuits related to memory operations can be arranged on and in the second semiconductor layer 320.

[0102] Figure 13 A top surface of the second semiconductor layer 420 in a memory device 400 having a COP structure according to an embodiment of the inventive concept is illustrated. Figure 14 ) is illustrated. Figure 14 is along Figure 13A cross-sectional view of the memory device 400 taken along line XIV-XIV′ in FIG. Figure 15 It is along Figure 13 4 is a cross-sectional view of the memory device 400 taken along line XV-XV′ in FIG.

[0103] Refer to it together Figures 13-15 The memory device 400 having a COP structure may include a first semiconductor layer 410 and a second semiconductor layer 420 that are vertically stacked, and a top surface of the second semiconductor layer 420 may be divided into first to fifth regions 421 to 425. The first region 421 and the second region 422 may be adjacent to each other in a first direction X, and the third region 423 and the fourth region 424 may be adjacent to each other in the first direction X. The fifth region 425 may be arranged at a central portion of an upper surface of the second semiconductor layer 420, and a column decoder CD for driving a bit line BL may be arranged in the fifth region 425.

[0104] A first row decoder RD1 for driving the lower word line WL1, a first global decoder GD1 for driving the global lower word line connected to the lower word line WL1, and a lower sense amplifier SA1 for sensing the first memory cell MC1 may be arranged in the first area 421 and the fourth area 424. A second row decoder RD2 for driving the upper word line WL2, a second global decoder GD2 for driving the global upper word line connected to the upper word line WL2, and an upper sense amplifier SA2 for sensing the second memory cell MC2 may be arranged in the second area 422 and the third area 423.

[0105] The first lower word line WL11 and the first upper word line WL21 may extend in a first direction X, and the bit lines BL may extend in a second direction Y. Each first row decoder RD1 may include a first row switch TRx1, each first global decoder GD1 may include a first global switch TRgx1, each second row decoder RD2 may include a second row switch TRx2, and each second global decoder GD2 may include a second global switch TRgx2. In this case, the first row switch TRx1 and the second row switch TRx2 may be driven by the word line select signal LX0, and the first global switch TRgx1 and the second global switch TRgx2 may be driven by the global word line select signal GX0. Therefore, a read operation can be performed simultaneously on the first memory cell MC1 and the second memory cell MC2 connected to the bit line BL. As described above, memory cells driven by the same word line select signal and the same global word line select signal and read simultaneously can be defined as a sense amplifier group. For example, the memory device 400 may include first to fourth sense amplifier groups SAG1 to SAG4.

[0106] The first row decoder RD1 may be connected to the lower word line WL1 through a first contact plug CP1 and may be electrically connected to the first global decoder GD1 and the first sense amplifier SA1 through a contact plug CP and a metal pattern MP. The second row decoder RD2 may be connected to the upper word line WL2 through a second contact plug CP2 and may be electrically connected to the second global decoder GD2 and the second sense amplifier SA2 through a contact plug CP and a metal pattern MP. The column decoder CD may be connected to the bit line BL through a third contact plug CP3.

[0107] Figure 16 A memory device 500 having a COP structure according to an embodiment of the inventive concept is shown (see FIG. Figure 17 ) in the top surface of the second semiconductor layer 520. Figure 17 It is along Figure 16 A cross-sectional view of the memory device 500 taken along line XVII-XVII′ in FIG. Figure 18 It is along Figure 16 A cross-sectional view of the memory device 500 taken along line XVIII-XVIII′ in FIG. Figure 19 It is along Figure 16 A cross-sectional view of the memory device 500 taken along line XIX-XIX′ in FIG. Figure 20 It is along Figure 16 5 is a cross-sectional view of the memory device 500 taken along line XX-XX′.

[0108] Refer to it together Figures 16-20 The memory device 500 having a COP structure may include a first semiconductor layer 510 and a second semiconductor layer 520 stacked vertically, and the top surface of the second semiconductor layer 520 may be divided into a first tile region 521 and a second tile region 522. The first memory array (i.e., the first tile) may be arranged on top relative to the first tile region 521 in the vertical direction Z, and the second memory array (i.e., the second tile) may be arranged on top relative to the second tile region 522 in the vertical direction Z. Therefore, the structure of the first tile region 521 may be substantially the same as that of the second tile region 522. Hereinafter, the first tile region 521 will be mainly described.

[0109] The first tile area 521 can be divided into a first area 521a to a fourth area 521d. For example, the first tile area 521 can be divided into the first area 521a to the fourth area 521d according to a windmill structure. The first area 521a and the second area 521b can be adjacent to each other in a first direction X, and the third area 521c and the fourth area 521d can be adjacent to each other in the first direction X. The first area 521a and the third area 521c can be adjacent to each other in a second direction Y, and the second area 521b and the fourth area 521d can be adjacent to each other in the second direction Y. Hereinafter, components arranged in the first area 521a and the second area 521b will be mainly described.

[0110] In the first area 521a, a first row decoder RD1 for driving a lower word line WL1, a first global decoder GD1 for driving a global lower word line connected to the lower word line WL1, a first sense amplifier SA1 for sensing a first memory cell MC1, a second sense amplifier SA2 for sensing a second memory cell MC2, a second global decoder GD2 for driving a global upper word line connected to an upper word line WL2, and a second row decoder RD2 for driving the upper word line WL2 can be arranged in a row in the first direction X.

[0111] In the second area 521b, a first peripheral circuit PERI1, a global decoder GY, and a column decoder CD can be arranged in a row in the second direction Y. The column decoder CD is a circuit for driving a bit line BL, and the global decoder GY is a circuit for driving a global bit line connected to the bit line BL. The first peripheral circuit PERI1 can include, for example, a write driver (for example, a write driver 122 in Figure 2 However, the inventive concept is not limited thereto.

[0112] The first row decoder RD1 can be connected to the lower word line WL1 through a first contact plug CP1, and can be electrically connected to the first global decoder GD1 and the first sense amplifier SA1 through a contact plug CP and a metal pattern MP. The second row decoder RD2 can be connected to the upper word line WL2 through a second contact plug CP2, and can be electrically connected to the second global decoder GD2 and the second sense amplifier SA2 through the contact plug CP and the metal pattern MP. The column decoder CD can be connected to the bit line BL through a third contact plug CP3.

[0113] Figure 21 A memory device 600 according to an embodiment of the inventive concept is illustrated. Referring to Figure 21 The memory device 600 can include first to fourth memory arrays, for example, first to fourth tiles TL1 to TL4, which can be arranged in a row in a first direction X. The first to fourth tiles TL1 to TL4 can be based on the above-described first to fourth tiles 521 to 524, respectively.Figures 1-4 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B and Figures 7-20 The first to fourth tiles TL1 to TL4 can be implemented according to the embodiments described above. For example, each of the first to fourth tiles TL1 to TL4 can correspond to the first semiconductor layer 310 of Figure 12 .

[0114] Each of the first to fourth tiles TL1 to TL4 can include a first layer L1 and a second layer L2 stacked vertically, the first layer L1 and the second layer L2 can share a bit line. In addition, a word line selection transistor in each of the first layer L1 and the second layer L2 can be driven by the same word line selection signal LX0. Accordingly, a read operation can be performed in parallel on eight memory cells in each of the first to fourth tiles TL1 to TL4 by controlling a voltage of the word line selection signal LX0. Accordingly, a read speed for the eight memory cells can be improved, and a read power consumption of the memory device 600 can be reduced.

[0115] Figure 22 A memory device 700 according to an embodiment of the inventive concept is illustrated.

[0116] Referring to Figure 22 , the memory device 700 can include a second row decoder (RD2) 720, a second sense amplifier (SA2) 740, a first sense amplifier (SA1) 730, and a first row decoder (RD1) 710 arranged in a row in a first direction X. In an embodiment, the memory device 700 can have a COP structure, the second row decoder 720, the second sense amplifier 740, the first sense amplifier 730, and the first row decoder 710 can be arranged under a first memory cell MC1 and a second memory cell MC2 in a vertical direction Z.

[0117] A lower word line WL1 and an upper word line WL2 can extend in the first direction X, the upper word line WL2 can be arranged above the lower word line WL1 in the vertical direction Z. A bit line BL can extend in a second direction Y. The first memory cell MC1 can be arranged in an area where the lower word line WL1 and the bit line BL cross, the second memory cell MC2 can be arranged in an area where the upper word line WL2 and the bit line BL cross.

[0118] The first row decoder 710 can include a first row switch 711, the first row switch 711 can be implemented as a transistor having a gate to which a word line selection signal LX0 is applied. For example, the first row switch 711 can have a source connected to the lower word line WL1 and a drain connected to the first sense amplifier 730. According to an embodiment, the first global decoder (e.g., the global decoder 810 of FIG. 8) can be implemented as a plurality of transistors having gates to which a plurality of word line selection signals LX0 to LX7 are applied. Figure 13 orFigure 15 The first global decoder GD1 in the first row decoder 710 and the first sense amplifier 730 can be arranged.

[0119] The second row decoder 720 can include a second row switch 721, which can be implemented as a transistor having a gate to which a word line selection signal LX0 is applied. For example, the second row switch 721 can have a source connected to an upper word line WL2 and a drain connected to the second sense amplifier 740. According to embodiments, a second global decoder (e.g., GD2 in FIG. 8) can be arranged between the second row decoder 720 and the second sense amplifier 740. Figure 13 or Figure 15 The second global decoder GD2 in the second row decoder 720 and the second sense amplifier 740 can be arranged.

[0120] Figure 23 A memory device 800 according to embodiments of the inventive concepts is shown.

[0121] Referring to Figure 23 The memory device 800 can include first row decoders 810a and 810b, second row decoders 820a and 820b, first sense amplifiers 830a and 830b, and second sense amplifiers 840a and 840b. The second row decoder 820a, the second sense amplifier 840a, the first sense amplifier 830a, and the first row decoder 810a can be arranged in a row in the first direction X. The second row decoder 820b, the second sense amplifier 840b, the first sense amplifier 830b, and the first row decoder 810b can be arranged in a row in the first direction X. In embodiments, the memory device 800 can have a COP structure, and the first row decoders 810a and 810b, the second row decoders 820a and 820b, the first sense amplifiers 830a and 830b, the second sense amplifiers 840a and 840b can be arranged under the first memory cells MC1a and MC1b and the second memory cells MC2a and MC2b in the vertical direction Z.

[0122] The lower word lines WL11 and WL12 and the upper word lines WL21 and WL22 can extend in the first direction X. The upper word lines WL21 and WL22 can be arranged above the lower word lines WL11 and WL12, respectively, in the vertical direction Z. The bit lines BL can extend in the second direction Y. The first memory cell MC1a can be arranged in an area where the lower word line WL11 and the bit line BL intersect, and the second memory cell MC2a can be arranged in an area where the upper word line WL21 and the bit line BL intersect.

[0123] The first row decoder 810a can include a first row switch 811, which can be implemented as a transistor having a gate to which a first word line selection signal LX1 is applied. For example, the first row switch 811 can have a source connected to a lower word line WL11 and a drain connected to a first sense amplifier 830a. The first row decoder 810b can include a first row switch 812, which can be implemented as a transistor having a gate to which the first word line selection signal LX1 is applied. For example, the first row switch 812 can have a source connected to a lower word line WL12 and a drain connected to a first sense amplifier 830b. According to driving of the first word line selection signal LX1, the first row switches 811 and 812 can be simultaneously driven, and a read operation on the first memory cells MC1a and MC1b can be performed in parallel by using the first sense amplifiers 830a and 830b.

[0124] The second row decoder 820a can include a second row switch 821, which can be implemented as a transistor having a gate to which a second word line selection signal LX2 is applied. For example, the second row switch 821 can have a source connected to an upper word line WL21 and a drain connected to a second sense amplifier 840a. The second row decoder 820b can include a second row switch 822, which can be implemented as a transistor having a gate to which the second word line selection signal LX2 is applied. For example, the second row switch 822 can have a source connected to an upper word line WL22 and a drain connected to a second sense amplifier 840b. According to driving of the second word line selection signal LX2, the second row switches 821 and 822 can be simultaneously driven, and a read operation on the second memory cells MC2a and MC2b can be performed in parallel by using the second sense amplifiers 840a and 840b.

[0125] According to an embodiment, a first global decoder (e.g., the first global decoder GD1 in the memory device 1000 of FIG. 10) can be disposed between the first row decoder 810a and the first sense amplifier 830a and between the first row decoder 810b and the first sense amplifier 830b. In addition, according to an embodiment, a second global decoder (e.g., the second global decoder GD2 in the memory device 1000 of FIG. 10) can be disposed between the second row decoder 820a and the second sense amplifier 840a and between the second row decoder 820b and the second sense amplifier 840b. Figure 13 Figure 15 According to an embodiment, a first global decoder (e.g., the first global decoder GD1 in the memory device 1000 of FIG. 10) can be disposed between the first row decoder 810a and the first sense amplifier 830a and between the first row decoder 810b and the first sense amplifier 830b. In addition, according to an embodiment, a second global decoder (e.g., the second global decoder GD2 in the memory device 1000 of FIG. 10) can be disposed between the second row decoder 820a and the second sense amplifier 840a and between the second row decoder 820b and the second sense amplifier 840b. Figure 13 Figure 15 According to an embodiment, a first global decoder (e.g., the first global decoder GD1 in the memory device 1000 of FIG. 10) can be disposed between the first row decoder 810a and the first sense amplifier 830a and between the first row decoder 810b and the first sense amplifier 830b. In addition, according to an embodiment, a second global decoder (e.g., the second global decoder GD2 in the memory device 1000 of FIG. 10) can be disposed between the second row decoder 820a and the second sense amplifier 840a and between the second row decoder 820b and the second sense amplifier 840b.

[0126] ​​As such, the memory device 800 can include four sense amplifiers, e.g., first sense amplifiers 830a and 830b and second sense amplifiers 840a and 840b, through which read operations for four memory cells, e.g., first memory cells MC1a and MC1b and second memory cells MC2a and MC2b, can be performed in parallel by controlling the first word line selection signal LX1 and the second word line selection signal LX2. Accordingly, read speed for the first memory cells MC1a and MC1b and the second memory cells MC2a and MC2b can be improved, and read power consumption of the memory device 800 can be reduced. In some examples, the first word line selection signal LX1 and the second word line selection signal LX2 can be generated based on an address related to a same page of the memory cell array. In some examples, each of the first word line selection signal LX1 and the second word line selection signal LX2 can be generated based on different addresses in a particular mode of the memory device. In this case, the read operation of the first memory cells MC1a and MC1b and the read operation of the second memory cells MC2a and MC2b can be performed independently.

[0127] Figure 24 A memory device 900 according to an embodiment of the inventive concepts is shown.

[0128] Referring to Figure 24 The memory device 900 can include first row decoders 910a and 910b, second row decoders 920a and 920b, first sense amplifiers 930a and 930b, and second sense amplifiers 940a and 940b. The second row decoder 920a, the second sense amplifier 940a, the first sense amplifier 930a, and the first row decoder 910a can be arranged in a row in the first direction X. The second row decoder 920b, the second sense amplifier 940b, the first sense amplifier 930b, and the first row decoder 910b can be arranged in a row in the first direction X. In an embodiment, the memory device 900 can have a COP structure, and the first row decoders 910a and 910b, the second row decoders 920a and 920b, the first sense amplifiers 930a and 930b, the second sense amplifiers 940a and 940b can be arranged under the first memory cells MC1a and MC1b and the second memory cells MC2a and MC2b in a vertical direction Z.

[0129] The first row decoder 910a may include a first row switch 911, which may be implemented as a transistor having a gate to which a first word line select signal LX1 is applied. For example, the first row switch 911 may have a source connected to the lower word line WL11 and a drain connected to the first sense amplifier 930a. The first row decoder 910b may include a first row switch 912, which may be implemented as a transistor having a gate to which a first word line select signal LX1′ is applied. For example, the first row switch 912 may have a source connected to the lower word line WL12 and a drain connected to the first sense amplifier 930b. Based on the driving of the first word line select signals LX1 and LX1′, the first row switches 911 and 912 may be driven simultaneously, and read operations for the first memory cells MC1a and MC1b may be performed in parallel using the first sense amplifiers 930a and 930b.

[0130] The second row decoder 920a may include a second row switch 921, which may be implemented as a transistor having a gate to which the second word line select signal LX2 is applied. For example, the second row switch 921 may have a source connected to the upper word line WL21 and a drain connected to the second sense amplifier 940a. The second row decoder 920b may include a second row switch 922, which may be implemented as a transistor having a gate to which the second word line select signal LX2′ is applied. For example, the second row switch 922 may have a source connected to the upper word line WL22 and a drain connected to the second sense amplifier 940b. Based on the driving of the second word line select signals LX2 and LX2′, the second row switches 921 and 922 may be driven simultaneously, and read operations for the second memory cells MC2a and MC2b may be performed in parallel using the second sense amplifiers 940a and 940b.

[0131] According to an embodiment, a first global decoder (e.g. Figure 13 or Figure 15 The first global decoder GD1 in the embodiment may be arranged between the first row decoder 910a and the first sense amplifier 930a and between the first row decoder 910b and the first sense amplifier 930b. In addition, according to an embodiment, the second global decoder (e.g., Figure 13 or Figure 15 The second global decoder GD2 in FIG. 1 may be disposed between the second row decoder 920a and the second sense amplifier 940a and between the second row decoder 920b and the second sense amplifier 940b.

[0132] As such, the memory device 900 can include four sense amplifiers, i.e., the first sense amplifiers 930a and 930b and the second sense amplifiers 940a and 940b, and the read operation for the four memory cells, i.e., the first memory cells MC1a and MC1b and the second memory cells MC2a and MC2b, can be performed in parallel by controlling the first word line selection signals LX1 and LX1’ and the second word line selection signals LX2 and LX2’. Accordingly, the read speed for the first memory cells MC1a and MC1b and the second memory cells MC2a and MC2b can be improved. In some examples, the first word line selection signals LX1 and LX1’ and the second word line selection signals LX2 and LX2’ can be generated based on an address related to a same page of the memory cell array. In some examples, each of the first word line selection signals LX1 and LX1’ and the second word line selection signals LX2 and LX2’ can be generated based on a different address in a specific mode of the memory device. In this case, the read operation for each of the first memory cells MC1a and MC1b and the second memory cells MC2a and MC2b can be performed independently.

[0133] Figure 25 is a block diagram illustrating an example in which a memory device according to some embodiments of the inventive concept is applied to a solid state drive (SSD) system 1000. Referring to Figure 25 , the SSD system 1000 can include a host 1100 and an SSD 1200. The SSD 1200 can exchange signals SGL with the host 1100 through a signal connector and receive power PWR through a power connector. The SSD 1200 can include an SSD controller 1210, an auxiliary power supply 1220, and memory devices (MEMs) 1230, 1240, and 1250. The SSD controller 1210 can communicate with the memory devices 1230, 1240, and 1250 through channels Ch1, Ch2, and Chn, respectively. The memory devices 1230, 1240, and 1250 can be implemented using the embodiments described above with reference to Figures 1-4 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B and Figures 7-24 .

[0134] Figure 26 is a block diagram illustrating a memory device having a chip-to-chip structure according to some embodiments of the inventive concept.

[0135] Referring to Figure 26, the memory device 2000 may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a cell area CELL on a first wafer, manufacturing a lower chip including a peripheral circuit area PERI on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip in a bonding manner. For example, the bonding method may include a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal may be formed of copper (Cu), the bonding method may be Cu-Cu bonding, and the bonding metal may also be formed of aluminum or tungsten.

[0136] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 2000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0137] The peripheral circuit region PERI may include a first substrate 2110, an interlayer insulating layer 2115, a plurality of circuit elements 2120a, 2120b, and 2120c formed on the first substrate 2110, first metal layers 2130a, 2130b, and 2130c connected to the plurality of circuit elements 2120a, 2120b, and 2120c, respectively, and second metal layers 2140a, 2140b, and 2140c formed on the first metal layers 2130a, 2130b, and 2130c. In example embodiments, the first metal layers 2130a, 2130b, and 2130c may be formed of tungsten having a relatively high resistance, and the second metal layers 2140a, 2140b, and 2140c may be formed of copper having a relatively low resistance.

[0138] exist Figure 26 In the example embodiment shown in , although the first metal layers 2130a, 2130b, and 2130c and the second metal layers 2140a, 2140b, and 2140c are shown and described, they are not limited thereto, and one or more metal layers may be formed on the second metal layers 2140a, 2140b, and 2140c. At least a portion of the one or more metal layers formed on the second metal layers 2140a, 2140b, and 2140c may be formed of aluminum or the like having a lower resistance than the copper forming the second metal layers 2140a, 2140b, and 2140c.

[0139] An interlayer insulating layer 2115 may be provided on the first substrate 2110 and cover the plurality of circuit elements 2120a, 2120b, and 2120c, the first metal layers 2130a, 2130b, and 2130c, and the second metal layers 2140a, 2140b, and 2140c. The interlayer insulating layer 2115 may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0140] Lower junction metals 2171b and 2172b can be formed on the second metal layer 2140b in a word line junction area WLBA. In the word line junction area WLBA, the lower junction metals 2171b and 2172b in the peripheral circuit region PERI can be electrically connected to the upper junction metals 2271b and 2272b in the cell region CELL in a junction manner, the lower junction metals 2171b and 2172b and the upper junction metals 2271b and 2272b can be formed of aluminum, copper, tungsten, or the like. In addition, the upper junction metals 2271b and 2272b in the cell region CELL can be referred to as first metal pads, and the lower junction metals 2171b and 2172b in the peripheral circuit region PERI can be referred to as second metal pads.

[0141] The cell region CELL can include at least one memory block. The cell region CELL can include a second base 2210 and a common source line 2220. On the second base 2210, a plurality of word lines 2231 to 2238 (i.e., 2230) can be stacked in a direction (Z direction) perpendicular to an upper surface of the second base 2210. At least one string selection line can be disposed above the plurality of word lines 2230, and at least one ground selection line can be disposed below the plurality of word lines 2230, and the plurality of word lines 2230 can be disposed between the at least one string selection line and the at least one ground selection line.

[0142] In the bit line junction area BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second base 2210 and pass through the plurality of word lines 2230, the at least one string selection line, and the at least one ground selection line. The channel structure CH can include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer can be electrically connected to a first metal layer 2250c and a second metal layer 2260c. For example, the first metal layer 2250c can be a bit line contact, and the second metal layer 2260c can be a bit line. In an example embodiment, the bit line 2260c can extend in a first direction (Y direction) parallel to the upper surface of the second base 2210.

[0143] In the example embodiment shown in Figure 26 In the example embodiment shown in

[0144] In the word line bonding region WLBA, the plurality of word lines 2230 can extend in a second direction (X direction) parallel to the upper surface of the second base 2210, and can be connected to the plurality of cell contact plugs 2241 to 2247 (i.e., 2240). The plurality of word lines 2230 and the plurality of cell contact plugs 2240 can be connected to each other in pads provided by at least portions of the plurality of word lines 2230 extending in the second direction at different lengths. The first metal layer 2250b and the second metal layer 2260b can be sequentially connected to upper portions of the plurality of word lines 2230 connected to the plurality of cell contact plugs 2240. The plurality of cell contact plugs 2240 can be connected to the circuit region PERI through the upper bonding metals 2271b and 2272b of the cell region CELL and the lower bonding metals 2171b and 2172b of the peripheral circuit region PERI in the word line bonding region WLBA.

[0145] The plurality of cell contact plugs 2240 can be electrically connected to the circuit elements 2120b providing the row decoders 2294 in the peripheral circuit region PERI. In an example embodiment, the operating voltage of the circuit elements 2120b providing the row decoders 2294 can be different from the operating voltage of the circuit elements 2120c providing the page buffer 2293. For example, the operating voltage of the circuit elements 2120c providing the page buffer 2293 can be greater than the operating voltage of the circuit elements 2120b providing the row decoders 2294.

[0146] The common source line contact plug 2280 can be disposed in the external pad bonding region PA. The common source line contact plug 2280 can be formed of an electrically conductive material such as a metal, a metal compound, polysilicon, etc., and can be electrically connected to the common source line 2220. The first metal layer 2250a and the second metal layer 2260a can be sequentially stacked on an upper portion of the common source line contact plug 2280. For example, a region in which the common source line contact plug 2280, the first metal layer 2250a, and the second metal layer 2260a are disposed can be defined as the external pad bonding region PA.

[0147] The input-output pads 2105 and 2205 can be disposed in the external pad bonding region PA. Referring to FIG. 21, the input-output pads 2105 and 2205 can be disposed in the external pad bonding region PA. The input-output pads 2105 and 2205 can be electrically connected to the circuit elements 2120a providing the input-output pads 2105 and 2205 in the peripheral circuit region PERI. Figure 26A lower insulating film 2101 covering a lower surface of the first base 2110 can be formed under the first base 2110, and a first input-output pad 2105 can be formed on the lower insulating film 2101. The first input-output pad 2105 can be connected to at least one of the plurality of circuit elements 2120a, 2120b, and 2120c disposed in the peripheral circuit region PERI through a first input-output contact plug 2103, and can be separated from the first base 2110 by the lower insulating film 2101. In addition, a side insulating film can be disposed between the first input-output contact plug 2103 and the first base 2110 to electrically separate the first input-output contact plug 2103 from the first base 2110.

[0148] Referring to Figure 26 An upper insulating film 2201 covering an upper surface of the second base 2210 can be formed on the second base 2210, and a second input-output pad 2205 can be disposed on the upper insulating film 2201. The second input-output pad 2205 can be connected to at least one of the plurality of circuit elements 2120a, 2120b, and 2120c disposed in the peripheral circuit region PERI through a second input-output contact plug 2203. For example, the second input-output contact plug 2203 can be connected to the circuit element 2120a through lower bonding metals 2171a and 2172a.

[0149] According to an embodiment, the second base 2210 and the common source line 2220 can not be disposed in a region in which the second input-output contact plug 2203 is disposed. In addition, the second input-output pad 2205 can not overlap the word line 2230 in the third direction (Z direction). Referring to Figure 26 The second input-output contact plug 2203 can be separated from the second base 2210 in a direction parallel to the upper surface of the second base 2210, and can pass through the interlayer insulating layer 2215 of the cell region CELL to be connected to the second input-output pad 2205.

[0150] According to an embodiment, the first input-output pad 2105 and the second input-output pad 2205 can be selectively formed. For example, the memory device 2000 can include only the first input-output pad 2105 disposed on the first base 2110 or the second input-output pad 2205 disposed on the second base 2210. Alternatively, the memory device 2000 can include both the first input-output pad 2105 and the second input-output pad 2205.

[0151] In each of the external pad bonding region PA and the bit line bonding region BLBA each included in the cell region CELL and the peripheral circuit region PERI, a metal pattern in the uppermost metal layer can be provided as a dummy pattern, or the uppermost metal layer can be absent.

[0152] In the external pad bonding region PA, the memory device 2000 can include a lower metal pattern 2173a in the uppermost metal layer of the peripheral circuit region PERI, the lower metal pattern 2173a corresponding to the upper metal pattern 2272a formed in the uppermost metal layer of the cell region CELL and having the same shape as that of the upper metal pattern 2272a of the cell region CELL, and can include an uppermost metal pattern 2271a connected to the second metal layer 2260a in the uppermost metal layer in the cell region CELL. In the peripheral circuit region PERI, the lower metal pattern 2173a formed in the uppermost metal layer of the peripheral circuit region PERI can not be connected to a contact. Similarly, in the external pad bonding region PA, an upper metal pattern can be formed in the uppermost metal layer of the cell region CELL, the upper metal pattern corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI and having the same shape as that of the lower metal pattern of the peripheral circuit region PERI.

[0153] The lower bonding metals 2171b and 2172b can be formed on the second metal layer 2140b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 2171b and 2172b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 2271b and 2272b of the cell region CELL by Cu-Cu bonding.

[0154] Further, in the bit line bonding region BLBA, an upper metal pattern 2292 can be formed in the uppermost metal layer of the cell region CELL, the upper metal pattern 2292 corresponding to the lower metal pattern 2152 formed in the uppermost metal layer of the peripheral circuit region PERI and having the same shape as that of the lower metal pattern 2152 of the peripheral circuit region PERI. A contact can not be formed on the upper metal pattern 2292 formed in the uppermost metal layer of the cell region CELL. For example, the lower metal pattern 2152 can be connected to the circuit element 2120c by the lower bonding metal 2151.

[0155] In an example embodiment, corresponding to a metal pattern in the uppermost metal layer formed in one of the cell region CELL and the peripheral circuit region PERI, a reinforcing metal pattern having the same shape as that of the metal pattern can be formed in the uppermost metal layer in the other of the cell region CELL and the peripheral circuit region PERI, and a contact can not be formed on the reinforcing metal pattern.

[0156] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the claims.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: an array of memory cells including a plurality of lower memory cells respectively arranged in regions where a plurality of lower word lines intersect a plurality of bit lines and a plurality of upper memory cells respectively arranged in regions where a plurality of upper word lines intersect the plurality of bit lines; a first sense amplifier connected to a first lower word line of the plurality of lower word lines, the first sense amplifier configured to perform a data sensing operation on a first lower memory cell connected between a first bit line of the plurality of bit lines and the first lower word line by comparing a voltage of the first lower word line to a first reference voltage; and a second sense amplifier connected to a first upper word line of the plurality of upper word lines, the second sense amplifier configured to perform a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line by comparing a voltage of the first upper word line to a second reference voltage, wherein the data sensing operation of the first sense amplifier and the data sensing operation of the second sense amplifier are performed in parallel and simultaneously.

2. The three-dimensional memory device of claim 1, further comprising: control logic configured to control the first sense amplifier and the second sense amplifier such that a read operation for the first lower memory cell and a read operation for the first upper memory cell are performed in parallel, wherein the control logic is further configured to control a pre-charge operation to be performed on the first lower word line and the first upper word line in a word line pre-charge time period of the three-dimensional memory device and to control a pre-charge operation for the first bit line in a bit line pre-charge time period of the three-dimensional memory device that is subsequent to the word line pre-charge time period.

3. The three-dimensional memory device of claim 2, further comprising: a first word line pre-charge circuit configured to apply a first word line pre-charge voltage to the first lower word line in the word line pre-charge time period; and a second word line pre-charge circuit configured to apply a second word line pre-charge voltage to the first upper word line in the word line pre-charge time period. each of the first word line pre-charge voltage and the second word line pre-charge voltage is a negative voltage.

5. The three-dimensional memory device of claim 2, further comprising:

4. The three-dimensional memory device of Claim 3, wherein, a first row decoder arranged between the plurality of lower word lines and the first sense amplifier, the first row decoder including a plurality of first row switches respectively connected to a corresponding one of the plurality of lower word lines and configured to perform a selection operation on the plurality of lower word lines; and a second row decoder arranged between the plurality of upper word lines and the second sense amplifier, the second row decoder including a plurality of second row switches respectively connected to a corresponding one of the plurality of upper word lines and configured to perform a selection operation on the plurality of upper word lines. ​ ​ ​ 6. The three-dimensional memory device of Claim 5, wherein, At least one of the first row switch connected to the first lower word line among the plurality of first row switches and the second row switch connected to the first upper word line among the plurality of second row switches is configured to be slightly turned on in the bit line pre-charge period.

7. The three-dimensional memory device of Claim 6, wherein, In the bit line pre-charge period, a control signal having a weak turn-on level is applied to at least one of the first row switch and the second row switch, and The weak turn-on level is a voltage level between a turn-on level that turns on each of the first row switch and the second row switch and an off level that turns off each of the first row switch and the second row switch.

8. The three-dimensional memory device of claim 2, further comprising: a column decoder including a plurality of column switches respectively connected to corresponding ones of the plurality of bit lines and configured to perform a selection operation on the plurality of bit lines; and a bit line pre-charge circuit configured to apply a bit line pre-charge voltage to the first bit line in a bit line pre-charge period.

9. The three-dimensional memory device of Claim 1, wherein, Each of the plurality of lower memory cells and the plurality of upper memory cells includes a selection element and a variable resistance element connected in series, and The variable resistance element includes a phase change material.

10. The three-dimensional memory device of Claim 1, wherein, The memory cell array is formed on a first semiconductor layer, The first sensing amplifier and the second sensing amplifier are formed on a second semiconductor layer, and The first semiconductor layer and the second semiconductor layer are stacked in a vertical direction, so the three-dimensional memory device has a periphery upper cell structure.

11. A three-dimensional memory device including a first semiconductor layer and a second semiconductor layer stacked in a vertical direction, wherein The first semiconductor layer includes a memory cell array including a plurality of lower memory cells respectively arranged in regions where a plurality of lower word lines intersect with a plurality of bit lines and a plurality of upper memory cells respectively arranged in regions where a plurality of upper word lines intersect with the plurality of bit lines, and The second semiconductor layer includes: a first sensing amplifier connected to a first lower word line among the plurality of lower word lines, the first sensing amplifier configured to perform a data sensing operation on a first lower memory cell connected between a first bit line among the plurality of bit lines and the first lower word line; and a second sensing amplifier connected to a first upper word line among the plurality of upper word lines, the second sensing amplifier configured to perform a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line, The data sensing operation of the first sensing amplifier and the data sensing operation of the second sensing amplifier are performed in parallel and simultaneously.

12. The three-dimensional memory device of Claim 11, wherein, The second semiconductor layer further includes: control logic configured to control the first sensing amplifier and the second sensing amplifier such that a read operation for the first lower memory cell and a read operation for the first upper memory cell are performed in parallel, and The control logic is further configured to control a pre-charge operation on the first lower word line and the first upper word line in a word line pre-charge period, and a pre-charge operation for the first bit line in a bit line pre-charge period after the word line pre-charge period.

13. The three-dimensional memory device of Claim 12, wherein, The second semiconductor layer further includes: a first word line pre-charge circuit configured to apply a first word line pre-charge voltage to a first lower word line in a word line pre-charge time period; and a second word line pre-charge circuit configured to apply a second word line pre-charge voltage to a second lower word line in the word line pre-charge time period.

14. The three-dimensional memory device of Claim 13, wherein, The voltage level of each of the first word line pre-charge voltage and the second word line pre-charge voltage is a negative voltage.

15. The three-dimensional memory device of Claim 12, wherein, The second semiconductor layer further includes: a first row decoder arranged between the plurality of lower word lines and a first sense amplifier, the first row decoder including a plurality of first row switches respectively connected to corresponding ones of the plurality of lower word lines to perform a selection operation on the plurality of lower word lines; and a second row decoder arranged between the plurality of upper word lines and a second sense amplifier, the second row decoder including a plurality of second row switches respectively connected to corresponding ones of the plurality of upper word lines to perform a selection operation on the plurality of upper word lines.

16. The three-dimensional memory device of Claim 15, wherein, At least one of a first row switch connected to a first lower word line among the plurality of first row switches and a second row switch connected to a first upper word line among the plurality of second row switches is configured to be slightly turned on in a bit line pre-charge time period.

17. The three-dimensional memory device of Claim 12, wherein, The second semiconductor layer further includes: a column decoder including a plurality of column switches respectively connected to corresponding ones of the plurality of bit lines and configured to perform a selection operation on the plurality of bit lines; and a bit line pre-charge circuit configured to apply a bit line pre-charge voltage to a first bit line in a bit line pre-charge time period.

18. A three-dimensional memory device, the three-dimensional memory device comprising: a memory cell array including a plurality of lower memory cells respectively arranged in regions where a plurality of lower word lines intersect a plurality of bit lines and a plurality of upper memory cells respectively arranged in regions where a plurality of upper word lines intersect the plurality of bit lines; a first row decoder including a plurality of lower row switches respectively connected to corresponding ones of the plurality of lower word lines, the first row decoder performing a selection operation on the plurality of lower word lines; a second row decoder including a plurality of upper row switches respectively connected to corresponding ones of the plurality of upper word lines, the second row decoder performing a selection operation on the plurality of upper word lines; a first sense amplifier connected to a first lower word line among the plurality of lower word lines, the first sense amplifier configured to perform a data sensing operation on a first lower memory cell connected between a first bit line among the plurality of bit lines and the first lower word line; and a second sense amplifier connected to a first upper word line among the plurality of upper word lines, the second sense amplifier configured to perform a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line, wherein the data sensing operation of the first sense amplifier and the data sensing operation of the second sense amplifier are performed in parallel and simultaneously. a first lower row switch connected to the first lower word line among the plurality of lower row switches and a first upper row switch connected to the first upper word line among the plurality of upper row switches are driven by a same row address.

19. The three-dimensional memory device of Claim 18, wherein, ​ 20. The three-dimensional memory device of Claim 18, wherein, The plurality of lower word lines also includes a second lower word line, wherein the plurality of lower column switches includes a first lower column switch connected to the first lower word line and a second lower column switch connected to the second lower word line, and wherein the three-dimensional memory device further comprises: a third sense amplifier connected to the second lower word line, the third sense amplifier configured to perform a data sensing operation on a second lower memory cell connected between the first bit line and the second lower word line.

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