Memory device including a power supply circuit and method of operating a memory device

Abstract

Provided are a storage device including a power supply circuit, and a method of operating the storage device, the storage device including: a power supply circuit that receives a power disable signal from a host device, and provides a first internal voltage and a second internal voltage; a nonvolatile memory including a memory device; and a storage controller that controls the nonvolatile memory, and includes a processor that performs a data recovery operation on data stored in the memory device, and a host interface that communicates with the host device. When the power disable signal is activated at a power-off time, the storage controller is powered off, the power supply circuit interrupts the first internal voltage and the second internal voltage during a reference time after the power-off time, and provides the first internal voltage to the processor after the reference time elapses from the power-off time.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0017902, filed on February 13, 2020, in the Korean Intellectual Property Office, the subject matter of which is incorporated herein by reference. Technical Field

[0003] The present inventive concept relates to a memory device and a method of operating the memory device. More particularly, the present inventive concept relates to a memory device including a power supply circuit and a method of operating the memory device. Background Art

[0004] Non-volatile memory can retain stored data without the application of power. In recent years, storage devices including flash-based non-volatile memory such as embedded multimedia cards (eMMC), universal flash memory (UFS), solid-state drives (SSDs), and memory cards have become widely used. Storage devices can be effectively used to store relatively large amounts of data.

[0005] However, when the memory device is kept in a power-off state, the threshold voltage of the constituent memory cells that are not frequently accessed by the host device may change, thereby causing data loss. This phenomenon is becoming more and more common as the data retention time increases. Summary of the Invention

[0006] Embodiments of the inventive concept provide a memory device having improved data retention characteristics and a method of operating such a memory device.

[0007] According to one aspect of the present inventive concept, a memory device is provided, the memory device including: a power supply circuit that receives a power deactivation signal from a host device and provides a first internal voltage and a second internal voltage; a nonvolatile memory that includes a memory device; and a memory controller that controls the nonvolatile memory and includes a processor and a host interface, the processor performing a data recovery operation on data stored in the memory device, and the host interface communicating with the host device. When the power deactivation signal is activated at a power-off time, the memory controller is powered off, the power supply circuit interrupts the first internal voltage and the second internal voltage during a reference time after the power-off time, and provides the first internal voltage to the processor after the reference time has elapsed from the power-off time.

[0008] According to an aspect of the present inventive concept, there is provided a storage device including a power supply circuit receiving a power down signal and an external voltage from a host device and providing a first internal voltage, a second internal voltage, and a third internal voltage; a nonvolatile memory including a memory device; and a storage controller controlling the nonvolatile memory and including a first processor receiving the first internal voltage, a host interface receiving the second internal voltage and communicating with the host device, and a second processor receiving the third internal voltage and controlling an operation of the storage controller. When the power down signal is activated at a power-off time, the power supply circuit interrupts the first internal voltage, the second internal voltage, and the third internal voltage to power off the storage controller and the nonvolatile memory, and after a reference time elapses from the power-off time, the power supply circuit periodically provides the first internal voltage to the first processor, and the first processor performs a data recovery operation on data stored in the nonvolatile memory.

[0009] According to an aspect of the present inventive concept, there is provided a method of operating a storage device including a nonvolatile memory including a memory device and a storage controller including a processor and a host interface. The method includes powering off the storage controller to put the processor and the host interface in a power-off state when an activated power down signal is received from a host device at a power-off time; determining whether a reference time elapses after the power-off time; and providing an internal voltage to the processor to put the processor in a power-on state when it is determined that the reference time elapses after the power-off time, so that the processor performs a data recovery operation on data stored in the memory device and the power-off state of the host interface is maintained.

[0010] According to an aspect of the present inventive concept, there is provided a method of operating a storage device including a non-volatile memory and a storage controller including a processor and a host interface. The method includes receiving a power-down signal from a host device, causing the storage device to operate in a power-down function active mode when the power-down signal is activated, and causing the storage device to operate in a power-down function inactive mode when the power-down signal is deactivated. Causing the storage device to operate in the power-down function active mode includes powering down the processor and the host interface at a power-down time, powering up the processor after a reference time elapses from the power-down time, performing a data recovery operation on data stored in the non-volatile memory using the processor, and powering down the processor when the data recovery operation is completed. BRIEF DESCRIPTION OF DRAWINGS

[0011] Embodiments of the present inventive concept can be more clearly understood with reference to the following detailed description considered in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram of a storage system according to an embodiment of the present inventive concept, shown in one example (1000);

[0013] Figure 2 is a block diagram of a storage controller 100 according to an embodiment of the present inventive concept, further shown in one example (100_1); Figure 1

[0014] Figure 3 is a block diagram of a storage device 200_1 according to an embodiment of the present inventive concept, further shown in one example (200_1);

[0015] Figure 1

[0016] Figure 4 is a flowchart of a method of operating a storage device according to an embodiment of the present inventive concept, outlined in one example;

[0017] Figure 5 is a block diagram of a power supply circuit 300 according to an embodiment of the present inventive concept, shown in one example (300_1); Figure 1

[0018] Figure 6A and Figure 6B are respective block diagrams of a power supply controller 310 according to an embodiment of the present inventive concept, shown in various examples (310_1 and 310_2); Figure 5

[0019] Figure 7 ​​​​is a flowchart outlining, in one example, a method of operating a storage device according to an embodiment of the inventive concept;

[0020] Figure 8 is a block diagram illustrating a storage system according to an embodiment of the inventive concept in one example (1000a);

[0021] Figure 9 In one example (100_2), an embodiment according to the present invention is shown. Figure 9 A block diagram of a storage controller 100a;

[0022] Figure 10 is a flowchart outlining, in one example, a method of operating a storage device according to an embodiment of the inventive concept;

[0023] Figure 11 In one example (300_2), an embodiment according to the present invention is shown. Figure 8 A block diagram of a power supply circuit 300a; and

[0024] Figure 12 is a flowchart outlining, in one example, a method of operating a memory device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0025] Throughout the written description and drawings, like reference numerals and labels refer to like or similar elements and / or features.

[0026] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the inventive concept in one example ( 1000 ).

[0027] Reference Figure 1 , the storage system 1000 may generally include a storage device 10 and a host device 20. Figure 1 Assume that the storage device 10 is a solid-state drive (SSD) device, but the present invention is not limited thereto, and the storage device 10 can be one of a variety of storage devices capable of receiving, storing, and / or retrieving data. In an example embodiment, the host device 20 can be implemented as an application processor (AP) or a system on a chip (SoC). The host device 20 can communicate with the storage device 10 through the host interface 120.

[0028] The memory device 10 generally includes a memory controller 100, a power supply circuit 300, and a non-volatile memory 200. The memory controller 100 can be used to control the overall operation of the power supply circuit 300 and the non-volatile memory 200.

[0029] The storage controller 100 can receive a request (REQ) provided by the host device 20 (e.g., a read request, a write request, etc.), and in response to the request, transmit data to and / or receive data from the host device 20. The storage controller 100 can provide data (DATA) stored in the nonvolatile memory 200 to the host device 20 in response to a read request. Alternatively, the storage controller 100 can control the nonvolatile memory 200 to write data received from the host device 20 in the nonvolatile memory 200 in response to a write request.

[0030] The power supply circuit 300 can receive an external voltage (EV) from the host device 20 through an external power line. Although a single external voltage is assumed for the example shown, the inventive concept is not limited thereto, and the power supply circuit 300 can receive a number of external voltages through one or more external power lines. For example, the power supply circuit 300 can receive a first external voltage and a second external voltage through a first external power line and a second external power line, respectively. Figure 1

[0031] The power supply circuit 300 can generate one or more internal voltages from the external voltage(s) as needed by various operations performed by the storage controller 100 and / or the nonvolatile memory 200. For example, the power supply circuit 300 can provide a first internal voltage to the processor 110 of the storage controller 100 through a first internal power line PL1, and a second internal voltage to the host interface 120 of the storage controller 100 through a second internal power line PL2.

[0032] The power supply circuit 300 can also receive a power down signal (PWDIS) from the host device 20 and selectively activate a power down function in response to the power down signal. For example, the power supply circuit 300 can receive the power down signal through a third external power line.

[0033] When the power down signal is deactivated, the power supply circuit 300 can operate in a power down function deactivation mode. In the power down function deactivation mode, the power supply circuit 300 provides internal voltages to the storage controller 100 and the nonvolatile memory 200 to put the storage controller 100 and the nonvolatile memory 200 in a power-on state. For example, when the power supply circuit 300 receives the power down signal at a low level, the power supply circuit 300 can provide internal voltages to the storage controller 100 and the nonvolatile memory 200, respectively, thereby powering on the storage controller 100 and the nonvolatile memory 200.

[0034] ​In contrast, when the power disable signal is activated, the power supply circuit 300 can operate in a power disable function activation mode. In the power disable function activation mode, the power supply circuit 300 will not provide internal voltage to the memory controller 100 and the non-volatile memory 200, and the memory controller 100 and the non-volatile memory 200 are in a power-off state. For example, when the power supply circuit 300 receives a high-level power disable signal, the power supply circuit 300 can power off the memory controller 100 and the non-volatile memory 200.

[0035] In the power-off function activation mode, the power supply circuit 300 may periodically supply power to the processor 110. That is, the power supply circuit 300 may periodically supply the first internal voltage to the processor 110 via the first internal power line. In this regard, the power supply circuit 300 may include a timer. When a reference time has passed since the power-off moment (e.g., the time point when the memory controller 100 and the non-volatile memory 200 are powered off), the power supply circuit 300 may again supply (or re-supply) power to the processor 110.

[0036] However, in the power disable function activation mode, the power supply circuit 300 may not supply power to the host interface 120 by interrupting the second internal voltage otherwise supplied to the host interface 120. Therefore, the host device 20 may recognize the power disable function of the storage device 10 as activated.

[0037] Even when the power-off function is activated, the memory device 10 according to an embodiment of the inventive concept can still periodically provide the first internal voltage to the processor 110, and thus the processor 110 can periodically perform a data recovery operation on the nonvolatile memory 200 as needed. In this regard, it should be noted that while a read error caused by a retention error may occur while the memory device 10 is maintained in a power-off state, the likelihood of such an outcome can be reduced (and the life of the memory device 10 can be extended) by performing a data recovery operation on the nonvolatile memory 200.

[0038] The nonvolatile memory 200 may be used as a storage medium of the memory apparatus 10. The nonvolatile memory 200 is connected to the memory controller 100 through a plurality of channels. In example embodiments, the nonvolatile memory 200 may include one or more memory devices 200_1.

[0039] Here, when the non-volatile memory 200 includes a flash memory, the flash memory can include a two-dimensional (2D) NAND memory array and / or a three-dimensional (3D) (or vertical) NAND (VNAND) memory array. The 3D memory array can be monolithically formed in at least one physical level of circuitry associated with operation of an array of memory cells having active regions disposed above a silicon substrate or operation of a memory cell, where the associated circuitry can be above or within the silicon substrate. In this regard, the term “monolithically” refers to layers of each level of the 3D memory array being directly deposited on layers of each lower level of the 3D memory array.

[0040] In an example embodiment, the 3D memory array can include a vertical NAND string in which at least one memory cell is vertically above another memory cell. The at least one memory cell can include a charge-trapping layer.

[0041] In an example embodiment, the non-volatile memory 200 can include various other types of non-volatile memory. For example, the non-volatile memory 200 can include various memories such as magnetic random access memory (MRAM), spin-transfer torque MRAM, conductive-bridge RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM (RRAM), nanotube RAM, polymer RAM (PoRAM), nanofloating gate memory (NFGM), holographic memory, molecular electronic memory, or chalcogenide random access memory.

[0042] In an example embodiment, the memory devices 200_1 of the non-volatile memory 200 can include at least one type of memory cell such as a single-level cell (SLC) capable of storing 1 bit of data and / or at least one multi-level cell (MLC) capable of storing 2 or more bits of data. For example, the memory devices 200_1 can include SLCs and / or MLCs (e.g., MLCs capable of storing 2 bits of data, 3 bits of data, and / or 4 bits of data).

[0043] In an example embodiment, when the power-down function is activated in the storage apparatus 10, a data recovery operation can be independently performed for each memory device 200_1. In this case, in the power-down function activation mode, for a memory device including constituent memory cells for storing a relatively smaller or larger number of bits, a data recovery operation can be performed at a relatively shorter or longer period.

[0044] Figure 2 is further illustrated in one example (100_1) according to an embodiment of the inventive concept Figure 1a block diagram of a storage controller 100.

[0045] Referring to Figure 1 and Figure 2 The storage controller 100 can include a processor 110, a host interface 120, a random access memory (RAM) 130, and a memory interface 140. The processor 110, the host interface 120, the RAM 130, and the memory interface 140 can communicate with each other through a bus 150. In addition, the storage controller 100 can further include other peripheral devices not shown in FIG. 1. Figure 2

[0046] The processor 110 can be used to control the overall operation of the storage controller 100. The processor 110 can include a central processing unit (CPU) or a microprocessor (MP). The processor 110 can drive firmware for driving the storage controller 100. The firmware can be loaded in the RAM 130 and driven by the processor 110. For example, the processor 110 can drive firmware that drives the storage controller 100 and a flash translation layer (FTL), and controls the execution of various operations such as a data recovery operation, a garbage collection operation, an address mapping operation, a storage cell wear leveling operation, etc.

[0047] The host interface 120 can communicate with the host device 20. For example, the host interface 120 can provide a physical connection between the host device 20 and the storage device 10.

[0048] The host interface 120 can adjust one or more characteristics (e.g., format, timing, size, etc.) of data, commands, and / or addresses exchanged between the storage device 10 and the host device 20. For example, the host interface 120 can serve as a physical layer interface. The bus format of the host device 20 can include at least one of a universal serial bus (USB), a small computer system interface (SCSI), a peripheral component interconnect (PCI) express (PCIe), an advanced technology attachment (ATA), a parallel ATA (PATA), a serial ATA (SATA), and a serial attached SCSI (SAS). In an example embodiment, the host interface 120 can communicate with the host device 20 configured to exchange data according to the PCIe using a non-volatile memory express (NVMe) protocol.

[0049] The processor 110 receives a first internal voltage IV1 from the power supply circuit 300 through a first internal power line PL1, and the host interface 120 receives a second internal voltage IV2 from the power supply circuit 300 through a second internal power line PL2. In an example embodiment, the first internal voltage IV1 and the second internal voltage IV2 can have the same voltage level. However, the inventive concept is not limited thereto, and the first internal voltage IV1 and the second internal voltage IV2 can have different voltage levels.​

[0050] When the power down function is activated, the first internal voltage IV1 and the second internal voltage IV2 supplied to the processor 110 and the host interface 120 can be interrupted. In an example embodiment, when a reference time elapses after a power-off time (e.g., after the power down function is activated), the first internal voltage IV1 can be temporarily supplied to the processor 110, and thus the processor 110 can drive firmware, thereby enabling a data recovery operation. In contrast, when the power down function is activated, the second internal voltage IV2 supplied to the host interface 120 can be interrupted. Accordingly, the host device 20 can recognize that the power down function of the storage device 10 is activated, and at the same time, the data recovery operation can be periodically performed in the storage device 10. In this way, deterioration of data stored in the nonvolatile memory 200 (e.g., due to increased retention time) that can occur when the storage device 10 enters a power-off state can be prevented.

[0051] The RAM 130 can operate under the control of the processor 110. The RAM 130 can be used as an operating memory, a cache memory, and / or a buffer memory of the processor 110. Software and firmware that control the memory controller 100 can be loaded to the RAM 130. The RAM 130 can be implemented using, for example, dynamic RAM (DRAM) and / or static RAM (SRAM), as a nonvolatile memory. Alternatively, the RAM 130 can be implemented as a resistive memory such as RRAM, PRAM, or MRAM.

[0052] In an example embodiment, the RAM 130 can be used as an operating memory, and an FTL mapping table can be loaded to the RAM 130. Here, the FTL can include various modules configured to perform various functions. For example, the FTL can include an address conversion module configured to convert a logical address received from the host device 20 to a physical address indicating a storage location of the nonvolatile memory 200. The FTL can also include modules configured to perform various background operations (e.g., a data recovery operation, a garbage collection operation, etc.) related to the nonvolatile memory 200. The mapping table can be operated by the FTL, and logical addresses and physical addresses corresponding thereto can be mapped to each other and stored in the mapping table.

[0053] In an example embodiment, the RAM 130 can be used as a buffer memory to temporarily store data. For example, data temporarily stored in the RAM 130 can be subsequently written to the nonvolatile memory 200 or transmitted to the host device 20.

[0054] The memory interface 140 can be used to control data exchange with the nonvolatile memory 200. The memory interface 140 can write the recovered data to the nonvolatile memory 200 via a channel when the storage controller 100 performs a data recovery operation.

[0055] In an example embodiment, the storage controller 100 can further include an error correction code (ECC) block and a redundant array of independent disks (RAID) recovery block. The ECC block can detect and correct errors included in data read from the nonvolatile memory. The RAID recovery block can read data and RAID parity included in a RAID stripe and perform a RAID recovery operation using the read data and RAID parity.

[0056] Figure 3 is further illustrated Figure 1 a block diagram of a memory device 200_1 of the nonvolatile memory 200 according to an embodiment of the inventive concept. Here, the memory device 200_1 can include one or more discrete memory devices.

[0057] Referring to Figure 1 and Figure 3 , the memory device 200_1 can include a memory cell array 210, an address decoder 220, a control logic block 230, a page buffer 240, an input / output (I / O) circuit 250, and a voltage generator 260. Although not shown, the memory device 200_1 can further include an I / O interface.

[0058] The memory cell array 210 can be connected to a word line WL, a string selection line SSL, a ground selection line GSL, and a bit line BL. The memory cell array 210 can be connected to the address decoder 220 through the word line WL, the string selection line SSL, and the ground selection line GSL, and connected to the page buffer 240 through the bit line BL. The memory cell array 210 can include a plurality of memory blocks BLK1 to BLKn.

[0059] The memory blocks BLK1 to BLKn can each include a plurality of memory cells and a plurality of selection transistors. The memory cells can be connected to the word line WL, and the selection transistors can be connected to the string selection line SSL or the ground selection line GSL. The memory cells of each of the memory blocks BLK1 to BLKn can include SLC and / or MLC.

[0060] In an example embodiment, the memory blocks BLK1 to BLKn can each include a plurality of pages. For example, a memory block can be characterized by an erase unit (e.g., a block) and a read / write unit (e.g., a page).

[0061] The address decoder 220 can select one of the memory blocks BLK1 to BLKn of the memory cell array 210, select one of the word lines WL of the selected memory block, and select one of the string selection lines SSL.

[0062] The control logic block 230 can provide various control signals for performing programming, reading, and erasing operations on the memory cell array 210 in response to the command CMD, the address ADDR, and / or the control signal CTRL. For example, the control logic block 230 provides a row address X-ADDR to the address decoder 220, a column address Y-ADDR to the page buffer 240, and a voltage control signal CTRL_Vol to the voltage generator 260.

[0063] The control logic block 230 can perform a data recovery operation in response to the command CMD received from the memory controller 100. For example, the control logic block 230 can read data from a particular page of a particular block, provide the read data to the memory controller 100, receive data that has been corrected for errors, and write the corrected data to a new free memory block. An exemplary data recovery operation for the memory device 10 will be described in greater detail below with reference to FIG. 4. Figure 7

[0064] The control logic block 230 can perform a garbage collection operation in response to a command received from the memory controller 100. For example, to perform a garbage collection operation, the control logic block 230 can copy data from valid pages of a victim block selected from the memory blocks BLK1 to BLKn to a target block, and then erase the victim block.

[0065] The page buffer 240 can function as a write driver or a sense amplifier depending on the mode of operation. During a read operation, the page buffer 240 can sense a bit line BL of a selected memory cell via control of the control logic block 230. The sensed data can be stored in a latch included in the page buffer 240. The page buffer 240 can dump the data stored in the latch to the I / O circuit 250 via control of the control logic block 230.

[0066] The I / O circuit 250 can temporarily store the command CMD, the address ADDR, the control signal CTRL, and / or the data DATA provided from an external source through one or more I / O lines. The I / O circuit 250 can temporarily store read data recovered from the memory device 200_1 and output the read data to the external source through the I / O lines.

[0067] ​The voltage generator 260 can be used to generate various voltages used during performance of various operations (e.g., program, read, and erase operations) on the memory cell array 210 in response to the voltage control signal CTRL_Vol. For example, the voltage generator 260 can generate a word line voltage VWL, a program voltage, a read voltage, a pass voltage, an erase verify voltage, and / or a program verify voltage. In addition, the voltage generator 260 can generate a string select line voltage and a ground select line voltage based on the voltage control signal CTRL_Vol. Further, the voltage generator 260 can generate an erase voltage to be supplied to the memory cell array 210.

[0068] Figure 4 A flowchart of a method of operating the storage device 10 according to an embodiment of the inventive concept is outlined in one example. Figure 1 A flowchart of a method of operating the storage device 10 according to an embodiment of the inventive concept is outlined in one example.

[0069] Referring to Figure 1 and Figure 4 , the power-off signal is activated (S10). For example, when the power-off signal changes from low to high, the storage device 10 can determine that the power-off signal is activated.

[0070] In response to the power-off signal, the storage device 10 can power off the storage controller 100 (S20). That is, the power supply circuit 300 can interrupt one or more internal voltages supplied to the storage controller 100 and / or the non-volatile memory 200.

[0071] Then, the storage device 10 determines whether a reference time has elapsed since the power-off of the storage controller 100 (S30). As long as the elapsed time is less than the reference time (S30 = No), the power supply circuit 300 keeps the storage controller 100 in the powered-off state.

[0072] In the example embodiment, the duration of the reference time depends on the characteristics of the constituent memory cells used to store data in the memory device 200_1. That is, as the number of data bits stored in the constituent memory cells increases, the duration of the reference time corresponding to the memory cells can be shortened. In the example embodiment, as the period of use of the storage device 10 (i.e., the use time) increases, the reference time can be shortened.

[0073] However, when the reference time elapses from the power-off time (S30 = Yes), the storage device 10 can power on the processor 120 while maintaining the power-off state of the host interface 120 (S40). For example, the power supply circuit 300 can provide the first internal voltage IV1 to the processor 110 through the first internal power line PL1, but not provide the second internal voltage IV2 to the host interface 120.

[0074] That is, the storage device 10 can power on other components except for the host interface 120 during S40. For example, the storage device 10 can power on components configured to perform a data recovery operation. In contrast, because the host interface 120 remains in the power-off state, the host device 20 can determine that the power-down function of the storage device 10 is activated.

[0075] Accordingly, when the processor 110 is powered on, the storage device 10 can perform a data recovery operation on data stored in the storage means 200_1 (S50).

[0076] The storage device 10 can perform a data recovery operation on data stored in the storage means 200_1 according to the elapse of a certain reference time. For example, the first reference time corresponding to SLC can be longer than the second reference time corresponding to MLC. Accordingly, the data recovery operation for a storage means including MLC can be performed more frequently than the data recovery operation for a storage means including SLC.

[0077] In addition, regarding S50 above, the storage device 10 can perform a garbage collection operation. The garbage collection operation for the storage device 10 can include selecting a victim block from the storage blocks (e.g., BLK1 to BLKn), copying valid pages from the victim block to a free storage block, and then erasing the victim block. Subsequently, the erased victim block can be reused as a free storage block. Figure 3

[0078] Then, the storage device 10 can determine whether the power-down signal has been deactivated (S60). When the power-down signal is in the activated state (S60 = No), the storage device 10 can again return to S20. Accordingly, the storage device 10 can periodically power on the processor 110 and perform a data recovery operation during the power-down function activation mode without intervention of the host device 200.

[0079] ​However, when the power down signal is deactivated (S60=YES), the memory device 10 can power on the memory controller 100 (S70). For example, when the power down signal changes from high to low, the memory device 10 can determine that the power down signal PWDIS is deactivated. Accordingly, during S70, the power supply circuit 300 can provide the first internal voltage IV1 to the processor 110 through the first internal power line PL1 and the second internal voltage IV2 to the host interface 120 through the second internal power line PL2.

[0080] Figure 5 is a block diagram of a power supply circuit 300 according to an embodiment of the present inventive concept. Figure 1

[0081] Referring to Figure 1 , Figure 2 and Figure 5 , the power supply circuit 300 can include a power supply controller 310, a voltage regulator 320, and a switching circuit 330, wherein the power supply controller 310 can include a timer 315.

[0082] The power supply controller 310 can receive a power down signal (PWDIS) through a third external power line. In an example embodiment, the power supply controller 310 can receive at least one external voltage (EV) through at least one of a first external power line and a second external power line. Alternatively, the power supply controller 310 can receive an operating voltage from the voltage regulator 320.

[0083] The power supply controller 310 can be configured to generate a first control signal CS1 and a second control signal CS2 in response to the power down signal. When the power down signal PWDIS is deactivated, the power supply controller 310 can provide the first control signal CS1 to the voltage generator 320 so that the voltage regulator 320 generates the first internal voltage IV1 and the second internal voltage IV2, and can provide the second control signal CS2 to the switching circuit 330 so that the switching circuit 330 transmits the second internal voltage IV2 to the second internal power line PL2.

[0084] ​When the power down signal is activated, the power supply controller 310 can provide the first control signal CS1 to the voltage regulator 320 so that the voltage regulator 320 does not generate the first internal voltage IV1 and the second internal voltage IV2. When the reference time Tr elapses after the power-off time (e.g., after the power down signal is activated), the power supply controller 310 can generate the first control signal CS1 so that the voltage regulator 320 generates the first internal voltage IV1 and the second internal voltage IV2 again. In this case, the power supply controller 310 can provide the second control signal CS2 so that the second internal voltage IV2 is not transmitted to the second internal power line PL2 by the switching circuit 330 (i.e., interrupted). Accordingly, when the reference time Tr elapses after the power down signal is activated, the first internal voltage IV1 can be provided to the processor 110, but the second internal voltage IV2 is not provided to the host interface 120 (i.e., interrupted).

[0085] The timer 315 of the power supply controller 310 can be used to determine (e.g., time) the elapsed time from the power-off time of the storage controller 100. For example, the timer 315 can time the elapsed time from the point in time at which the power down signal is activated. Alternatively, the timer 315 can time the elapsed time from the point in time at which the data recovery operation is completed during the power down function activation mode. That is, during the power down function activation mode, the timer 315 can be reset after the data recovery operation is completed when the storage controller 100 is powered off. The power supply controller 310 can generate the first control signal CS1 and the second control signal CS2 based on the comparison result between the predetermined reference time Tr and the elapsed time timed by the timer 315.

[0086] In this regard, the power supply controller 310 can receive a time setting signal (CTS) and set the reference time (Tr) in response to the time setting signal. In an example embodiment, the power supply controller 310 can receive the time setting signal from the storage controller 100. For example, information about the reference time Tr can be stored in the RAM 130, and the processor 110 can drive the firmware, generate the time setting signal based on the information about the reference time stored in the RAM 130, and transmit the time setting signal to the power supply controller 310. Alternatively, for example, the storage controller 100 can receive a signal including information about the reference time from the host device 20, and the processor 110 can drive the firmware and transmit the time setting signal to the power supply controller 310.

[0087] Alternatively, in an example embodiment, the power controller 310 can receive the time setting signal directly from the host device 20. For example, the time setting signal can be included in the power disable signal. That is, when the power disable signal has a specific pattern, the power controller 310 can set a reference time corresponding to the specific pattern. In this way, the power controller 310 can receive both the power disable signal and the time setting signal from the host device 20 through the same external power line (e.g., the third external power line).

[0088] In an example embodiment, the power controller 310 can store a lookup table (e.g., a LUT or a LUTa) including information about the reference time in response to the time setting signal, in order to set the reference time. Figure 6A Figure 6B In an example embodiment, the power controller 310 can store a lookup table (e.g., a LUT or a LUTa) including information about the reference time in response to the time setting signal, in order to set the reference time.

[0089] However, the operation of the power controller 310 is not limited to receiving the time setting signal. For example, the reference time can be set in the power controller 310, and the power controller 310 can generate the first control signal CS1 and the second control signal CS2 in response to the reference time.

[0090] Further, in this regard, the power controller 310 can adaptively change the duration of the reference time in response to, for example, a change in the data reliability of the storage device 10. For example, when it is determined that the data recovery operation does not need to be performed too frequently during the power disable function activation mode, the power controller 310 can increase the reference time (e.g., Tr+ΔTra). In contrast, when the number of read errors increases due to an increase in the data retention time, the power controller 310 can shorten the reference time Tr (e.g., Tr-ΔTrb), so that the frequency of the data recovery operation can be increased during the power disable function activation mode.

[0091] When the first internal voltage IV1 is supplied to the processor 110 while the power disable signal is activated, the processor 110 can perform the data recovery operation. When the data recovery operation is completed, the power controller 310 can again supply the first control signal CS1 such that the voltage regulator 320 does not generate the first internal voltage IV1 and the second internal voltage IV2.

[0092] ​The voltage regulator 320 can be selectively activated in response to the first control signal CS1. The voltage regulator 320 can receive the external voltage EV and generate a first internal voltage IV1 and a second internal voltage IV2. The first internal voltage IV1 can be an operating voltage of the processor 110, and the second internal voltage IV2 can be an operating voltage of the host interface 120. The voltage regulator 320 can provide the first internal voltage IV1 to the first internal power line PL1 and the second internal voltage IV2 to the switching circuit 330. In an example embodiment, the first internal voltage IV1 and the second internal voltage IV2 can have the same voltage level. However, the inventive concept is not limited thereto, and the first internal voltage IV1 and the second internal voltage IV2 can have different voltage levels.

[0093] The switching circuit 330 can receive the second internal voltage IV2 from the voltage regulator 320 in response to the second control signal CS2 and provide the second internal voltage IV2 to the second internal power line PL2. In an example embodiment, the switching circuit 330 can include a multiplexer.

[0094] Figure 6A and Figure 6B are respective block diagrams of the power controller 310 according to embodiments of the inventive concept in various examples (310_1 and 310_2). Figure 5

[0095] Referring to Figure 1 and Figure 6A , a plurality of reference times having different values can be stored in the power controller 310. For example, a lookup table LUT including information about reference times corresponding to characteristics of memory cells can be stored in the power controller 310. However, the inventive concept is not limited to the case where the power controller 310 stores the lookup table LUT. The power controller 310 can store information about reference times corresponding to characteristics of memory cells in various ways.

[0096] In an example embodiment, the non-volatile memory 200 can include one or more memory devices including one or more SLCs, 2-bit MLCs (or MLCs), 3-bit MLCs (or TLCs), and / or 4-bit MLCs (or QLCs). A first reference time (Tr_SLC) corresponding to the SLC, a second reference time (Tr_MLC) corresponding to the 2-bit MLC, a third reference time (Tr_TLC) corresponding to the TLC, and / or a fourth reference time (Tr_QLC) corresponding to the QLC can be stored in a lookup table LUT associated with the power controller 310.

[0097] ​In an example embodiment, the first reference time can be longer than the second reference time, the second reference time can be longer than the third reference time, and the third reference time can be longer than the fourth reference time. That is, as the number of bits stored in the various storage units increases, the respective reference times of the storage units can be shortened. As the number of bits stored in one storage unit increases, a read error due to charge leakage in the storage unit can occur more easily. Accordingly, as the number of bits stored in the storage unit increases, the reference time corresponding to the storage unit can be shortened, and thus, a data recovery operation can be performed in a shorter period of the memory device. Accordingly, a read error due to charge leakage can be reduced or prevented.

[0098] The timer 315 can be used to time elapsed times corresponding to the first reference time, the second reference time, the third reference time, and the fourth reference time, respectively. For example, the timer 315 can include a first timer corresponding to the SLC and a second timer corresponding to the MLC. In the power-off function activation mode, when a data recovery operation of the memory device including the SLC is completed, the first timer can be reset, and when a data recovery operation of the memory device including the MLC is completed, the second timer can be reset. That is, the storage apparatus according to an embodiment of the inventive concept can independently perform the operations S10 to S70 with respect to each of the memory devices including the SLC, the MLC, the TLC, and / or the QLC. Figure 4 The operations S10 to S70 are described.

[0099] As described above, the non-volatile memory 200 can include one or more memory devices including the SLC, the MLC, the TLC, and / or the QLC. However, the reference times corresponding to the one or more memory devices included in the non-volatile memory 200 can be stored in the power supply controller 310, compared to the embodiments described. Figure 6A

[0100] Referring to Figure 1 and Figure 6B , a plurality of reference times having different values can be stored in the power supply controller 310. For example, a lookup table LUTa including information about the reference times corresponding to the usage period of the storage apparatus can be stored in the power supply controller 310.

[0101] In an example embodiment, as the usage period of the storage apparatus increases, the reference times stored in the lookup table LUTa can have smaller values. For example, when the usage period of the storage apparatus is less than or equal to a threshold usage period T1, the reference time can have a first value Tr1. When the usage period of the storage apparatus is less than or equal to a k-th period Tk, the reference time can have a k-th value Trk. In this case, "k" can be a natural number greater than or equal to 2. The k-th value Trk can be smaller than the first value Tr1.​

[0102] When the usage period of the storage device increases, read errors due to charge leakage of data stored in the storage unit are more likely to occur. Therefore, the reference time can be shortened as the usage period of the storage device increases. Accordingly, the data recovery operation can be performed relatively more frequently, and occurrence of read errors due to charge leakage can be reduced or prevented.

[0103] However, the power controller 310 is not limited to storing the lookup table LUTa, and can store information about the reference time corresponding to the usage period in various ways. For example, a relationship between the usage period and the change in the reference time can be stored in the power controller 310, and the power controller 310 can calculate the reference time corresponding to the usage period based on the relationship.

[0104] Figure 7 is further outlined in one example in accordance with an embodiment of the inventive concepts Figure 4 of operation S50. Here, it is assumed that the data recovery operation (S50) performed with respect to the target storage block includes operation (S51), operation (S53), and operation (S55).

[0105] Referring to Figure 1 , Figure 4 and Figure 7 , the storage device 10 can correct errors in the target storage block in which data is stored in units of pages (S51). For example, the storage device 10 can read user data and ECC parity bits corresponding thereto from a page of the target storage block, and perform an error correction operation using the ECC parity bits.

[0106] The storage device 10 can determine whether errors in the detected data are correctable. For example, in a page in which the number of faulty bits detected in the data exceeds a certain error correction capability of the storage device 10, the storage device 10 can determine that errors in the data are not correctable.

[0107] In the example embodiment, when errors in the data are not correctable, the storage device 10 can further perform a RAID recovery operation. The storage device 10 can read data included in a RAID stripe and RAID parity bits from a unit area other than the unit area including a page in which errors are determined to be not correctable, and perform a RAID recovery operation using the read data and the RAID parity bits. Accordingly, the recovered data can be output using the RAID recovery operation.

[0108] Then, the storage device 10 can write valid data among the data stored in the target storage block to the free storage block (S53). For example, the storage device 10 can determine some uncorrectable data as invalid data (S51), and can also determine some correctable data as valid data (S51). In an example embodiment, even if the error in the data is uncorrectable, the data recovered due to the RAID recovery operation can be valid data.

[0109] Because the valid data is written to the free storage block, the target storage block corresponding to the valid data in the mapping table changes to the free storage block. The page address can also change according to the number of valid pages of the valid data written in the target storage block.

[0110] Then, when all the valid data among the data stored in the target storage block is written to the free storage block (S53), the storage device 10 can erase the data stored in the target storage block (S55), that is, the storage device 10 can perform (S55). The target storage block from which the data is erased can become a new free storage block that can be reused.

[0111] Figure 8 is a block diagram of a storage system according to an embodiment of the inventive concept, Figure 9 is a block diagram of a storage controller 100a according to an embodiment of the inventive concept. Figure 8 of the storage controller 100a.

[0112] Referring to Figure 8 The storage system 1000a can generally include a storage device 10a and a host device 20, where the host device 20 can communicate with the storage device 10a through a host interface 120.

[0113] The power supply circuit 300a can be used to generate internal voltages required for respective operations of the storage controller 100a and the non-volatile memory 200 from one or more external voltages (EV). For example, the power supply circuit 300a can provide a first internal voltage to the first processor 110_1 through a first internal power line PL1, a second internal voltage to the host interface 120 through a second internal power line PL2, and a third internal voltage to the second processor 110_2 through a third internal power line PL3.

[0114] When the power down signal (PWDIS) is activated, the power supply circuit 300a can not supply the internal voltage to the storage controller 100a and the nonvolatile memory 200, respectively, and power off the storage controller 100a and the nonvolatile memory 200. For example, when the power supply circuit 300a receives the power down signal of a high level, the power supply circuit 300a can power off the storage controller 100a and the nonvolatile memory 200. In contrast, when the power supply circuit 300a receives the power down signal of a low level, the power supply circuit 300a can supply the internal voltage to the storage controller 100a and the nonvolatile memory 200, respectively, and power on the storage controller 100a and the nonvolatile memory 200.

[0115] After the power supply circuit 300a powers off the storage controller 100a and the nonvolatile memory 20 in response to the activated power down signal, when a reference time elapses, the power supply circuit 300a of the storage device 10a can temporarily power on the first processor 110_1. For example, when the power supply circuit 300a receives the activated power down signal, the power supply circuit 300a can not supply the internal voltage to the storage controller 100a and the nonvolatile memory 200 for the reference time. When the reference time elapses, the power supply circuit 300a can supply the first internal voltage to the first processor 110_1 through the first internal power line PL1. Accordingly, even when the power down function is activated, the storage device 10a can periodically supply the first internal voltage to the first processor 110_1, and thus, the first processor 110_1 can perform the data recovery operation on the nonvolatile memory 200 during the first internal voltage is applied to the first processor 110_1. Read errors caused by retention errors that can occur when the storage device 10a is maintained in the powered-off state can be reduced, and the lifespan of the storage device 10a can be extended.

[0116] Referring to Figure 9 , the storage controller 100a can include the first processor 110_1, the second processor 110_2, the host interface 120, the RAM 130, and the memory interface 140. The first processor 110_1, the second processor 110_2, the host interface 120, the RAM 130, and the memory interface 140 can communicate with each other through the bus 150. Although the first processor 110_1 and the second processor 110_2 are shown as separate components in Figure 8 , the storage controller 100a according to the present embodiment is not limited thereto, and the first processor 110_1 and the second processor 110_2 can constitute one processor and perform different operations in the storage controller 100a, respectively.

[0117] The first processor 110_1 may be an additional core processor configured to perform data recovery operations when the power-off function of the memory controller 100a is activated. For example, the first processor 110_1 may be a programmable logic device (PLD). In an example embodiment, the first processor 110_1 may have lower power consumption than the second processor 110_2.

[0118] The second processor 110_2 may be a controller configured to control the overall operation of the storage controller 100a. The second processor 110_2 may include a CPU or an MP. The second processor 110_2 may drive firmware for driving the storage controller 100a. The firmware may be loaded and driven in the RAM 130. Therefore, when the power-off function is deactivated, the second processor 110_2 may drive the firmware loaded in the RAM 130 and perform a data recovery operation.

[0119] The first processor 110_1 can receive power from a power supply circuit (eg, Figure 8 The host interface 120 may receive the second internal voltage IV2 from the power supply circuit 300a via the second internal power line PL2. In an example embodiment, the first internal voltage IV1 and the third internal voltage IV3 may have the same voltage level. However, the present invention is not limited thereto, and the first internal voltage IV1 and the third internal voltage IV3 may have different voltage levels.

[0120] When the power-off function is activated, the first internal voltage IV1, the second internal voltage IV2, and the third internal voltage IV3 supplied to the first processor 110_1, the second processor 110_2, and the host interface 120 may be blocked. In an exemplary embodiment, when a reference time has elapsed after the power-off function is activated, the first internal voltage IV1 may be temporarily supplied to the first processor 110_1, and the second internal voltage IV2 and the third internal voltage IV3 supplied to the host interface 120 and the second processor 110_2 may be interrupted. Thus, the host device 20 can recognize that the power-off function of the storage device 10a has been activated and, at the same time, can periodically perform data recovery operations within the storage device 10a. This can prevent the storage device 10a from degrading due to an increase in the retention time of the non-volatile memory 200, which may occur when the storage device 10a is placed in a power-off state.

[0121] The RAM 130 can operate via the control of the first and second processors 110_1 and 110_2. In an example embodiment, the RAM 130 can be used as a buffer memory and temporarily store data. For example, data temporarily stored in the RAM 130 can be written to the nonvolatile memory 200 or transmitted to the host device 20. In the power-down function activation mode, the first processor 110_1 can restore data of a target memory block, temporarily store the data in the RAM 130, and then re-write the data to the target memory block. However, the inventive concept is not limited thereto, and the first processor 110_1 can further include a buffer memory directly connected thereto without using the bus 150. Accordingly, in the power-down function activation mode, the first processor 110_1 can perform a data restoration operation by using the buffer memory directly connected thereto.

[0122] Figure 10 A flowchart of a method of operating the storage device 10a according to an embodiment of the inventive concept is outlined in one example. Here, except that operation S40 and operation S50 are replaced with operation S40a and operation S50a, respectively, Figure 10 The method of Figure 4 is substantially similar to the method of

[0123] Referring to Figure 8 , Figure 9 and Figure 10 , after operation S10 and operation S20 are performed, and upon determining that the reference time has elapsed (S30 = Yes), the storage device 10a can maintain the power-off state of the second processor 110_2, but power on the first processor 110a (S40a). That is, the power supply circuit 300a can temporarily provide the first internal voltage IV1 to the first processor 110_1 through the first internal power line PL1, but not provide the second internal voltage IV2 or the third internal voltage IV3 to the host interface 120 and the second processor 110_2, respectively. Because the host interface 120 is maintained in the power-off state, the host device 20 can determine that the power-up function of the storage device 10a is activated. In this way, power consumption can be reduced by powering off the second processor 110_2 that is not used during the data restoration operation.

[0124] Then, the storage device 10a can perform a data recovery operation on the data written to the nonvolatile memory 200 (S50a). Because the first processor 110_1 is powered on in operation S40a, the data recovery operation can be performed using the first processor 110_1. For example, power consumption caused by the data recovery operation performed by the first processor 110_1 can be lower than power consumption caused by the data recovery operation performed by the second processor 110_2. Therefore, because the storage device 10a according to the present embodiment includes the first processor 110_1 as an additional processor configured to internally perform the data recovery operation in the power-off function activation mode, power consumption caused by the data recovery operation can be relatively reduced.

[0125] Figure 11 is further illustrated in one example (300_2) of a power supply circuit 300a according to an embodiment of the present inventive concept. Figure 8

[0126] Referring to Figure 8 and Figure 11 , the power supply circuit 300a can include a power supply controller 310a, a voltage regulator 320a, a first switching circuit 330_1, and a second switching circuit 330_2, wherein the power supply controller 310a can include a timer 315.

[0127] Here, the power supply controller 310a can generate the first control signal CS1, the second control signal CS2, and the third control signal CS3 in response to the power-off signal. In an example embodiment, the power supply controller 310a can generate the first control signal CS1, the second control signal CS2, and the third control signal CS3 based on a comparison result between a predetermined reference time (Tr) and an elapsed time counted by the timer 315.

[0128] In an example embodiment, at least one of a lookup table LUT of Figure 6A and a lookup table LUTa of Figure 6B may be used in the power supply controller 310a. That is, the power supply controller 310a can store reference time information corresponding to a storage unit characteristic, and store reference time information corresponding to a usage period of the storage device.

[0129] ​When the power down signal is deactivated, the power supply controller 310a can provide the first control signal CS1 to the voltage regulator 320a so that the voltage regulator 320a generates the first internal voltage IV1, the second internal voltage IV2, and the third internal voltage IV3. When the power down signal is deactivated, the power supply controller 310a can provide the second control signal CS2 to the first switching circuit 330_1 so that the first switching circuit 330_1 transfers the second internal voltage IV2 to the second internal power line PL2. Also, when the power down signal is deactivated, the power supply controller 310a can provide the third control signal CS3 to the second switching circuit 330_2 so that the second switching circuit 330_2 transfers the third internal voltage IV3 to the third internal power line PL3.

[0130] When the power down signal is activated, the power supply controller 310a can provide the first control signal CS1 to the voltage regulator 320a so that the voltage regulator 320a does not provide (i.e., interrupts) the first internal voltage IV1, the second internal voltage IV2, and the third internal voltage IV3. When a reference time elapses after the power down signal is activated, the power supply controller 310a can generate the first control signal CS1 again so that the voltage regulator 320a generates the first internal voltage IV1, the second internal voltage IV2, and the third internal voltage IV3. In this case, the power supply controller 310a can provide the second control signal CS2 to the first switching circuit 330_1 so that the second internal voltage IV2 to the second internal power line PL2 is interrupted by the first switching circuit 330_1. Also, the power supply controller 310a can provide the third control signal CS3 to the second switching circuit 330_2 so that the third internal voltage IV3 to the third internal power line PL3 is interrupted. Accordingly, when the reference time elapses after the power down signal is activated, the first internal voltage IV1 can be provided to the first processor 110_1, the second internal voltage IV2 is not provided to the host interface 120 (i.e., is interrupted), and the third internal voltage IV3 is not provided to the second processor 110_2 (i.e., is interrupted).

[0131] When the first internal voltage IV1 is supplied to the first processor 110_1 while the power down signal is activated, the first processor 110_1 can perform a data recovery operation. When the data recovery operation is completed, the power controller 310a can again supply the first control signal CS1 to the voltage regulator 320a so that the voltage regulator 320a interrupts the first internal voltage IV1, the second internal voltage IV2, and the third internal voltage IV3. In the storage device according to an embodiment of the inventive concept, while the power down signal is activated, power can be supplied to the first processor 110_1 while power to the second processor 110_2 is interrupted. In this way, the data recovery operation can be performed using the first processor 110_1 but relatively little power is consumed.

[0132] The voltage regulator 320a can be selectively activated in response to the first control signal CS1. The voltage regulator 320a can receive the external voltage EV and generate the first internal voltage IV1 to the third internal voltage IV3. The first internal voltage IV1 can be an operating voltage of the first processor 110_1, the second internal voltage IV2 can be an operating voltage of the host interface 120, and the third internal voltage IV3 can be an operating voltage of the second processor 110_2.

[0133] The first switching circuit 330_1 can receive the second internal voltage IV2 from the voltage regulator 320a and supply the second internal voltage IV2 to the second internal power line PL2 in response to the second control signal CS2. The second switching circuit 330_2 can receive the third internal voltage IV3 from the voltage regulator 320a and supply the third internal voltage IV3 to the third internal power line PL3 in response to the third control signal CS3. In an example embodiment, the first switching circuit 330_1 and the second switching circuit 330_2 can each include a multiplexer.

[0134] Figure 12 The operation S50 of FIG. 50 is further outlined in one example (S50a) according to an embodiment of the inventive concept. Here, it is assumed that the data recovery operation performed with respect to the target storage block (S50a) includes the operations (S51) and (S55) as described with respect to the method of FIG. 51. However, the operation (S53a) is substituted for the operation (S53), and a new operation (S57a) is added. Figure 7 Figure 7 The operation S50 of FIG. 50 is further outlined in one example (S50a) according to an embodiment of the inventive concept. Here, it is assumed that the data recovery operation performed with respect to the target storage block (S50a) includes the operations (S51) and (S55) as described with respect to the method of FIG. 51. However, the operation (S53a) is substituted for the operation (S53), and a new operation (S57a) is added.

[0135] Referring to Figure 7 , Figure 8 , Figure 9 and Figure 12 ​After the storage device 10a corrects an error of the data stored in the target storage block (for example, using the ECC parity bit corresponding to the data of the target storage block), the storage device 10a can store valid data among the data stored in the target storage block in the buffer memory (S53a). For example, the storage device 10a can store the valid data in the RAM 130. However, the storage device 10a is not limited thereto, but can also include a buffer memory directly connected to the first processor 110_1, and the valid data can be stored in the buffer memory.

[0136] In the example embodiment, the storage device 10a can determine that the data in which the error is uncorrectable is invalid data. The data in which the uncorrectable error has occurred can be determined to be invalid data.

[0137] Then, the storage device 10a can erase the data stored in the target storage block (S55). That is, when all the valid data among the data stored in the target storage block is stored in the buffer memory (S53a), the storage device 10a can perform operation S55.

[0138] Then, the storage device 10a can re-write the valid data stored in the buffer memory to the target storage block (S57a). Here, because the valid data is re-written to the target storage block, there is no need to change the storage block address in the mapping table.

[0139] Regarding Figure 12 The described method S50a can involve a data recovery method performed by the first processor 110_1 on the target storage block when the power down function of the storage device 10a is activated. When the power down function of the storage device 10a is deactivated, the data recovery operation described in operation S50 of the method S50 can be performed by the second processor 110_2. Figure 7

[0140] While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.​

Claims

1. A storage device, comprising: a power circuit that receives a power disable signal from the host device and provides a first internal voltage to the processor and a second internal voltage to the host interface; A non-volatile memory, the non-volatile memory comprising a storage device; as well as a storage controller that controls the nonvolatile memory and includes the processor and the host interface, the processor performing a data recovery operation on data stored in the storage device, and the host interface communicating with the host device, wherein When the power deactivation signal is activated at a power-off moment, the storage controller is powered off, the power supply circuit interrupts the first internal voltage and the second internal voltage during a reference time after the power-off moment, and provides the first internal voltage to the processor and does not provide the second internal voltage to the host interface after the reference time has passed from the power-off moment.

2. The storage device according to claim 1, wherein The power supply circuit sets the reference time in response to a time setting signal received from the memory controller.

3. The storage device according to claim 1, wherein The power supply circuit sets the reference time in response to a time setting signal received from the host device. The storage device according to claim 3 , wherein: The power supply circuit receives the power deactivation signal and the time setting signal from the host device through the same external power line. The storage device according to claim 1 , wherein: The power supply circuit comprises: a power controller that generates a first control signal and a second control signal in response to the power deactivation signal; a voltage regulator that generates the first internal voltage and the second internal voltage in response to the first control signal; and A switch circuit interrupts the second internal voltage in response to the second control signal. The storage device according to claim 5 , wherein: The power controller further includes: a timer for measuring the elapsed time from the power-off moment, The power controller compares the elapsed time with the reference time to generate a comparison result, and generates the first control signal and the second control signal in response to the comparison result.

7. The storage device according to claim 5, wherein: The power controller stores a plurality of reference times, and one of the plurality of reference times is selected as the reference time. The storage device according to claim 7 , wherein: Each of the plurality of reference times corresponds to a different usage period of the storage device.

9. The storage device according to claim 8, wherein: The plurality of reference times include a first reference time corresponding to a usage period less than or equal to a threshold usage period and a second reference time corresponding to a usage period greater than the threshold usage period.

10. A method for operating a storage device, the storage device comprising a non-volatile memory and a storage controller, the non-volatile memory comprising a storage device, the storage controller comprising a processor and a host interface, the method comprising: upon receiving an activated power disable signal from a host device at a power-off moment, powering off the memory controller to place the processor and the host interface in a power-off state; determining whether a reference time has elapsed after the power-off moment; as well as When it is determined that the reference time has passed after the power-off moment, an internal voltage is supplied to the processor to put the processor in a power-on state, thereby causing the processor to perform a data recovery operation on the data stored in the storage device and maintain the power-off state of the host interface.

11. The method according to claim 10, wherein: The data recovery operation includes: correcting errors in data stored in a target memory block of the memory device; writing valid data among the data stored in the target memory block to a free memory block of the memory device; and Another free memory block is generated by erasing the target memory block.

12. The method according to claim 11, wherein The correcting of errors in the data stored in the target memory block of the memory device is performed in units of pages.

13. The method according to claim 10, wherein: The data recovery operation includes: correcting errors in data stored in a target memory block of the memory device; storing valid data among the data stored in the target storage block into a buffer memory; erasing the target storage block; and The valid data is rewritten from the buffer memory to the target memory block.

14. The method according to claim 10, further comprising: receiving a time setting signal from the host device; as well as The reference time is set in response to the time setting signal.

15. The method according to claim 14, wherein The power deactivation signal includes the time setting signal.

16. A method for operating a storage device, the storage device comprising a nonvolatile memory and a storage controller, the storage controller comprising a processor and a host interface, the method comprising: receiving a power disable signal from a host device; causing the storage device to operate in a power-disable function activation mode when the power-disable signal is activated, and causing the storage device to operate in a power-disable function deactivation mode when the power-disable signal is deactivated, Wherein, causing the storage device to operate in the power-disable function activation mode includes: Powering off the processor and the host interface at a power-off moment; powering on the processor after a reference time has elapsed from the power-off moment; performing a data recovery operation on data stored in the non-volatile memory using the processor; and The processor is powered off when the data recovery operation is completed.

17. The method according to claim 16, wherein The data recovery operation includes: correcting errors in data stored in a target memory block of the nonvolatile memory; writing valid data among the data stored in the target memory block to a free memory block of the nonvolatile memory; and Another free memory block is generated by erasing the target memory block.

18. The method according to claim 16, wherein The data recovery operation includes: correcting errors in data stored in a target memory block of the nonvolatile memory; storing valid data among the data stored in the target storage block in a buffer memory; erasing the target storage block; and The valid data is rewritten from the buffer memory to the target memory block.

19. The method according to claim 16, wherein Causing the storage device to operate in the power-off function deactivation mode also includes performing a data recovery operation on the data stored in the non-volatile memory by correcting errors in the data stored in a target storage block of the non-volatile memory, writing valid data among the data stored in the target storage block to a free storage block of the non-volatile memory, and generating another free storage block by erasing the target storage block.

20. The method according to claim 16, wherein Causing the storage device to operate in the power-disable function activation mode includes: receiving a time setting signal from the host device; and The reference time is set in response to the time setting signal.

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