Semiconductor device and method of forming a semiconductor device

Abstract

Embodiments of the present application disclose a semiconductor device and a method for forming the same, the semiconductor device comprising a nanosheet field effect transistor (NSFET) located in a first region and a fin field effect transistor (FinFET) located in a second region. In one embodiment, a device comprises a first memory cell, the first memory cell comprising: a first transistor comprising a first channel region, the first channel region comprising a first plurality of semiconductor nanostructures; and a second transistor comprising a second channel region, the second channel region comprising a semiconductor fin.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming semiconductor devices. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to one embodiment of the present application, a semiconductor device is provided, including: a first memory unit, the first memory unit including: a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.

[0005] According to another embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a multilayer semiconductor stack located above a semiconductor substrate, the multilayer semiconductor stack comprising alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material; etching the multilayer semiconductor stack to form a first opening exposing the semiconductor substrate; forming a third semiconductor material filling the first opening; etching the multilayer semiconductor stack and the semiconductor substrate to form a first nanostructure extending from the semiconductor substrate; and etching the third semiconductor material and the semiconductor substrate to form a first fin extending from the semiconductor substrate.

[0006] According to another embodiment of the present application, a semiconductor device is provided, including: a first nanostructure extending from a semiconductor substrate in a first region of the semiconductor substrate, the first nanostructure including a plurality of semiconductor layers located above the semiconductor substrate; and a first fin extending from the semiconductor substrate in a second region of the semiconductor substrate, the first fin including a semiconductor material located above the semiconductor substrate, the semiconductor material having a constant composition, a top surface of the semiconductor material being flush with a top surface of a topmost semiconductor layer of the plurality of semiconductor layers, and a bottom surface of the semiconductor material being flush with a bottom surface of a bottommost semiconductor layer of the plurality of semiconductor layers; and a gate stack extending above the first nanostructure and the first fin. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 An example of a semiconductor device including a nanosheet field effect transistor (NSFET) and a fin field effect transistor (FinFET) in a perspective view according to some embodiments is shown;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B , Fig. 21C , Fig.22A , Fig. 22B , Fig. 22C , Fig.23A , Fig. 23B , Fig.23C , Fig.24A , Fig. 24B , Fig.24C , Fig.25A , Fig.25B , Fig.25C , Fig.26A , Fig.26B , Fig.26C , Fig.27A , Fig.27B ,and Fig.27C is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device according to some embodiments;

[0010] Figures 28A-30B A circuit diagram and layout of a static random access memory (SRAM) cell according to some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0012] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] Various embodiments provide semiconductor devices including both nanostructure (e.g., nanosheets, nanowires, etc.) field effect transistors (NSFETs) and fin field effect transistors (FinFETs). NSFETs can be used to provide transistors with relatively high drive currents, which increases the performance and speed of semiconductor devices. FinFETs can include fins having a width less than the width of the nanostructures in NSFETs, can be used to reduce cell size, and provide transistors with relatively low drive currents. FinFETs can also have better N-well / P-well boundaries, and can reduce leakage and latching problems. In some embodiments, the semiconductor device can be a static random access memory (SRAM) cell, etc. For SRAM cells, it may be desirable to use strong transistors in the NMOS region, which may include pull-down transistors and pass-gate transistors, and weak transistors in the PMOS region, which may include pull-up transistors. In various embodiments, NSFETs can be formed in the NMOS region of the SRAM cell, and FinFETs can be formed in the PMOS region of the SRAM cell. Including both NSFETs and FinFETs can result in faster SRAM operation, reduced cell size (compared to an SRAM cell including only NSFETs), better cell current, and smaller threshold voltage (Vt ) mismatch, and a lower minimum supply voltage (V ccmin ).

[0014] Figure 1 An exemplary perspective view of a semiconductor device including both a NSFET and a FinFET according to some embodiments is shown. The NSFET includes a nanostructure 110 located on a substrate 50 (e.g., a semiconductor substrate). The nanostructure 110 includes a first semiconductor layer 52A-52D, which serves as a channel region of the nanostructure 110. The FinFET includes a fin 112 located on the substrate 50. The fin 112 includes a first epitaxial semiconductor material 84, which serves as a channel region of the fin 112. Isolation regions 114 are disposed in the substrate 50, and the nanostructure 110 and the fin 112 protrude above and from adjacent isolation regions 114. Although the isolation region 114 is described / illustrated as being separated from the substrate 50, the term "substrate" as used herein may be used to refer to only the semiconductor substrate, or to a combination of the semiconductor substrate and the isolation region. In addition, although the nanostructure 110 and the fin 112 are shown as a single continuous material with the substrate 50, the nanostructure 110, the fin 112, and / or the substrate 50 may include a single material or multiple materials. In this document, the nanostructure 110 and the fin 112 refer to the portions extending between adjacent isolation regions 114.

[0015] The gate dielectric layer 150 is along the top surface and sidewalls of the first semiconductor layer 52A and the first epitaxial semiconductor material 84, and along the top surface, sidewalls and bottom surface of the first semiconductor layers 52B-52D. The gate electrode 152 is located above the gate dielectric layer 150. The epitaxial source / drain region 136 is disposed on the opposite side of the nanostructure 110 and the fin 112 relative to the gate dielectric layer 150 and the gate electrode 152. Figure 1 Reference cross sections used in subsequent figures are also shown. Cross section AA' is along the longitudinal axis of the gate electrode 152, and along a direction perpendicular to the direction of current flow between, for example, the epitaxial source / drain regions 136 of the NSFET / FinFET. Cross section BB' is perpendicular to cross section AA', and along the longitudinal axis of the nanostructure 110 in the NMOS region of the NSFET, and along the direction of current flow between, for example, the epitaxial source / drain regions 136 of the NSFET. Cross section CC' is parallel to cross section BB', and extends through the fin 112 in the PMOS region of the FinFET, and along the direction of current flow between, for example, the epitaxial source / drain regions 136 of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0016] Some embodiments discussed herein are discussed in the context of forming NSFETs / FinFETs using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices such as planar FETs.

[0017] Figures 2 to 27C is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device including a NSFET and a FinFET according to some embodiments. Figures 2 to 14 , Fig.15A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A ,and Fig.27A Shows Figure 1 Reference section AA' shown in . Fig. 15B , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig. 21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B , Fig.26B ,and Fig.27B Shows Figure 1 Reference section BB' is shown. Fig. 15C , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig. 21C , Fig. 22C , Fig.23C , Fig.24C , Fig.25C , Fig.26C ,and Fig.27C Shows Figure 1 Reference section CC' is shown.

[0018] exist Figure 2In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0019] The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form an n-type device such as an NMOS transistor, for example, an n-type NSFET. The region 50P can be used to form a p-type device such as a PMOS transistor, for example, a p-type FinFET. The region 50N can be physically separated from the region 50P (not shown separately), and any number of device features (such as other active devices, doped regions, isolation structures, etc.) can be set between the region 50N and the region 50P. Although two regions 50N and one region 50P are shown, any number of regions 50N and regions 50P can be provided.

[0020] The substrate 50 may be lightly doped with p-type or n-type impurities. An anti-punch-through (APT) implant may be performed on an upper portion of the substrate 50 to form an APT region 51. During the APT implant, dopants may be implanted into the regions 50N and 50P. The dopants may have a similar polarity to the source / drain regions to be formed in each of the regions 50N and 50P (e.g., as shown below with respect to Fig. 20A and Fig. 20B The APT region 51 may be of a conductivity type opposite to the conductivity type of the epitaxial source / drain region 136 discussed above. The APT region 51 may extend below the subsequently formed source / drain region in the resulting NSFET / FinFET to be formed in a subsequent process. The APT region 51 may be used to reduce leakage from the source / drain region to the substrate 50. In some embodiments, the doping concentration in the APT region 51 may be approximately 1×10 13 Atom / cm 3 About 1×10 14 Atom / cm 3 For the sake of simplicity and clarity, the APT region 51 is not shown in subsequent figures.

[0021] In addition Figure 2In the embodiment of the present invention, a multilayer stack 70 is formed over a substrate 50. The multilayer stack 70 includes alternating first semiconductor layers 52 and second semiconductor layers 54 of different semiconductor materials. The first semiconductor layer 52 may be formed by a first semiconductor material, which may include, for example, silicon (Si), siliconized carbon (SiC), etc. The second semiconductor layer 54 may be formed by a second semiconductor material, which may include, for example, silicon germanium (SiGe), a III-V compound semiconductor material (e.g., gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), etc.). In other embodiments, the first semiconductor layer 52 may be formed by a second semiconductor material, and the second semiconductor layer 54 may be formed by a first semiconductor material. For purposes of illustration, the multilayer stack 70 includes five first semiconductor layers 52 (e.g., first semiconductor layers 52A-52E) and four second semiconductor layers 54 (e.g., second semiconductor layers 54A-54D). In other embodiments, the multilayer stack 70 may include any number of first semiconductor layers 52 and second semiconductor layers 54. Each layer of the multilayer stack 70 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like.

[0022] For the purpose of illustration, the first semiconductor layer 52 will be described as forming a channel region in a complete NSFET device. The second semiconductor layer 54 may be a sacrificial layer that may be removed later. Each of the first semiconductor layers 52A-52D may have a thickness of about 8 nm to about 10 nm (e.g., about 9 nm), and each of the second semiconductor layers 54A-54C may have a thickness of about 6 nm to about 8 nm (e.g., about 7 nm). The second semiconductor layer 52E and the first semiconductor layer 54D may form an etch stop layer, etc. The second semiconductor layer 54D may have a thickness of about 6 nm to about 7 nm (e.g., about 6.5 nm), and the first semiconductor layer 52E may have a thickness of about 6 nm to about 7 nm (e.g., about 6.5 nm). However, in some embodiments, the second semiconductor layers 54A-54C may form a channel region in a complete NSFET device, and the first semiconductor layers 52A-52D may be sacrificial layers.

[0023] exist Figure 3 In the embodiment of the present invention, a patterned mask such as a first patterned photoresist 80 is formed on the multilayer stack 70. The first patterned photoresist 80 can be formed by depositing a photoresist layer over the multilayer stack 70 using spin coating or the like. The photoresist layer can then be patterned by exposing the photoresist layer to a patterned energy source (e.g., a patterned light source) and developing the photoresist layer to remove exposed or unexposed portions of the photoresist layer, thereby forming the first patterned photoresist 80. Figure 3As shown, the first patterned photoresist 80 may cover the region 50N, and the opening in the first patterned photoresist 80 may expose the region 50P.

[0024] exist Figure 4 In the embodiment of the present invention, the multilayer stack 70 in the region 50P is etched using the first patterned photoresist 80 as a mask to form a first opening 82 in the multilayer stack 70. The multilayer stack 70 may be etched by a suitable etching process such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching process may be anisotropic. Figure 4 As shown, each of the first semiconductor layers 52A- 52E and each of the second semiconductor layers 54A- 54D are etched in the region 50P to expose the substrate 50 .

[0025] exist Figure 5 In the embodiment of the present invention, the first patterned photoresist 80 is removed, and a first epitaxial semiconductor material 84 filling the first opening 82 is formed. The first patterned photoresist 80 can be removed by any acceptable process such as an ashing process, a stripping process, or a combination thereof. The first epitaxial semiconductor material 84 can be deposited by an epitaxial growth process such as CVD, ALD, VPE, MBE, etc. The first epitaxial semiconductor material 84 may include a semiconductor material such as silicon, silicon carbide, silicon germanium, silicon phosphide, etc., and may include a material that is the same as or different from the semiconductor material used to form the multilayer stack 70.

[0026] In various embodiments, the first epitaxial semiconductor material 84 may be doped with n-type impurities, such as phosphorus, arsenic, antimony, etc., or with p-type impurities, such as boron, boron fluoride, indium, etc. The first epitaxial semiconductor material 84 may be doped in situ during growth, or the first epitaxial semiconductor material 84 may be doped using subsequent implantation.

[0027] The first epitaxial semiconductor material 84 may be grown such that the first epitaxial semiconductor material 84 extends above the top surface of the multilayer stack 70. After the first epitaxial semiconductor material 84 is grown, the first epitaxial semiconductor material 84 and the multilayer stack 70 may be planarized using an acceptable planarization process such as chemical mechanical polishing (CMP), an etch-back process, or the like, or a combination thereof. The planarization process may remove the first semiconductor layer 52E, and may be performed until the second semiconductor layer 54D is exposed. Thus, after the planarization process, the top surface of the second semiconductor layer 54D may be flush with the top surface of the first epitaxial semiconductor material 84, as shown in FIG. Figure 5 shown.

[0028] Relative to Figures 2 to 5The described process is only one example of how to form the multilayer stack 70 and the first epitaxial semiconductor material 84. In some embodiments, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the substrate 50 below. The epitaxial growth process may be implemented to epitaxially grow the multilayer stack 70 in the trenches, and remove the dielectric layer so that the multilayer stack 70 is formed over the substrate 50. The first epitaxial semiconductor material 84 may then be formed in the recess formed by removing the dielectric layer. Any other suitable process may be used to form the multilayer stack 70 and the first epitaxial semiconductor material 84.

[0029] exist Figure 6-Figure 12 In the embodiment, the multilayer stack 70 and the first epitaxial semiconductor material 84 are patterned to form nanostructures (e.g., Fig.12 The nanostructures 110 discussed below) and the fins (eg, Fig.12 The fin 112 discussed). Figure 6 In the embodiment of the present invention, one or more mask layers are formed over the multilayer stack 70 and the first epitaxial semiconductor material 84. For example, in some embodiments, a first mask layer 90, a second mask layer 92, and a patterned mask such as a patterned mask 94 are formed over the multilayer stack 70 and the first epitaxial semiconductor material 84. The first mask layer 90 may include: a nitride, such as silicon nitride (SiN); a high-k dielectric material, such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), tantalum oxide (Ta2O5), titanium dioxide (TiO2), etc.; etc. The first mask layer 90 may have a thickness of about 20nm to about 25nm (e.g., about 22.5nm). The first mask layer 90 may be deposited by a process such as CVD, physical vapor deposition (PVD), ALD, etc. The second mask layer 92 may include an oxide, such as silicon oxide, etc. The second mask layer 92 may have a thickness of about 50nm to about 60nm (e.g., about 55nm). The second mask layer 92 may be deposited by processes such as CVD, PVD, ALD, etc. The patterned mask 94 may include: silicon, such as amorphous silicon (a-Si); high-k dielectric materials, such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), tantalum oxide (Ta2O5), titanium dioxide (TiO2), etc.; and the like. The patterned mask 94 may be formed using CVD, PVD, ALD, etc. The patterned mask 94 may have a thickness of about 60 nm to about 80 nm (e.g., about 70 nm). In some embodiments, the patterned mask 94 may be formed by a material having an etch selectivity to the second mask layer 92, so that the patterned mask 94 may be removed without etching or removing the second mask layer 92.

[0030] The patterned mask 94 can be patterned by using photolithography and etching. For example, a mask layer (not shown separately) can be deposited above the second mask layer 92. A photoresist (not shown separately) can be deposited above the mask layer using spin coating or the like. The photoresist layer can then be patterned by exposing the photoresist layer to a patterned energy source (e.g., a patterned light source) and developing the photoresist layer to remove exposed or unexposed portions of the photoresist layer, thereby forming a patterned photoresist. The pattern of the patterned photoresist can then be transferred to the mask layer using an appropriate etching process, such as RIE, NBE, etc., or a combination thereof, to form a patterned mask 94. The etching process can be anisotropic. The patterned photoresist can be removed by any acceptable process such as an ashing process, a stripping process, etc., or a combination thereof.

[0031] exist Figure 7 , a first spacer 96 is formed along the sidewalls of the patterned mask 94. The first spacer 96 may have a thickness of about 8 nm to about 10 nm (e.g., about 9 nm). The first spacer 96 may include a nitride (e.g., silicon nitride (SiN)), an oxide (e.g., silicon oxide), etc., or a combination thereof. The first spacer 96 may be deposited by a process such as CVD, PVD, ALD, etc. The first spacer 96 may then be anisotropically etched using a process such as RIE, NBE, etc., so that only a portion on the sidewalls of the patterned mask 94 remains. In various embodiments, the first spacer 96 may be formed by a material having an etch selectivity to the second mask layer 92 and the patterned mask 94, so that the first spacer 96 may be removed, but the second mask layer 92 or the patterned mask 94 is not etched or removed.

[0032] exist Figure 8 In the embodiment, a patterned mask such as a second patterned photoresist 98 is formed over the region 50P, and the first spacer 96 is removed from the region 50N. The second patterned photoresist 98 can be formed by using spin coating or the like. Figure 7 The photoresist layer 98 may be formed by depositing a photoresist layer over the structure shown in FIG. The photoresist layer may then be patterned by exposing the photoresist layer to a patterned energy source (e.g., a patterned light source) and developing the photoresist layer to remove exposed or unexposed portions of the photoresist layer, thereby forming a second patterned photoresist 98. The first spacer 96 may then be removed from the region 50N using a suitable etching process, such as an isotropic etching (e.g., a wet etching process), an anisotropic etching (e.g., a dry etching process), etc. The second patterned photoresist 98 may be removed by any acceptable process such as an ashing process, a stripping process, etc., or a combination thereof. In some embodiments, an additional mask layer may be used with the second patterned photoresist 98 to provide additional protection during the etching process used to remove the first spacer 96 from the region 50N.

[0033] exist Fig. 9 In the embodiment, a patterned mask such as the third patterned photoresist 100 is formed over the region 50N, and the patterned mask 94 is removed from the region 50P. The third patterned photoresist 100 may be formed on the region 50N by using spin coating or the like. Figure 8 50P。 The photoresist layer may be formed by depositing a photoresist layer (after removing the second patterned photoresist) above the structure shown. The photoresist layer may then be patterned by exposing the photoresist layer to a patterned energy source (e.g., a patterned light source) and developing the photoresist layer to remove exposed or unexposed portions of the photoresist layer, thereby forming a third patterned photoresist 100. The patterned mask 94 may then be removed from the region 50P using an appropriate etching process, such as isotropic etching (e.g., a wet etching process), anisotropic etching (e.g., a dry etching process), etc. The third patterned photoresist 100 may be removed by any acceptable process such as an ashing process, a stripping process, etc., or a combination thereof. In some embodiments, an additional mask layer may be used with the third patterned photoresist 100 to provide additional protection during the etching process used to remove the patterned mask 94 from the region 50P.

[0034] exist Fig.10 , a second spacer 102 is formed adjacent to the patterned mask 94 and the first spacer 96. The second spacer 102 may have a thickness of about 2 nm to about 4 nm (e.g., about 3 nm). The second spacer 102 may include a nitride (e.g., silicon nitride (SiN)), an oxide (e.g., silicon oxide), etc., or a combination thereof. The second spacer 102 may be deposited by a process such as CVD, PVD, ALD, etc. The second spacer 102 may then be anisotropically etched using a process such as RIE, NBE, etc., so that only portions on the sidewalls of the patterned mask 94 and the first spacer 96 remain. If desired, the second spacer 102 may be used to expand the patterned mask 94 and / or the first spacer 96.

[0035] exist Fig.11 In the embodiment, the patterned mask 94, the first spacer 96, and the second spacer 102 are used as masks to etch the second mask layer 92 and the first mask layer 90. The second mask layer 92 and the first mask layer 90 can be etched using an anisotropic etching process such as RIE, NBE, etc. The second mask layer 92 and the first mask layer 90 can be etched by a single process or multiple processes. Fig.11 As shown, the first spacers 96 and the second spacers 102 may be consumed by a process for etching the second mask layer 92 and the first mask layer 90 .

[0036] exist Fig.12In the embodiment of the present invention, the patterned mask 94, the second mask layer 92, and the first mask layer 90 are used as masks to etch the multilayer stack 70, the first epitaxial semiconductor material 84, and the substrate 50 to form the nanostructure 110 in the region 50N and the fin 112 in the region 50P. The multilayer stack 70, the first epitaxial semiconductor material 84, and the substrate 50 can be etched using an anisotropic etching process such as RIE, NBE, etc. Fig.12 As shown, patterned mask 94 and second mask layer 92 may be consumed by a process for etching multilayer stack 70 , first epitaxial semiconductor material 84 , and substrate 50 .

[0037] The nanostructure 110 may have a width of about 10 nm to about 40 nm (e.g., about 30 nm). The fin 112 may have a width of about 6 nm to about 8 nm (e.g., about 7 nm). The ratio of the width of the nanostructure 110 to the width of the fin 112 may be about 3 to about 8. Adjacent nanostructures 110 in region 50N may have a fin-to-fin spacing of about 40 nm to about 50 nm (e.g., about 45 nm). Adjacent fins 112 in region 50P may have a fin-to-fin spacing of about 35 nm to about 45 nm (e.g., about 40 nm). The nanostructure 110 in region 50N may have a fin-to-fin spacing of about 40 nm to about 55 nm (e.g., about 47.5 nm) between the adjacent fins 112 in region 50P. The ratio of the fin-to-fin spacing in region 50N to the fin-to-fin spacing in region 50P may be about 1 to about 1.5, for example, about 1.2. Since the fin 112 has a width that is smaller than the width of the nanostructure 110, and the fin-to-fin spacing in the region 50P including the fin 112 is smaller than the fin-to-fin spacing in the region 50N including the nanostructure 110, including both the nanostructure 110 and the fin 112 can reduce the area required for the semiconductor device including the nanostructure 110 and the fin 112.

[0038] In addition, NSFET devices may have stronger device performance, faster speed, and smaller threshold voltage (V T ) mismatch, and a lower minimum supply voltage (V ccmin ). FinFET devices can have better N / P well boundaries, reduced leakage, and reduced latching issues. The inclusion of nanostructures 110 in region 50N and fins 112 in region 50P allows semiconductor devices including both NSFETs and FinFETs to optimize the advantages of both NSFETs and FinFETs, thereby improving device performance, optimizing cell area, and reducing device defects.

[0039] exist Fig.13In the embodiment, the shallow trench isolation region 114 is formed adjacent to the nanostructure 110 and the fin 112, and the first mask layer 90 is removed. The STI region 114 can be formed by forming an insulating material (not shown separately) above the substrate 50 and between the adjacent nanostructures 110 and the fin 112. The insulating material can be an oxide such as silicon oxide, a nitride, or the like, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (for example, depositing a CVD-based material in a remote plasma system with a post-curing function to convert the deposited material into another material, such as an oxide), or the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the embodiment shown, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be implemented. In one embodiment, the insulating material is formed so that an excess of the insulating material covers the nanostructure 110 and the fin 112. The insulating material can include a single layer or multiple layers that can be utilized. For example, in some embodiments, a liner (not separately shown) may first be formed along the surfaces of substrate 50, nanostructures 110, and fins 112. Then, a fill material such as those discussed above may be formed over the liner.

[0040] Then, a removal process is performed on the insulating material to remove excess insulating material on the nanostructure 110 and the fin 112. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be used. The planarization process may remove the first mask layer 90 and planarize the nanostructure 110 and the fin 112. The planarization process exposes the nanostructure 110 and the fin 112 so that after the planarization process is completed, the nanostructure 110 and the fin 112 and the top surface of the insulating material are flush.

[0041] Then, the insulating material is recessed to form a Fig.13 The STI regions 114 shown. The insulating material is recessed so that the upper portions of the nanostructures 110 in region 50N and the fins 112 in region 50P protrude from between adjacent STI regions 114. In addition, the top surface of the STI region 114 may have a flat surface, a convex surface, a concave surface (e.g., a recess), or a combination thereof as shown. The top surface of the STI region 114 may be formed into a flat, convex, and / or concave surface by suitable etching. Recessing the STI region 114 may use an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than etching the material of the nanostructures 110 and the fins 112). For example, oxide removal using an acid such as dilute hydrofluoric acid (dHF) may be used.

[0042] In addition Fig.13 In the embodiment of the present invention, appropriate wells (not separately shown) may be formed in nanostructure 110, fin 112, and / or substrate 50. In some embodiments, a P-well may be formed in region 50N, and an N-well may be formed in region 50P. In other embodiments, a P-well and an N-well may be formed in each of region 50N and region 50P.

[0043] In embodiments including different well types, different implantation steps for region 50N and region 50P may be implemented using a photoresist or other mask (not shown separately). For example, a photoresist may be formed over nanostructure 110 and STI region 114 in region 50N. The photoresist is patterned to expose region 50P of substrate 50. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation may be performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region, with a concentration equal to or less than 1×10 14 Atom / cm 3 , for example about 1×10 13 Atom / cm 3 About 1×10 14 Atom / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0044] After the implantation of region 50P, a photoresist is formed over fin 112 and STI region 114 in region 50P. The photoresist is patterned to expose region 50N of substrate 50. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P. The p-type impurity may be boron, boron fluoride, indium, etc., implanted into the region at a concentration equal to or less than 1×10 14 Atom / cm 3 , for example about 1×10 13 Atom / cm 3 About 1×10 14 Atom / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0045] After implantation of regions 50N and 50P, annealing may be performed to repair implant damage and activate implanted p-type and / or n-type impurities. In some embodiments, the grown material of the epitaxial fins may be in-situ doped during growth, which may omit implantation, although in-situ doping and implantation doping may be used together.

[0046] exist Fig.14 In the embodiment of the present invention, a pseudo dielectric layer 116 is formed on the nanostructure 110 and the fin 112. The pseudo dielectric layer 116 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to an acceptable technique. A pseudo gate layer 118 is formed above the pseudo dielectric layer 116, and a mask layer 120 is formed above the pseudo gate layer 118. The pseudo gate layer 118 can be deposited above the pseudo dielectric layer 116 and then planarized, for example, by CMP. The mask layer 120 can be deposited above the pseudo gate layer 118. The pseudo gate layer 118 can be a conductive or non-conductive material and can be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polysilicon germanium), metal nitrides, metal silicides, metal oxides, and metals. The pseudo gate layer 118 can be deposited by PVD, CVD, sputtering deposition, or other techniques known and used in the art for depositing selected materials. The dummy gate layer 118 may be made of other materials having high etch selectivity to the etching of the isolation region (e.g., STI region 114). The mask layer 120 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 118 and a single mask layer 120 are formed to span the region 50N and the region 50P. It should be noted that, for illustrative purposes only, the dummy dielectric layer 116 is shown to cover only the nanostructure 110 and the fin 112. In some embodiments, the dummy dielectric layer 116 may be deposited so that the dummy dielectric layer 116 covers the STI region 114 and extends between the dummy gate layer 118 and the STI region 114.

[0047] exist Figure 15A-Figure 15C In the embodiment, the mask layer 120 (see Fig.14 ) is patterned to form a mask 124. The pattern of the mask 124 can then be transferred to the dummy gate layer 118. In some embodiments (not shown separately), the pattern of the mask 124 can also be transferred to the dummy dielectric layer 116 by an acceptable etching technique to form a dummy gate 122. The dummy gate 122 covers the corresponding channel regions of the nanostructures 110 and the fins 112. The pattern of the mask 124 can be used to physically pattern the dummy gate layer 118 into different dummy gates 122. Within process variations, the dummy gate 122 can also have a length direction that is substantially perpendicular to the length direction of each nanostructure 110 and the fin 112.

[0048] exist Fig.16A and Fig. 16BIn the embodiment, the gate sealing spacer 126 is formed on the exposed surfaces of the dummy gate 122, the mask 124, the dummy dielectric layer 116, and / or the nanostructure 110 and the fin 112. Thermal oxidation or deposition followed by anisotropic etching can form the gate sealing spacer 126. The gate sealing spacer 126 can be formed by silicon oxide, silicon nitride, silicon oxynitride, etc.

[0049] After the formation of the gate sealing spacer 126, implantation for lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the above in Fig.13 As discussed in the implantation described above, a mask, such as a photoresist, may be formed over region 50N while exposing region 50P, and an appropriate type of impurity (e.g., p-type) may be implanted into the exposed fin 112 in region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over region 50P while exposing region 50N, and an appropriate type of impurity (e.g., n-type) may be implanted into the exposed nanostructure 110 in region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a thickness of approximately 1×10 15 Atom / cm 3 About 1×10 19 Atom / cm 3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0050] In addition Fig.16A and 16B In the embodiment, the gate spacer 128 is formed on the gate sealing spacer 126 along the sidewalls of the dummy gate 122, the mask 124, and the dummy dielectric layer 116. The gate spacer 128 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 128 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, etc.

[0051] It should be noted that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the gate sealing spacer 126 may not be etched before the gate spacer 128 is formed, thereby producing an "L-shaped" gate sealing spacer), spacers may be formed or removed, etc. In addition, n-type and p-type devices may be formed using different structures and steps. For example, an LDD region for an n-type device may be formed before the gate sealing spacer 126 is formed, and an LDD region for a p-type device may be formed after the gate sealing spacer 126 is formed.

[0052] exist Fig.17A and Fig. 17B In the embodiment, the first recess 130 is formed in the nanostructure 110 and the fin 112. Fig.17A As shown, the first recess 130 in the region 50N extends through the first semiconductor layer 52A-52D and the second semiconductor layer 54A-54C and into the substrate 50. Fig. 17B As shown, the first recess 130 in the region 50P extends through the first epitaxial semiconductor material 84 into the substrate 50 .

[0053] The first recess 130 may be formed by etching the nanostructure 110 and the fin 112 using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the first recess 130, the gate spacers 128, the gate sealing spacers 126, and the mask 124 mask portions of the nanostructure 110 and the fin 112. A single etching process may be used to etch each layer of the multilayer stack 70 and the first epitaxial semiconductor material 84. In other embodiments, multiple etching processes may be used to etch the layers of the multilayer stack 70 and the first epitaxial semiconductor material 84. A timed etching process may be used to stop etching the first recess 130 after the first recess 130 reaches a desired depth.

[0054] In some embodiments, the first recess 130 in the region 50N may be etched separately from the first recess 130 in the region 50P. A photoresist or other mask (not shown separately) may be used to etch the first recess 130 in the region 50N and the region 50P separately. For example, the photoresist may be formed on the first recess 130 in the region 50N. Fig.16A The structure shown in FIG. 1 is formed by patterning the photoresist to expose the region 50P. The photoresist may be formed by using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, the first recess 130 in the region 50P may be formed by etching. The etching may be performed using hydrogen (H2) plasma or the like. After etching, the photoresist may be removed, for example, by an acceptable ashing process. The photoresist may then be formed in the region 50P. Fig. 16B 50N. The photoresist may be formed by using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a first recess 130 in the region 50N may be formed by etching. The etching may be performed using a plasma formed by a process gas such as trifluoromethane (CHF3), tetrafluoromethane (CF4), hydrogen bromide (HBr), etc. After etching, the photoresist may be removed, for example, by an acceptable ashing process.

[0055] exist Fig.18A and Fig.18B In the embodiment, a portion of the sidewall of the layer of the multilayer stack 70 formed of the second semiconductor material (e.g., the second semiconductor layers 54A-54C) exposed by the first recess 130 is etched to form a sidewall recess 132. The sidewall may be etched using an isotropic etching process, such as wet etching. Fig.18A As shown, the sidewalls of the second semiconductor layers 54A-54C may be etched in the region 50N. During the isotropic etching of the region 50N, a photoresist or other mask (not separately shown) may or may not be used to mask the region 50P.

[0056] The etchant used to etch the second semiconductor layers 54A-54C can be selective to the second semiconductor material, so that the first semiconductor layers 52A-52D, the substrate 50, and the first epitaxial semiconductor material 84 remain relatively unetched compared to the second semiconductor layers 54A-54C. In embodiments where the second semiconductor layers 54A-54C include, for example, SiGe and the first semiconductor layers 52A-52D include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to etch the sidewalls of the multilayer stack 70 in the region 50N. In other embodiments, the layers of the multilayer stack 70 can be etched using a dry etching process. Hydrogen fluoride, another fluorine-based gas, or the like can be used to etch the sidewalls of the multilayer stack 70 in the region 50N.

[0057] exist Fig.19A and Fig.19B In the embodiment, the inner spacer 134 is formed in the side wall recess 132. The inner spacer 134 can be formed by Fig.18A and Fig.18B An inner spacer layer (not separately shown) is deposited over the structure shown. The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, etc. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, although any suitable material such as a low-k material having an k value less than about 3.5 may be utilized.

[0058] Then, the inner spacer layer may be etched to form inner spacers 134. The inner spacer layer may be etched by an anisotropic etching process such as RIE, NBE, etc. The inner spacers 134 may be used to prevent damage to source / drain regions (e.g., epitaxial source / drain regions 136, hereinafter referred to as such) that are subsequently formed by a subsequent etching process. Fig. 20A and 20B for discussion).

[0059] exist Fig. 20A and Fig. 20BIn the embodiment of the present invention, epitaxial source / drain regions 136 are formed in the first recess 130 to apply stress on the channel layer of the multilayer stack 70 and the first epitaxial semiconductor material 84 to improve performance. The epitaxial source / drain regions 136 are formed in the first recess 130 so that each dummy gate 122 is disposed between respective adjacent pairs of epitaxial source / drain regions 136. In some embodiments, the gate spacers 128 are used to offset the epitaxial source / drain regions 136 from the dummy gates 122 by an appropriate lateral distance so that the epitaxial source / drain regions 136 do not short the gates of the resulting NSFETs and FinFETs formed subsequently. The internal spacers 134 are also used to separate the epitaxial source / drain regions 136 from the dummy gates 122 to prevent short circuits between the epitaxial source / drain regions 136 and the gates of the resulting NSFETs and FinFETs formed subsequently.

[0060] The epitaxial source / drain regions 136 in the region 50N (e.g., NMOS region) may be formed by masking the region 50P (e.g., PMOS region). The epitaxial source / drain regions 136 in the region 50N are then epitaxially grown in the first recess 130. The epitaxial source / drain regions 136 may include any acceptable material, such as a material suitable for an n-type NSFET. For example, in an embodiment where the first semiconductor layers 52A-52D are formed by a first semiconductor material (e.g., Si or SiC), the epitaxial source / drain regions 136 in the region 50N may include a material that applies tensile strain to the first semiconductor layers 52A-52D, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 136 in the region 50N may have surfaces elevated from corresponding surfaces of the multilayer stack 70 and may have facets.

[0061] The epitaxial source / drain regions 136 in the region 50P (e.g., PMOS region) may be formed by masking the region 50N (e.g., NMOS region). The epitaxial source / drain regions 136 in the region 50P are then epitaxially grown in the first recess 130. The epitaxial source / drain regions 136 may include any acceptable material, such as a material suitable for a p-type NSFET. For example, in an embodiment where the first epitaxial semiconductor material 84 is formed by a material such as silicon, the epitaxial source / drain regions 136 in the region 50P may include a material that exerts a compressive strain on the first epitaxial semiconductor material 84, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 136 in the region 50P may also have a surface that is elevated from a corresponding surface of the first epitaxial semiconductor material 84 and may have facets.

[0062] The epitaxial source / drain regions 136, the multilayer stack 70, and / or the first epitaxial semiconductor material 84 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, and then annealed. The source / drain regions may have a dopant density of approximately 1×10 19 Atom / cm 3 About 1×10 21 Atom / cm 3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 136 may be in-situ doped during growth.

[0063] exist Figure 21A-Figure 21C In the embodiment, a first interlayer dielectric (ILD) 142 is deposited on Fig.15A , Fig. 20A ,and Fig. 20B Above the structure shown ( Figures 16A-20B The process will not change Fig.15A ). The first ILD 142 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 140 is disposed between the first ILD 142 and the epitaxial source / drain regions 136, the mask 124, the gate spacer 128, and the gate sealing spacer 126. The CESL 140 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc., having a different etching rate than the material of the overlying first ILD 142.

[0064] exist Figure 22A-22C In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD 142 flush with the top surface of the dummy gate 122 or the mask 124. The planarization process may also remove the mask 124 on the dummy gate 122, and portions of the gate sealing spacer 126 and the gate spacer 128 along the sidewalls of the mask 124. After the planarization process, the top surfaces of the dummy gate 122, the gate sealing spacer 126, the gate spacer 128, and the first ILD 142 are flush. Therefore, the top surface of the dummy gate 122 is exposed through the first ILD 142. In some embodiments, the mask 124 may be retained, in which case the planarization process makes the top surface of the first ILD 142 flush with the top surfaces of the mask 124, the gate sealing spacer 126, and the gate spacer 128.

[0065] exist Figure 23A-23C In some embodiments, the dummy gate 122 and the mask 124 (if present) are removed in (some) etching steps, thereby forming a second recess 144. Portions of the dummy dielectric layer 116 in the second recess 144 may also be removed. In some embodiments, only the dummy gate 122 is removed, while the dummy dielectric layer 116 is retained and exposed through the second recess 144. In some embodiments, the dummy dielectric layer 116 is removed from the second recess 144 in the first area of ​​the die (e.g., the core logic area), while remaining in the second recess 144 in the second area of ​​the die (e.g., the input / output area). In some embodiments, the dummy gate 122 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (some) reactive gases that selectively etches the dummy gate 122 at a faster rate than etching the first ILD 142, the gate sealing spacer 126, or the gate spacer 128. Each second recess 144 exposes and / or covers the multilayer stack 70 or the first epitaxial semiconductor material 84, which is used as a channel region in the subsequently completed NSFET and FinFET. The portion of the multilayer stack 70 or the first epitaxial semiconductor material 84 used as the channel region is disposed between adjacent pairs of epitaxial source / drain regions 136. During removal, the dummy dielectric layer 116 can be used as an etch stop layer when etching the dummy gate 122. The dummy dielectric layer 116 can then be optionally removed after removing the dummy gate 122.

[0066] exist Figure 24A-Figure 24C , the second semiconductor layers 54A-54C are removed from the region 50N, extending the second recess 144. The second semiconductor layers 54A-54C can be removed by an isotropic etching process such as wet etching. The second semiconductor layers 54A-54C can be removed using an etchant that is selective to the material of the second semiconductor layers 54A-54C, while the first semiconductor layers 52A-52D and the first epitaxial semiconductor material 84 remain relatively unetched compared to the second semiconductor layers 54A-54C. In embodiments where the second semiconductor layers 54A-54C include, for example, SiGe and the first semiconductor layers 52A-52D include, for example, Si or SiC, a solution including hydrofluoric acid (HF) and hydrogen peroxide (H2O2), a solution including hydrofluoric acid and nitric acid (HNO3) and water (H2O), etc. can be used to remove the second semiconductor layers 54A-54C. In other embodiments, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), or the like may be used to remove the second semiconductor layers 54A- 54C.

[0067] exist Figure 25A-Figure 25CIn the embodiment of the present invention, a gate dielectric layer 150 and a gate electrode 152 are formed to replace the gate. The gate dielectric layer 150 is conformally deposited in the second recess 144, for example, on the top surface and sidewalls of the first semiconductor layer 52A and the first epitaxial semiconductor material 84, and on the top surface, sidewalls, and bottom surface of the first semiconductor layer 52B-52D. The gate dielectric layer 150 may also be deposited on the top surface of the first ILD 142. According to some embodiments, the gate dielectric layer 150 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 150 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 150 may have a k value greater than about 7.0, and may include metal oxides or silicides of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric layer 150 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0068] The gate electrodes 152 are respectively deposited over the gate dielectric layers 150 and fill the remaining portions of the second recesses 144. The gate electrodes 152 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Figure 25A-Figure 25C , but the gate electrode 152 may include any number of liner layers, any number of work function adjustment layers, and fill materials. After filling the second recess 144, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 150 and the gate electrode 152 material that are located above the top surface of the first ILD 142. The remaining portions of the gate electrode 152 and the gate dielectric layer 150 material thus form a replacement gate for the resulting NSFET and FinFET. The gate electrode 152 and the gate dielectric layer 150 may be collectively referred to as a "gate stack". The gate stack may surround each of the first semiconductor layers 52B-52D and along the top surface and sidewalls of the first semiconductor layer 52A and the first epitaxial semiconductor material 84.

[0069] The formation of the gate dielectric layer 150 in the region 50N and the region 50P may occur simultaneously, such that the gate dielectric layer 150 in each region may be formed from the same material, and the formation of the gate electrode 152 may occur simultaneously, such that the gate electrode 152 in each region may be formed from the same material. In some embodiments, the gate dielectric layer 150 in each region may be formed by a different process, such that the gate dielectric layer 150 may be a different material, and / or the gate electrode 152 in each region may be formed by a different process, such that the gate electrode 152 may be a different material. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0070] exist Figure 26A-26C In the process, the second ILD 154 is deposited over the first ILD 142. In some embodiments, the second ILD 154 is a flowable film formed by FCVD. In some embodiments, the second ILD 154 is formed by a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method such as CVD, PECVD, etc. According to some embodiments, before forming the second ILD 154, the gate stack (including the gate dielectric layer 150 and the corresponding overlying gate electrode 152) is recessed so that the recess is formed directly above the gate stack and between the opposite portions of the gate sealing spacer 126. A gate mask 156 including one or more layers of a dielectric material such as silicon nitride, silicon oxynitride, etc. is filled into the recess, and then a planarization process is performed to remove excess portions of the dielectric material extending over the first ILD 142. The gate contact (e.g., below relative to the gate contact) formed subsequently Figure 27A-27C A gate contact 158 ​​is discussed that passes through the gate mask 156 to contact the top surface of the recessed gate electrode 152 .

[0071] exist Figure 27A-27C In the embodiment of the present invention, a gate contact 158 ​​and a source / drain contact 160 are formed. An opening for the source / drain contact 160 is formed through the second ILD 154 and the first ILD 142, and an opening for the gate contact 158 ​​is formed through the second ILD 154 and the gate mask 156. The opening can be formed using acceptable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 154. The remaining liner and conductive material form a source / drain contact 160 and a gate contact 158 ​​in the opening. An annealing process may be performed to form a silicide at the interface between the epitaxial source / drain region 136 and the source / drain contact 160. The source / drain contact 160 is physically and electrically connected to the epitaxial source / drain region 136, and the gate contact 158 ​​is physically and electrically connected to the gate electrode 152. The source / drain contact 160 and the gate contact 158 ​​can be formed in different processes, or can be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contact 160 and the gate contact 158 ​​can be formed in different cross-sections, which can avoid shorting of the contacts.

[0072] Fig.28A and Fig.28BA circuit diagram and layout of a six-transistor (6-T) single-port SRAM cell 200 is shown, which includes a pull-up transistor 208, a pull-down transistor 206, and a pass-gate transistor 204. Bit lines BL and BLB and a word line WL are connected to the 6-T SRAM cell 200. The operation of a 6-T SRAM cell is known in the art and will not be discussed herein.

[0073] like Fig.28B As shown, the epitaxial source / drain region 136 is the active region of the pull-up transistor 208, the pull-down transistor 206, and the pass-gate transistor 204, which is used to form the source and drain regions of the corresponding transistors. The nanostructure 110 can form the channel of the pass-gate transistor 204, and the fin 112 can form the channel of the pull-up transistor 208, so that the pass-gate transistor 204 has a higher driving strength than the pull-up transistor 208, thereby increasing the α ratio, increasing the cell stability, and reducing the write time. The nanostructure 110 can also form the channel of the pull-down transistor 206, so that the pull-down transistor 206 has a relatively high driving strength, which reduces the read access time. In this way, using the nanostructure 110 for the channel of the pass-gate transistor 204 and the pull-down transistor 206, and using the fin 112 for the channel of the pull-up transistor 208, can improve the read access time and the write access time. Pull-down transistor 206 and pass-gate transistor 204 are disposed in region 50N, while pull-up transistor 208 is disposed in region 50P. Gate electrode 152 may extend over each of pull-up transistor 208, pull-down transistor 206, and pass-gate transistor 204.

[0074] Fig.29A and Fig.29B 1 shows a circuit diagram and layout of an eight-transistor (8-T) dual-port SRAM cell 201, which includes a read pass-gate transistor 210 and a read pull-down transistor 212 in addition to a pull-up transistor 208, a pull-down transistor 206, and a pass-gate transistor 204. The read bit line RBL, the write bit lines WBL and WBLB, the read word line WWL, and the write word line RWL are connected to the 8-T dual-port SRAM cell 201. Fig.29B As shown, read pass-gate transistor 210 and read pull-down transistor 212 are disposed in region 50N. Nanostructure 110 forms channels of read pass-gate transistor 210 and read pull-down transistor 212, which provides a faster read access time. In addition, since read pass-gate transistor 210 and read pull-down transistor 212 are connected between read bit line RBL and pull-up transistor 208 and pull-down transistor 206, a smaller load is loaded on pull-up transistor 208 and pull-down transistor 206, so that a lower minimum power supply voltage (V ccmin). The nanostructure 110 may be used for the channels of the pass-gate transistor 204 and the pull-down transistor 206 , while the fin 112 may be used for the channel of the pull-up transistor 208 for the same reasons discussed above with respect to the 6-T single-port SRAM cell 200 .

[0075] Fig. 30A and Fig. 30B A circuit diagram and layout of a ten-transistor (10-T) dual-port SRAM cell 202 is shown, wherein each of the pull-up transistor 208, the pull-down transistor 206, the pass-gate transistor 204, the read pass-gate transistor 210, and the read pull-down transistor 212 includes two. Read bit lines RBL and RBLB, write bit lines WBL and WBLB, read word line WWL, and write word line RWL are connected to the 10-T dual-port SRAM cell 202. Fig. 30B As shown, read pass-gate transistor 210 and read pull-down transistor 212 are disposed in region 50N. Nanostructure 110 may be used for the channels of pass-gate transistor 204, pull-down transistor 206, read pass-gate transistor 210, and read pull-down transistor 212, while fin 112 may be used for the channel of pull-up transistor 208 for the same reasons discussed above with respect to 8-T dual-port SRAM cell 201.

[0076] As previously discussed, the nanostructure 110 can be disposed in the region 50N to provide a transistor with a relatively high drive current, which increases the performance and speed of the semiconductor device. The fin 112 disposed in the region 50P can have a width less than the nanostructure 110, which can be used to reduce the cell size and provide a transistor with a relatively low drive current. The fin 112 can also have a better N-well / P-well boundary and can reduce leakage and latching problems. Including both the nanostructure 110 and the fin 112 can achieve faster SRAM operation, reduced cell size (compared to an SRAM cell including only the nanostructure), better cell current, and a smaller threshold voltage (V t ) mismatch, and a lower minimum supply voltage (V ccmin ).

[0077] According to one embodiment, a semiconductor device includes: a first memory cell, the first memory cell including: a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin. In one embodiment, the first transistor includes a pull-down transistor, and the second transistor includes a pull-down transistor. In one embodiment, the first memory cell also includes: a third transistor including a third channel region, the third channel region including a second plurality of semiconductor nanostructures, and the third transistor includes a pass-gate transistor. In one embodiment, the first transistor and the third transistor are arranged in an NMOS region above a semiconductor substrate, and the second transistor is arranged in a PMOS region above the semiconductor substrate. In one embodiment, the first memory cell also includes: a fourth transistor including a fourth channel region, the fourth channel region including a third plurality of semiconductor nanostructures, the fourth transistor including a read pull-down transistor; and a fifth transistor including a fifth channel region, the fifth channel region including a fourth plurality of semiconductor nanostructures, and the fifth transistor including a read pass-gate transistor. In one embodiment, a ratio of a width of the first channel region along a current flow direction across the first channel region to a width of the second channel region along a current flow direction across the second channel region is 3 to 8.

[0078] According to another embodiment, a method includes: forming a multilayer semiconductor stack located above a semiconductor substrate, the multilayer semiconductor stack including alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material; etching the multilayer semiconductor stack to form a first opening exposing the semiconductor substrate; forming a third semiconductor material filling the first opening; etching the multilayer semiconductor stack and the semiconductor substrate to form a first nanostructure extending from the semiconductor substrate; and etching the third semiconductor material and the semiconductor substrate to form a first fin extending from the semiconductor substrate. In one embodiment, the method also includes: forming one or more first recesses by etching the multilayer semiconductor stack to remove alternating layers of the multilayer semiconductor stack including the second semiconductor material, the first semiconductor material and the third semiconductor material including silicon, and the second semiconductor material including silicon germanium. In one embodiment, the method also includes: forming a gate stack filling the first recess and extending along the top surface and sidewall of the first nanostructure and the first fin. In one embodiment, the method also includes: planarizing the multilayer semiconductor stack and the third semiconductor material, the top surface of the first nanostructure being flush with the top surface of the first fin. In one embodiment, etching the multilayer semiconductor stack and the semiconductor substrate to form the first nanostructure and etching the third semiconductor material and the semiconductor substrate to form the first fin are performed simultaneously. In one embodiment, the method further includes: forming a dummy gate located above the first nanostructure and the first fin; etching the first nanostructure to form a first recess adjacent to the dummy gate; etching the first fin to form a second recess adjacent to the dummy gate; epitaxially growing a first source / drain region in the first recess; and epitaxially growing a second source / drain region in the second recess. In one embodiment, etching the first nanostructure and etching the first fin are performed simultaneously, and epitaxially growing the first source / drain region and epitaxially growing the second source / drain region are performed simultaneously.

[0079] According to yet another embodiment, a semiconductor device includes: a first nanostructure extending from a semiconductor substrate in a first region of the semiconductor substrate, the first nanostructure including a plurality of semiconductor layers located above the semiconductor substrate; and a first fin extending from the semiconductor substrate in a second region of the semiconductor substrate, the first fin including a semiconductor material located above the semiconductor substrate, the semiconductor material having a constant composition, a top surface of the semiconductor material being flush with a top surface of a topmost semiconductor layer of the plurality of semiconductor layers, and a bottom surface of the semiconductor material being flush with a bottom surface of a bottommost semiconductor layer of the plurality of semiconductor layers; and a gate stack extending above the first nanostructure and the first fin. In one embodiment, the gate stack extends along a top surface, a sidewall, and a bottom surface of the topmost semiconductor layer, the gate stack extends along a top surface and a sidewall of the bottommost semiconductor layer, and the gate stack extends along a sidewall and a top surface of the semiconductor material. In one embodiment, the first region includes an NMOS region, and the second region includes a PMOS region. In one embodiment, a ratio of a first width of the first nanostructure to a second width of the first fin is 3 to 8. In one embodiment, the semiconductor material and each semiconductor layer of the plurality of semiconductor layers include silicon. In one embodiment, the semiconductor device further comprises: a first epitaxial source / drain region adjacent to the gate stack, the first epitaxial source / drain region contacting a semiconductor layer of the plurality of semiconductor layers; and a second epitaxial source / drain region adjacent to the gate stack, the second epitaxial source / drain region contacting the semiconductor material. In one embodiment, the semiconductor device further comprises: an internal spacer extending between adjacent semiconductor layers of the plurality of semiconductor layers, the internal spacer separating the first epitaxial source / drain region from the gate stack.

[0080] According to one embodiment of the present application, a semiconductor device is provided, comprising: a first memory cell, the first memory cell comprising: a first transistor, comprising a first channel region, the first channel region comprising a first plurality of semiconductor nanostructures; and a second transistor, comprising a second channel region, the second channel region comprising a semiconductor fin. In some embodiments, the first transistor comprises a pull-down transistor, and the second transistor comprises a pull-down transistor. In some embodiments, the first memory cell further comprises: a third transistor, comprising a third channel region, the third channel region comprising a second plurality of semiconductor nanostructures, wherein the third transistor comprises a pass-gate transistor. In some embodiments, the first transistor and the third transistor are disposed in an NMOS region above a semiconductor substrate, and wherein the second transistor is disposed in a PMOS region above the semiconductor substrate. In some embodiments, the first memory cell further comprises: a fourth transistor, comprising a fourth channel region, the fourth channel region comprising a third plurality of semiconductor nanostructures, wherein the fourth transistor comprises a read pull-down transistor; and a fifth transistor, comprising a fifth channel region, the fifth channel region comprising a fourth plurality of semiconductor nanostructures, wherein the fifth transistor comprises a read pass-gate transistor. In some embodiments, a ratio of a width of the first channel region along a current flow direction across the first channel region to a width of the second channel region along a current flow direction across the second channel region is 3 to 8.

[0081] According to another embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a multilayer semiconductor stack located above a semiconductor substrate, the multilayer semiconductor stack comprising alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material; etching the multilayer semiconductor stack to form a first opening exposing the semiconductor substrate; forming a third semiconductor material filling the first opening; etching the multilayer semiconductor stack and the semiconductor substrate to form a first nanostructure extending from the semiconductor substrate; and etching the third semiconductor material and the semiconductor substrate to form a first fin extending from the semiconductor substrate. In some embodiments, the method for forming a semiconductor device further comprises: forming one or more first recesses by etching the multilayer semiconductor stack to remove alternating layers of the multilayer semiconductor stack comprising the second semiconductor material, wherein the first semiconductor material and the third semiconductor material comprise silicon, and wherein the second semiconductor material comprises silicon germanium. In some embodiments, the method for forming a semiconductor device further comprises: forming a gate stack filling the first recess and extending along the top surface and sidewalls of the first nanostructure and the first fin. In some embodiments, the method for forming a semiconductor device further comprises: planarizing the multilayer semiconductor stack and the third semiconductor material, wherein the top surface of the first nanostructure is flush with the top surface of the first fin. In some embodiments, etching the multilayer semiconductor stack and the semiconductor substrate to form the first nanostructure is performed simultaneously with etching the third semiconductor material and the semiconductor substrate to form the first fin. In some embodiments, the method of forming a semiconductor device further includes: forming a dummy gate located above the first nanostructure and the first fin; etching the first nanostructure to form a first recess adjacent to the dummy gate; etching the first fin to form a second recess adjacent to the dummy gate; epitaxially growing a first source / drain region in the first recess; and epitaxially growing a second source / drain region in the second recess. In some embodiments, etching the first nanostructure and etching the first fin are performed simultaneously, and epitaxially growing the first source / drain region and epitaxially growing the second source / drain region are performed simultaneously.

[0082] According to another embodiment of the present application, a semiconductor device is provided, comprising: a first nanostructure extending from a semiconductor substrate in a first region of the semiconductor substrate, the first nanostructure comprising a plurality of semiconductor layers located above the semiconductor substrate; and a first fin extending from the semiconductor substrate in a second region of the semiconductor substrate, the first fin comprising a semiconductor material located above the semiconductor substrate, the semiconductor material having a constant composition, a top surface of the semiconductor material being flush with a top surface of a topmost semiconductor layer of the plurality of semiconductor layers, and a bottom surface of the semiconductor material being flush with a bottom surface of a bottommost semiconductor layer of the plurality of semiconductor layers; and a gate stack extending above the first nanostructure and the first fin. In some embodiments, the gate stack extends along a top surface, a sidewall, and a bottom surface of the topmost semiconductor layer, the gate stack extends along a top surface and a sidewall of the bottommost semiconductor layer, and the gate stack extends along a top surface and a sidewall of the semiconductor material. In some embodiments, the first region comprises an NMOS region, and the second region comprises a PMOS region. In some embodiments, a ratio of a first width of the first nanostructure to a second width of the first fin is 3 to 8. In some embodiments, the semiconductor material and each semiconductor layer of the plurality of semiconductor layers comprises silicon. In some embodiments, the semiconductor device further comprises: a first epitaxial source / drain region adjacent to the gate stack, wherein the first epitaxial source / drain region contacts a semiconductor layer of the plurality of semiconductor layers; and a second epitaxial source / drain region adjacent to the gate stack, wherein the second epitaxial source / drain region contacts the semiconductor material. In some embodiments, the semiconductor device further comprises: an internal spacer extending between adjacent semiconductor layers of the plurality of semiconductor layers, the internal spacer separating the first epitaxial source / drain region from the gate stack.

[0083] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A first memory unit, the first memory unit comprising: a first transistor comprising a first channel region including a first plurality of semiconductor nanostructures; and A second transistor comprising: a second channel region, the second channel region comprising a semiconductor fin; a source / drain region adjacent to the semiconductor fin; and A substrate, wherein the first transistor and the second transistor are formed above the substrate, the substrate includes an anti-punch-through region located in a top portion of the substrate, and the anti-punch-through region extends continuously below the first channel region, the second channel region, and the source / drain region.

2. The semiconductor device according to claim 1, wherein The first transistor comprises a pull-down transistor and the second transistor comprises a pull-up transistor.

3. The semiconductor device according to claim 2, wherein: The first memory cell further includes a third transistor including a third channel region including a second plurality of semiconductor nanostructures, wherein the third transistor includes a pass-gate transistor.

4. The semiconductor device according to claim 3, wherein: The first transistor and the third transistor are disposed in an NMOS region above a semiconductor substrate, and wherein the second transistor is disposed in a PMOS region above the semiconductor substrate.

5. The semiconductor device according to claim 3, wherein: The first memory unit further comprises: a fourth transistor comprising a fourth channel region including a third plurality of semiconductor nanostructures, wherein the fourth transistor comprises a read pull-down transistor; and A fifth transistor includes a fifth channel region including a fourth plurality of semiconductor nanostructures, wherein the fifth transistor includes a read pass-gate transistor.

6. The semiconductor device according to claim 1, wherein A ratio of a width of the first channel region along a current flow direction across the first channel region to a width of the second channel region along a current flow direction across the second channel region is 3 to 8.

7. A method of forming a semiconductor device, comprising: forming a multi-layer semiconductor stack over a semiconductor substrate, the multi-layer semiconductor stack comprising alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material, wherein the multi-layer semiconductor stack comprises a first etch stop layer of the first semiconductor material and a second etch stop layer of the second semiconductor material; etching the multi-layer semiconductor stack to form a first opening exposing the semiconductor substrate; forming a third semiconductor material filling the first opening; removing the first etch stop layer; etching the multilayer semiconductor stack and the semiconductor substrate to form a first nanostructure extending from the semiconductor substrate; and etching the third semiconductor material and the semiconductor substrate to form a first fin extending from the semiconductor substrate; The second etch stop layer is removed.

8. The method according to claim 7, further comprising: One or more first recesses are formed by etching the multilayer semiconductor stack to remove the alternating layers of the multilayer semiconductor stack including the second semiconductor material, wherein the first semiconductor material and the third semiconductor material include silicon, and wherein the second semiconductor material includes silicon germanium.

9. The method according to claim 8, further comprising: A gate stack is formed that fills the first recess and extends along top surfaces and sidewalls of the first nanostructure and the first fin.

10. The method according to claim 7, further comprising: The multilayer semiconductor stack and the third semiconductor material are planarized, wherein a top surface of the first nanostructure is flush with a top surface of the first fin.

11. The method according to claim 7, wherein: Etching the multilayer semiconductor stack and the semiconductor substrate to form the first nanostructure is performed simultaneously with etching the third semiconductor material and the semiconductor substrate to form the first fin.

12. The method according to claim 7, further comprising: forming a dummy gate located above the first nanostructure and the first fin; etching the first nanostructure to form a first recess adjacent to the dummy gate; etching the first fin to form a second recess adjacent to the dummy gate; epitaxially growing a first source / drain region in the first recess; and A second source / drain region is epitaxially grown in the second recess.

13. The method according to claim 12, wherein: Etching the first nanostructure and etching the first fin are performed simultaneously, and epitaxially growing the first source / drain region and epitaxially growing the second source / drain region are performed simultaneously.

14. A semiconductor device comprising: a first nanostructure extending from a semiconductor substrate in a first region of the semiconductor substrate, the first nanostructure comprising a plurality of semiconductor layers located above the semiconductor substrate; as well as a first fin extending from the semiconductor substrate in the second region of the semiconductor substrate, the first fin comprising a semiconductor material located above the semiconductor substrate, the semiconductor material having a constant composition, a top surface of the semiconductor material being flush with a top surface of a topmost semiconductor layer of the plurality of semiconductor layers, and a bottom surface of the semiconductor material being flush with a bottom surface of a bottommost semiconductor layer of the plurality of semiconductor layers; as well as a gate stack extending over the first nanostructure and the first fin; A first epitaxial source / drain region is adjacent to the gate stack, wherein the semiconductor substrate includes an anti-punch-through region located in an upper region of the semiconductor substrate, and the anti-punch-through region extends continuously below the first nanostructure, the first fin, and the first epitaxial source / drain region.

15. The semiconductor device according to claim 14, wherein: The gate stack extends along the top surface, sidewalls and bottom surface of the topmost semiconductor layer, the gate stack extends along the top surface and sidewalls of the bottommost semiconductor layer, and the gate stack extends along the top surface and sidewalls of the semiconductor material.

16. The semiconductor device according to claim 14, wherein The first region includes an NMOS region, and the second region includes a PMOS region.

17. The semiconductor device according to claim 14, wherein: A ratio of a first width of the first nanostructure to a second width of the first fin is 3 to 8.

18. The semiconductor device according to claim 14, wherein: The semiconductor material and each semiconductor layer of the plurality of semiconductor layers include silicon.

19. The semiconductor device according to claim 14, in, The first epitaxial source / drain region contacts the semiconductor layer of the plurality of semiconductor layers; as well as The semiconductor device further comprises: A second epitaxial source / drain region is adjacent to the gate stack, wherein the second epitaxial source / drain region contacts the semiconductor material.

20. The semiconductor device according to claim 19, further comprising: An inner spacer extends between adjacent ones of the plurality of semiconductor layers, the inner spacer separating the first epitaxial source / drain region from the gate stack.

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