Integrated Circuit, Flyback Converter, and Its Control Circuit and Method

Abstract

Embodiments disclose an integrated circuit, a flyback converter, and its control circuit and method. A control circuit for driving an electronic switch associated with a switching node of a flyback converter includes a comparison circuit configured to generate a turn-off signal by comparing a current measurement signal with a current measurement threshold signal. A valley detection circuit is configured to generate a trigger in a trigger signal when a valley signal indicates a valley in the voltage at the switching node of the flyback converter, and a blanking circuit is configured to generate a turn-on signal by combining the trigger signal and a timer signal provided by a timer circuit. The timer signal indicates whether a blanking time interval has elapsed.

Description

Technical Field

[0001] Embodiments of the present specification relate to a control device for a flyback converter, and more particularly to a control device for a quasi-resonant flyback converter. Background Art

[0002] Electronic converters, such as AC / DC or DC / DC switched-mode power supplies, are well known in the art. There are many types of electronic converters, which can be mainly divided into isolated converters and non-isolated converters. For example, non-isolated electronic converters are buck, boost, buck-boost, Cuk, SEPIC, and ZETA type converters. Conversely, isolated converters include transformers, such as flyback and forward converters. These types of converters are well known to those skilled in the art.

[0003] For example, Figure 1 an example of a flyback converter is shown.

[0004] In the example considered, the electronic converter 20 includes a first input terminal 200a and a second input terminal 200b for receiving a DC input voltage V in and a first output terminal 202a and a second output terminal 202b for providing a DC output voltage V out . For example, the input voltage V in can be provided by a DC voltage source 10 (such as a battery). Generally, the DC input voltage V in can also be generated from an AC voltage via a rectifier circuit (such as a bridge rectifier). Conversely, the output voltage V out can be used to supply power to an electrical load 30.

[0005] The flyback converter includes a transformer T, and the transformer T includes a primary winding T1 and a secondary winding T2. In particular, the first terminal of the primary winding T1 is (e.g., directly) connected to the (positive) input terminal 200a, and the second terminal of the primary winding T1 is (e.g., directly) connected to the (negative) input terminal 200b via the current path of an electronic switch SW. The (negative) input terminal 200b generally represents ground. Thus, the electronic switch SW is configured to selectively connect the primary winding to the input terminals 200a and 200b, i.e., the voltage V in . For example, in the example considered, the electronic switch SW is implemented with an n-channel field effect transistor (FET) (such as an n-channel metal oxide semiconductor field effect transistor (MOSFET), i.e., NMOS). In this case, the drain terminal of the transistor SW is connected to the second terminal of the primary winding T1 representing the switch node SN of the flyback converter, and the source terminal of the transistor SW is connected to the terminal 200b.

[0006] Furthermore, in the example considered, the diode D and the secondary winding T2 are connected in series (e.g., directly) between the output terminals 202a and 202b. For example, the first terminal of the secondary winding T2 can be (e.g., directly) connected to the (positive) output terminal 202a via the diode D, and the second terminal of the secondary winding T2 can be (e.g., directly) connected to the (negative) output terminal 202b. Generally, in addition to the diode D, an electronic switch can also be used as an alternative to the diode D.

[0007] Therefore, the diode (and / or electronic switch) D is configured to selectively connect the secondary winding T2 to the output terminals 202a and 202b.

[0008] Furthermore, the capacitor C is generally (e.g., directly) connected between the terminals 202a and 202b.

[0009] As is well known, the conventional flyback converter 20 operates via a control circuit 210, which is basically configured to drive the electronic switch SW via a corresponding drive signal DRV in order to regulate the output voltage Vout or the output current Iout provided via the terminals 202a and 202b to a given reference value. For example, for this purpose, the control circuit 210 is configured to periodically drive the switch SW through two switching states having corresponding durations T ON and T OFF . During the duration T ON , when the switch SW is closed and the diode / switch D is open, the primary winding T1 of the transformer T1 is (directly) connected to the input voltage V in . Therefore, the primary current Ipri and the magnetic flux in the transformer T increase, thereby storing energy in the transformer T. In this case, the capacitor C supplies energy to the output terminals 202a and 202b (i.e., the load 30). Conversely, during the interval T OFF , when the switch SW is open and the diode / switch D is closed, the primary current Ipri drops to zero, while the secondary-side current Isec begins to flow in the secondary winding, and the energy from the transformer core T recharges the capacitor C and supplies the load 30.

[0010] In particular, in an ideal flyback converter, when the control circuit 210 turns off the electronic switch SW, the current Ipri in the primary winding T1 immediately stops, while due to the closing of the diode / switch D, the current begins to flow in the secondary side T2. In an actual transformer T, however, the two windings T1 and T2 are not perfectly coupled, and leakage inductance still exists on the primary side. Substantially, this leakage inductance can be represented by an inductance L connected in series with the primary winding T1 STo simulate. Conversely, the magnetizing inductance of transformer T (for simulating magnetic flux) can be an inductor L connected in parallel with the primary winding T1 M To simulate.

[0011] Therefore, when the control circuit 210 turns off the electronic switch SW, due to the leakage inductance L s , the primary current Ipri continues to flow in the primary side T1, thus generating a spike across the primary winding T1. In particular, the electronic switch SW has an associated parasitic capacitance CSW connected in parallel with the electronic switch SW, such as the parasitic drain-source capacitance of the corresponding FET. Therefore, the leakage inductance L of transformer T S The current provided will charge this capacitance CSW. Typically, this spike is followed by ringing, which decays due to losses in the system until all the energy stored in the leakage inductance L S (when the electronic switch SW has been turned off) is dissipated.

[0012] To reduce this effect, a flyback converter typically includes a buffer / clamping circuit 204.

[0013] For example, Figure 2 An embodiment of such a buffer / clamping circuit 204 is shown.

[0014] In particular, in Figure 2 , the clamping circuit 204 is connected in parallel with the primary winding T1 of the transformer T and includes a series connection of a clamping capacitor CS and a diode DS, i.e., the clamping capacitor CS and the diode DS are connected in series between the terminals of the primary winding T1. Typically, in addition to the diode D, an electronic switch can also be used as an alternative to the diode D. Typically, a resistor RS is connected in parallel with the capacitor CS (e.g., directly).

[0015] Therefore, the diode / switch DS is configured to selectively connect the capacitor CS (and optionally the resistor RS) in parallel with the primary winding T1.

[0016] In particular, in the example considered, the first terminal of the primary winding T1 is connected (e.g., directly) to the first terminal of the capacitor CS, and the second terminal of the primary winding T1 (i.e., the switch node SN) is connected (e.g., directly) to the second terminal of the capacitor CS via the diode / switch DS.

[0017] Substantially, the addition of the capacitor CS and the diode / switch DS allows the energy in the leakage inductance LS to be diverted into the clamping capacitor CS. In particular, when the control circuit 210 turns off the electronic switch SW, the switch node SN (between the primary winding T1 and the electronic switch SW, e.g., the drain terminal of the transistor SW) rises, as in a normal flyback converter (without clamping). In any case, when the voltage at the switch node SN bypasses the voltage at the clamping capacitor CS, the diode / switch DS turns on and the primary current Ipri also flows to the capacitor CS until the primary current Ipri drops to zero. When the switch DS is used, the energy stored on the capacitor CS can be fed back to the system by turning on the electronic switch DS. Alternatively, the capacitor CS can be discharged via the resistor RS.

[0018] Thus, the clamping circuit 204 typically operates in a complementary mode, i.e., the diode / switch DS is off when the electronic switch SW is closed, and the diode / switch DS is on when the electronic switch SW is open (usually after a short dead time).

[0019] As previously mentioned, the control circuit 210 is configured to drive the electronic switch SW by turning it on for a duration T on and off for a duration T off and, by varying the on-duration T on and / or the off-duration T off , the control circuit 210 can control the energy transfer to the secondary side.

[0020] For example, a known solution involves pulse-width modulation (PWM) of the drive signal DRV, where the duration of the switching period T SW = T ON + T OFF is constant, but the duty cycle T ON / T SW is varied in order to obtain a given output voltage Vout or output current Iout.

[0021] Another type of control is based on the quasi-resonant (QR) switching operation of the flyback converter. In particular, in this case, the control circuit 210 is configured to turn on the switch SW after the transformer demagnetizes (i.e., when the secondary current Isec becomes zero).

[0022] Figure 3 An example of the voltage VSN at the switch node SN is shown in this regard.

[0023] In particular, as previously mentioned, the control circuit 210 is configured to close the switch SW within a given interval T ON by, for example, setting the drive signal DRV high. Thus, the switch SW turns off at time t1.

[0024] Once the switch SW is turned off, the primary - side current Ipri remains positive and thus charges the capacitor CSW associated with the switch node SN. As previously described, once the voltage at the capacitor CS is exceeded, the primary - side current Ipri also charges the capacitor CS, and the voltage V at the switch node SN SN reaches the value Vin + V R , where V R is the "reflected" voltage (i.e., the voltage at the secondary winding T2, i.e., the output voltage Vout), reported to the primary side T1 based on the turns ratio of the transformer T.

[0025] Once the voltage at the secondary side T2 becomes zero / negative (i.e., when the transformer T demagnetizes), the diode / switch D turns off. Thus, the inductance of the transformer T (magnetizing inductance L M and leakage inductance L S ) is now in series with the capacitor CSW between the input terminals 200a and 200b, essentially implementing an LC resonant circuit, thereby generating a resonance (oscillating around Vin) with an amplitude V R and a period T R . Due to this resonance and also considering that the reflected voltage VR is typically less than Vin, the voltage V SN will decrease according to (damped) oscillations, reaching a minimum value at times t3, t3’, t3” etc. Thus, by turning on the switch SW at one of the times t3, t3’, t3” etc. (so - called valley points), the switching losses can be reduced.

[0026] For example, Figure 4 shows a possible implementation of the operation of the control circuit 210.

[0027] In particular, according to Figure 2 the description, the control circuit 210 is configured to generate a drive signal DRV for the electronic switch SW, which is connected in series with the primary winding T1 between the terminals 200a and 200b, where the intermediate node between the primary winding T1 and the electronic switch SW represents the switch node SN. Additionally, in this case, the clamping circuit 204 is also connected to the switch node SN and the capacitor CSN is associated with the switch node SN, which is schematically shown via a capacitor connected between the switch node SN and the terminal 200b (ground). Generally, the capacitor CSN includes the parasitic capacitor CSW of the electronic switch SW, possible other parasitic capacitors (e.g., the parasitic capacitance of the corresponding printed - circuit - board traces), and optionally one or more capacitors connected to the switch node SN.

[0028] In the example considered, the control circuit 210 is associated with:

[0029] A feedback circuit 212, configured to provide a feedback signal FB that indicates an output quantity to be regulated (e.g., an output voltage Vout);

[0030] A current measurement circuit 214, configured to generate a signal CS that indicates (at least) the current Ipri flowing through the primary winding T1 during the on-time period T ON (e.g., is proportional thereto); and

[0031] A valley monitoring circuit 216, configured to generate a signal ZCD that indicates a valley in the voltage V at the switching node SN, such as a demagnetization monitoring circuit, configured to generate a signal that indicates (at least) the magnetization and demagnetization of the transformer T during the off-time period T SN OFF

[0032] For example, in Figure 4 it, the current measurement circuit 214 is implemented by a current sensor (such as a resistor RCS) connected in series with the switch SW (e.g., between the source terminal of the n-channel FET SW and the terminal 200b (ground)), where the voltage across the resistor RCS (corresponding to the signal CS) is proportional to the current flowing through the switch SW.

[0033] Conversely, in the example considered, the valley / demagnetization monitoring circuit 216 is implemented by an auxiliary winding of the transformer T, whereby the voltage across the auxiliary winding indicates (at least) the magnetization of the transformer T during the off-time period T, since the voltage is zero when the transformer T is demagnetized. Further, in the example considered, the demagnetization monitoring circuit 216 includes an optional voltage divider, e.g., implemented by two resistors R1 and R2 connected in series (e.g., directly) between the terminals of the auxiliary winding Taux, where preferably one of the terminals of the auxiliary winding Taux is connected to the terminal 200b (ground). Thus, in the example considered, the voltage across the resistor R1 (corresponding to the signal ZCD) is proportional to the voltage across the terminals of the auxiliary winding Taux. OFF

[0034] Typically, one or more of the following circuits may also be implemented together with the control circuit 210 in an integrated circuit:

[0035] The electronic switch SW;

[0036] At least a part of the feedback circuit 212;

[0037] The current measurement circuit 214; and / or

[0038] The voltage divider R1 / R2.

[0039] Therefore, the control circuit 210 can generate the drive signal DRV based on the signals CS, FB, and ZCD. For example, the control circuit 210 can:

[0040] When the signal CS reaches a given reference value, turn off the electronic switch SW. For example, set the signal DRV to low, where the reference value is determined according to the feedback signal FB; and

[0041] When the signal ZCD reaches zero or becomes negative, turn on the electronic switch SW. For example, set the signal DRV to high, which indicates the demagnetization of the transformer T / the valley of the voltage VSN.

[0042] For example, the feedback circuit 212 or the control circuit 210 can implement a regulator with at least one integral (I) component, whereby the reference value for comparison with the signal CS increases / decreases until the output quantity (Vout or Iout) corresponds to a given requested value.

[0043] Therefore, basically, the switch SW turns off at a given peak of the current Ipri and turns on at one of the valley points in the valley point t3. In particular, in this current-mode QR flyback converter, the switch activity is achieved by synchronizing the turn-on of the switch SW with the valley of the voltage V SN / the demagnetization of the transformer, for example, by detecting the negative edge of the voltage across the auxiliary winding Taux of the generated transformer T, which is connected to the pin of the control circuit 210, usually referred to as the zero-current detection pin (ZCD pin).

[0044] Therefore, Figure 4 The solution shown in

[0045] operates near the boundary between the discontinuous (DCM) and continuous conduction (CCM) of the transformer T, and its operating mode is usually referred to as "valley switching". Figure 3 Typically, the QR flyback converter switches at the first valley, which (as shown in V ) occurs after the time T between the demagnetization moment (moment t2) and the first valley (moment t3), where the time T V corresponds to half of the resonant period T R , that is, T V = T R / 2 = 1 / (2f R ).

[0046] In particular, considering the operation of the converter described with respect to Figure 4 , the switching frequency f of the QR flyback converter SW can be expressed by the following equation:

[0047]

[0048] where f R is the inductance L of the primary winding T1 P (i.e., L P = L S + L M ) and the resonant frequency between the capacitance CSN associated with the switching node SN, i.e.:

[0049]

[0050] And f T is the switching frequency, which corresponds to the frequency of operation of the converter in the transition mode (i.e., at the boundary between continuous and discontinuous conduction modes, i.e., T R = 1 / f R → 0), i.e.:

[0051]

[0052] where V R is still the reflected voltage (i.e., the output voltage Vout reported to the primary winding T1 through the turns ratio of the primary and secondary), the parameter M is the ratio V R / Vin, and P INt is the input power of the transformer.

[0053] As described above, the QR flyback converter has many advantages compared to fixed-frequency (PWM) operation, especially the reduction of switching losses, because the switch SW closes when the voltage across the switch SW reaches the minimum value.

[0054] However, the QR flyback converter also has disadvantages, especially those stemming from the variable frequency, depending on the operating conditions. In fact, as shown in equations (1), (2), and (3), the switching frequency f SW increases with the increase of the input voltage Vin and / or the decrease of the load. This behavior may have a great impact on the switching losses of the converter, which may make it difficult to meet the efficiency recommendations and specifications, such as EuP, EU CoC, or DoE.

[0055] To overcome this problem, the control circuit 210 can be configured to switch the switch SW not at the first valley (t3) but at one of the following valleys (t3’, t3”, etc.), thereby preventing the switching frequency f SW from exceeding a given threshold. For example, for this purpose, the control circuit 210 can include a circuit that is configured to mask the signal ZCD or the corresponding trigger signal T generated by the zero-current detector / comparator of the control circuit 210 based on the signal ZCD ZCD .

[0056] For example, possible solutions include having a corresponding blanking interval TBLANK The timer circuit shields the trigger signal T from the zero current detector / comparator ZCD , which ensures that the switch SW remains open for at least the interval T BLANK ends. This blanking time T BLANK can start when the switch SW is turned on (at one of the times t3) or when the switch SW is turned off (at time t1). In this way, when the trigger signal T ZCD one or more pulses of are within T BLANK window, the turn-on of the switch SW is delayed until the first valley appears after the time T BLANK time, thus limiting the maximum value of the switch operating frequency. This function is sometimes called "valley skipping".

[0057] Therefore, the total switch period TSW is given by the following equation:

[0058]

[0059] where T V(k) corresponds to the time after transformer demagnetization (time t2) and the k-th valley, and can be calculated, for example, by the following equation:

[0060]

[0061] Typically, the blanking time T BLANK can be fixed or variable. For example, in some commercial control circuits 210 (implemented in the corresponding IC), the blanking time T BLANK can vary according to the feedback level FB to gradually reduce the operating frequency f as the load decreases SW . Alternatively, a current sensing signal CS can be used because the (peak) of the signal CS is also smaller in the case of a lower load.

[0062] Therefore, more and more ringing periods are skipped and the operating frequency gradually decays. For example, based on the load conditions (and thus also based on the input power), the control circuit 210 can operate the electronic converter in the following modes:

[0063] When the input power exceeds the first value, it is in the quasi-resonant mode, where the switch SW turns on with the first valley;

[0064] When the input power is less than the first value, it is in the valley-skipping mode, where one or more valleys are skipped to limit the switch frequency f SW , and

[0065] When the input power is less than a second value (the second value being less than the first value), it is optionally in burst mode, where the control circuit generates one or more switching cycles, for example, until the output voltage exceeds a given upper threshold and then waits until the output voltage drops below a given lower threshold.

[0066] However, when the blanking time T BLANK ends near one of the multiple valleys, the sequence of switching cycles may be irregular because in this case, the control circuit 210 can switch during the cycle at valley i and during the next cycle at valley i - 1, and vice versa. This "valley hopping" phenomenon may introduce a low - frequency component in the primary current Ipri, which may fall within the audible range. If the amplitude of this periodic perturbation is large enough, audible noise can be generated, for example, through the mechanical vibration of magnetic components.

[0067] Various control circuits for solving the valley - hopping problem are known. For example, ON Semiconductor offers two QR flyback controllers (NCP1379, NCP1380) equipped with a "valley lock" function, as described in patent US 8,391,027 B2. Similarly, Infineon offers a series of QR flyback controllers (ICE2QS03x) equipped with a "digital frequency decreases as the load decreases" function.

[0068] In addition, the present applicant has disclosed a "valley lock" function in patent US 9,083,250 B2. Basically, the method defines a baseline blanking time T BLANK_0 (a fixed value or function of the current sensing signal CS) and a per - cycle dynamically adjustable blanking time T BLANK_0 with an initial setting equal to T BLANK . A counter calculates the number of valleys i after transformer demagnetization in each switching cycle through a resettable N - bit counter until the switch SW turns on through the first valley after time T BLANK ends. The value k is sampled, and the blanking time T BLANK_0 for the next switching cycle is determined by proportionally offsetting the baseline blanking time T BLANK to the sampled value k, for example, by using the following relationship:

[0069] T BLANK = T BLANK_0 + iΔT B

[0070] where ΔT B is an appropriate "time lag" that ensures stable operation with a given number of skipped valleys. Summary of the Invention

[0071] In view of the above, the aim of the various embodiments is thus to provide alternative solutions for driving a quasi-resonant flyback converter, in particular to prevent or at least reduce valley jumps.

[0072] According to one or more embodiments, one or more of the above aims are achieved by a control circuit for a flyback converter, which flyback converter has unique elements specifically set forth in the following claims. The embodiments also relate to related integrated circuits, electronic flyback converters and methods.

[0073] The claims form part of the technical teaching of the specification provided herein.

[0074] As previously mentioned, the various embodiments of the present disclosure relate to a control circuit for a flyback converter. Such a flyback converter generally includes a positive input terminal and a negative input terminal for receiving an input voltage, and two output terminals for providing an output voltage or an output current. The flyback converter also includes a transformer having a primary winding and a secondary winding, an electronic switch, and another electronic switch (such as a diode). For example, a first terminal of the primary winding may be connected to the positive input terminal, and a second terminal of the primary winding may represent a switching node. The electronic switch may be connected between the switching node and the negative input terminal. The other electronic switch may be connected in series with the secondary winding between the two output terminals.

[0075] In various embodiments, the control circuit is thus configured to generate a drive signal for the electronic switch, wherein the control circuit is configured to generate a switching period by setting the drive signal to a first logic level for the on-duration for closing the electronic switch and a second logic level for the off-duration for opening the electronic switch.

[0076] In various embodiments, the control circuit includes a terminal configured to be connected to a current measurement circuit configured to generate a current measurement signal indicative of the current flowing through the primary winding during the on-duration; and a terminal configured to be connected to a valley monitoring circuit configured to provide a valley signal indicative of a valley in the voltage at the switching node.

[0077] In various embodiments, the control circuit further includes a comparison circuit configured to generate an off signal by comparing the current measurement signal with a current measurement threshold signal; and a valley detection circuit configured to generate a trigger in a trigger signal when the valley signal indicates a valley in the voltage at the switching node. For example, the valley detection circuit may include a comparator circuit configured to compare the valley signal with a reference signal; and an edge detector configured to generate a pulse in the trigger signal when setting the signal at the output of the comparator circuit.

[0078] In various embodiments, the control circuit further includes a blanking circuit configured to generate an on signal by combining a trigger signal and a timer signal provided by a timer circuit, where the timer signal indicates whether a blanking time interval has elapsed. For example, the timer circuit can be implemented by a digital counter circuit configured to reset an internal count value in response to an on signal or an off signal, increment the internal count value in response to a clock signal, and set the timer signal to a first logic level when the internal count value is less than a reference value indicating the duration of the blanking time interval, and set the timer signal to a second logic level when the internal count value is greater than the reference value. In various embodiments, the reference value can be determined based on a feedback signal, a current measurement signal, or a current measurement threshold signal.

[0079] Thus, in various embodiments, the control circuit can include a (driver) circuit configured to set a drive signal to a first logic level for closing an electronic switch in response to an on signal and set the drive signal to a second logic level for opening the electronic switch in response to an off signal.

[0080] In particular, in various embodiments, the blanking circuit is configured to start the timer circuit in response to an on signal or an off signal. Then, the blanking circuit monitors a first number of triggers in the trigger signal during each switching cycle, where the first number indicates the number of valleys in the voltage at the switch node until the electronic switch is closed, and monitors a second number of triggers in the trigger signal during each switching cycle until the timer signal indicates that the blanking time interval has elapsed, where the second number indicates the number of valleys in the voltage at the switch node during the blanking time interval. For example, for this purpose, the blanking circuit can include a first digital counter configured to increment the first number in response to the trigger signal and reset the first number in response to an on signal or an off signal; and / or a second digital counter configured to increment the second number in response to the trigger signal and reset the second number in response to an on signal or an off signal when the timer signal indicates that the blanking time interval has not elapsed.

[0081] In various embodiments, the blanking circuit is configured to determine whether a blanking signal indicates that a blanking time interval has elapsed and whether a first number has reached or exceeded a given maximum value. When the first number exceeds the maximum value, the blanking circuit stores the first number as the new maximum value. When the blanking signal indicates that the blanking time interval has not elapsed or the second number is less than the given maximum value, the blanking circuit disables the turn-on signal. When the blanking signal indicates that the blanking time interval has elapsed and the second number has reached or exceeded the given maximum value, the blanking circuit sets the turn-on signal in response to a trigger signal. For example, for this purpose, the blanking circuit may include combinational logic circuitry configured to generate the turn-on signal by combining the trigger signal with the blanking signal; and comparator circuitry configured to set the blanking signal to a first logic level when the blanking signal indicates that the blanking time interval has not elapsed or the second number is less than the given maximum value, and to set the blanking signal to a second logic level when the blanking signal indicates that the blanking time interval has elapsed and the second number has reached or exceeded the given maximum value.

[0082] In various embodiments, the blanking circuit is configured to selectively reset the maximum value by comparing the second number with the first number or the maximum value. For example, in various embodiments, the blanking circuit includes comparator circuitry configured to set the blanking signal by comparing the second number with the first number, thereby determining a first condition when the second number is less than the first number minus a first threshold, a second condition when the second number is equal to or greater than the first number minus the first threshold but less than the first number minus a second threshold, and a third condition when the second number is equal to or greater than the first number minus the second threshold. In such a case, the blanking circuit may include a reset circuit configured to reset the maximum value when the comparator circuitry indicates the first condition for consecutive switching cycles of the first number, or when the comparator circuitry indicates the second condition for consecutive switching cycles of the second number, the consecutive switching cycles of the second number being greater than the consecutive switching cycles of the first number.

[0083] In various embodiments, the control circuit may further include a terminal configured to be connected to a feedback circuit configured to provide a feedback signal indicative of an output voltage or an output current; and a regulator circuit including an integrating component and optional proportional and / or derivative components configured to generate a current measurement threshold signal based on the feedback signal. In such a case, the reset circuit may be configured to periodically store the value of the feedback signal and to reset the maximum value when the feedback signal increases beyond a given amount.

[0084] Additionally or alternatively, the reset circuit may be configured to determine whether a current measurement signal has reached a maximum threshold signal and to reset the maximum value when the current measurement signal reaches the maximum threshold signal for a given number of consecutive switching cycles. Description of the Drawings

[0085] The features and advantages of the present disclosure will become apparent from the following detailed description of non - limiting examples shown in the accompanying drawings, in which:

[0086] Figure 1 A circuit schematic diagram of a flyback converter is shown;

[0087] Figure 2 A circuit schematic diagram of a flyback converter with a clamping circuit is shown;

[0088] Figure 3 Shows Figure 2 Exemplary waveforms of the converter of

[0089] Figure 4 A circuit schematic diagram of a flyback converter including a quasi - resonant control circuit is shown;

[0090] Figure 5 Shows a first embodiment of the quasi - resonant control circuit according to the present specification;

[0091] Figure 6 Shows a second embodiment of the quasi - resonant control circuit according to the present specification;

[0092] Figure 7 Shows Figure 5 Or Figure 6 Examples of the operation of the control circuit of

[0093] Figure 8 And Figure 9 And Figure 10 And Figure 11 And Figure 12 Shows Figure 5 Or Figure 6 Examples of various sub - circuits of the control circuit of Detailed Description of the Invention

[0094] In the following description, various specific details are shown in order to provide a thorough understanding of the embodiments. The embodiments may be practiced without one or more of the specific details, or may have other methods, components, materials, etc. In other instances, well - known structures, materials, or operations are not shown or described in detail so as not to obscure various aspects of the embodiments.

[0095] References to "one embodiment" or "an embodiment" in the context of this specification mean that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases such as "in one embodiment" or "in an embodiment" that may appear at various points in this specification are not necessarily all referring to the same embodiment. Furthermore, the particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0096] The references used herein are provided for convenience only and thus do not limit the scope of protection or the scope of the embodiments.

[0097] In the following description Figures 5 to 12 of Figures 1 to 4 the components, elements, or assemblies described with reference to the previous figures are designated by the same reference numerals as those previously used in these figures. Since these elements have been described, they will not be repeated herein to avoid burdening this detailed specification.

[0098] Figure 5 An embodiment of a control / driver circuit 210a for a flyback converter according to the present disclosure is shown. For a general description of a quasi-resonant flyback converter, reference may be made to the previous description, particularly with respect to Figure 2 and Figure 4 .

[0099] In particular, in the embodiment shown in Figure 5 , the control circuit 210a (such as an integrated circuit) includes:

[0100] Two terminals for receiving a power supply voltage, such as a (positive) terminal VDD and a ground terminal GND;

[0101] A terminal configured to be connected to a feedback circuit 212, the feedback circuit 212 providing a feedback signal FB, the feedback signal FB indicating an output quantity to be regulated, such as an output voltage Vout or an output current Iout;

[0102] A terminal configured to be connected to a current measurement circuit 214, the current measurement circuit 214 being configured to generate a signal CS, the signal CS indicating the current Ipri flowing through the primary winding T1 (e.g., being proportional thereto) at least during the on-time period T ON ; and

[0103] A terminal configured to be connected to a valley / demagnetization monitoring circuit 216, the valley / demagnetization monitoring circuit 216 being configured to generate a signal ZCD, the signal ZCD indicating the valley in the voltage V SN , e.g., the magnetization and demagnetization of the transformer T at least during the off-time period T OFF .

[0104] In the embodiment under consideration, the control circuit 210 includes a terminal for providing a drive signal DRV to an external electronic switch SW, such as the gate terminal of a corresponding n-channel FET (e.g., NMOS).

[0105] Conversely, Figure 6 An embodiment is shown in which the electronic switch SW is integrated in the integrated circuit of the control circuit 210a. In this case, the control circuit 210a may include a terminal configured to be connected to the switching node SN. For example, when the electronic switch SW is an n-channel FET (e.g., NMOS), the drain terminal of the n-channel FET SW may be (e.g., directly) connected to the terminal SN.

[0106] In various embodiments, the current measurement circuit 214 may be implemented with a current sensor (such as a resistor RCS) connected in series with the switch SW (e.g., between the source terminal of the corresponding n-channel FET SW and the ground terminal GND), where the voltage across the resistor RCS is proportional to the current flowing through the switch SW. Also in this case, the current measurement circuit 214 (e.g., the resistor RCS) may be internal (see Figure 6 ) or external (see Figure 5 ) with respect to the integrated circuit of the control circuit 210a.

[0107] In various embodiments, the control circuit 210a includes a comparison circuit 2110 configured to compare a signal CS with a threshold signal PTH, where the signal CS indicates the primary side current Ipri.

[0108] In particular, in various embodiments, when the value of CS reaches (or exceeds) the value of the threshold signal PTH, the switch SW is turned off. Thus, in various embodiments, the comparison circuit 2110 includes (preferably an analog) comparator 2116 configured to generate a signal S_OFF by comparing the signal CS with the threshold signal PTH, where the signal S_OFF indicates that the switch SW should be turned off.

[0109] In various embodiments, the comparison circuit 2110 further includes a second (preferably an analog) comparator 2114 configured to generate a signal OCP by comparing the signal CS with a second threshold signal OTH, where the signal OTH indicates a maximum value, thereby implementing overcurrent protection. In this case, the signals at the output terminals of the comparators 2116 and 2114 may be combined, for example, via a logical OR gate 2118 to generate the signal S_OFF. In the case where such overcurrent protection is not used, the signal S_OFF may directly correspond to the comparison signal at the output of the comparator 2116.

[0110] In various embodiments, the threshold signal PTH is generated based on an output quantity (i.e., the output voltage Vout or the output current Iout). For example, in various embodiments, an electronic converter for this purpose includes:

[0111] A feedback circuit 212 configured to generate a feedback signal FB, the feedback signal FB indicating the output quantity, such as a voltage or current sensor, and optionally further including an optocoupler (or other type of transmission circuit) for transmitting the feedback signal FB from the secondary side of the transformer T to the primary side; and

[0112] A regulator circuit 2112 including an integral component (I) and an optional proportional component (P) and / or derivative component (D), these components being configured to generate the threshold signal PTH based on the feedback signal FB.

[0113] In various embodiments, the feedback signal FB may be proportional to the output quantity, or may already represent an error signal that indicates the difference between the output quantity and the requested value of the output quantity.

[0114] In various embodiments, at least a portion of the regulator circuit 2112 and / or the feedback circuit 212 may be implemented in an integrated circuit of the control circuit 210a. For example, in Figure 5 and Figure 6 the regulator 2112 is implemented directly in the control circuit 210a.

[0115] In the considered embodiment, in order to turn on the switch SW, the control circuit 210a includes:

[0116] A valley / demagnetization detection circuit 2100 configured to analyze the signal ZCD provided by the valley / demagnetization monitoring circuit 216 and generate a trigger signal T ZCD , where the signal ZCD indicates the valley in the voltage V SN / demagnetization of the transformer T; and

[0117] A blanking circuit 2140 configured to generate a signal BLANK for enabling the valley / demagnetization detection circuit 2100.

[0118] For example, in the considered embodiment, the valley / demagnetization detection circuit 2100 includes:

[0119] A comparator 2102 configured to compare the signal ZCD with a reference signal REF (usually close to 0V), where when the signal ZCD drops below the value of the reference signal REF, the output of the comparator 2102 is set; and

[0120] An edge detector 2104 configured to generate a pulse in the signal T ZCD when the signal at the output of the comparator 2100 is set.

[0121] In the embodiment under consideration, the valley / demagnetization detection circuit 2100 is enabled via a logic gate 2120, such as an AND gate, which is configured to generate a signal S_ON that indicates that the switch SW should be turned on according to a trigger signal T ZCD and a signal BLANK, i.e., the signal BLANK masks the signal T ZCD ).

[0122] Thus, in the embodiment under consideration, the signals S_ON and S_OFF can be provided to a latch or flip-flop 2130, e.g., to the set and reset inputs of a corresponding set-reset latch or flip-flop, and the signal at the output of the latch or flip-flop 2130 can be used to drive the switch SW, e.g., via an optional FET driver circuit 2132, which is configured to generate a drive signal DRV according to the signal at the output of the latch or flip-flop 2130.

[0123] Thus, in addition to the circuits 2100 to 2140, (at least) one or more of the following circuits can also be implemented together with the control circuit 210 in the integrated circuit:

[0124] The electronic switch SW;

[0125] The driver circuit 2132;

[0126] At least a part of the feedback circuit 212, such as a corresponding optocoupler;

[0127] The current measurement circuit 214, such as a resistor RCS; and / or

[0128] The valley / demagnetization monitoring circuit 216, such as a voltage divider R1 / R2.

[0129] Figure 7 A first embodiment of the operation of the blanking circuit 2140 is shown.

[0130] After starting step 1000, e.g., corresponding to the power-on of the control circuit 210a, the blanking circuit 2140 performs an initialization operation at step 1002. During this step, the blanking circuit 1040 determines a value indicating the requested blanking time T BLANK . Typically, the blanking time T BLANK can be predefined / constant, or the blanking circuit 1040 can be configured to determine the blanking time T according to an input or output power level BLANK , e.g., as indicated by a feedback signal FB or a threshold signal PTH that is used as the peak of a signal CS, i.e., the blanking circuit 1040 can determine the blanking time T according to the feedback signal FB, the threshold signal PTH, or the signal CS (at least one of them) BLANKIn addition, the blanking circuit 1040 may initialize other parameters, such as parameters k and k M .

[0131] Next, the blanking circuit 1040 starts a timer circuit at step 1004, and the timer circuit is configured to determine when the blanking time T BLANK elapses. For example, the timer circuit may start when the switch SW is turned off (at time t1) or when the switch SW is turned on (at one of the times t3). For example, in Figure 5 and Figure 6 In the embodiment shown, the blanking circuit 1040 may set the signal BLANK to low, while the timer circuit issues a signal indicating that the blanking time T BLANK has not elapsed yet.

[0132] Next, the blanking circuit 1040 monitors the trigger signal T ZCD (or the signal at the output of the comparator 2102) at step 1006 in order to determine the number of valleys that occur after the transformer demagnetizes until the first valley is detected after the elapsed time T BLANK . For example, for this purpose, the blanking circuit 1040 may reset the count value k between times t1 and t2, and preferably at the time when the switch SW is turned off (time t1). Then, when the signal of the timer circuit indicates that the blanking time TBLANK has not elapsed, the count value k may be incremented at each valley (e.g., at each trigger in the signal T ZCD ).

[0133] Next, the blanking circuit 1040 determines the value of the parameter k M at step 1008. In particular, in various embodiments, the blanking circuit 1040 compares the current value of the parameter k M with the count value k, and when the count value k is greater than the parameter k M (i.e., k>k M ), the blanking circuit 1040 stores the current count value k as the parameter k M (i.e., k M =k). Thus, essentially, the parameter k M indicates the maximum value of the count value k.

[0134] At the verification step 1010, the blanking circuit 1040 compares the current count value k with the parameter k M .

[0135] When the count value k does not correspond to the value k M and thus is less than the value k MIn the case of (verifying the output “N” of step 1010), the blanking circuit 1040 proceeds to step 1012, where the blanking circuit 1040 signals, for example, by keeping the signal BLANK low that the next valley should be skipped. At the subsequent step 1014, the blanking circuit 1040 then waits for the next valley (in accordance with the description of step 1006), increments the count value k by 1, and returns to step 1008.

[0136] In the case of the count value corresponding to the value kM (verifying the output “Y” of step 1010), the blanking circuit 1040 proceeds to step 1018.

[0137] Basically, steps 1004 to 1014 implement a loop, where the signal BLANK is set low (thus keeping the switch SW off) until the blanking time T BLANK has elapsed and the value k corresponds to the value k M is reached.

[0138] Typically, as schematically shown via step 1016, in the case where the blanking time T BLANK has not elapsed, the blanking circuit 1040 can also directly use steps 1008 to 1014 to sequentially increment the count value k instead of determining the number of valleys during the blanking time T BLANK at step 1006. For this purpose, the blanking circuit 1040 can verify at step 1010 or an additional verification step 1016 whether the blanking time T BLANK has elapsed. In the case where the blanking time T BLANK has not elapsed (verifying the output N of step 1012), the blanking circuit 1040 can return to step 1012. Conversely (verifying the output Y of step 1012), the blanking circuit 1040 can proceed to step 1018.

[0139] Thus, the blanking circuit 1040 is configured (via steps 1006 to 1016) to monitor the number of valleys k until the following two conditions are met:

[0140] The timer circuit of the blanking circuit 1040 indicates that the blanking time T BLANK has elapsed, and

[0141] the number of valleys k has reached or exceeded a given maximum value k M .

[0142] In this case, if the number k is greater than the maximum value k M (i.e., the number of valleys during the blanking time T BLANK is greater than the value k M ), then the blanking circuit 1040 stores the current number k as the new maximum value k M, so that, for example, the value k increases due to a reduced load or an increased input voltage Vin M .

[0143] Assume that blanking does not occur initially (i.e., k = 0 and k M = 0). A reduced load may cause the frequency to increase until one or more valleys k fall within the blanking interval, and the corresponding number k of valleys will also be stored as the parameter k M . In the case where the load increases again, the blanking circuit 1040 will continue to skip k M valleys, thus implementing the valley-locking function.

[0144] Therefore, steps 1004 to 10016 basically follow a reduced load but do not handle an increased load.

[0145] Therefore, in various embodiments, the blanking circuit 1040 is also configured to reset the value k when a given condition is met M .

[0146] In particular, in the Figure 7 embodiment shown, the blanking circuit 1040 is configured to store the blanking interval T by, for example, storing the value k at step 1006 BLANK the number k of valleys during QR . Alternatively, the value k QR may only increase during the blanking time, thus indicating the number of valleys for which the converter will operate without the valley-locking feature. Therefore, the blanking circuit 1040 is generally also configured to monitor the number k of valleys QR until the timer circuit of the blanking circuit 1040 indicates that the blanking time T BLANK has elapsed.

[0147] In particular, in the case of an increased load, the value k QR will decrease. Therefore, in various embodiments, the blanking circuit 1040 is configured to compare the value k QR with the value k M or a similar k (as long as these values should correspond at the end of steps 1004 to 1018).

[0148] In particular, in various embodiments, the blanking circuit 1040 is configured to:

[0149] determine a first condition "A", the first condition "A" by verifying whether the current value k QR is less than k M (or k) the current value minus a first threshold n H (i.e., k QR < k M - n H ) to indicate a rapid change;

[0150] Determine the second condition "B", where the second condition "B" is determined by verifying whether the current value of k QR is greater than k M (or k) minus the first threshold value n H , but less than k M (or k) minus the second threshold value n L (i.e., k M -n H ≤k QR <k M –n L ) to indicate a slow change; and

[0151] Determine the third condition "C", where the third condition "C" is determined by verifying whether the current value of k QR is greater than k M (or k) minus the second threshold value n L (i.e., k QR ≥k M –n L ) to indicate that no substantial change has occurred.

[0152] For example, in various embodiments, the first threshold value n H is 2 (i.e., n H = 2), and the second threshold value n L is 1 (i.e., n L = 1). In this case, the blanking circuit can determine the following conditions:

[0153] Condition A: k QR <k M -2;

[0154] Condition B: k QR =k M -2; and

[0155] Condition C: k QR >k M -2.

[0156] In various embodiments, if the blanking circuit 1040 determines condition "A" (verifying the output "A" of step 1018), then the blanking circuit 1040 is configured to reset the value of k M .

[0157] In various embodiments, instead of proceeding directly to step 1026, the blanking circuit 1040 increments the fast change count value FCNT at step 1022 and compares the fast change count value FCNT with a threshold value FTH at step 1024.

[0158] Specifically, in the considered embodiment, when the fast change count value FCNT reaches the threshold FTH (the output "Y" of verification step 1024), the blanking circuit 1040 proceeds to step 1026. Conversely (the output "N" of verification step 1024), the blanking circuit 1040 resets the count value at step 1032 and returns to step 1004. Therefore, if steps 1022 and 1024 are omitted, essentially the threshold FTH corresponds to 1.

[0159] Similarly, the blanking circuit 1040 proceeds from step 1026 to step 1032 to monitor the next switching cycle.

[0160] Therefore, when the value k QR remains in the (fast change) condition "A" for a given number FTH of switching cycles, the value k M is reset.

[0161] In various embodiments, if the blanking circuit 1040 determines condition "B" (the output "B" of verification step 1018), the blanking circuit 1040 is configured to similarly reset the value k at step 1026 M . Specifically, in this case, the blanking circuit 1040 does not directly proceed to step 1026, but instead increments the slow change count value SCNT at step 1028 and compares the slow change count value SCNT with a threshold STH at step 1030, where this threshold is greater than the threshold FTH (if optional steps 1022 and 1024 are used).

[0162] Specifically, in the considered embodiment, when the slow change count value SCNT reaches the threshold STH (the output "Y" of verification step 1028), the blanking circuit 1040 advances to step 1026. Conversely (the output "N" of verification step 1028), the blanking circuit 1040 advances to step 1032 to monitor the next switching cycle.

[0163] Therefore, when the value k QR remains in the (slow change) condition "B" for a given number STH of switching cycles, the value k M is reset.

[0164] Finally, if the blanking circuit 1040 determines condition "C" (the output "C" of verification step 1018), the blanking circuit 1040 advances to step 1032 to monitor the next switching cycle, that is, when no substantial change occurs, the value k M is not reset, thus essentially implementing a hysteresis function.

[0165] In various embodiments, the blanking circuit 1040 is configured to:

[0166] Optionally, in response to the detection of condition A, for example, at step 1022, reset the count value SCNT;

[0167] In response to the detection of condition B, for example, at step 1028, reset the count value FCNT; and

[0168] In response to the detection of condition C, for example, at step 1034, reset the count value FCNT and the count value SCNT.

[0169] Thus, in various embodiments, the value k M is not reset for small load variations, and the value k M is reset after fewer switching cycles in the case of larger load variations.

[0170] Figure 8 illustrates an embodiment of an electronic circuit configured to implement the operation of the blanking circuit 2140 described with respect to Figure 7 the described blanking circuit 2140.

[0171] In the considered embodiment, the blanking circuit 2140 includes a timer circuit 428, which is configured to monitor the time interval T BLANK when a time interval T has elapsed (e.g., relative to the turn - on or turn - off moment of the switch SW), BLANK and generate a timer signal BLANK_T. For example, in the considered embodiment, the timer circuit 428 is implemented by a digital counter circuit, which is configured to:

[0172] reset the internal count value in response to the signal S_ON or S_OFF;

[0173] increase the internal count value in response to the clock signal CLK; and

[0174] set the timer signal BLANK_T to a first logic level (e.g., low level) when the internal count value is less than a reference value C_BLANK, the reference value C_BLANK indicating the duration of the time interval T BLANK and set the timer signal BLANK_T to a second logic level (e.g., high level) when the internal count value is greater than the reference value C_BLANK. As described above, the value of the time interval T BLANK (e.g., the value C_BLANK) can be determined according to power requirements, for example, as indicated by the signal FB or PTH.

[0175] In the considered embodiment, the blanking circuit 2140 further includes a valley counter 408, which is configured to count the valleys indicated by the signal ZCD, for example, by incrementing the count value in response to the signal T ZCD thereby providing the value k.

[0176] As described above, the blanking circuit 2140 is configured to provide two additional values:

[0177] The maximum value k of the count value k M ; and

[0178] The number of valleys k during the time interval T BLANK QR .

[0179] Thus, generally, these values can be determined according to the count value k.

[0180] For example, in various embodiments, the comparison circuit 424 is configured to compare the current value k M with the value k, and generate a trigger signal when the value k is greater than the value k M . Conversely, the second circuit 422 is configured to store the value k if the comparison circuit 424 generates a trigger signal. Thus, generally, the circuit 424 can be implemented by a memory (such as a latch or a register), and the memory is configured to store the signal / value k in response to the trigger signal generated by the comparison circuit 424. Conversely, in the considered embodiment, the circuit 422 is implemented by a counter, and the counter is configured to increase its count value in response to the trigger signal generated by the comparison circuit 424.

[0181] Similarly, the circuit 400 may include a memory, and the memory is configured to store the value k in response to the timer signal BLANK_T (e.g., in response to its rising edge), so as to provide only the number of valleys k during the blanking interval T BLANK QR . Conversely, in the considered embodiment, the circuit 400 includes a separate counter circuit 404, and the counter circuit 404 is configured to separately monitor the valleys during the blanking interval T BLANK . For this purpose, the counter circuit 404 is associated with a combinational logic circuit 402, and the combinational logic circuit 402 is configured to provide a trigger signal by combining the trigger signal TZCD and the timer signal BLANK_T. Thus, in various embodiments, the counter circuit 404 is configured to increase the signal / value k in response to the trigger signal T BLANK only when the signal BLANK_T indicates that the time interval T has not elapsed (i.e., when the signal BLANK_T has a first logic level) ZCD QR .

[0182] Thus, in the considered embodiment, three separate counters are used to generate the signals k, k M and k QR , but generally a single counter (or two counters) can also be used. ​​​

[0183] As described above, once the time interval T has elapsed BLANK , the blanking circuit 2140 should enable the activation of the switch SW with the next valley. For example, in the embodiment under consideration, the comparison circuit 426 is configured to set the blanking signal BLANK (e.g., see Figure 4 ) to:

[0184] a first logic level (e.g., low), when the time interval T has not elapsed BLANK or the value k is less than the value k M (i.e., k < k M ); and

[0185] a second logic level (e.g., high), when the time interval T has elapsed BLANK and the values k and k M correspond (i.e., k = k M ).

[0186] For example, to determine whether the time interval T BLANK has passed, the comparison circuit 426 can monitor the signal BLANK_T.

[0187] Thus, substantially blocks 402, 403, 408, 422, 424, and 426 implement Figure 7 steps 1002 to 1018.

[0188] In particular, these blocks determine the values k, k M and k QR , and follow and increase the maximum value kM. However, as described above, the value k QR should be used to decide whether the value kM should be reset. More specifically, as described above, the value k (stored in the counter 408) and k QR (stored in the counter or only stored in the memory 404) should be reset for each switching cycle before the moment of transformer demagnetization. For example, in various embodiments, these circuits 404 and 408 are reset in response to the signal S_ON or S_OFF (e.g., in response to the closing of the power switch SW).

[0189] Thus, once the signal T ZCD issues a valley signal in the signal ZCD, the counter k is incremented (and similarly the count value k QR ). In parallel, the blanking circuit 4140 performs several operations:

[0190] When the value k is greater than the current value kM, the comparison circuit 424 compares the value k with the current value k M and updates the value k M (i.e., stores the value k or increments the value k M );

[0191] When the blanking interval T has not elapsed BLANK the circuit 400 updates the value k QR (i.e., stores the value k or increments the value k QR ); and

[0192] When the time interval T has elapsed BLANK and the values of k and k M correspond, the comparison circuit 426 sets the signal BLANK to a second logic level (e.g., high).

[0193] Conversely, the value of k M (stored in the counter or only in the memory 422) should be reset according to the value of k QR .

[0194] In the embodiment under consideration, the circuit 400 is thus associated with a comparison circuit 406 configured to implement a comparison operation at Figure 7 step 1020.

[0195] Specifically, the comparison circuit 406 is configured to compare the value of k QR with the value of k M or k. More specifically, in the embodiment under consideration, the comparison circuit 406 is configured to compare the value of k QR with the value of k, as this avoids any additional combinational or sequential logic circuitry, since these signals increase in parallel during the blanking interval T BLANK and the value of k can only increase further when the blanking interval TBLANK ends. However, it is also possible to start the comparison only when the blanking interval TBLANK has elapsed, e.g., by starting the comparison in response to the signal BLANK.

[0196] In various embodiments, the comparison circuit 406 provides one or more comparison signals at the output indicating whether conditions "A", "B" or "C" are met (see the description of step 1020). For example, in the embodiment under consideration, two signals S_C and F_C are used, which are set to:

[0197] For condition A (e.g., k QR < k M - 2), F_C = "1" and S_C = "1";

[0198] For condition B (e.g., k QR = k M - 2), F_C = "0" and S_C = "1"; and

[0199] For condition C (e.g., k QR > k M-2), F_C = "0" and S_C = "0".

[0200] In the considered embodiment, the signals F_C and S_C are illustrated by a circuit 410, which is configured to selectively reset a memory or a counter 422.

[0201] In particular, in the considered embodiment, the circuit 410 includes a first sub - circuit 412 configured to implement steps 1028 and 1030 and a second sub - circuit 414 configured to implement steps 1022 and 1024.

[0202] For example, Figure 9 An embodiment of the circuit 412 is shown.

[0203] In the considered embodiment, the circuit 412 is implemented by an auto - reload counter circuit that increments in response to the signal S_C. In particular, in the considered embodiment, the circuit 412 includes a counter 4126 configured to:

[0204] Increment an internal count value in response to the signal S_C;

[0205] Generate / set a trigger signal S_R when the internal count value reaches a given threshold (e.g., 256 or 512); and

[0206] Reset the internal count value when the trigger signal S_R is set.

[0207] In various embodiments, the circuit 4126 may be associated with an additional reset circuit configured to generate an additional reset signal RS for the counter 4126 when the signal S_C is low when the switch SW is on. For example, in the considered embodiment, the reset circuit includes:

[0208] A latch 4120 (such as a set - reset latch) configured to set its output Q high when the signal S_C is set; this latch 4120 may be reset once per switch cycle, e.g., in response to the signal S_OFF; and

[0209] A logic gate 4122 (such as an AND gate) configured to set the reset signal RS when the output Q of the latch 4120 is low when the switch is closed (e.g., when the output Q of the latch 4120 is low and the signal S_ON is high).

[0210] In the considered embodiment, the reset terminal of the counter 4126 may thus receive the trigger signal S_R and the reset signal RS via, for example, a logical OR gate 4124.

[0211] Typically, circuit 414 generates a trigger signal F_R in response to signal F_C. In various embodiments, signal F_R may correspond to signal F_C.

[0212] Conversely, Figure 10 An embodiment of circuit 414 is shown, which substantially corresponds to circuit 412.

[0213] In particular, in the considered embodiment, circuit 414 is also implemented by an auto-reload counter circuit that increments in response to signal F_C. In particular, in the considered embodiment, circuit 414 includes a counter 4146 that is configured to:

[0214] Increment an internal count value in response to signal F_C;

[0215] Generate / set the trigger signal F_R when the internal count value reaches a given threshold (e.g., 4 or 8); and

[0216] Reset the internal count value when the trigger signal F_R is set.

[0217] In various embodiments, circuit 4146 may also be associated with an additional reset circuit that is configured to generate an additional reset signal RF for counter 4146 when signal F_C is low while switch SW is on. For example, in the considered embodiment, the reset circuit includes:

[0218] A latch 4140 (such as a set-reset latch) configured to set its output Q high when signal F_C is set; this latch 4140 may be reset once per switch cycle, e.g., in response to signal S_OFF; and

[0219] A logic gate 4142 (such as an AND gate) configured to set the reset signal RF when the output Q of latch 4120 is low while switch SW is closed (e.g., when the output Q of latch 4140 is low and signal S_ON is high).

[0220] In the considered embodiment, the reset terminal of counter 4146 may thus receive the trigger signal F_R and the reset signal RF via, for example, a logic OR gate 4144.

[0221] Thus, in the considered embodiment, the memory / counter 422 is reset when signal S_R is set (e.g., when signal S_C goes high during a given first number of switch cycles), or when signal F_R is set (e.g., when signal F_C goes high during a given second number of switch cycles), where the first number is greater than the second number.

[0222] For example, for this purpose, a combinational logic circuit 420 (such as an OR gate) can generate a reset signal for the memory / counter 422 by combining the signals S_R and F_R.

[0223] In various embodiments, the circuit 410 can include additional sub - circuits that can generate a reset of the memory / counter 422.

[0224] For example, as described above, when the circuit is operating under condition C (i.e., k QR ≤k M –n L ), the memory / counter 422 is not reset. Although this behavior is required when the control circuit 410a must avoid transitions between valleys, this verification operation also prevents the reset of the value k M when the off - duration increases and the converter can switch through the first valley, because when k M ≤n L (e.g., when k M = 1), the above operation cannot reset the value k M .

[0225] Thus, in various embodiments, the circuit 410 can include a sub - circuit configured to detect this condition.

[0226] For example, the inventors have observed that such a condition can be detected because the converter is not operating under "optimal" drive conditions, e.g., because:

[0227] when the feedback signal FB is an error signal, this signal may increase; and / or

[0228] the peak value of the signal CS may increase.

[0229] Thus, in various embodiments, the circuit 410 can include a feedback tracking circuit 418 configured to monitor changes in the feedback signal FB.

[0230] For example, Figure 11 shows a possible embodiment of the circuit 416.

[0231] In the considered embodiment, the circuit 416 is configured to sample the feedback signal FB at a constant rate F SH and compare the sampled feedback signal FB S with the current feedback signal FB.

[0232] For this purpose, the circuit 416 can include:

[0233] a trigger generator 4186, implemented, for example, by a counter, configured to generate a trigger signal at a rate of F SH ; and

[0234] A sample and hold circuit 4180, configured to sample the feedback signal FB in response to a trigger signal provided by a trigger generator 4186.

[0235] In the embodiment under consideration, the feedback signal FB and the sampled feedback signal FB S are provided to a comparator 4184. In particular, in the embodiment under consideration, the signals are not directly compared, but an offset V fb_h is added to the sampled feedback value FB S at an adder 4182, i.e., the comparator 4184 generates / sets the signal FB_R when FB > FB S +V fb_h .

[0236] Thus, in the embodiment under consideration, the circuit 418 is configured to periodically store the feedback signal FB and generate a trigger signal FB_R when the feedback signal increases beyond V fb_h .

[0237] In various embodiments, in this case, the sample and hold circuit 4180 may also immediately store the feedback signal FB (as shown via an OR gate 4188) and / or restart the trigger generator 4186.

[0238] Thus, the combinational logic circuit 420 ( Figure 8 ) may also receive the signal FB_R at its input, i.e., reset the memory / counter 422 in response to the signal FB_R.

[0239] Conversely, Figure 12 an embodiment of a circuit 416 configured to monitor the peak of the signal CS is shown.

[0240] In the embodiment under consideration, the circuit 416 is implemented by an auto - reload counter circuit that increments when the signal CS exceeds a given threshold. For example, in the embodiment under consideration, the circuit 416 includes a counter 4166 configured to:

[0241] increment an internal count value in response to a signal OCP provided by a comparator 2114 (see Figure 4 ) as long as this comparator has compared the signal CS with a threshold OTH;

[0242] generate / set a trigger signal OCP_R when the internal count value reaches a given threshold (e.g., 4 or 8); and

[0243] reset the internal count value when the trigger signal OCP_R is set.

[0244] In various embodiments, circuit 4146 may also be associated with an additional reset circuit configured to generate an additional reset signal ROCP for counter 4166, which is used to disable counter 4146 when feedback signal FB is less than a given threshold.

[0245] For example, in the considered embodiment, the reset circuit includes:

[0246] Comparator 4160, configured to determine whether feedback signal FB is greater than threshold V FB_EN (such as 2.5V), preferably a comparator with a given hysteresis V FB_EN_HYST (such as 100mV); and

[0247] Latch 4162 (such as a set-reset latch), configured to set the output Q (providing signal ROCP) of the latch to high when set signal OCP_R is present, and wherein latch 4140 is reset in response to a signal at the output of comparator 4160.

[0248] In the considered embodiment, the reset terminal of counter 4166 may thus receive trigger signal OCP_R and reset signal ROCP, for example, via logic OR gate 4164.

[0249] Thus, when using the signal at output Q of latch 4162 as reset signal ROCP, this signal ROCP will be set to high in response to a first trigger in signal OCP_R and then will remain set to high until signal FB is greater than threshold V FB_EN . Thus, when signal FB is small, signal ROCP will remain high and counter 4166 remains reset, thereby suppressing the generation of further triggers in signal OCP_R.

[0250] Thus, combinational logic circuit 420 ( Figure 8 ) may also receive signal OCP_R at the input, i.e., reset memory / counter 422 in response to signal OCP_R.

[0251] Of course, without prejudice to the principles of the present disclosure, the details of the construction and the embodiments may vary widely with respect to what is only described and illustrated herein by way of example, without departing from the scope of the invention as defined by the following claims.

[0252] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which these claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A control circuit for a flyback converter, the flyback converter comprising: A positive input terminal and a negative input terminal configured to receive an input voltage; A first output terminal and a second output terminal configured to provide an output voltage or an output current; A transformer having a primary winding and a secondary winding, wherein a first terminal of the primary winding is connected to the positive input terminal, and a second terminal of the primary winding represents a switching node; A first electronic switch connected between the switching node and the negative input terminal; And A second electronic switch connected in series with the secondary winding between the two output terminals, Wherein the control circuit is configured to generate a drive signal for the first electronic switch, and wherein the control circuit is configured to: generate a switching period by setting the drive signal to a first logic level for a turn-on duration for closing the first electronic switch and a second logic level for a turn-off duration for opening the first electronic switch, and Wherein the control circuit comprises: A first terminal configured to be connected to a current measurement circuit, and the first terminal is configured to generate a current measurement signal, the current measurement signal indicating the current flowing through the primary winding during the turn-on duration; and A second terminal configured to be connected to a valley monitoring circuit, and the second terminal is configured to provide a valley signal, the valley signal indicating a valley in the voltage at the switching node; A comparison circuit configured to generate a turn-off signal by comparing the current measurement signal with a current measurement threshold signal; A valley detection circuit configured to: generate a trigger in a trigger signal when the valley signal indicates a valley in the voltage at the switching node; and A blanking circuit configured to: generate a turn-on signal by combining the trigger signal with a timer signal provided by a timer circuit, the timer signal indicating whether a blanking time interval has elapsed, Wherein the blanking circuit is configured to: Start the timer circuit in response to the turn-on signal or the turn-off signal; Monitor a first number of triggers in the trigger signal during each switching period, wherein the first number indicates the number of valleys in the voltage at the switching node until the electronic switch is closed; and Monitor a second number of triggers in the trigger signal during each switching period until the timer signal indicates that the blanking time interval has elapsed, wherein the second number indicates the number of valleys in the voltage at the switching node during the blanking time interval.

2. The control circuit according to claim 1, further comprising: A circuit configured to: Set the drive signal to the first logic level for closing the first electronic switch in response to the turn-on signal, and Set the drive signal to the second logic level for opening the first electronic switch in response to the turn-off signal.

3. The control circuit according to claim 1, wherein the blanking circuit is further configured to: Determine whether the timer signal indicates that the blanking time interval has elapsed and whether the first number has reached or exceeded a maximum value; In response to the first number exceeding the maximum value, store the first number as the new maximum value; In response to the timer signal indicating that the blanking time interval has not elapsed or in response to the second number being less than the maximum value, disable the turn-on signal; and In response to the timer signal indicating that the blanking time interval has elapsed and the second number has reached or exceeded the maximum value, set the turn-on signal in response to the trigger signal.

4. The control circuit according to claim 3, wherein the blanking circuit is further configured to: Selectively reset the maximum value by comparing the second number with the first number or the maximum value.

5. The control circuit according to claim 4, wherein the blanking circuit includes a first comparator circuit configured to set a blanking signal by comparing the second number with the first number, and the blanking circuit is further configured to: Determine a first condition in response to the second number being less than the first number minus a first threshold; Determine a second condition in response to the second number being equal to or greater than the first number minus the first threshold but less than the first number minus a second threshold; and Determine a third condition in response to the second number being equal to or greater than the first number minus the second threshold.

6. The control circuit according to claim 5, wherein the blanking circuit includes a reset circuit configured to: Reset the maximum value in response to the first comparator circuit indicating the first condition for consecutive switching cycles of the first number; and Reset the maximum value in response to the first comparator circuit indicating the second condition for consecutive switching cycles of the second number, the consecutive switching cycles of the second number being greater than the consecutive switching cycles of the first number.

7. The control circuit according to claim 6, comprising: A terminal configured to be connected to a feedback circuit and configured to provide a feedback signal indicating the output voltage or output current; And A regulator circuit including an integrating component configured to generate the current measurement threshold signal based on the feedback signal.

8. The control circuit according to claim 7, wherein the reset circuit is configured to: periodically store the value of the feedback signal and reset the maximum value when the feedback signal increases beyond a given amount.

9. The control circuit according to any one of claims 6, wherein the reset circuit is configured to: Determine whether the current measurement signal has reached a maximum threshold signal, and Reset the maximum value in response to the current measurement signal reaching the maximum threshold signal for consecutive switching cycles of a third number.

10. The control circuit according to claim 1, wherein the blanking circuit includes a first digital counter configured to: increment the first number in response to the trigger signal and reset the first number in response to the on signal or the off signal.

11. The control circuit according to claim 10, wherein the blanking circuit includes a second digital counter configured to: increment the second number in response to the trigger signal when the timer signal indicates that the blanking time interval has not elapsed, and reset the second number in response to the on signal or the off signal.

12. The control circuit according to claim 1, wherein the blanking circuit includes: a combinational logic circuit configured to generate the on signal by combining the trigger signal with a blanking signal, and a comparator circuit configured to: set the blanking signal to a first logic level when the timer signal indicates that the blanking time interval has not elapsed or when the second number is less than a given maximum value; and set the blanking signal to a second logic level when the timer signal indicates that the blanking time interval has elapsed and the second number reaches or exceeds the maximum value.

13. The control circuit according to claim 7, wherein the timer circuit is implemented with a digital counter circuit configured to: reset an internal count value in response to the on signal or the off signal; increment the internal count value in response to a clock signal; and set the timer signal to a first logic level when the internal count value is less than a reference value indicating the duration of the blanking time interval and set the timer signal to a second logic level when the internal count value is greater than the reference value, wherein the reference value is determined based on the feedback signal, the current measurement signal, or the current measurement threshold signal.

14. The control circuit according to claim 1, wherein the valley detection circuit includes: a comparator circuit configured to compare the valley signal with a reference signal; and an edge detector configured to generate a pulse in the trigger signal when the signal at the output of the comparator circuit is set.

15. An integrated circuit including the control circuit according to claim 1.

16. A flyback converter, comprising: a positive input terminal and a negative input terminal configured to receive an input voltage; two output terminals configured to provide an output voltage or an output current; a transformer having a primary winding and a secondary winding, wherein a first terminal of the primary winding is connected to the positive input terminal and a second terminal of the primary winding represents a switch node; a first electronic switch connected between the switch node and the negative input terminal; a second electronic switch connected in series with the secondary winding between the two output terminals; A current measurement circuit configured to generate a current measurement signal indicative of a current flowing through the primary winding T1 during an on-duration; A valley monitoring circuit configured to provide a valley signal indicative of a demagnetization of a valley in a voltage at the switching node; And A control circuit configured to generate a drive signal for the first electronic switch, wherein the control circuit is configured to: generate a switching cycle by setting the drive signal to a first logic level for closing the first electronic switch for an on-duration and a second logic level for turning off the first electronic switch for an off-duration, the control circuit comprising: A comparison circuit configured to generate a turn-off signal by comparing the current measurement signal with a current measurement threshold signal; A valley detection circuit configured to: generate a trigger in a trigger signal when the valley signal indicates a valley in the voltage at the switching node; and A blanking circuit configured to: generate an on-signal by combining the trigger signal with a timer signal provided by a timer circuit, the timer signal indicating whether a blanking time interval has elapsed, Wherein the blanking circuit is configured to: Start the timer circuit in response to the on-signal or the turn-off signal; Monitor a first number of triggers in the trigger signal during each switching cycle, wherein the first number indicates the number of valleys in the voltage at the switching node until the electronic switch is closed; and Monitor a second number of triggers in the trigger signal during each switching cycle until the timer signal indicates that the blanking time interval has elapsed, wherein the second number indicates the number of valleys in the voltage at the switching node during the blanking time interval.

17. The flyback converter according to claim 16, wherein the blanking circuit is further configured to: Determine whether the timer signal indicates that the blanking time interval has elapsed and whether the first number has reached or exceeded a maximum value; Store the first number as a new maximum value in response to the first number exceeding the maximum value; Disable the on-signal in response to the timer signal indicating that the blanking time interval has not elapsed or in response to the second number being less than the maximum value; and Set the on-signal in response to the trigger signal in response to the timer signal indicating that the blanking time interval has elapsed and the second number reaching or exceeding the maximum value.

18. The flyback converter according to claim 16, wherein the valley monitoring circuit includes an auxiliary winding of the transformer.

19. A method of operating a flyback converter, the flyback converter comprising: A positive input terminal and a negative input terminal configured to receive an input voltage; A first output terminal and a second output terminal configured to provide an output voltage or an output current; A transformer having a primary winding and a secondary winding, wherein a first terminal of the primary winding is connected to the positive input terminal and a second terminal of the primary winding represents a switching node; A first electronic switch connected between the switching node and the negative input terminal; A second electronic switch connected in series with the secondary winding between the two output terminals; And A control circuit configured to generate a drive signal for the first electronic switch, wherein the control circuit is configured to: generate a switching period by setting the drive signal to a first logic level for an on-duration for closing the first electronic switch and a second logic level for an off-duration for opening the first electronic switch, wherein the control circuit includes: A first terminal configured to be connected to a current measurement circuit and configured to generate a current measurement signal indicative of a current flowing through the primary winding during the on-duration; and A second terminal configured to be connected to a valley monitoring circuit and configured to provide a valley signal indicative of a valley in the voltage at the switching node; A comparison circuit configured to generate an off signal by comparing the current measurement signal with a current measurement threshold signal; A valley detection circuit configured to: generate a trigger in a trigger signal when the valley signal indicates a valley in the voltage at the switching node; and A blanking circuit configured to: generate an on signal by combining the trigger signal with a timer signal provided by a timer circuit, the timer signal indicating whether a blanking time interval has elapsed, The method includes: Starting the timer circuit in response to the on signal or the off signal; Monitoring a first number of triggers in the trigger signal during each switching period, wherein the first number indicates the number of valleys in the voltage at the switching node until the first electronic switch is closed; and Monitoring a second number of triggers in the trigger signal during each switching period until the timer signal indicates that the blanking time interval has elapsed, wherein the second number indicates the number of valleys in the voltage at the switching node during the blanking time interval.

20. The method according to claim 19, further comprising: Determining whether the timer signal indicates that the blanking time interval has elapsed and whether the first number has reached or exceeded a given maximum value, and Storing the first number as a new maximum value in response to the first number exceeding the maximum value; Disabling the on signal in response to the timer signal indicating that the blanking time interval has not elapsed or the second number being less than the maximum value; and Setting the on signal in response to the trigger signal in response to the timer signal indicating that the blanking time interval has elapsed and the second number having reached or exceeded the maximum value; and Selectively resetting the maximum value by comparing the second number with the first number or the maximum value.

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