A convolutional turbo code decoder and decoding method based on MAP algorithm

Abstract

The present invention discloses a convolutional Turbo code decoder and decoding method based on the MAP algorithm, belonging to the field of hardware implementation technology in the field of communications. In view of the problems existing in the prior art, such as the CTC decoder being inconvenient to integrate at high frequencies, being incompatible with different interleaving standards, and poorly supporting the tail bit characteristics of the convolutional Turbo code, the present invention provides a data interleaving unit to interleave / deinterleave the data stream through the configured pattern; the training unit trains the branch metrics in parallel during decoding; and the inference unit infers external information based on the branch metrics. The present invention adopts adaptive parallelism to balance the window size and the length of the block under limited storage conditions, thereby ensuring the performance and accuracy requirements in the communication hardware system; at the same time, an alternating pipeline iteration method is used in the computing unit to reduce computing resource overhead and decoding delay.

Description

Technical Field

[0001] The present invention relates to the technical field of hardware implementation in the field of communications, and more particularly to a convolutional Turbo code decoder and a decoding method based on a MAP algorithm. Background Art

[0002] Turbo codes, also known as Parallel Concatenated Convolutional Codes (PCCC), implement the concept of random coding while constructing long codes from short codes through an interleaver. They also employ soft-output iterative decoding to approximate maximum likelihood decoding. Turbo codes fully exploit the fundamental conditions of Shannon's channel coding theorem, achieving performance close to the Shannon limit.

[0003] The 802.16e protocol introduces a convolutional turbo code (CTC) as an optional channel code. CTC is a parallel dual-binary input turbo code that does not require the trailing bits to reset the encoder state to zero; instead, it ensures that the encoder states are identical at the beginning and end. Compared with traditional turbo codes, CTC offers strong iterative convergence, improved minimum codeword distance characteristics, and higher bit rates.

[0004] The Maximum A Posteriori (MAP) algorithm is an optimal algorithm for estimating Markov processes in the presence of memoryless noise. Since the introduction of Turbo codes in 1993, the MAP algorithm has been widely used. The MAP algorithm not only decodes the bit values of a sequence but also outputs information about the reliability of each bit, which is highly consistent with the iterative decoding characteristics of Turbo codes.

[0005] The MAP algorithm involves numerous multiplications and additions, as well as exponential and logarithmic operations that are difficult to implement in digital circuits, making it unsuitable for practical applications. The Max-Log-MAP algorithm proposed by Koch, Baier, and Erfanian et al. makes certain approximations in its calculations, eliminating exponential and logarithmic operations and significantly simplifying the complexity of the MAP algorithm. It is widely used in Turbo hardware decoders.

[0006] Application-Specific Integrated Circuits (ASICs) are designed and manufactured for the specific needs of specific users and electronic systems. Compared to general-purpose architectures, they offer advantages such as high performance, low cost, and minimal hardware overhead. Reducing hardware power consumption and overhead while ensuring algorithm performance and hardware reliability, while also ensuring good algorithm adaptability, has become a key research topic in the ASIC field.

[0007] The existing convolutional turbo decoding hardware implementation has the following problems in practice:

[0008] 1. The main frequency of existing convolutional turbo decoders is usually not high, resulting in limited throughput and inconvenience in integration into high-frequency SoCs;

[0009] 2. The interleaving method of the existing convolutional turbo decoder is relatively fixed and cannot be compatible with different interleaving standards;

[0010] 3. Most existing Turbo decoders use a sliding window structure, which does not support the tail bit characteristic of convolutional Turbo codes well. Summary of the Invention

[0011] 1. Technical problems to be solved

[0012] To address the problems existing in the prior art, such as the inconvenience of high-frequency integration of CTC decoders, incompatibility with different interleaving standards, and poor support for the tail-bit characteristics of convolutional Turbo codes, the present invention provides a convolutional Turbo code decoder and decoding method based on the MAP algorithm. Taking into account the accuracy, area and power consumption, and iteration cycle of hardware implementation, a high-performance CTC decoder with high main frequency and variable interleaving is designed. A hardware-friendly CTC decoding scheme is proposed and corresponding hardware implementation is performed to improve the performance of the communication system.

[0013] 2. Technical solution

[0014] The purpose of the present invention is achieved through the following technical solutions.

[0015] The present invention proposes a convolutional Turbo code decoder and decoding method based on the MAP algorithm, which can effectively reduce the complexity of decoding, improve the main frequency and throughput of hardware implementation, and thus improve the performance of the entire system.

[0016] A convolutional turbo code decoder based on the MAP algorithm includes a data preprocessing module, a sub-decoder module, and a hard decision module. The data processing module is connected to the sub-decoder module, and the sub-decoder module is also connected to the hard decision module. The data preprocessing module is used to split and pre-interleave input coded data. The sub-decoder module performs training, inference, and data interleaving on the data sent by the data preprocessing module. The hard decision module makes hard decisions on the data after multiple iterative calculations by the sub-decoder module.

[0017] The decoder also includes a core control module and a memory. The core control module is connected to the data preprocessing module, the sub-decoder module and the hard decision module, and is used to schedule computing tasks and connect data streams; the memory is connected to the data preprocessing module, the sub-decoder module and the hard decision module, and is used to store data from each module in the decoder.

[0018] The present invention inputs an interleaved image into a data preprocessing module for controlling interleaving within decoding, and can support non-standard interleavers other than the 802.16e protocol.

[0019] Preferably, the sub-decoder module includes several decoder computing units, each of which includes a training unit, an inference unit and a data interleaving unit. The output end of the training unit is connected to the input end of the inference unit, and the output end of the inference unit is connected to the input end of the training unit through the data interleaving unit. The output end of the inference unit is also the output end of the sub-decoder; the training unit is used to calculate the branch metric value, the inference unit is used to calculate the external information, and the data interleaving unit is used to send the calculated external information to the sub-decoder module again for iterative calculation.

[0020] Preferably, the number of data sub-block channels into which the encoded data is divided in the data preprocessing module is no greater than the number of decoder computing units in the sub-decoder module. The present invention implements block-wise parallel decoding of convolutional Turbo codes. The number of divided data sub-blocks is no greater than the number of decoder computing units in the sub-decoder module. Each decoder computing unit processes in parallel, improving decoder performance. The present invention can employ different degrees of parallelism based on different sub-block lengths N. To ensure decoding performance, the sub-block length N must not be less than 24.

[0021] Preferably, each decoder calculation unit includes four adders, two comparators and two selectors;

[0022] The output end of the first adder, the output end of the second adder, and the output end of the first selector are all connected to a fourth adder, the input signal of the fourth adder also includes a log-likelihood ratio of a check bit of the encoded data, the input signal of the first adder is a log-likelihood ratio of a systematic bit of the encoded data, the input signal of the second adder is a log-likelihood ratio of a priori information of the encoded data, the input signal of the first selector is the output signal of the third adder and an iteration metric value, and the input signal of the third adder is a branch metric signal;

[0023] The output end of the fourth adder is connected to the input end of the second selector, the output end of the second selector is connected to the first comparator and the second comparator, and the output signal of the second comparator is fed back to the iterative metric value input of the first selector after normalization operation.

[0024] Preferably, the selector includes a training mode and an inference mode. When the training unit calculates, the selector is in the training mode, and when the inference unit calculates, the selector is in the inference mode.

[0025] The MAP-based convolutional Turbo decoder hardware implementation of the present invention has a simple structure and is easy to implement. It supports hardware decoding of non-standard convolutional Turbo codes and is highly configurable. It ensures the decoding performance of the decoder while reducing the chip area. It uses a data interleaving unit to improve the parallelism of the decoder and enhance the throughput of the decoder, making it suitable for wide application.

[0026] A convolutional Turbo code decoding method based on the MAP algorithm, using the convolutional Turbo code decoder based on the MAP algorithm, comprises the following steps:

[0027] Step 1: In the data preprocessing module, the decoder is configured with an interleaving pattern through external configuration, the decoder iteration information is set, the input coded information is split into several channel data sub-blocks and pre-interleaved;

[0028] Step 2: The sub-decoder module trains branch metrics based on the input encoding information, infers external information and performs data interleaving. The channel boundary information is bidirectionally exchanged between adjacent decoder calculation units.

[0029] Step 3: Repeat step 2 to perform data iterative calculation. When the number of iterations of the data in the sub-decoder module is equal to the set value, the sub-decoder module sends the soft bit output to the hard decision module to complete the decision.

[0030] The input convolutional Turbo coded information through the channel is split into several channel data sub-blocks and sent to a single soft-input soft-output decoder for decoding. The soft-input soft-output decoder can retain the log-likelihood ratio information of each codeword, which can improve performance during iterative decoding.

[0031] The inter-channel boundary information in the sub-decoder module is bidirectionally exchanged between adjacent decoder calculation units. The exchange method is to assign the last forward branch metric Alpha of the previous channel to the first forward branch metric Alpha of the next channel, and to assign the first backward branch metric Beta of the next channel to the last backward branch metric Beta of the previous channel.

[0032] Alpha i+1，start =Alpha i，end

[0033] Beta i-1，start =Beta i，end

[0034] Where i represents the i-th channel in the sub-decoder module, start represents the first branch metric of the channel, and end represents the last branch metric of the channel.

[0035] Preferably, the sub-decoder module training unit outputs a training branch metric value according to the systematic bits, check bits and soft bits of the input coding information, wherein the branch metric value includes a forward branch metric and a backward branch metric;

[0036] The sub-decoder reasoning unit infers the extrinsic information according to the systematic bits, check bits, soft bit outputs and branch metric values of the input coded information.

[0037] Preferably, the forward branch metric and the backward branch metric are calculated in parallel on the same hardware pipeline. The forward branch metric and the backward branch metric share the first and third stages of the pipeline, and data is fed into the training unit in an interleaved manner, filling the idle time of the pipeline iterative calculation.

[0038] Preferably, the branch metric values output by the sub-decoder module's training unit are normalized, and the extrinsic information output by the sub-decoder module's inference unit is adjusted using an adaptive coefficient. The sub-decoder's training unit uses a fixed-value normalization method for normalization. When a value in a set of branch metrics exceeds a normalization boundary b, the set of branch metrics is normalized, and b is subtracted from all metrics, thereby suppressing the growth of branch metrics in the decoder.

[0039] Preferably, the inference unit of the sub-decoder module uses a shift and lookup table method to calculate extrinsic information. The present invention uses a shift and lookup table method in the inference unit instead of fixed-point multiplication to achieve a higher clock frequency and a smaller area, avoiding the large area overhead caused by multiplier settings in hardware design and reducing the impact on timing.

[0040] The decoding method disclosed in this invention is based on the aforementioned hardware architecture and implements MAP-based convolutional Turbo code decoding in conjunction with this hardware architecture. Adaptive parallelism is employed during the decoding process to balance window size and block length within limited memory, ensuring performance and accuracy requirements within the communication hardware system. Furthermore, an alternating pipeline iteration method is employed within the computational unit, significantly reducing computational resource overhead and decoding latency. The high configurability meets the transmission requirements of communication systems, resulting in excellent performance and high adaptability.

[0041] 3. Beneficial effects

[0042] Compared with the prior art, the advantages of the present invention are:

[0043] This paper discloses a MAP-based convolutional turbo code decoder hardware implementation. The hardware design is highly configurable and supports hardware decoding of non-standard convolutional turbo codes. Compared to existing convolutional turbo code decoder solutions, this approach offers advantages in both area and timing, while also meeting accuracy requirements and improving overall system performance.

[0044] The decoding method of the present invention, based on the hardware structure, effectively increases the chip's main frequency, improves decoder throughput, and reduces hardware overhead and decoding complexity. In the hardware structure, the present invention uses shift and lookup table units to replace multipliers and modulo calculations, splitting the calculation into pipelines, optimizing circuit timing, and increasing the chip's main frequency.

[0045] The present invention uses a data preprocessing module to perform block division and pre-interleaving during sub-decoder calculations. The block-divided data is then fed into the sub-decoder module for parallel calculations, increasing decoding parallelism and, in turn, decoder throughput. Furthermore, an externally configured variable interleaver is used in the hardware. This interleaving pattern is configured externally, achieving internal interleaving variability and lightweight hardware implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Schematic diagram of the hardware module of the MAP-based convolutional Turbo code decoder of the present invention;

[0047] Figure 2 This is a flow chart of the convolutional Turbo code decoding method based on MAP of the present invention;

[0048] Figure 3 This is a schematic diagram of the hardware structure of the sub-decoder module operation pipeline of the present invention;

[0049] Figure 4 It is a structural diagram of the sub-decoder module of the present invention. DETAILED DESCRIPTION

[0050] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] Example 1

[0052] This example discloses a hardware implementation of a convolutional Turbo code decoder based on the MAP algorithm. Figure 1 As shown, the decoder includes a data preprocessing module, a sub-decoder module and a hard decision module. The data preprocessing module preprocesses the input data and sends the preprocessed data to the sub-decoder module. The sub-decoder module trains, infers and interleaves the data sent by the data preprocessing module. After multiple iterations, the data is sent to the hard decision module for hard decision as the structural output of the decoding. The decoder also includes a core control module and a memory. The core control module is connected to the data preprocessing module, the sub-decoder module and the hard decision module to schedule computing tasks and connect data streams. The memory is also connected to the data preprocessing module, the sub-decoder module and the hard decision module to store data from each module in the decoder.

[0053] like Figure 1 As shown, the data preprocessing module is used to process the externally input interleaving pattern and pre-interleave the input codewords according to the interleaving pattern. During the pre-interleaving process, the code blocks are segmented and the sub-code blocks are placed in the source data area of each channel. The data preprocessing module includes several storage units, which are connected to the externally input interleaving pattern, iteration information, and LLR sequences that have undergone convolutional turbo encoding. During data processing, the data preprocessing module transfers data from dynamic memory (DRAM) to static memory (SRAM). Although DRAM has a larger storage space than SRAM, SRAM is faster in storing and reading data. Therefore, this embodiment uses SRAM as the memory to speed up the decoder's operation.

[0054] The sub-decoder module includes several decoder computing units, each of which includes a training unit, an inference unit and a data interleaving unit. Figure 4 The decoder computation unit architecture is shown in Figure 1. The output of the training unit is connected to the input of the inference unit, which is then connected to the input of the training unit via the data interleaving unit. The output of the inference unit is also connected to the input of the hard decision module. The data preprocessing module splits the encoded information into several channel data sub-blocks, which are then fed into the sub-decoder modules in parallel. The sub-decoders decode the information in parallel, improving decoding efficiency.

[0055] The hardware structure of the decoder calculation unit pipeline is as follows Figure 3 As shown, it includes four adders, two comparators and two selectors. The selectors are in training mode when the training unit calculates, and the selectors are in inference mode when the inference unit calculates.

[0056] The output end of the first adder, the output end of the second adder, and the output end of the first selector are all connected to the fourth adder, and the input end of the fourth adder also receives the LLR output of the coded data check bit, wherein the first adder is a systematic bit adder, and the input end of the first adder is connected to the LLR of the systematic bit, the second adder is a priori information adder, and the input end of the second adder is connected to the LLR of the priori information, the first selector is a branch metric selector, and the input end of the first selector is the sum of the forward branch metric Alpha and the backward branch metric Beta (implemented by the third adder), as well as the iteration metric value. The first selector selects the iterative metric value in the training mode and selects the output of the third adder in the inference mode; the output of the fourth adder is connected to the input of the second selector, and the second selector compares the output values of multiple fourth adders and outputs the maximum value; the output of the second selector is respectively connected to the first comparator and the second comparator, the first comparator is an eight-input comparator, and the second comparator is a four-input comparator. The second selector selects the second comparator in the training mode and selects the first comparator in the inference mode. The output of the second comparator is fed back to the iterative metric value input of the first selector through the normalization unit.

[0057] The sub-decoder module training unit controls the sub-decoder corresponding to each channel data sub-block to read the system bit and check bit of the sub-block, recursively calculates the forward branch metric and backward branch metric through the MAP algorithm, and sends the data to the intermediate result memory. The basic calculation formula of the branch metric is:

[0058] A k (s)=max[A k-1 (s′)+Γ k-1 (s′, s)],

[0059] B k-1 (s′)=max[B k (s)+Γ k (s′, s)],

[0060] Among them, A k (s) represents the forward branch metric Alpha, B k (s) represents the backward branch metric Beta, s and s′ represent different states of the CTC code, Γ k (s′, s) represents the metric value of transitioning from state s to state s′, k represents different moments, and when calculating the branch metric, the eight states s defined in the CTC code are traversed and the metric value Γ from the current codeword state s′ to the four possible states s of the next codeword is calculated. k (s′, s), and then add it to the current metric and select the maximum value.

[0061] After each branch metric calculation, the training unit performs normalization. That is, after comparing all branch metrics with the normalization boundary b, if there is a branch metric greater than b, the branch metric boundary b is subtracted from all branch metrics. In this embodiment, the branch metric boundary b is set to 8.

[0062] After the forward branch metric and the backward branch metric are calculated, the inference unit of the sub-decoder module uses the forward branch metric and the backward branch metric to jointly infer the soft bit output information L all , according to L all Calculate external information L e , external information L e After passing through the data interleaving unit, the next sub-decoder input is formed, and the data calculated by the inference unit is also sent to the intermediate result memory.

[0063] Infer the soft bit output information L based on the forward branch metric Alpha and the backward branch metric Beta all , soft bit output L all The calculation formula is:

[0064] L all =max(A k-1 (s′)+Γ k (s′, s)+B k-1 (s)),

[0065] According to L all Calculate external information L e , the external information L e Multiply by an adaptive coefficient to correct the unreliability of external information caused by the approximate operation of the Max-Log-MAP algorithm. The formula is:

[0066] L all =factor*L e

[0067] The adaptive coefficient is reduced or increased according to decoding requirements. In this embodiment, the adaptive coefficient is 0.75.

[0068] After the sub-decoder completes the decoding, the data interleaving unit changes the interleaved or deinterleaved data and outputs the information L according to the soft bit. all The calculated external information L e It is sent to the sub-decoder for decoding again to form the next sub-decoder input L a .

[0069] The core control module controls the sending of the demodulated coded codeword to the decoder, and controls the access of the intermediate result data and the iteration of the decoding. a Send it to the hard decision module to complete the final decoding calculation, L aIndicates the possibility of the code word being 0 or 1. When L a A positive number indicates that the code word is 0. When L a A negative number indicates the codeword is 1.

[0070] The hard decision module is used to make a hard decision on the soft bit output of the sub-decoder module after the sub-decoder module iteration is completed. iter When the hard decision unit outputs the soft bit information L all Direct decision. To conserve hardware resources and reduce chip size, the sub-decoder includes two modes: primary and secondary. These modes alternate during each iterative decoding process. Generally, each mode functions as the primary decoder at the beginning of a decoding round. To save interleaving time, the hard decision module makes a decision on the output while the sub-decoder is functioning as the primary decoder. The decoding process ends when the decision is complete.

[0071] Example 2

[0072] This embodiment is based on the decoder hardware implementation method disclosed in Example 1, and describes the decoding process of the decoder in detail. Figure 2 As shown, the convolutional Turbo code decoding method based on the MAP algorithm includes the following steps:

[0073] Step 1: Set the interleaving pattern and iteration information of the decoder, and input the encoded codeword bit information into the data pre-processing module for data pre-interleaving processing.

[0074] At the start of decoding, the interleaving pattern is configured from an external DRAM and stored in the decoder's interleaving pattern storage area. The input codeword sub-blocks are then divided into multiple channels for pre-interleaving. The channel-passed convolutional turbo codes are then fed into the data preprocessing module in the codeword order specified in the protocol.

[0075] The data preprocessing module calculates the address index required for interleaving according to the method specified by the protocol, and maps the addresses one by one to enable the interleaving pattern to complete data preprocessing and sub-block segmentation. The data preprocessing module sends the preprocessed data to the sub-decoder module. Each decoder in the sub-decoder module processes the sub-block data of the encoded codeword in parallel, improving the parallelism of decoding and thereby improving the decoder throughput.

[0076] Step 2: The sub-decoder module performs training, inference, and data interleaving on the data output by the data preprocessing module.

[0077] The sub-decoder module includes several decoder computation units, each of which comprises a training unit, an inference unit, and a data interleaving unit. The training unit trains branch metrics based on the encoded data, and the inference unit infers external information based on the training unit's data. The core control module controls the iteration of training and inference for each channel data sub-block in the sub-decoder module's corresponding decoder computation unit, extracts data from the decoder system's storage module, sends it to the corresponding channel, and exchanges intermediate results between channels.

[0078] like Figure 3 and Figure 4 As shown, the sub-decoder module training unit receives the read system bit X s , check digit X p and prior information L a Sequence, the pipeline alternately calculates the forward branch metric Alpha and the backward branch metric Beta, such as Figure 3 As shown, the input values of A and B are system bit X s The log-likelihood ratio of the two codewords in the codeword, where the input value Y is the check bit X p The log-likelihood ratio of L1 and L2 is the prior information X of the two codewords. p When the branch metric mode control signal value in the hardware is 1, the branch metric output in this cycle is the forward branch metric Alpha; when the branch metric mode control signal value is 2, the branch metric output in this cycle is the backward branch metric Beta.

[0079] The sub-decoder module reasoning unit receives the system bit X sent by the sub-decoder module training unit s , check digit X p , prior information L a And the branch metric Alpha / Beta sequence, the soft bit output L is calculated through the hardware pipeline hardware structure all Soft bit output L all After calculation, it is converted into external information L e , external information L e After being interleaved and corrected by the data interleaving unit of the sub-decoder module, it is sent to the next-level sub-decoder as the prior information L a .

[0080] The boundary information between sub-decoder channels is exchanged bidirectionally between adjacent sub-decoders. The exchange method is to assign the last forward branch metric Alpha of the previous channel to the first forward branch metric Alpha of the next channel, and to assign the first backward branch metric Beta of the next channel to the last backward branch metric Beta of the previous channel.

[0081] Alpha i+1，start =Alphai，end

[0082] Beta i-1，start =Beta i，end

[0083] Where i represents the i-th channel of the sub-decoder module, start represents the first branch metric of the channel, and end represents the last branch metric of the channel.

[0084] After the sub-decoder of the sub-decoder module completes a calculation, the core control module controls the sub-decoder to switch between the first decoder and the second decoder. The process of the sub-decoder changing from the first decoder to the second decoder and then back to the first decoder is defined as one decoding iteration.

[0085] Step 3: When the number of iterations of the data in the sub-decoder module is equal to the set value, the sub-decoder module sends the data to the hard decision module for decision.

[0086] Set the number of iterations N according to data processing requirements iter The core control module controls the number of iterations of the sub-decoder module through the iteration counter. The count value of the iteration counter is equal to the set number of iterations N. iter When the count value of the iteration counter is equal to the set number of iterations N, the sub-decoder performs iterative calculation. iter When the two are equal, the decoder sends the soft bit output of the first decoder to the hard decision module for decision and completes the decoding. When the hard decision module makes a decision, the internal information log-likelihood ratio L output by the sub-decoder module is a Indicates the possibility that the codeword is 0 or 1. When the log-likelihood ratio L a When it is a positive number, it means the codeword is 0. When the log-likelihood ratio L a When it is a negative number, it represents the codeword is 1.

[0087] In this embodiment, the encoded code blocks are divided into multiple channels for parallel decoding by the decoder computing units of the sub-decoder module. Combined with the configurable interleaving pattern input externally, the hardware implementation of the convolutional turbo decoder can be used in various communication scenarios that comply with the 802.16e standard. It can be implemented in the form of a dedicated integrated circuit or a field programmable gate array.

[0088] The above schematically describes the invention and its implementation methods. This description is not restrictive. Without departing from the spirit or basic features of the invention, the invention can be implemented in other specific forms. What is shown in the accompanying drawings is only one of the implementation methods of the invention. The actual structure is not limited to this. Any figure mark in the claims should not limit the claims involved. Therefore, if a person of ordinary skill in the art is inspired by it and designs a structural method and embodiment similar to the technical solution without creativity without departing from the purpose of the invention, they should all fall within the scope of protection of this patent. In addition, the word "including" does not exclude other elements or steps, and the word "one" before an element does not exclude the inclusion of "multiple" elements. The multiple elements stated in the product claim can also be implemented by one element through software or hardware. Words such as first and second are used to indicate names and do not indicate any specific order.

Claims

1. A convolutional turbo code decoder based on the MAP algorithm, characterized in that: It includes a data preprocessing module, a sub-decoder module and a hard decision module. The data processing module is connected to the sub-decoder module, and the sub-decoder module is also connected to the hard decision module. The data preprocessing module is used to split and pre-interleave the input coded data. The sub-decoder module performs training, inference and data interleaving on the data sent by the data preprocessing module. The hard decision module makes hard decisions on the data after multiple iterative calculations of the sub-decoder module. The decoder also includes a core control module and a memory. The core control module is connected to the data preprocessing module, the sub-decoder module, and the hard decision module, and is used to schedule computing tasks and connect data streams. The memory is connected to the data preprocessing module, the sub-decoder module, and the hard decision module, and is used to store data from each module in the decoder. The sub-decoder module includes a plurality of decoder computing units, each of which includes a training unit, an inference unit, and a data interleaving unit. The output of the training unit is connected to the input of the inference unit, and the output of the inference unit is connected to the input of the training unit through the data interleaving unit. The output of the inference unit is also the output of the sub-decoder. The training unit is used to calculate branch metrics, the inference unit is used to calculate extrinsic information, and the data interleaving unit is used to feed the calculated extrinsic information back into the sub-decoder module for iterative calculation. The number of data sub-block channels into which the encoded data is divided in the data preprocessing module is no greater than the number of decoder calculation units in the sub-decoder module. Each decoder calculation unit includes four adders, two comparators, and two selectors. The output end of the first adder, the output end of the second adder, and the output end of the first selector are all connected to a fourth adder, the input signal of the fourth adder also includes a log-likelihood ratio of a check bit of the encoded data, the input signal of the first adder is a log-likelihood ratio of a systematic bit of the encoded data, the input signal of the second adder is a log-likelihood ratio of a priori information of the encoded data, the input signal of the first selector is the output signal of the third adder and an iteration metric value, and the input signal of the third adder is a branch metric signal; The output end of the fourth adder is connected to the input end of the second selector, the output end of the second selector is connected to the first comparator and the second comparator, and the output signal of the second comparator is fed back to the iterative metric value input of the first selector after normalization operation.

2. The convolutional turbo code decoder based on the MAP algorithm according to claim 1, characterized in that: The selector includes a training mode and an inference mode. When the training unit is calculating, the selector is in the training mode, and when the inference unit is calculating, the selector is in the inference mode.

3. A convolutional Turbo code decoding method based on the MAP algorithm, characterized in that: Using a convolutional turbo code decoder based on the MAP algorithm as claimed in claim 1 or 2, comprising the following steps: Step 1: In the data preprocessing module, the decoder is configured with an interleaving pattern through external configuration, the decoder iteration information is set, the input coded information is split into several channel data sub-blocks and pre-interleaved; Step 2: The sub-decoder module trains branch metrics based on the input encoding information, infers external information and performs data interleaving. The channel boundary information is bidirectionally exchanged between adjacent decoder calculation units. Step 3: Repeat step 2 to perform data iterative calculation. When the number of iterations of the data in the sub-decoder module is equal to the set value, the sub-decoder module sends the soft bit output to the hard decision module to complete the decision.

4. The convolutional Turbo code decoding method based on the MAP algorithm according to claim 3, characterized in that: The sub-decoder module training unit outputs a training branch metric value according to the systematic bit, check bit and soft bit of the input coding information, wherein the branch metric value includes a forward branch metric and a backward branch metric; The sub-decoder reasoning unit infers the extrinsic information according to the systematic bits, check bits, soft bit outputs and branch metric values of the input coded information.

5. The convolutional Turbo code decoding method based on the MAP algorithm according to claim 4, characterized in that: The forward branch metric and the backward branch metric are computed in parallel on the same hardware pipeline.

6. The convolutional Turbo code decoding method based on the MAP algorithm according to claim 4, characterized in that: The branch metric values output by the training unit of the sub-decoder module are normalized, and the extrinsic information output by the inference unit of the sub-decoder module is adjusted using an adaptive coefficient.

7. The convolutional Turbo code decoding method based on the MAP algorithm according to claim 4, characterized in that: The inference unit of the sub-decoder module calculates the extrinsic information using a shift and lookup table method.

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