Product-sum operator, logic operation device, neuromorphic device and product-sum operation method

Abstract

The present invention provides a product-sum operator, which comprises: a plurality of product operation units, which multiply input signals corresponding to input values ​​by weights to generate output signals and output the output signals; a current detection unit, which detects currents output by a plurality of product operation units with a predetermined time delay from the input signal from the time when a first transient response caused by charging of a parasitic capacitor to the product operation unit according to the input of the input signal converges and becomes a constant state to the time before a second transient response caused by discharging of a parasitic capacitor from the product operation unit according to the input of the input signal is generated, and then performs current detection processing for detecting currents output by a plurality of product operation units at a certain time interval; and an operation unit, which operates a value associated with the sum of the output signals based on the current detected by the current detection unit at each certain time interval.

Description

Technical Field

[0001] The invention relates to a product-sum operator, a logic operation device, a neuromorphic device and a product-sum operation method. Background Art

[0002] In existing neural networks, weights are accumulated in input signals, and the sum of all of them is input to the activation function to obtain the output. Here, an attempt is made to realize the product-sum operation in an analog circuit by combining two or more memristors whose resistance changes continuously and reading the sum of the current values ​​output from them.

[0003] In the learning process of the neural network, the resistance value is changed in such a way that the memristor assigned to each synapse becomes a predetermined weight, and the value can be maintained even if the power is cut off. In the inference process, pulse width modulation (PWM) is used, which uses the value of the memristor that holds the information to change the length of the voltage pulse according to the level of the input data.

[0004] For example, Patent Document 1 discloses a product-sum operation device that stores information written from a data line and a bit line to a variable resistance element as an amount of charge in a capacitor.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent No. 5160304 Summary of the invention

[0008] Problems to be solved by the invention

[0009] The memristor has a circuit structure in which parasitic capacitance and parasitic resistance are connected in parallel as an equivalent circuit. Therefore, when an input signal as a voltage pulse is input to the memristor, a transient response caused by charging the parasitic capacitance and a transient response caused by discharging from the parasitic capacitance are generated. Therefore, in the product-sum operation device, in addition to the stable state charge that does not generate these transient responses, the charge of these transient responses is stored in the capacitor, so that the capacitor is sometimes saturated and the product-sum operation cannot be performed.

[0010] Therefore, an object of the present invention is to provide a product-sum operator, a logic operation device, a neuromorphic device, and a product-sum operation method that can avoid the situation where the product-sum operation cannot be performed due to the saturation of the capacitor.

[0011] Technical solutions to solve problems

[0012] One aspect of the present invention provides a product-sum operator, which comprises: a plurality of product operation units, which multiply input signals corresponding to input values ​​by weights to generate output signals and output the output signals; a current detection unit, which detects currents output by a plurality of product operation units with a predetermined time delay from the input signal from the time when a first transient response caused by charging of a parasitic capacitor to the product operation unit according to the input signal converges and becomes a constant state to the time before a second transient response caused by discharging of a parasitic capacitor from the product operation unit according to the input signal is generated, and then performs a current detection process for detecting currents output by a plurality of product operation units at a certain time interval; and a calculation unit, which calculates a value associated with the sum of the output signals based on the current detected by the current detection unit at each certain time interval.

[0013] According to one aspect of the present invention, each of the plurality of product operation sections includes a magnetoresistance effect element that exhibits a magnetoresistance effect.

[0014] In one aspect of the present invention, the sum calculation unit calculates a product of a total current, which is a total of currents detected by the current detection unit at each fixed time interval, and a coefficient time as a value associated with the sum of the output signals.

[0015] In addition, based on one aspect of the present invention, the coefficient time is the shortest length that the input signal can obtain, the input signal has a length that is an integer multiple of the coefficient time, and is simultaneously input to multiple product operation units, and the current detection unit performs the current detection processing with a period equal to the coefficient time.

[0016] In one aspect of the present invention, the current detection unit ends the current detection process when a time equal to a longest length that the input signal can obtain has elapsed since the current detection process was initially executed.

[0017] In addition, according to one aspect of the present invention, the current detection unit ends the current detection process when the current detected by the current detection process is equal to the current when the input signal is not input to the plurality of product calculation units.

[0018] In addition, one aspect of the present invention provides a logic operation device including any one of the above-mentioned product-sum operators.

[0019] In addition, one aspect of the present invention provides a neuromorphic device comprising any one of the above-mentioned product-sum operators.

[0020] In addition, one aspect of the present invention provides a product-sum operation method, which is performed by any one of the above-mentioned product-sum operators, wherein the method includes: a product operation step, by using multiple product operation units, multiplying an input signal corresponding to an input value by a weight, generating an output signal, and outputting the output signal; a current detection step, from the time when a first transient response caused by charging of a parasitic capacitor to the product operation unit according to the input of the input signal converges and becomes a constant state to the time before a second transient response caused by discharging of a parasitic capacitor from the product operation unit according to the input of the input signal is generated, detecting the current output by multiple product operation units with a specified time delay from the input signal, and then performing current detection processing for detecting the current output by multiple product operation units at a certain time interval; and a sum operation step, based on the current detected at each certain time interval in the current detection step, calculating a value associated with the sum of the output signals.

[0021] Effects of the Invention

[0022] According to the described product-sum operator, logic operation device, neuromorphic device and product-sum operation method, it is possible to provide a product-sum operator, logic operation device, neuromorphic device and product-sum operation method that can avoid the situation where the product-sum operation cannot be performed due to the saturation of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a diagram showing an example of a structure of a part of a product-sum operator according to an embodiment.

[0024] Figure 2 A diagram showing an example of a variable resistance element according to an embodiment.

[0025] Figure 3 It is a diagram showing an example of an equivalent circuit of a part of the structure of the product-sum operator according to the embodiment.

[0026] Figure 4 It is a diagram showing an example of an input signal input to the product calculation unit of the embodiment.

[0027] Figure 5 It is a diagram showing an example of an output signal output from the product calculation unit of the embodiment.

[0028] Figure 6 This is a diagram showing an example of the current input to the current detection unit according to the embodiment.

[0029] Figure 7 This is a diagram for explaining the timing at which the current detection unit according to the embodiment executes the current detection process.

[0030] Figure 8This is a diagram for explaining an example of a neural network operation performed by a product-sum operator according to an embodiment. DETAILED DESCRIPTION

[0031] Reference Figure 1 and Figure 2 , an example of the structure of the product-sum operator of the implementation method is described.

[0032] Figure 1 FIG. 1 is a diagram showing an example of a partial structure of a product-sum operator according to an embodiment of the present invention. Figure 1 As shown, the product-sum operator 1 includes product operation units 111, 121, 211, 221, 311, 321, ..., k11, k21, input units 101E, 201E, 301E, ..., k01E, current detection units 10D, 20D, and sum operation units 10S, 20S.

[0033] Figure 2 is a diagram showing an example of a resistance variable element according to an embodiment. The product calculation unit 111 is a resistance variable element, for example Figure 2 The magnetoresistance effect element shown in FIG. Figure 1 and Figure 2 As shown, the product calculation unit 111 includes a variable resistor 111R, a read terminal 111X, a common terminal 111Y, and a write terminal 111Z. Figure 1 The multiplication units 121, 211, 221, 311, 321, ..., k11, k21 shown in the figure are resistance change elements, for example, Figure 2 The magnetoresistance effect elements similar to the elements shown in the figure respectively include: variable resistors 121R, 211R, 221R, 311R, 321R, ..., k11R, k21R, read terminals 121X, 211X, 221X, 311X, 321X, ..., k11X, k21X, common terminals 121Y, 211Y, 221Y, 311Y, 321Y, ..., k11Y, k21Y, write terminals 121Z, 211Z, 221Z, 311Z, 321Z, ..., k11Z, k21Z. In the following description, the product operation unit 111 is described by way of example, but the same applies to the other product operation units 121, 211, 221, 311, 321, ..., k11, k21.

[0034] Here, the variable resistor 111R provided in the product calculation unit 111 is, for example, Figure 2 As shown, it has: a magnetization fixed layer 1111, a non-magnetic layer 1112, a first region 1113, a magnetic domain wall 1114, a second region 1115, a first magnetization supply layer 1116, and a second magnetization supply layer 1117. Figure 2 In the description, use Figure 2The x-axis, y-axis, and z-axis are shown. The x-axis, y-axis, and z-axis form a three-dimensional rectangular coordinate system of a right-hand system. The magnetization fixed layer 1111, the nonmagnetic layer 1112, the first region 1113, the second region 1115, the first magnetization supply layer 1116, and the second magnetization supply layer 1117 are formed in a rectangular parallelepiped shape that is thin in the z-axis direction, and the surface with the largest area is parallel to the xy plane and is electrically and magnetically connected to the first region 1113 and the second region 1115. The magnetization fixed layer 1111, the nonmagnetic layer 1112, the first region 1113 and the second region 1115, the first magnetization supply layer 1116, and the second magnetization supply layer 1117 are stacked in order from the +z direction to the -z direction, but the stacking direction may be opposite. When the stacking directions are opposite, the read terminal 111X is set on the -z direction side, and the common terminal 111Y and the write terminal 111Z are set on the +z direction side.

[0035] The magnetization fixed layer 1111 is fixed in the magnetization direction of the +z direction or the -z direction. Here, the fixed magnetization means that the magnetization direction does not change during the initialization for introducing the magnetic domain wall 1114 and before and after writing using a write current. In addition, the magnetization fixed layer 1111 may be, for example, an in-plane magnetization film having in-plane magnetic anisotropy or a perpendicular magnetization film having perpendicular magnetic anisotropy.

[0036] In the non-magnetic layer 1112, the surface facing the +z direction is in contact with the surface facing the -z direction in the magnetization fixed layer 1111, and the surface facing the -z direction is in contact with the first region 1113 and the second region 1115. Figure 2 As shown in FIG. 1 , the surface of the magnetization fixed layer 1111 facing the −z direction and the surface of the non-magnetic layer 1112 facing the +z direction have the same shape and area. Figure 2 The illustrated embodiment is expanded to more widely cover the surface of the first region 1113 facing the +z direction and the surface of the second region 1115 facing the +z direction. The nonmagnetic layer 1112 is used by the product operation unit 111 to read the change in the magnetization state of the magnetization free layer with respect to the magnetization fixed layer 1111 as a change in resistance value.

[0037] The first region 1113, the magnetic domain wall 1114 and the second region 1115 form a magnetization free layer. The magnetization free layer is made of ferromagnetic material. The magnetization direction of the first region 1113 and the magnetization direction of the second region 1115 are opposite to each other in a direction parallel to the z-axis. The magnetic domain wall 1114 is sandwiched by the first region 1113 and the second region 1115 in a direction parallel to the y-axis.

[0038] The first magnetization supply layer 1116 is expected not to overlap with the magnetization fixed layer 1111 in the direction parallel to the z-axis, and the surface facing the +z direction is in contact with the surface of the first region 1113 facing the -z direction. In addition, the first magnetization supply layer 1116 has a function of fixing the magnetization direction of the range overlapping with the first magnetization supply layer 1116 in the direction parallel to the z-axis in the first region 1113 to a desired direction. Furthermore, a write terminal 111Z is connected to the surface of the first magnetization supply layer 1116 facing the -z direction. In addition, the first magnetization supply layer 1116 is composed of, for example, the same material as the ferromagnetic material that can be used in the magnetization fixed layer 1111, a material having a synthetic antiferromagnetic structure (Synthecic antiferromagnetic) including an antiferromagnetic material such as IrMn, a ferromagnetic material such as Ru, Ir, etc. sandwiched by a non-magnetic intermediate layer, and a non-magnetic material and a ferromagnetic material.

[0039] It is desirable that the second magnetization supply layer 1117 does not overlap with the magnetization fixed layer 1111 in the direction parallel to the z-axis, and the surface facing the +z direction is in contact with the surface of the second region 1115 facing the -z direction. In addition, the second magnetization supply layer 1117 has a function of fixing the magnetization direction of the range overlapping with the second magnetization supply layer 1117 in the direction parallel to the z-axis in the second region 1115 to a desired direction. Furthermore, a common terminal 111Y is connected to the surface of the second magnetization supply layer 1117 facing the -z direction. In addition, the first magnetization supply layer 1116 is composed of, for example, the same material as the ferromagnetic material that can be used in the magnetization fixed layer 1111, a material having a synthetic antiferromagnetic structure (Synthecic antiferromagnetic) including an antiferromagnetic material such as IrMn, a ferromagnetic material such as Ru, Ir, etc. sandwiched by a non-magnetic intermediate layer, and a non-magnetic material and a ferromagnetic material.

[0040] In the variable resistor 111R, the magnetization directions of the magnetization fixed layer 1111, the first region 1113, the second region 1115, the first magnetization supply layer 1116, and the second magnetization supply layer 1117 are not only parallel to the z-axis, but also parallel to the x-axis or the y-axis. In this case, it is desirable that the magnetization direction of the magnetization fixed layer 1111 and the magnetization directions of the first region 1113, the second region 1115, the first magnetization supply layer 1116, and the second magnetization supply layer 1117 are parallel. For example, when the magnetization direction of the magnetization fixed layer 1111 is the +y direction, the magnetization direction of the first region is the +y direction, the magnetization direction of the second region is the -y direction, the magnetization direction of the first magnetization supply layer 1116 is the +y direction, and the magnetization direction of the second magnetization supply layer 1117 is the -y direction.

[0041] The multiplication unit 111 changes the position of the magnetic domain wall 1114 in the direction parallel to the y-axis by adjusting the magnitude and time of the write current flowing between the common terminal 111Y and the write terminal 111Z. Thus, the multiplication unit 111 can continuously change the ratio of the area of ​​the region where the magnetization direction is parallel to the area where the magnetization direction is antiparallel, and change the resistance value of the variable resistor 111R approximately linearly. Here, the region where the magnetization direction is parallel is the area of ​​the portion overlapping the magnetization fixed layer 1111 in the direction parallel to the z-axis in the first region 1113. In addition, the region where the magnetization direction is antiparallel is the area of ​​the portion overlapping the magnetization fixed layer 1111 in the direction parallel to the z-axis in the second region 1115. In addition, the write current is input to the write terminal 111Z. The magnitude and time of the write current are adjusted based on at least one of the number and time of the current pulses.

[0042] In addition, the product operation units 111, 121, 211, 221, 311, 321, ..., k11, k21 may also be tunnel magnetoresistance elements. The tunnel magnetoresistance element comprises: a magnetization fixed layer, a magnetization free layer, and a tunnel barrier layer as a non-magnetic layer. The magnetization fixed layer and the magnetization free layer are made of ferromagnetic materials and have magnetization. The tunnel barrier layer is sandwiched between the magnetization fixed layer and the magnetization free layer. The tunnel magnetoresistance element can change the resistance value by changing the relationship between the magnetization of the magnetization fixed layer and the magnetization of the magnetization free layer.

[0043] return Figure 1 , the input unit 101E is connected to the readout terminals 111X and 121X. Figure 1 The input section 201E is connected to the readout terminals 211X and 221X shown in the figure, the input section 301E is connected to the readout terminals 311X and 321X, and the input section k01E is connected to the readout terminals k11X and k21X.

[0044] The input unit 101E inputs an input signal corresponding to the input value to the readout terminals 111X and 121X. Similarly, the input unit 201E inputs an input signal corresponding to the input value to the readout terminals 211X and 221X. The input unit 301E inputs an input signal corresponding to the input value to the readout terminals 311X and 321X. The input unit k01E inputs an input signal corresponding to the input value to the readout terminals k11X and k21X. These input signals are all voltage signals that implement pulse width modulation (PWM) corresponding to the input value.

[0045] The multiplication unit 111 multiplies the input signal corresponding to the input value by the weight, generates an output signal, and outputs the output signal. That is, the multiplication unit 111 reads the resistance value of the variable resistor 111R as the weight, performs a multiplication operation with respect to the input signal input to the read terminal 111X, generates an output signal, and outputs the output signal from the common terminal 111Y. Similarly, the multiplication units 121, 211, 221, 311, 321, ..., k11, k21 respectively multiply the input signal corresponding to the input value by the weight, generates an output signal, and outputs the output signal.

[0046] The current detection unit 10D detects the current output from the plurality of multiplication units with a predetermined time delay from the input signal between the time when the first transient response converges and becomes a stable state and before the second transient response caused by the discharge of the parasitic capacitance from the multiplication unit according to the input signal is generated, and then performs a current detection process of detecting the current output from the multiplication units 111, 211, 311, ..., k11 at a certain interval. Similarly, the current detection unit 20D detects the current output from the plurality of multiplication units with a predetermined time delay from the input signal between the time when the first transient response converges and becomes a stable state and before the second transient response caused by the discharge of the parasitic capacitance from the multiplication unit according to the input signal is generated, and then performs a current detection process of detecting the current output from the multiplication units 121, 221, 321, ..., k21 at a certain interval. The details of the current detection units 10D and 20D will be described later.

[0047] The sum operation unit 10S calculates a value associated with the sum of the output signals based on the current detected by the current detection unit 10D at regular time intervals. Similarly, the sum operation unit 20S calculates a value associated with the sum of the output signals based on the current detected by the current detection unit 20D at regular time intervals. The sum operation units 10S and 20S will be described in detail later.

[0048] Next, refer to Figure 3 to Figure 6 , an example of the processing performed by the product-sum operator of the implementation method is described.

[0049] Figure 3 FIG. 1 is a diagram showing an example of an equivalent circuit of a part of the structure of the product-sum operator according to the embodiment. Figure 3As shown, the multiplication unit 111 includes a parasitic capacitor 111C and a parasitic resistor 111P as an equivalent circuit of a magnetoresistive element, and it is considered that the parasitic capacitor 111C is connected in parallel with the variable resistor 111R, and the parasitic resistor 111P is connected in series with the variable resistor 111R. Similarly, the multiplication units 121, 211, 221, 311, 321, ..., k11, k21 include parasitic capacitors 121C, 211C, 221C, 311C, 321C, ..., k11C, k21C and parasitic resistors 121P, 211P, 221P, 311P, 321P, ..., k11P, k21P, respectively. Furthermore, it can be considered that wiring resistances 111W, 121W, 211W, 221W, 311W, 321W, ..., k11W, k21W are respectively connected in series to the product operation parts 111, 121, 211, 221, 311, 321, ..., k11, k21.

[0050] Figure 4 101E is a diagram showing an example of an input signal input to the product operation unit of the embodiment. The input unit 101E outputs, for example, Figure 4 (a) shows the input signal V1. Similarly, the input unit 201E outputs, for example, Figure 4 (b) shows the input signal V2. In addition, the input unit 301E outputs, for example, Figure 4 (c) shows the input signal V3.

[0051] Input signal V1 is a voltage pulse with a pulse height of 0.1 mV and a coefficient time, for example, 20 [ns]. This 20 [ns] is an example of the shortest length that the input signal can obtain. Input signal V2 is a voltage pulse with a pulse height of 0.1 mV and a length of 40 [ns], which is twice the coefficient time. Input signal V3 is a voltage pulse with a pulse height of 0.1 mV and a length of 80 [ns], which is four times the coefficient time. In addition, as Figure 4 As shown, the time when the input signal V1 is input to the multiplication unit 111, the time when the input signal V2 is input to the multiplication unit 211, and the time when the input signal V3 is input to the multiplication unit 311 are all time t0. That is, the input signal V1, the input signal V2, and the input signal V3 are input to the multiplication units 111, 211, and 321 at the same time, respectively.

[0052] Figure 5 FIG. 1 is a diagram showing an example of an output signal output from a product operation unit of the embodiment. Figure 4 When the input signal V1 shown in (a) is input to the product operation unit 111, Figure 5 The output signal A1 shown in (a) is input to the current detection unit 10D. Figure 4 When the input signal V2 shown in (b) is input to the product operation unit 211, Figure 5The output signal A2 shown in (b) is input to the current detection unit 10D. Figure 4 When the input signal V3 shown in (c) is input to the product operation unit 311, Figure 5 The output signal A3 shown in (c) is input to the current detection unit 10D. In the following description, an example is given in which the difference in capacitance between the parasitic capacitors 111C, 211C, and 311C can be almost ignored.

[0053] Figure 5 The output signal A1 shown in (a) is a current signal including a first transient response T11, a constant portion S1, and a second transient response T12. The first transient response T11 is a transient response caused by charging the parasitic capacitance 111C of the product operation unit 111 according to the input signal V1. The constant portion S1 is a portion of the output signal A1 where a constant current C [nA] flows between the time when the generation of the first transient response T11 ends and the time when the generation of the next second transient response T12 begins. The second transient response T12 is a transient response caused by discharging from the parasitic capacitance 111C of the product operation unit 111 according to the input signal V1. The length of the first transient response T11 and the length of the second transient response T12 are so short that they can be almost ignored compared to the length of the constant portion S1. In addition, the length of the output signal A1 is equal to the sum of 20 [ns], which is the length of the input signal V1, and the time of the transient response caused by discharging from the parasitic capacitance 111C.

[0054] Figure 5 The output signal A2 shown in (b) is a current signal including a first transient response T21, a constant portion S2, and a second transient response T22. The first transient response T21 is a transient response caused by charging the parasitic capacitance 211C of the product operation unit 211 according to the input signal V1. The constant portion S2 is a portion of the output signal A2 where a constant current [nA] flows between the moment when the generation of the first transient response T21 ends and the moment when the generation of the next second transient response T22 begins. The second transient response T22 is a transient response caused by discharging from the parasitic capacitance 211C of the product operation unit 211 according to the input signal V2. The length of the first transient response T21 and the length of the second transient response T22 are so short that they can be almost ignored compared to the length of the constant portion S2. In addition, the length of the output signal A2 is equal to the sum of 40 [ns], which is the length of the input signal V2, and the time of the transient response caused by discharging from the parasitic capacitance 211C.

[0055] Figure 5The output signal A3 shown in (c) is a current signal including a first transient response T31, a constant portion S3, and a second transient response T32. The first transient response T31 is a transient response caused by charging the parasitic capacitance 311C of the product operation unit 311 according to the input signal V3. The constant portion S3 is a portion of the output signal A3 where a constant current C [nA] flows between the moment when the generation of the first transient response T31 ends and the moment when the generation of the next second transient response T32 begins. The second transient response T32 is a transient response caused by discharging from the parasitic capacitance 311C of the product operation unit 311 according to the input signal V3. The length of the first transient response T31 and the length of the second transient response T32 are so short as to be almost negligible compared to the length of the constant portion S3. In addition, the length of the output signal A3 is equal to the sum of 80 [ns], which is the length of the input signal V3, and the time of the transient response caused by discharging from the parasitic capacitance 311C.

[0056] In addition, when the difference in capacitance between the parasitic capacitors 111C, 211C, and 311C is almost negligible, the first transition response T11, the first transition response T21, and the first transition response T31 become transition responses having almost the same length and height, and the second transition response T12, the second transition response T22, and the second transition response T32 become transition responses having almost the same length and height.

[0057] Figure 6 FIG. 1 is a diagram showing an example of current input to the current detection unit of the embodiment. Figure 4 When the input signals V1, V2, and V3 are simultaneously input to the product operation units 111, 211, and 311, respectively, the current signal A is input to the current detection unit 10D. Figure 6 As shown, the current signal A includes: a first transient response T4, a constant portion S41, a second transient response T41, a constant portion S42, a second transient response T42, a constant portion S43, and a second transient response T43.

[0058] The first transition response T4 is obtained by Figure 5 The constant portion S41 is a transient response generated by adding the first transient response T11, the first transient response T21, and the first transient response T31 shown in FIG. Figure 5 The constant parts S1, S2, and S3 shown are added together to allow a constant current of 3C [nA] to flow.

[0059] The second transient response T41 is obtained by combining the constant portion S2 and the constant portion S3 with Figure 5 The constant portion S42 is obtained by adding the second transient response T12 shown in FIG. Figure 5The constant portion S2 and the constant portion S3 shown in FIG. 4 are added together to allow a constant current 2C [nA] to flow. The second transient response T42 is obtained by adding the constant portion S3 to the constant portion S3. Figure 5 The constant portion S43 is the same as the constant portion S3, and is a portion where a constant current 1C [nA] flows. The second transient response T43 is Figure 5 The second transition response T32 is shown.

[0060] The current detection unit 10D performs current detection processing of the current output by the detection product calculation unit 111, 211, 311 at each coefficient time from the time when the generation of the first transient response or the second transient response ends to the time when the generation of the next first transient response or the second transient response starts. The coefficient time here is, for example, equivalent to Figure 6 The periods of the constant portion S41, the constant portion S42 and the constant portion S43 are shown.

[0061] For example, Figure 6 As shown at the midpoint D1, the current detection unit 10D initially detects a current 3C [nA] at a time delayed by a certain time, for example, 10 [ns] from the time t0. Figure 6 As shown in the midpoint D2, point D2, point D3, point D4, point D5 and point D6, the current detection unit 10D detects currents of 2C [nA], 1C [nA], 1 [nA], 0 [nA] and 0 [nA] with the above-mentioned coefficient time, for example, 20 [ns] cycle.

[0062] In addition, the current detection unit 10D ends the current detection process when the current detected by the current detection process is equal to the current when the input signal is not input to the product operation unit 111, 211, 311, ..., k11. Figure 6 As shown by the midpoint D5, when the current detection unit 10D detects a current of 0 [nA] in the fifth cycle, it stops the current detection process at the point D6 of the sixth cycle and after the seventh cycle.

[0063] Alternatively, the current detection unit 10D terminates the current detection process when a time equal to the longest length of the input signal that can be obtained has passed since the current detection process was initially executed. For example, the current detection unit 10D stops the current detection process after the 257th cycle when the length of the input signal that can be obtained is 1 times, 2 times, 3 times, ..., 254 times, 255 times, or 256 times the shortest length of the input signal.

[0064] In addition, in reference Figure 3 to Figure 6 In the example described above, the current detection process is executed when 10 [ns] has passed from the start time of each cycle, but the current detection process may be executed at other timings. Figure 7This is a diagram for explaining the timing at which the current detection unit according to the embodiment executes the current detection process.

[0065] For example, at time t0, consider the case where the input signal V1 is input to the product operation unit 111, the input signal V2 is input to the product operation unit 211, and the input signal V3 is input to the product operation unit 311. In this case, as shown in FIG. Figure 6 As explained above, a first transient response T4 is generated. Figure 7 As shown, the first transient response T4 converges to the current 3C [nA] after reaching a current larger than the current 3C [nA].

[0066] The state where the current magnitude is in the range of 3C-Δ[nA] to 3C+Δ[nA] is a stable state where a constant current flows. The magnitude of Δ[nA] is preferably 10% p-p of the current 3[nA], more preferably 5% p-p of the current 3[nA].

[0067] For example, Figure 7 As shown, the magnitude of the current is within this range at time t1. The time from time t0 to time t1 is also called convergence time. The convergence time is, for example, 5 times the time constant τ=RC (R: the resistance value of the parasitic resistance of the above-mentioned product operation unit, C: the capacitance of the parasitic capacitance of the above-mentioned product operation unit). The resistance value R of the parasitic resistance and the capacitance C can be calculated by inputting a plurality of rectangular voltage pulses with different pulse lengths to at least one of the product operation units 111, 211, 311, ..., k11 and evaluating the transient response characteristics.

[0068] The convergence time of the first transient response is equal to the time required for discharge from the parasitic capacitance, and can also be calculated using the following formula (1).

[0069] t=-C×R×ln(V1 / V0) …(1)

[0070] The convergence time of the second transient response described above is equal to the time required for discharge from the parasitic capacitance, and can also be calculated using the following formula (2).

[0071] t=-C×R×ln(1-V1 / V0) … (2)

[0072] On the other hand, the second transient response T41 starts to be generated at time 20 [ns]. Therefore, the above-mentioned constant part 41 is generated during the period from time t1 to time 20 [ns]. The current detection unit 10D performs the current detection process at an arbitrary timing of the constant part 41, that is, during the period from time t1 to time 20 [ns]. In addition, by determining the timing in such a way that the period from time t1 to time 20 [ns] is longer than the convergence time calculated based on the above-mentioned time constant τ, the current detection unit 10D can reliably perform the current detection process through the constant part 41.

[0073] In addition, the current obtained by the current detection processing performed by the current detection unit 10D can also be converted into digital data by analog-to-digital conversion and stored in a storage medium. In addition, the current detection unit 10D can detect the current at a predetermined time from the time when the first transient response converges and becomes a steady state to the time period before the second transient response is generated, or it can detect the current during the predetermined period. Furthermore, when the current detection unit 10D detects the current during the predetermined period, the statistical value of the detected current, such as the average value or the median value, can be used as the result of the current detection processing.

[0074] The sum calculation unit 10S calculates the product of the total current, which is the sum of the currents detected by the current detection unit 10D at each predetermined time interval, and the coefficient time as a value associated with the sum of the output signals.

[0075] For example, the sum operation unit 10S calculates Figure 6 The total current 7[nA] of the currents 3C[nA], 2C[nA], C[nA], C[nA], 0[nA] and 0[nA] detected at the moments indicated by points D1, D2, D3, D4, D5 and D6 respectively. Moreover, the sum operation unit 10S calculates the product of the total current 7[nA] and 20[ns], which is an example of the coefficient time, as a value associated with the sum of the output signals. Alternatively, the sum operation unit 10S calculates the value associated with the sum of the output signals by calculating the sum of the six products after multiplying the currents 3C[nA], 2C[nA], C[nA], C[nA], 0[nA] and 0[nA] respectively by 20[ns], which is an example of the coefficient time. The value associated with the sum of the output signals calculated by these two methods is equivalent to Figure 6 The area of ​​the region indicated by the oblique line is proportional to the sum of the output signals.

[0076] In addition, refer to Figure 3 to Figure 7 The same applies to the product calculation units 121 , 221 , and 321 , the current detection unit 20D, and the sum calculation unit 20S.

[0077] Next, refer to Figure 8, an example of a neural network operation performed by the product-sum operator of an implementation method is described. Figure 8 This is a diagram for explaining an example of a neural network operation performed by a product-sum operator according to an embodiment.

[0078] Nodes 101, 201, 301, ..., k01 form the input layer. Perceptrons 10 and 20 form the hidden layer or output layer. Figure 1 and Figure 3 The nodes 201, 301, ..., k01 correspond to the input units 201E, 301E, ..., k01E, respectively, and output input values ​​corresponding to the input signals to the perceptrons 10 and 20.

[0079] Arrow 111A corresponds to product operation unit 111, indicating that the input value output by node 101 is multiplied by a weight, and a value corresponding to the output signal is input to perceptron 10. Similarly, arrow 121A corresponds to product operation unit 121, indicating that the input value output by node 101 is multiplied by a weight, and a value corresponding to the output signal is input to perceptron 20. The same is true for arrows 211A, 221A, 311A, 321A, ..., k11A, and k21A.

[0080] Perceptron 10 and Figure 1 and Figure 3 The current detection unit 10D shown corresponds to the calculation unit 10S, performs the above-mentioned current detection processing on the signal obtained by adding the output signals output from arrows 111A, 211A, 311A, ..., k11A, and calculates the value associated with the sum of the output signals. Then, the sensor 10 performs activation function processing on the value and outputs it.

[0081] The above is a description of the product-sum operator 1 of the embodiment. The product-sum operator 1 calculates the value associated with the sum of the output signals based on the current detected at each fixed time interval, so it is not necessary to have a capacitor for accumulating charge. Therefore, the product-sum operator 1 can avoid the capacitor from saturating and being unable to perform the product-sum operation. In addition, the product-sum operator 1 can omit the capacitor, so by reducing the circuit scale, it is possible to save space and cost.

[0082] In addition, at least one of the product operation units 111, 121, 211, 221, 311, 321, ..., k11, and k21 of the product-sum operation unit 1 includes a magnetoresistive effect element showing a magnetoresistive effect. Magnetoresistive effect elements have a larger parasitic capacitance than other variable resistance elements, and therefore, are more likely to cause saturation of the capacitor due to a transient response than other variable resistance elements. Therefore, when the above-mentioned product operation unit includes a magnetoresistive effect element, the above-mentioned effect is particularly useful.

[0083] In addition, in the product-sum operator 1, the shortest length of the input signal that can be obtained is the coefficient time, and the length having an integral multiple of the coefficient time is simultaneously input to the product operation parts 111, 121, 211, 221, 311, 321, ..., k11, k21. Moreover, the product-sum operator 1 performs the current detection processing with a period equal to the coefficient time. Therefore, the product-sum operator 1 can reliably detect the current when the first transient response and the second transient response reliably converge and become a stable state, and perform correct product-sum operation.

[0084] Furthermore, the product-sum operator 1 ends the current detection process when a time equal to the longest length of the input signal has elapsed since the current detection process was first executed. Therefore, the product-sum operator 1 can make the execution time of the current detection process constant and simplify the process.

[0085] In addition, when the current detected by the current detection process is equal to the current when the input signal is not input to the plurality of product operation units 111, 121, 211, 221, 311, 321, ..., k11, k21, the product-sum operator 1 ends the current detection process. Therefore, the product-sum operator 1 can end the current detection process early.

[0086] In addition, in the above-mentioned embodiment, the case where the time when the input signal V1 is input to the product operation unit 111, the time when the input signal V2 is input to the product operation unit 211, and the time when the input signal V3 is input to the product operation unit 311 are all time t0 is taken as an example, but the present invention is not limited to this. That is, the time when these three input signals are input may be different from each other. In this case, the coefficient time may be a period from the time when the generation of the first transient response or the second transient response ends to the time when the generation of the next first transient response starts.

[0087] In addition, the above-mentioned product-sum operator 1 can be included in a logic operation device or a neuromorphic device. The logic operation device mentioned here is a logic circuit formed by combining multiple product-sum operators 1, such as an AND circuit and an ØR circuit. In addition, the logic operation described here includes the concept of deep learning. In addition, the neuromorphic device mentioned here is a device that uses the brain structure and the mechanism of nerve cells called neurons to be used for machine learning, etc.

[0088] Alternatively, a program for realizing the functions of each device such as the product-sum calculator 1 in the above-described embodiment may be stored in a computer-readable storage medium, and the program stored in the storage medium may be read into a computer system and executed to perform processing.

[0089] The computer system mentioned here may also be a system including hardware such as an operating system (OS) or peripheral devices. In addition, computer-readable storage media include, for example, writable non-volatile memories such as floppy disks, optical disks, ROMs (Read Only Memory), flash memories, portable media such as DVDs (Digital Versatile Discs), storage devices such as hard disks built into computer systems, and storage media that retain programs for a certain period of time, such as volatile memories inside computer systems that become servers or clients when sending programs via networks or communication lines.

[0090] In addition, the above-mentioned program can also be transmitted from a computer system storing the program in a storage device, etc. to another computer system via a transmission medium or a transmission wave in the transmission medium. Here, the transmission medium for transmitting the program refers to a medium having the function of transmitting information, such as a network such as the Internet or a communication line such as a telephone line.

[0091] In addition, the above program can be a program for realizing a part of the above functions, or a so-called differential program that can realize the above functions by combining with a program already stored in the computer system. The above program is read out and executed by a processor such as a CPU (Central Processing Unit) of the computer.

[0092] The embodiments of the present invention are described in detail above with reference to the drawings, but the specific structure is not limited to the embodiments, and various modifications and substitutions can be added without departing from the spirit of the present invention. The structures described in the above embodiments can also be combined.

[0093] Explanation of symbols

[0094] 1…product-sum operator, 111, 121, 211, 221, 311, 321, k11, k21…product operation unit, 10D, 20D…current detection unit, 10S, 20S…sum operation unit

Claims

1. A product-sum operator, comprising: a plurality of product operation units that multiply input signals corresponding to input values ​​by weights to generate output signals, and output the output signals; a current detection unit that detects the currents outputted from the plurality of multiplication units with a predetermined time delay from the input signal from the time when a first transient response caused by charging of the parasitic capacitance of the multiplication unit according to the input signal converges and becomes a steady state to the time before a second transient response caused by discharging of the parasitic capacitance of the multiplication unit according to the input signal occurs, and then performs a current detection process for detecting the currents outputted from the plurality of multiplication units at a predetermined time interval; A sum calculation unit calculates a value associated with the sum of the output signals based on the current detected by the current detection unit at each fixed time interval.

2. The product-sum operator according to claim 1, wherein: Each of the plurality of product operation sections includes a magnetoresistive effect element that exhibits a magnetoresistive effect.

3. The product-sum operator according to claim 1 or 2, wherein: The sum calculation unit calculates a product of a total current, which is a total of the currents detected by the current detection unit at each fixed time interval, and a coefficient time as a value associated with the sum of the output signals.

4. The product-sum operator according to claim 3, wherein: The coefficient time is the shortest length that the input signal can obtain, The input signal has a length that is an integral multiple of the coefficient time and is simultaneously input to the plurality of product operation units. The current detection unit executes the current detection process in a cycle equal to the coefficient time.

5. The product-sum operator according to claim 1 or 2, wherein: The current detection unit ends the current detection process when a time equal to the longest length that the input signal can obtain has elapsed since the current detection process was initially executed.

6. The product-sum operator according to claim 3, wherein: The current detection unit ends the current detection process when a time equal to the longest length that the input signal can obtain has elapsed since the current detection process was initially executed.

7. The product-sum operator according to claim 4, wherein: The current detection unit ends the current detection process when a time equal to the longest length that the input signal can obtain has elapsed since the current detection process was initially executed.

8. The product-sum operator according to claim 1 or 2, wherein: The current detection unit ends the current detection process when the current detected by the current detection process is equal to the current when the input signal is not input to the plurality of product calculation units.

9. The product-sum operator according to claim 3, wherein: The current detection unit ends the current detection process when the current detected by the current detection process is equal to the current when the input signal is not input to the plurality of product calculation units.

10. The product-sum operator according to claim 4, wherein: The current detection unit ends the current detection process when the current detected by the current detection process is equal to the current when the input signal is not input to the plurality of product calculation units. 11 . A logic operation device comprising the product-sum operator according to claim 1 . 12 . A neuromorphic device comprising the product-sum operator according to claim 1 .

13. A product-sum operation method, which is performed by the product-sum operator according to any one of claims 1 to 10, wherein: The method comprises: a product operation step of multiplying an input signal corresponding to an input value by a weight by using a plurality of product operation units to generate an output signal, and outputting the output signal; a current detection step of detecting the currents outputted by the plurality of the multiplication units with a predetermined time delay from the input signal from the time when a first transient response caused by charging the parasitic capacitance of the multiplication unit according to the input signal converges and becomes a steady state to the time before a second transient response caused by discharging the parasitic capacitance of the multiplication unit according to the input signal occurs, and then performing a current detection process of detecting the currents outputted by the plurality of the multiplication units at a predetermined time interval; The sum calculation step calculates a value associated with the sum of the output signals based on the current detected at each fixed time interval in the current detection step.

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