Method and device for detecting illegal commands

Abstract

The present application relates to methods and apparatus for detecting illegal commands. A memory device, such as a dynamic random access memory (DRAM), may receive a command to perform an access operation on at least one memory unit of the memory device from a device, such as a host device. The memory device may determine, using a detection component, that performing the access operation will violate a timing threshold associated with an operation of the memory device. The memory device may refrain from performing the access operation based on determining that performing the access operation included in the command will violate the timing threshold. The memory device may transmit an indication to the device that performing the command will violate the timing threshold.

Description

[0001] Cross Reference

[0002] This patent application claims priority to PCT application No. PCT / US2019 / 067500, entitled “DETECTION OF ILLEGAL COMMANDS,” filed by Richter et al. on December 19, 2019, which claims priority to U.S. patent application No. 16 / 719,891, entitled “DETECTION OF ILLEGAL COMMANDS,” filed by Richter et al. on December 18, 2019, and U.S. provisional patent application No. 62 / 784,927, entitled “DETECTION OF ILLEGAL COMMANDS,” filed by Richter et al. on December 26, 2018, both of which are assigned to the present assignee and are expressly incorporated herein by reference in their entirety.

[0003] The technical field relates to illegal command detection. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, often represented by a logical 1 or a logical 0. In other devices, more than two states may be stored. To access the stored information, a component of the device may read or sense at least one stored state in the memory device. To access information, a component of the device may write or program a state in the memory device.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even when no external power is present. Volatile memory devices (e.g., DRAM) can lose their stored state over time unless they are periodically refreshed by an external power source. Summary of the invention

[0006] A method is described. The method may include receiving a command from a host device to perform an access operation on a memory unit of a memory device; determining, using a detection component of the memory device, that performing the access operation will violate a timing threshold associated with an operation of the memory device; and transmitting an indication to the host device that executing the command on the memory device will violate the timing threshold based at least in part on determining that the timing threshold will be violated.

[0007] An apparatus is described. The apparatus may include a memory cell array including one or more storage components; a command decoder configured to receive a command from a host device to perform an access operation on a memory cell of the memory cell array; a detection component configured to determine whether performing the access operation will violate a timing threshold associated with the memory cell; and a transmitter configured to transmit an indication that performing the command will violate the timing threshold based at least in part on determining using the detection component that the timing threshold will be violated.

[0008] A method is described. The method may include transmitting, from a host device, a command to perform an access operation on a memory unit of a memory device; and receiving, by the host device, an indication that executing the command on the memory device will violate a timing threshold associated with an operation of the memory device based at least in part on a determination that the timing threshold will be violated. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system operating a memory device supporting illegal command detection as disclosed herein is described.

[0010] Figure 2 An example memory die supporting illegal command detection as disclosed herein is described.

[0011] Figure 3 An example of a command validation flow supporting illegal command detection according to aspects as disclosed herein is described.

[0012] Figure 4 An example of a detection component circuit that supports illegal command detection according to aspects as disclosed herein is illustrated.

[0013] Figure 5 An example of a training process supporting illegal command detection according to aspects as disclosed herein is described.

[0014] Figure 6 A block diagram is shown of an apparatus supporting illegal command detection according to aspects as disclosed herein.

[0015] Figure 7 A block diagram is shown of an apparatus supporting illegal command detection according to aspects as disclosed herein.

[0016] Figures 8 to 11 A flow chart illustrating one or more methods of supporting illegal command detection according to aspects as disclosed herein is shown. DETAILED DESCRIPTION

[0017] A memory device such as a dynamic random access memory (DRAM) may receive a command to perform an operation on one or more memory cells of a memory bank. The command may contain information related to the memory bank on which the operation is to be performed, the row or column of memory cells, and / or the location (e.g., address) of a particular memory cell.

[0018] In some cases, a memory device may receive an illegal or invalid command. A command may be illegal, for example, if executing the command may result in one or more of the array timing violations. For example, a command may be illegal if the bank, row, column, and / or memory cell indicated by the command is currently participating in an operation that is incompatible with the operation requested by the command (e.g., executing the requested operation may violate the timing of the operation currently participating).

[0019] In one example, an illegal command may direct a read (RD) operation to a memory bank that is not in a state to receive an RD command (e.g., the memory bank is closed, in the process of closing, or still in the process of opening), which may cause the host to receive erroneous read data. In another example, an illegal command may direct a write (WR) operation to a memory bank that is not in a state to receive a WR command (e.g., the memory bank is closed, in the process of closing, or still in the process of opening), which may cause unintentional overwriting of data. In another example, a row activation (ACT) or row precharge (PRE) command may occur at a time where either or both of these operations are illegal (e.g., relevant timings such as row address strobe time (tRAS), row precharge time (tRP), and / or row refresh cycle time (tRFC) have not yet passed). Executing such a command may destroy data on an entire row. Even if the probability of an error (e.g., a transmission error, such as a transmission error on a command / address (C / A) bus, or an error in an associated circuit) is low, the error may still be unacceptable in applications with high safety requirements (e.g., in the case of autonomous self-driving cars).

[0020] To determine that a command is illegal, the memory device may determine whether the received command violates one or more array timings. For example, the memory device may decode the command and may determine whether the array timing associated with the command will be violated if the command is executed. To achieve this determination, the memory device may use a detection component containing one or more timers, counters, or a combination thereof. The detection component may select a subset of the one or more timers and / or counters corresponding to one or more array timings and may check that the array timing associated with the command has passed. Additionally or alternatively, the memory device may use a detection component containing a single or multiple processors that perform this process.

[0021] The memory device may execute the command if it is determined that the command is legal. In some cases, the relevant timer and / or counter may be reset if the command is determined to be legal (e.g., to prepare for checking subsequent commands). If the command is determined to be illegal, the memory device may stop executing the command and may report an error to the host (e.g., the memory device may send an error indication to the host). The relevant timers and / or counters of the detection components may be selected (e.g., for closing open rows in each group), and each group of the memory device may be closed autonomously once the timing of these relevant timers and / or counters is met, and the group may be closed without the risk of losing data content. In some cases, the memory device may enter a locked state after determining that the command is illegal and after completing the previous command currently being executed by the memory device. The memory device may wait to receive an indication (e.g., from a host device) before unlocking and continuing normal operation. In some cases, the memory device may enter a self-refresh mode during the locked state, which may enable the memory device to maintain memory content without any additional commands from the host device. Additionally or alternatively, when the memory device is in the locked state, the host device may analyze the root cause of the error condition and / or may prepare corrective actions. In general, the methods disclosed herein can add protection against data loss for a memory device (eg, a memory device) that receives an illegal command. By not executing the illegal command, the data stored in the memory array can retain its integrity.

[0022] In some cases, (e.g., where the host device wishes to determine the duration of one or more timers and / or counters of a detection component of a memory device), the host device may send a training command (e.g., a command that uses an existing opcode but sets at least one otherwise unused C / A bit differently) to the memory device. The memory device may recognize that the command is a training command and may refrain from entering a locked state. In some cases, the training command may be executed after power-up (e.g., as part of initialization). Such training commands may enable the host device to determine the latency between sending a command and receiving an error indication from the memory device.

[0023] First, in the reference Figure 1 Features of the present disclosure are described in the context of a memory system described herein. Figures 2 to 5 Features of the present disclosure are further described in the context of the described memory die, command verification process, detection component circuitry, and training process. Figures 6 to 11 These and other features of the present disclosure are further illustrated by the block diagrams and flow diagrams described for illegal command detection and are further described with reference to the block diagrams and flow diagrams.

[0024] Figure 1 An example of a system 100 utilizing one or more memory devices according to aspects disclosed herein is illustrated. The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 with the memory device 110. The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0025] System 100 may include aspects of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a handheld computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, and the like. Memory device 110 may be a component of the system configured to store data for one or more other components of system 100. In some examples, system 100 is configured for two-way wireless communication with other systems or devices using a base station or access point. In some examples, system 100 is capable of machine type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0026] At least a portion of the system 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to perform a process, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a portable computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, etc. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functions of the external memory controller 105. In some cases, the external memory controller 105 or a graphics processing unit (GPU) may be referred to as a host or host device. In some examples, the system 100 is a graphics card.

[0027] In some cases, memory device 110 (e.g., DRAM) may be a standalone device or component configured to communicate with other components of system 100 and provide physical memory addresses / space that may be used or referenced by system 100. In some examples, memory device 110 may be configurable to work with at least one or more different types of systems 100. Signaling between components of system 100 and memory device 110 may be operable to support modulation schemes used to modulate signals, different pin designs for communicating signals, different packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0028] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may act as a slave device of the system 100 (e.g., responding to and executing commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) that support a desired or specified capacity for data storage. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0029] In some cases, a host device (e.g., external memory controller 105) may transmit an illegal command to a memory device 110 (e.g., DRAM). The memory device 110 may determine that the command is illegal based on determining that executing the command will violate one or more associated array timings. If the memory device 110 determines that the command is illegal, the memory device 110 may refrain from executing the command. Additionally or alternatively, the memory device 110 may provide an error indication or otherwise report the error to the host device.

[0030] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may electronically communicate with each other using a bus 140.

[0031] Processor 120 may be configured to control at least a portion of system 100. Processor 120 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In these cases, processor 120 may be an instance of a central processing unit (CPU), a GPU, a general purpose GPU (GPGPU), or a system on a chip (SoC), among other instances.

[0032] BIOS component 125 may be a software component including BIOS operating as firmware that may initialize and run various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100, such as peripheral components 130, I / O controller 135, etc. BIOS component 125 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0033] Peripheral component 130 may be any input device or output device, or an interface to such a device, that may be integrated into or with system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI). Peripheral component 130 may be other components that are understood by those skilled in the art to be peripheral devices.

[0034] I / O controller 135 may manage data communications between processor 120 and peripheral components 130, input device 145, or output device 150. I / O controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0035] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0036] Output 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0037] The components of system 100 may be composed of general or special purpose circuits designed to perform their functions. This may include various circuit elements such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements configured to perform the functions described herein.

[0038] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, each of which is configured to store at least one bit of digital data. Figure 2 Features of memory array 170 and / or memory cells are described in greater detail.

[0039] The memory device 110 may be an example of a two-dimensional (2D) memory cell array or may be an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., a memory die 160-a, a memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, a plurality of memory dies 160-N may be stacked on top of each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a stack, a level, a layer, or a die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two high stacked memory dies, three high stacked memory dies, four high stacked memory dies, five high stacked memory dies, six high stacked memory dies, seven high stacked memory dies, eight high stacked memory dies). This can increase the number of memory cells that can be positioned on a substrate compared to a single 2D memory device, which in turn can reduce production costs or increase performance of the memory array, or both. In some 3D memory devices, different stacks can share at least one common access line, such that some stacks can share at least one of a word line, a digit line, and / or a plate line.

[0040] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. Thus, the device memory controller 155 may include hardware, firmware, and software that enables the memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information regarding the memory device 110. The device memory controller 155 may be configured to communicate with the external memory controller 105, one or more memory dies 160, or the processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command indicating that the memory device 110 will store certain data on behalf of a component of the system 100 (e.g., the processor 120), or receive a read command indicating that the memory device 110 will provide certain data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, etc. In some cases, the device memory controller 155 may contain detection component circuitry that verifies whether a command is illegal. The detection component circuitry may contain one or more timers and / or counters that check whether an associated array timing has elapsed.

[0041] A local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. Moreover, the local memory controller 165 may be configured to communicate (e.g., receive and transmit data and / or commands) with the device memory controller 155. The local memory controller 165 may support the device memory controller 155 to control the operation of the memory device 110 as described herein. In some cases, the memory device 110 does not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120. In some cases, the local memory controller 165 may contain a detection component circuit that verifies whether a command is illegal. The detection component circuit may contain one or more timers and / or counters that check whether the associated array timing has elapsed.

[0042] The external memory controller 105 may be configured to enable the transfer of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110, so that the components of the system 100 may not need to know the operating details of the memory device. The components of the system 100 may present requests (e.g., read commands or write commands) to the external memory controller 105 that the external memory controller 105 satisfies. The external memory controller 105 may convert or translate communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0043] In some cases, the external memory controller 105 or other components of the system 100, or the functions thereof described herein, may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or the functions thereof described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Likewise, in some cases, one or more functions attributed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (separate from or included in processor 120 ).

[0044] Components of system 100 may exchange information with memory device 110 using a plurality of channels 115. In some examples, channels 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal including one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to function as part of a channel.

[0045] In some cases, the pins or pads of the terminals may be part of a signal path of channel 115. Additional signal paths may be coupled with the terminals of the channel for routing signals within components of system 100. For example, memory device 110 may include signal paths (e.g., internal to memory device 110 or a component thereof, such as a signal path internal to memory die 160) that route signals from the terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0046] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting a specific type of information. In some cases, channel 115 may be an aggregate channel and may therefore include multiple individual channels. For example, data channel 190 may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), etc.

[0047] In some cases, channel 115 may include one or more command and address (CA) channels 186. CA channel 186 may be configured to transmit commands between external memory controller 105 and memory device 110, including control information associated with the commands (e.g., address information). For example, CA channel 186 may include a read command regarding the address of the desired data. In some cases, CA channel 186 may register on a rising clock signal edge and / or a falling clock signal edge. In some cases, CA channel 186 may include multiple (e.g., eight or nine) signal paths.

[0048] In some cases, the channel 115 may include one or more clock signal (CK) channels 188. The CK channel 188 may be configured to transmit one or more common clock signals between the external memory controller 105 and the memory device 110. Each clock signal may be configured to oscillate between a high state and a low state, and coordinate the actions of the external memory controller 105 and the memory device 110. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal) and the signal path of the CK channel 188 may be configured accordingly. In some cases, the clock signal may be single-ended. The CK channel 188 may include any number of signal paths. In some cases, the clock signal CK (e.g., a CK_t signal and a CK_c signal) may provide a timing reference for command and addressing operations of the memory device 110 or other system-wide operations of the memory device 110. The clock signal CK may therefore be variously referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0049] In some cases, channels 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to transfer data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may transfer (e.g., bidirectionally) information to be written to memory device 110 or information to be read from memory device 110.

[0050] In some cases, channel 115 may include one or more other channels 192 that may be dedicated for other purposes. These other channels 192 may include any number of signal paths.

[0051] In some cases, other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally stand for "write", the write clock signal WCK (e.g., WCK_t signal and WCK_c signal) may provide a timing reference generally used for access operations of the memory device 110 (e.g., a timing reference for both read and write operations). Therefore, the write clock signal WCK may also be referred to as the data clock signal WCK. The WCK channel may be configured to communicate a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t signal and WCK_c signal), and the signal path of the WCK channel may be configured accordingly. The WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0052] In some cases, other channels 192 may include one or more error detection code (EDC) channels. EDC channels may be configured to convey error detection signals, such as checksums, to improve system reliability. EDC channels may include any number of signal paths.

[0053] Channel 115 may couple external memory controller 105 with memory device 110 using a variety of different architectures. Examples of various architectures may include a bus, a point-to-point connection, a crossbar switch, a high-density interposer such as a silicon interposer, or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer such as a silicon interposer or a glass interposer.

[0054] A variety of different modulation schemes may be used to modulate signals transmitted over the channel 115. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to two. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return to zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and the like.

[0055] Figure 2An example of a memory die 200 according to various examples of the present disclosure is illustrated. The memory die 200 may be a reference Figure 1 1. An example of a memory die 160 described herein. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cell 205 may be configured to store one bit of digital logic (e.g., logic 0 and logic 1) at a time. In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic (e.g., logic 00, logic 01, logic 10, or logic 11) at a time.

[0056] The memory cell 205 can store a charge representing a programmable state in a capacitor. A DRAM architecture can include a capacitor that includes a dielectric material to store a charge representing a programmable state. In other memory architectures, other storage devices and components are also possible. For example, a nonlinear dielectric material can be used.

[0057] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines such as word line 210 and / or digit line 215. In some cases, digit line 215 may also be referred to as a bit line. References to access lines, word lines, and digit lines, or the like, are interchangeable and do not affect understanding or operation. Activating or selecting word line 210 or digit line 215 may include applying a voltage to the corresponding line.

[0058] The memory die 200 may include access lines (e.g., word lines 210 and digit lines 215) arranged in a grid-like pattern. Memory cells 205 may be positioned at the intersections of the word lines 210 and digit lines 215. By biasing the word lines 210 and digit lines 215 (e.g., applying a voltage to the word lines 210 or the digit lines 215), a single memory cell 205 may be accessed at their intersections.

[0059] Access to the memory cell 205 may be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 may receive a row address from the local memory controller 260 and activate the word line 210 based on the received row address. The column decoder 225 may receive a column address from the local memory controller 260 and may activate the digit line 215 based on the received column address. For example, the memory die 200 may include a plurality of word lines 210 labeled WL_1 to WL_M and a plurality of digit lines 215 labeled DL_1 to DL_N, where M and N depend on the size of the memory array. Thus, by activating a word line 210 and a digit line 215, such as WL_1 and DL_3, a memory cell 205 at the intersection thereof may be accessed. The intersection of a word line 210 and a digit line 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of the memory cell 205.

[0060] Memory cell 205 may include a logic storage component, such as capacitor 230 and switching component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switching component 235, and a second node of capacitor 230 may be coupled to voltage source 240. In some cases, voltage source 240 may be a cell plate reference voltage, such as Vpl, or may be grounded, such as Vss. In some cases, voltage source 240 may be an example of a plate line coupled to a plate line driver. Switching component 235 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components.

[0061] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switch component 235. Capacitor 230 can be in electronic communication with digit line 215 using switch component 235. For example, when switch component 235 is deactivated, capacitor 230 can be isolated from digit line 215, and when switch component 235 is activated, capacitor 230 can be coupled to digit line 215. In some cases, switch component 235 is a transistor, and its operation can be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source can be greater than or less than the threshold voltage of the transistor. In some cases, switch component 235 can be a p-type transistor or an n-type transistor. Word line 210 can be in electronic communication with the gate of switch component 235, and switch component 235 can be activated / deactivated based on the voltage applied to word line 210.

[0062] The word line 210 may be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. In some architectures, the word line 210 may be in electronic communication with a gate of a switching element 235 of the memory cell 205 and may be configured to control the switching element 235 of the memory cell. In some architectures, the word line 210 may be in electronic communication with a node of a capacitor of the memory cell 205 and the memory cell 205 may not include a switching element.

[0063] The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing component 245. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during a portion of an access operation. For example, the word line 210 and the switching component 235 of the memory cell 205 can be configured to couple and / or isolate the capacitor 230 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 can be in electronic communication with the digit line 215 (e.g., constant).

[0064] The sensing component 245 may be configured to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205, and determine the logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by the memory cell 205 may be extremely small. Therefore, the sensing component 245 may include one or more sense amplifiers to amplify the signal output by the memory cell 205. The sense amplifier may detect a small change in the charge of the digit line 215 during a read operation, and may generate a signal corresponding to a logic state 0 or a logic state 1 based on the detected charge. During a read operation, the capacitor 230 of the memory cell 205 may output a signal (e.g., release charge) to its corresponding digit line 215. The signal may cause the voltage of the digit line 215 to change. The sensing component 245 may be configured to compare the signal received from the memory cell 205 across the digit line 215 with a reference signal 250 (e.g., a reference voltage). The sensing component 245 may determine the storage state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digit line 215 has a higher voltage than the reference signal 250, the sensing component 245 can determine that the storage state of the memory cell 205 is a logic 1, and if the digit line 215 has a lower voltage than the reference signal 250, the sensing component 245 can determine that the storage state of the memory cell 205 is a logic 0. The sensing component 245 can include various transistors or amplifiers to detect and amplify the difference in signals. The detected logic state of the memory cell 205 can be output as an output 255 via the column decoder 225. In some cases, the sensing component 245 can be part of another component (e.g., column decoder 225, row decoder 220). In some cases, the sensing component 245 can be in electronic communication with the row decoder 220 or the column decoder 225.

[0065] The local memory controller 260 may control the operation of the memory cell 205 through various components (eg, the row decoder 220, the column decoder 225, and the sensing component 245). The local memory controller 260 may be a reference Figure 1 105 . In some cases, one or more of the row decoder 220, column decoder 225, and sense component 245 may be co-located with the local memory controller 260. The local memory controller 260 may be configured to receive data from the external memory controller 105 (or reference 105). Figure 1 The local memory controller 260 may receive commands and / or data, translate the commands and / or data into information that the memory die 200 may use, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the external memory controller 105 (or the device memory controller 155) in response to performing the one or more operations. The local memory controller 260 may generate row and column address signals to activate the target word lines 210 and the target digit lines 215. The local memory controller 260 may also generate and control various voltages or currents used during the operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory die 200.

[0066] In some cases, the local memory controller 260 may be configured to perform a WR operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify a target memory cell 205 on which a write operation will be performed. The local memory controller 260 may identify a target word line 210 and a target digit line 215 in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The local memory controller 260 may apply a specific signal (e.g., a voltage) to the digital line 215 during a write operation to store a specific state (e.g., a charge) in the capacitor 230 of the memory cell 205, which may indicate a desired logic state. In some cases, performing a WR operation may first involve opening the rows of the group (e.g., at the instruction of an ACT command). The WR command may be followed by at least one activation write time (tRCDWR) after the row of the open group. The local memory controller 260 may wait for at least one write recovery time (tWR) from the write operation before closing the row of the group. Additionally or alternatively, the local memory controller 260 may wait for at least one tRAS from the row of the open group before closing the row of the group. The local memory controller 260 may close the row of the group (e.g., at the instruction of a PRE or precharge command) and may wait for at least one tRP before reopening the row of the memory group. The time that elapses from opening a row of a group for the first time to opening a row of a memory group for the next time may be a row cycle time (tRC), which may be equal to the sum of tRAS and tRP (eg, the sum of tRAS and tRP as a minimum).

[0067] In some cases, the local memory controller 260 may be configured to perform an RD operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During a read operation, a logic state stored on a memory cell 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 may identify a target memory cell 205 on which a read operation will be performed. The local memory controller 260 may identify a target word line 210 and a target digit line 215 in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 may pass a signal to the sensing component 245 in response to the biased access line. The sensing component 245 may amplify the signal. The local memory controller 260 may activate the sensing component 245 (e.g., latch the sensing component) and thereby compare the signal received from the memory cell 205 with the reference signal 250. Based on the comparison, the sensing component 245 may determine the logic state stored on the memory cell 205. As part of the read operation, the local memory controller 260 may transmit the logic state stored on the memory cell 205 to the external memory controller 105 (or the device memory controller 155). In some cases, performing the RD operation may first involve the rows of the open group (e.g., at the instruction of the ACT command). The RD command may be followed by at least an activation to read delay time (tRCDRD) after the rows of the open group. The local memory controller 260 may wait at least a read to precharge time (tRTP) from the read operation before closing the rows of the group. Additionally or alternatively, the local memory controller 260 may wait at least a time tRAS from the rows of the open group before closing the rows of the group. After closing a bank, local memory controller 260 may close a row (eg, via a PRE command) and may wait at least a time tRP before reopening a row of a bank. The time from the first opening of a bank row to the next opening of a bank row may be tRC.

[0068] The amount of time between the first RD and the next RD operation or the first WR and the next WR may be the column-to-column delay time (tCCD). The amount of time between the RD and the next WR may be the read-to-write time (tRTW) and the amount of time between the WR and the next RD may be the write-to-read time (tWTR).

[0069] In some memory architectures, accessing the memory cell 205 may degrade or destroy the logic state stored in the memory cell 205. For example, a read operation performed in a DRAM architecture may partially or completely discharge the capacitor of the target memory cell. The local memory controller 260 may perform a rewrite operation or a refresh (REF) operation to restore the memory cell to its original logic state. The local memory controller 260 may rewrite the logic state to the target memory cell after the read operation. In some cases, the rewrite operation may be considered as part of the read operation. In addition, activating a single access line (e.g., word line 210) may disturb the state stored in some memory cells that are in electronic communication with the access line. Therefore, a rewrite operation or a REF operation may be performed on one or more memory cells that may not have been accessed. In some cases, performing a REF operation may involve a single group or all groups (e.g., in the case of all group refresh) being idle and / or at least a time tRP has passed since the group was last closed. After performing the REF operation, the local memory controller 260 may wait for at least a tRFC before opening the memory group.

[0070] Determining that a command (e.g., an ACT, PRE, RD, WR, and / or REF command) is illegal may involve determining that executing the command will violate a group of array timings (e.g., one or more of tRC, tRCDRD, tRCDWR, tRFC, tWR, tRTP, tRP, tRAS, tCCD, tWTR, and tRTW). The array timing group that is checked may depend on which command is to be executed (e.g., tRCDRD may be checked if the local memory controller 260 is to perform an RD operation, and tRCDWR may be checked if the local memory controller 260 is to perform a WR operation).

[0071] Figure 3 An example of a command verification process 300 supporting illegal command detection according to aspects as disclosed herein is described. In some examples, the command verification process 300 can be implemented by aspects of the system 100 and / or memory die 200 as described herein. For example, the command verification process 300 can be implemented by reference to Figure 1 and 2 The described host device (eg, external memory controller 105) or memory device 110 (eg, DRAM) or a combination thereof is implemented.

[0072] At 305, the memory device 110 may receive a command from a host device (e.g., an external memory controller 105). More specifically, the device memory controller 155 and / or the local memory controller 165 (e.g., a local memory controller 165 associated with the memory die 160 where the row to which the command is directed is located) may receive the command. Examples of commands received from the host device may include an activate command, a precharge command, a write command, a read command, or a refresh command, or a combination thereof.

[0073] At 310, the memory device 110 may select one or more timers and / or counters containing one or more corresponding timing parameters (e.g., array timing) associated with executing the received command by the memory device. In some cases, the timer may be an instance of an analog component and may be calibrated or programmed to the corresponding array timing. In some cases, the counter may be an instance of a digital component (e.g., a binary counter) and may be programmed to count the number of clock cycles associated with executing the received command at a given clock frequency. As part of an executed DRAM configuration program (e.g., executed at power-on or when there is an operating frequency change), each timer and / or counter may be programmable. In some cases, the memory device 110 may use a processor containing the corresponding array timing instead of a timer and / or counter. Each timer, counter, and / or processor may be configured to track tRC, tRAS, tRP, tRFC, tRCDRD, tRCDWR, tRTP, tWR, tCCD, tRTW, tWTR, or a combination of these. Some of the timers and / or counters may be provided for each group (eg, tRAS, tRP), and other timers and / or counters may be provided once per device or once per group (eg, tRFC, tCCD).

[0074] At 315, the memory device 110 may determine whether the received command is illegal. If the memory device 110 determines that the received command is legal, the memory device 110 may execute the command, as shown at 320. If the memory device determines that the received command is illegal, the memory device 110 may perform the operations illustrated at 330. Determining whether the received command is illegal may involve using a detection component (e.g., external or internal to the memory device 110) to determine what operation the received command is associated with (e.g., via decoding and / or parsing); whether one or more timing thresholds associated with the command have been met; the bank status of one or more memory banks to which the command is directed; or a combination of these. Determining whether the command is illegal may involve using one or more analog timers and / or analog counters or may be performed by a processor.

[0075] In one example, the detection component may determine that an ACT command has been received. The detection component may flag an error if: a row in the group pointed to by the ACT command is already open; the group is in the process of precharging; tRP has not passed; tRFC has not passed (e.g., from the previous REF command); or a combination thereof.

[0076] In another example, the detection component may determine that a PRE command has been received. The detection component may flag an error if: a row in the group pointed to by the PRE command is already open; tRAS has not passed; tWR has not passed; tRTP has not passed; or a combination thereof.

[0077] In another example, the detection component may determine that a WR command has been received. The detection component may flag an error if: the bank to which the WR command points is idle or in the process of precharging; the row of the bank is open and tRCDWR has not passed; tCCD has not passed (e.g., from a previous WR command); tRTW has not passed (e.g., from a previous RD command); tRP has not passed; or a combination thereof.

[0078] In another example, the detection component may determine that an RD command has been received. The detection component may flag an error if: the bank pointed to by the RD command is idle or in the process of precharging; the row of the bank is open and tRCDRD has not passed; tCCD has not passed (e.g., from the previous RD command); tWTR has not passed (e.g., from the previous WR command); tRP has not passed; or a combination thereof.

[0079] In another example, the detection component may determine that a REF command has been received. The detection component may flag an error if: the row of the group pointed to by the REF command is open; any group is in the process of precharging; tRP has not passed; tRAS has not passed; tRFC has not passed; or a combination thereof. Additionally or alternatively, all groups may be checked, and the detection component may flag an error if: any row of any group is open; any group is in the process of precharging; every group has not passed tRP; every group has not passed tRAS; every group has not passed tRFC; or a combination thereof.

[0080] At 320, memory device 110 may determine to execute the received command. In some cases, the command may be executed by a processor, a controller, or dedicated logic, or a combination thereof.

[0081] At 325, the memory device 110 may reset timers and / or counters that may be timed with respect to an array associated with a command to detect the component, if any. The memory device 110 may reset all timers and / or counters of the detection component or may reset timers and / or counters selected by the memory device 110. After 325, the memory device 110 may continue normal operation. The memory device 110 may skip the timer reset if the program described herein is executed by a processor.

[0082] At 330, memory device 110 may refrain from executing the command. In some cases, the operation of refraining from executing the command may be performed by a processor.

[0083] At 335, memory device 110 may transmit an error indication or otherwise report the error to the host device. For example, memory device 110 may contain an error pin set connected to an interrupt input of the host device. Additionally or alternatively, one or more output pins of memory device 110 (e.g., an EDC pin) may signal the error to the host device by stopping toggling and driving a fixed high (H) or low (L) level. Additionally or alternatively, one or more output pins of memory device 110 that normally drive a known pattern (e.g., a checksum) may drive an inverted known pattern, which the host device may detect as an indication of an illegal command. Error reporting may be cycle accurate (e.g., the duration from receiving a command to reporting an error may be a known value), which may enable the host device to accurately identify which command failed. The delay may be a fixed number of clock cycles or may vary (e.g., the host device may dynamically or otherwise program a delay into an internal register of memory device 110). In some cases, the operations of 330 and 335 may be switched (e.g., 335 may be performed before, after, or after 330).

[0084] At 340, the memory device 110 may wait for all or a subset of one or more timers and / or counters (e.g., one or more timers and / or counters selected by the memory device 110) to satisfy their respective timing thresholds. For example, the memory device 110 may wait for the completion of a current command being executed by the memory device. Once the current command is completed, the memory device may move to other functions.

[0085] At 345, the memory device 110 may shut down all or some of the memory banks of the memory device 110, and the memory device 110 may enter a locked state. The locked state may prevent other commands from being executed on the memory banks of the memory device. The memory device 110 may enter a self-refresh mode during the locked state, which may preserve memory contents.

[0086] At 350, memory device 110 may wait until it receives an unlock indication (eg, from a host device). Once memory device 110 is unlocked, memory device 110 may execute the new command (eg, memory device may execute 305).

[0087] Figure 4 An example of a detection component circuit 400 that supports illegal command detection according to aspects as disclosed herein is illustrated. In some examples, the detection component circuit 400 can implement aspects of the system 100 and / or the memory die 200 as described herein. Figure 4 All functions of the components may be performed by a processor.

[0088] The command decoder 405 may receive a command (e.g., sent from a host device) via one or more command pins. The command decoder 405 may decode and / or parse the command and may output a logic value (e.g., a logic low or a logic high) along at least one command line 410. The command decoder may determine on which line to output the logic value based on the operation associated with the command. For example, the command decoder may output a logic high (e.g., 1) on command line 410-a if the command is an ACT command; output a logic high (e.g., 1) on command line 410-b if the command is a PRE command; output a logic high (e.g., 1) on command line 410-c if the command is a WR command; output a logic high (e.g., 1) on command line 410-d if the command is an RD command; and output a logic high (e.g., 1) on command line 410-e if the command is a REF command. In some cases, any of these command lines 410 may be omitted. In some cases, these individual commands may be transmitted across a common command line.

[0089] The detection component circuit 400 may include one or more timing components 415. The timing component 415 may be a timer (e.g., an analog timer), a counter (e.g., a digital counter), or any other device that can be used for timing. Each timing component 415 may check a different array timing. For example, the timing component 415-a may check whether tRAS has passed; the timing component 415-b may check whether tRCDRD has passed; the timing component 415-c may check whether tRCDWR has passed; the timing component 415-d may check whether tRTP has passed; the timing component 415-e may check whether tWR has passed; the timing component 415-f may check whether tRP has passed; the timing component 415-g may check whether tRFC has passed; the timing component 415-h may check whether tCCD has passed; the timing component 415-i may check whether tRTW has passed; and the timing component 415-j may check whether tWTR has passed. Additionally or alternatively, there may be a timing component 415 that checks whether tRC has passed. The output of each timing component 415 may be a logic high (e.g., 1) if the relevant timing has not passed and may be a logic low (e.g., 0) if the timing has passed. Any of the timing components 415 may be omitted.

[0090] The detection component circuit 400 may compare the output of the command decoder 405 (e.g., via the command line 410) with one or more outputs of the timing component 415 (e.g., via the timing component output line). The comparison may, for example, include passing the output of the command decoder 405 and the output of the timing component 415 through an AND component 420 (e.g., an AND gate) for each of the one or more timings associated with the received command. In some cases, comparing the outputs via the AND component 420 may enable the command signal to select the corresponding timing parameters (tRAS, tRP, etc.). The output of each AND component 420 of the command may be input into an OR component 425 (e.g., an OR gate), which may output an indication of a timing violation (e.g., a logic high) if the relevant command is in effect and one or more of the relevant timings have not been passed (e.g., if at least one of the relevant AND components 420 outputs a logic high). Otherwise, the OR component 425 may indicate that the timing is not violated (e.g., the OR component 425 may output a logic low). In some cases, other logic components (e.g., a combination of NOT, AND, and OR) may be used. Additionally or alternatively, AND component 420 may be omitted entirely and each OR component 425 may directly receive an output of command decoder 405 and / or timing component 415 .

[0091] Command line 410-a (e.g., command line 410 associated with an ACT command) can be coupled to AND component 420-a and / or 420-b. Additionally, timing component 415-f (e.g., timing component 415 that checks tRP) can be coupled to AND component 420-a and / or timing component 415-g (e.g., timing component 415 that checks tRFC) can be coupled to AND component 420-b. The outputs of AND components 420-a and / or 420-b can be coupled to OR component 425-a. In some cases, one or more additional AND components 420 and connections to corresponding timing components 415 (e.g., Figure 4 ), the other timing components 415 described in ), the command line 410-a and the connection parts of the OR component 425-a.

[0092] Command line 410-b (e.g., command line 410 associated with a PRE command) may be coupled to AND components 420-c, 420-d, 420-e, or a combination. Additionally, timing component 415-a (e.g., timing component 415 that checks tRAS) may be coupled to AND component 420-c; timing component 415-d (e.g., timing component 415 that checks tRTP) may be coupled to AND component 420-d; timing component 415-e (e.g., timing component 415 that checks tWR) may be coupled to AND component 420-e; or a combination of these scenarios may occur. The outputs of AND components 420-c, 420-d, 420-e, or a combination may be coupled to OR component 425-b. In some cases, one or more additional AND components 420 may be added and connected to corresponding timing components 415 (e.g., Figure 4 ), the other timing components 415 described in ), the command line 410-b and the connection parts of the OR component 425-b.

[0093] Command line 410-c (e.g., command line 410 associated with a WR command) may be coupled to AND component 420-f, 420-g, 420-h, 420-i, or a combination. Additionally, timing component 415-c (e.g., timing component 415 that checks tRCDWR) may be coupled to AND component 420-f; timing component 415-f (e.g., timing component 415 that checks tRP) may be coupled to AND component 420-g; timing component 415-h (e.g., timing component 415 that checks tCCD) may be coupled to AND component 420-h; timing component 415-i (e.g., timing component 415 that checks tRTW) may be coupled to AND component 420-i; or a combination of these scenarios may occur. The outputs of AND components 420-f, 420-g, 420-h, 420-i, or a combination may be coupled to OR component 425-c. In some cases, one or more additional AND components 420 may be added and connected to corresponding timing components 415 (e.g., Figure 4 ), the other timing components 415 described in ), the command line 410-c and the connection parts of the OR component 425-c.

[0094] Command line 410-d (e.g., command line 410 associated with the RD command) can be coupled to AND components 420-j, 420-k, 420-1, 420-m, or a combination. In addition, timing component 415-b (e.g., timing component 415 that checks tRCDRD) can be coupled to AND component 420-j; timing component 415-f (e.g., timing component 415 that checks tRP) can be coupled to AND component 420-k; timing component 415-h (e.g., timing component 415 that checks tCCD) can be coupled to AND component 420-1; timing component 415-j (e.g., timing component 415 that checks tWTR) can be coupled to AND component 420-m; or a combination of these scenarios can occur. The outputs of AND components 420-j, 420-k, 420-1, 420-m, or a combination can be coupled to OR component 425-d. In some cases, one or more additional AND components 420 may be added and connected to corresponding timing components 415 (e.g., Figure 4 ), the other timing components 415 described in ), the command line 410-d and the connection parts of the OR component 425-c.

[0095] Command line 410-e (e.g., a command line associated with a REF command) may be coupled to AND components 420-n, 420-o, 420-p, or a combination. Additionally, timing component 415-a (e.g., a timing component 415 that checks tRAS) may be coupled to AND component 420-n; timing component 415-f (e.g., a timing component 415 that checks tRP) may be coupled to AND component 420-o; timing component 415-g (e.g., a timing component 415 that checks tRFC) may be coupled to AND component 420-p; or a combination of these scenarios may occur. The output of AND components 420-n, 420-o, 420-p, or a combination may be coupled to OR component 425-e. In some cases, one or more additional AND components 420 may be added and connected to corresponding timing components 415 (e.g., Figure 4 ), the other timing components 415 described in ), the command line 410-e and the connection of the OR component 425-e.

[0096] OR components 425-a, 425-b, 425-c, 425-d, 425-e, or a combination may be coupled with OR component 430. OR component 430 may output an error indication (e.g., a logic high) if at least one of the OR components 425 outputs a logic high. In some cases, OR components 425-a, 425-b, 425-c, 425-d, 425-e, or a combination may alternatively be coupled with one or more other logic components (e.g., components that perform NOT, AND, and / or OR operations) that may output an error indication.

[0097] The detection component circuit 400 may compare the complement of the output of each OR component 425 (e.g., the output of the OR component 425 that passes through a NOT component (e.g., a NOT gate)) with the corresponding output of the command decoder 405 (e.g., via command line 410). The comparison may, for example, include passing the output of the command decoder 405 and the complement of the output of the corresponding OR component 425 through an AND component 435 (e.g., the output along command line 410-a and the complement of the output of the OR component 425-a (which may be associated with command line 410-a) may be compared through an AND component 435-a). After the outputs are compared, the AND component 435 may output an indication of whether to execute the command (e.g., a logic high may mean that the command will be executed and a logic low may mean that the command will not be executed). In some cases, the AND component 435 may be omitted entirely, and the complement of the output of each OR component 425 and / or the output of the command decoder 405 may be directly output.

[0098] In some cases, the detection component 400 may include one or more components forming a selection component that is configured to select a timing threshold from a set of timing thresholds based at least in part on the type of command received from the host device. Not every command received from the host device implies every array timing. Thus, the detection component 400 (e.g., using the selection component) may identify or select the array timing associated with a given command. In some cases, the selection component may include analog components and the wiring may be hardwired into those components. In some cases, the selection component may be executed by a digital component (including hardware, firmware, or software) to select the array timing associated with the received command.

[0099] Figure 5 An example of a training flow 500 that supports illegal command detection according to aspects as disclosed herein is illustrated. In some examples, the training flow 500 can be implemented by aspects of the system 100 and / or memory die 200 as described herein.

[0100] At 505 , a host device (eg, external memory controller 105 ) may initialize a memory device 110 (eg, DRAM).

[0101] At 510, the host device may transmit a training command to the memory device 110. The training command may be a specific training command that the memory device 110 recognizes therefrom. The training command may be configured to indicate to the memory device that a timing associated with an error indication is to be determined. For example, when the memory device detects that a command is illegal and sends an error indication back to the host device, there may be a certain delay between when the host device transmits the command and when the host device receives the indication. Such delays may be measured in clock cycles or in units of seconds (e.g., nanoseconds). The delay may cause it to be difficult for the host device to determine which command is illegal and may therefore cause it to be difficult for the host device to resend a command containing an error. One purpose of the training procedure may be to identify a delay between transmitting a command and receiving an error indication (e.g., a command-to-indication delay). Such delays may be used by the host device to identify illegal commands. When performing a training operation, the memory device 110 may not immediately enter a locked state after detecting an error.

[0102] At 515, the host device may receive an error signal from the memory device 110. For example, the memory device 110 may receive a specific training command and may set and transmit an error flag with the same timing as if a normal training command was received. The memory device 110 may contain a set of error pins connected to an interrupt input of the host device. Additionally or alternatively, one or more output pins (e.g., EDC pins) of the memory device 110 may signal an error to the host device by stopping toggling and driving a fixed logic high or logic low level. Additionally or alternatively, one or more output pins of the memory device 110 that normally drive a known pattern (e.g., a checksum) may drive an inverted known pattern, which the host device may detect as an indication of an illegal command.

[0103] At 520, the host device may determine and store a round trip delay (e.g., command to indication delay). The round trip delay may be the number of clock cycles between sending the training command and receiving the error signal. Determining the round trip delay may enable the host device to determine which command has failed. This may result from the error reporting having cycle accuracy (e.g., resulting from having a known value for the duration from receiving the command to reporting the error).

[0104] The host device may begin normal operations (eg, operations occurring after initialization) based on determining the round trip delay at 525. The round trip delay may be used by the host device to determine which command was illegal after receiving the error indication.

[0105] Figure 6 A block diagram 600 of a controller 605 supporting illegal command detection according to aspects as disclosed herein is shown. The controller 605 may be a reference Figure 1 , 24 and 5. Controller 605 may include a command receiver 610, a timing threshold determiner 615, an error indication transmitter 620, an operation component 625, a command identifier 630, a group lock component 635, a training command determiner 640, and an error indication receiver 645. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0106] The command receiver 610 may receive a command from a host device to perform an access operation on a memory cell of a memory device. In some examples, the command receiver 610 may receive a command from a host device to perform an access operation on at least one memory cell of a group. In some cases, the memory device includes a group having one or more rows of memory cells, wherein at least one of the one or more rows includes a memory cell. In some cases, the command includes a row activation command, a row precharge command, a write command, a read command, or a refresh command, or any combination thereof. In some cases, the memory device includes a DRAM memory device.

[0107] The timing threshold determiner 615 may determine, using a detection component of the memory device, that performing an access operation will violate a timing threshold associated with an operation of the memory device. In some examples, the timing threshold determiner 615 may determine that performing an access operation will violate a timing threshold associated with accessing at least one memory cell. In some examples, the timing threshold determiner 615 may select a timing threshold from a set of timing thresholds based on a command, wherein determining whether the timing threshold will be violated is based on selecting the timing threshold. In some examples, the set of timing thresholds is selected from the set of timing thresholds based on a command, wherein determining whether the timing threshold will be violated includes determining whether at least one of the set of timing thresholds will be violated. In some examples, the timing threshold determiner 615 may identify a state of a group associated with a memory cell based on receiving a command, wherein transmitting the indication to the host device is based on the state of the group when the command is received. In some examples, the timing threshold determiner 615 may determine that a row of a group of the memory device is open, the group is being precharged, has not passed tRP, or has not passed tRFC associated with a refresh command, or any combination thereof. In some instances, the timing threshold determiner 615 may determine that the row of the group of the memory device is not open, the row of the group is open and has not yet passed tRAS, has not yet passed tWR associated with a write command, has not yet passed tRTP associated with a read command, or any combination thereof. In some instances, the timing threshold determiner 615 may determine that the group of the memory device is idle or being precharged, the row of the group is open and has not yet passed tRCDWR, has not yet passed tCCD associated with a previous write command, has not yet passed tRTW associated with a previous read command, or any combination thereof. In some instances, the timing threshold determiner 615 may determine that the group of the memory device is idle or being precharged, the group is open and has not yet passed tRCDRD, has not yet passed tCCD associated with a previous read command, has not yet passed tWTR associated with a previous write command, or any combination thereof. In some instances, the timing threshold determiner 615 may determine that the row of the group of the memory device is open, the group is being precharged, has not yet passed tRP, or any combination thereof. In some cases, the timing threshold includes tRC, tRAS, tRCDRD, tRCDWR, tRTP, tWR, tRP, tRFC, tCCD, tRTW, tWTR, or any combination thereof.

[0108] The error indication transmitter 620 may transmit an indication to the host device that the memory device's execution of the command will violate the timing threshold based on the determination that the timing threshold will be violated. The error indication transmitter 620 may transmit an error signal to the host device indicating that the memory device is unable to execute a command received from the host device based on the determination that the timing threshold will be violated.

[0109] The operation component 625 can refrain from performing the access operation based on determining that a timing threshold will be violated using the detection component, wherein transmitting the indication is based on refraining from performing the access operation. In some examples, the operation component 625 can refrain from performing the access operation based on determining that a timing threshold will be violated using the detection component, wherein transmitting the indication occurs after refraining from performing the access operation.

[0110] The command identifier 630 may identify a command received from the host device after receiving the command.

[0111] The group lock component 635 can lock a group associated with the memory unit and / or memory device to prevent additional operations from being performed on the group based on determining that a timing threshold will be violated, wherein the indication is used to indicate the group lock. In some examples, the group lock component 635 can identify that the memory device has completed a current access operation, wherein locking the group occurs after the current access operation is completed. In some examples, the group lock component 635 can receive a message from the host device including information configured to unlock the group to enable additional operations to be performed on the group based on transmitting the indication.

[0112] The training command determiner 640 may determine that a command is a training command, wherein receiving the command occurs during initialization of the memory device.

[0113] Figure 7 A block diagram 700 is shown of an apparatus 705 for supporting illegal command detection according to aspects as disclosed herein. The apparatus 705 may be a reference Figure 1 An example of aspects of the described host device, such as external memory controller 105. Device 705 may include a command transmitter 710, an error indication receiver 715, a command identifier 720, a delay identifier 725, and a training command transmitter 730. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0114] The command transmitter 710 may transmit a command from the host device to perform an access operation on a memory unit of the memory device. In some examples, the command transmitter 710 may resend the command to the memory device through the host device based on receiving the indication.

[0115] The error indication receiver 715 may receive, by the host device, an indication that execution of a command to the memory device will violate a timing threshold associated with operation of the memory device based on determining that the timing threshold will be violated. In some examples, the error indication receiver 715 may receive an error signal from the memory device based on transmitting a training command.

[0116] Command identifier 720 may identify, based on receiving the indication, a command from a set of commands sent by the host device that will violate the timing threshold.

[0117] The delay identifier 725 may identify a command-to-indication delay associated with a duration between when the host device transmits the command and when the indication is received, wherein identifying the command associated with the indication is based on identifying the command-to-indication delay. In some examples, the delay identifier 725 may identify the command-to-indication delay associated with a duration between when the host device transmits the command and when the indication is received based at least in part on a difference between a first time when the training command is transmitted and a second time when the error signal is received, wherein identifying the command associated with the indication is based on identifying the command-to-indication delay. In some examples, the delay identifier 725 may store the command-to-error delay for use when identifying the command associated with the indication.

[0118] The training command transmitter 730 may transmit a training command to the memory device, the training command configured to identify a command-to-instruction delay associated with the memory device.

[0119] Figure 8 A flow chart illustrating a method 800 for supporting illegal command detection according to aspects disclosed herein is shown. The operation of the method 800 may be referred to as Figure 1 and 2 The operations of method 800 may be implemented by the controller or components described herein. Figure 6 The controller described (e.g., device memory controller 155 or local memory controller 165) performs. In some examples, the controller may execute an instruction set to control the functional elements of the controller to perform the functions described below. In addition or alternatively, the controller may use dedicated hardware to perform aspects of the functions described below.

[0120] At 805, the controller may receive a command from a host device to perform an access operation on a memory unit of a memory device. The operation of 805 may be performed according to the methods described herein. In some examples, the command may be performed by reference to Figure 6 The described command receiver 610 performs aspects of the operations of 805 .

[0121] At 810, the controller may use a detection component of the memory device to determine that performing an access operation will violate a timing threshold associated with the operation of the memory device. The operation of 810 may be performed according to the methods described herein. In some examples, the reference Figure 6 The described timing threshold determiner 615 performs aspects of the operations of 810 .

[0122] At 815, the controller may transmit to the host device an indication that the memory device executing the command will violate the timing threshold based on determining that the timing threshold will be violated. The operations of 815 may be performed according to the methods described herein. In some examples, the memory device executing the command may be transmitted to the host device based on determining that the timing threshold will be violated. Figure 6The described error indication transmitter 620 performs aspects of the operation of 815 .

[0123] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, means, or instructions for: receiving a command from a host device to perform an access operation on a memory unit of a memory device; determining, using a detection component of the memory device, that performing the access operation will violate a timing threshold associated with an operation of the memory device; and transmitting an indication to the host device that executing the command on the memory device will violate the timing threshold based at least in part on determining that the timing threshold will be violated.

[0124] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for: refraining from performing the access operation based at least in part on determining using the detection component that the timing threshold will be violated, wherein transmitting the indication is based at least in part on refraining from performing the access operation.

[0125] Some instances of the method 800 and apparatus described herein may further include operations, features, devices, or instructions for: identifying the command received from the host device after receiving the command; and selecting the timing threshold from a set of timing thresholds based at least in part on the command, wherein determining whether the timing threshold will be violated is based at least in part on selecting the timing threshold.

[0126] Some instances of the method 800 and apparatus described herein may further include operations, features, devices, or instructions for selecting multiple timing thresholds from the timing threshold set based at least in part on the command, wherein determining whether the timing threshold will be violated includes determining whether at least one of the multiple timing thresholds will be violated.

[0127] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for: locking a group associated with the memory cell to prevent additional operations from being performed on the group based at least in part on a determination that the timing threshold will be violated, wherein the indication is used to indicate that the group is locked.

[0128] Some examples of method 800 and apparatus described herein may additionally include operations, features, means, or instructions for recognizing that the memory device has completed a current access operation, wherein locking the group occurs after completion of the current access operation.

[0129] Some examples of the method 800 and apparatus described herein may additionally include operations, features, means, or instructions for: based at least in part on transmitting the indication, receiving from the host device a message including information configured to unlock the group to enable additional operations to be performed on the group.

[0130] Some examples of the method 800 and apparatus described herein may additionally include operations, features, means, or instructions for determining that the command is a training command, wherein receiving the command occurs during initialization of the memory device.

[0131] Some instances of the method 800 and apparatus described herein may further include operations, features, devices, or instructions for: identifying a state of a group associated with the memory unit based at least in part on receiving the command, wherein transmitting the indication to the host device is based at least in part on the state of the group when the command is received.

[0132] In some examples of the methods 800 and apparatus described herein, the memory device includes a group having one or more rows of memory cells, wherein at least one of the one or more rows includes the memory cell.

[0133] Some instances of the method 800 and apparatus described herein may further include operations, features, devices, or instructions for determining that a row of a group of the memory device is open, the group being precharged and has not yet passed tRP, or has not yet passed tRFC associated with a refresh command, or any combination thereof, wherein the command comprises a row activate command.

[0134] Some instances of the method 800 and apparatus described herein may further include operations, features, devices, or instructions for determining that a row of a group of the memory device is not open, that a row of the group is open and has not passed tRAS, has not passed tWR associated with a write command, has not passed tRTP associated with a read command, or any combination thereof, wherein the command comprises a row precharge command.

[0135] Some instances of the method 800 and apparatus described herein may further include operations, features, devices, or instructions for determining that a group of the memory device is idle or being precharged, that a row of the group is open and tRCDWR has not passed, tCCD associated with a previous write command has not passed, tRTW associated with a previous read command has not passed, or any combination thereof, wherein the command comprises a write command.

[0136] Some examples of the method 800 and apparatus described herein may further include operations, features, devices, or instructions for determining that a group of the memory device is idle or being precharged, that the group is open and has not yet passed tRCDRD, has not yet passed tCCD associated with a previous read command, has not yet passed tWTR associated with a previous write command, or any combination thereof, wherein the command comprises a read command.

[0137] Some examples of method 800 and apparatus described herein may additionally include operations, features, means, or instructions for determining that a row of a group of the memory device is open, the group is being precharged and tRP has not passed, or any combination thereof, wherein the command comprises a refresh command.

[0138] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for: refraining from performing the access operation based at least in part on determining using the detection component that the timing threshold will be violated, wherein transmitting the indication occurs after refraining from performing the access operation.

[0139] In some examples of the method 800 and apparatus described herein, the command includes a row activate command, a row precharge command, a write command, a read command, or a refresh command, or any combination thereof.

[0140] In some examples of the method 800 and apparatus described herein, the timing threshold includes tRC, tRAS, tRCDRD, tRCDWR, tRTP, tWR, tRP, tRFC, tCCD, tRTW, tWTR, or any combination thereof.

[0141] In some examples of the methods 800 and apparatus described herein, the memory device comprises a DRAM memory device.

[0142] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, means, or instructions for: receiving a command from a host device to perform an access operation on at least one memory cell of a group; determining that performing the access operation will violate a timing threshold associated with accessing the at least one memory cell; and transmitting an error signal to the host device indicating that the memory device cannot perform the command received from the host device based at least in part on determining that the timing threshold will be violated.

[0143] Fig. 9 A flow chart illustrating a method 900 for supporting illegal command detection according to aspects disclosed herein is shown. The operation of the method 900 may be referred to as Figure 1 and 2The operations of method 900 may be implemented by the controller or components thereof described herein. Figure 6 The controller described (e.g., device memory controller 155 or local memory controller 165) performs. In some examples, the controller may execute an instruction set to control the functional elements of the controller to perform the functions described below. In addition or alternatively, the controller may use dedicated hardware to perform aspects of the functions described below.

[0144] At 905, the controller may receive a command from a host device to perform an access operation on a memory unit of a memory device. The operation of 905 may be performed according to the methods described herein. In some examples, the command may be performed by reference to Figure 6 The described command receiver 610 performs aspects of the operations of 905 .

[0145] At 910, the controller may use a detection component of the memory device to determine that performing an access operation will violate a timing threshold associated with the operation of the memory device. The operation of 910 may be performed according to the methods described herein. In some examples, the reference Figure 6 The described timing threshold determiner 615 performs aspects of the operations of 910 .

[0146] At 915, the controller may transmit to the host device an indication that the memory device executing the command will violate the timing threshold based on determining that the timing threshold will be violated. The operations of 915 may be performed according to the methods described herein. In some examples, the memory device executing the command may be transmitted to the host device based on determining that the timing threshold will be violated. Figure 6 The described error indication transmitter 620 performs aspects of the operation of 915 .

[0147] At 920, the controller may refrain from performing the access operation based on determining that a timing threshold will be violated using the detection component, wherein transmitting the indication is based on refraining from performing the access operation. The operations of 920 may be performed according to the methods described herein. In some examples, the access operation may be performed by reference to Figure 6 The described operation component 625 performs aspects of the operation of 920.

[0148] Fig.10 A flow chart illustrating a method 1000 for supporting illegal command detection according to aspects disclosed herein is shown. The operation of the method 1000 may be referred to as Figure 1 and 2 The described host device (eg, external memory controller 105) or its components are implemented. For example, the operations of method 1000 may be performed by reference to Figure 7 The described device (e.g., a host device) performs. In some examples, the device may execute an instruction set to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the device may use dedicated hardware to perform aspects of the functions described below.

[0149] At 1005, the host device may transmit a command to perform an access operation on a memory unit of the memory device. The operation of 1005 may be performed according to the methods described herein. In some examples, the command may be executed by reference to Figure 7 The described command transmitter 710 performs aspects of the operations of 1005.

[0150] At 1010, the host device may receive an indication that executing a command to the memory device will violate a timing threshold associated with an operation of the memory device based on determining that the timing threshold will be violated. The operations of 1010 may be performed according to the methods described herein. In some examples, the host device may receive an indication that executing a command to the memory device will violate a timing threshold associated with an operation of the memory device. Figure 7 The described error indication receiver 715 performs aspects of the operations of 1010 .

[0151] In some examples, an apparatus as described herein may perform one or more methods, such as method 1000. The apparatus may include features, means, or instructions for transmitting, from a host device, a command to perform an access operation on a memory unit of a memory device; and receiving, by the host device, an indication that executing the command on the memory device will violate a timing threshold associated with an operation of the memory device based at least in part on a determination that the timing threshold will be violated.

[0152] Some examples of the method 1000 and apparatus described herein may additionally include operations, features, means, or instructions for: identifying the command from a plurality of commands sent by the host device that will violate the timing threshold based at least in part on receiving the indication.

[0153] Some instances of the method 1000 and apparatus described herein may further include operations, features, devices, or instructions for identifying a command-to-indication delay associated with a duration between when the host device transmits the command and when the indication is received, wherein identifying the command associated with the indication is based at least in part on identifying the command-to-indication delay.

[0154] Some examples of the method 1000 and apparatus described herein may additionally include operations, features, devices, or instructions for: transmitting to the memory device a training command configured to identify a command-to-indication delay associated with the memory device; receiving an error signal from the memory device based at least in part on transmitting the training command; and identifying a command-to-indication delay associated with a duration between when the host device transmits the command and when the indication is received based at least in part on a difference between a first time when the training command is transmitted and a second time when the error signal is received, wherein identifying the command associated with the indication is based at least in part on identifying the command-to-indication delay.

[0155] Some examples of the method 1000 and apparatus described herein may additionally include operations, features, means, or instructions for storing the command-to-error delay for use when identifying a command associated with an indication.

[0156] Some examples of the method 1000 and apparatus described herein may additionally include operations, features, means, or instructions for: resending, by the host device, the command to the memory device based at least in part on receiving the indication.

[0157] Fig.11 A flowchart illustrating a method 1100 for supporting illegal command detection according to aspects disclosed herein is shown. The operation of the method 1100 may be referred to as Figure 1 and 2 The described host device (eg, external memory controller 105) or its components are implemented. For example, the operations of method 1100 may be performed by reference to Figure 7 The described device (e.g., a host device) performs. In some examples, the device may execute an instruction set to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the device may use dedicated hardware to perform aspects of the functions described below.

[0158] At 1105, the host device may transmit a command to perform an access operation on a memory unit of the memory device. The operation of 1105 may be performed according to the methods described herein. In some examples, the command may be executed by reference to Figure 7 Aspects of the operations of command transmitter 710 to perform 1105 are described.

[0159] At 1110, the host device may receive an indication that executing a command on the memory device will violate a timing threshold associated with an operation of the memory device based on determining that the timing threshold will be violated. The operations of 1110 may be performed according to the methods described herein. In some examples, the host device may receive an indication that executing a command on the memory device will violate a timing threshold associated with an operation of the memory device. Figure 7The described error indication receiver 715 performs aspects of the operations of 1110 .

[0160] At 1115, the host device may identify a command from the set of commands sent by the host device that will violate the timing threshold based on receiving the indication. The operation of 1115 may be performed according to the methods described herein. In some examples, the command may be referred to as Figure 7 The described command identifier 720 performs aspects of the operations of 1115 .

[0161] An apparatus is described. In some examples, the apparatus may include a memory cell array including one or more storage components; a command decoder configured to receive a command from a host device to perform an access operation on a memory cell of the memory cell array; a detection component configured to determine whether performing the access operation will violate a timing threshold associated with the memory cell; and a transmitter configured to transmit an indication that performing the command will violate the timing threshold based at least in part on determining using the detection component that the timing threshold will be violated.

[0162] In some examples, the apparatus may include a selection component configured to select the timing threshold from a set of timing thresholds based at least in part on the type of the command received from the host device, wherein the detection component is configured to determine whether the timing threshold will be violated based at least in part on the selection of the timing threshold by the selection component. In some examples, the detection component may include one or more analog timers, one or more digital counters, or any combination thereof configured to output one or more timings associated with the operation of the memory cell array, wherein the detection component is configured to compare at least one of the one or more timings associated with the operation of the memory cell array with the type of the command. In some examples, the detection component is further configured to cause the memory cell array to refrain from performing the access operation based at least in part on the comparison of the at least one timing associated with the operation of the memory cell array with the type of the command.

[0163] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate signaling as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a bus of signals, where the bus may have various bit widths.

[0164] As used herein, the term "virtual ground" refers to a node of a circuit being maintained at a voltage of approximately zero volts (0V) but not directly coupled to the ground. Thus, the voltage of the virtual ground may fluctuate over time and return to approximately 0V in a steady state. Virtual ground may be implemented using various electronic circuit elements such as a voltage divider consisting of an operational amplifier and a resistor. Other implementations are also possible. "Virtual ground" or "virtual ground" refers to a connection to approximately 0V.

[0165] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between the components that are in electronic communication with each other (or in conductive contact or connected or coupled) may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some cases, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as a switch or transistor.

[0166] The term "coupled" refers to the condition of moving from an open circuit relationship between components, in which signals are currently unable to communicate between components through conductive paths, to a closed circuit relationship between components, in which signals are able to communicate between components through conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that previously did not permit signal flow.

[0167] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, components separated by a switch positioned between two components are isolated from one another when the switch is open. When a controller separates two components, the controller implements a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0168] The term "layer" as used herein refers to a geometrically structured layer or sheet, each layer may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer may be a three-dimensional structure, such as a film, in which two dimensions are greater than the third dimension. A layer may include different elements, components, and / or materials. In some cases, a layer may be composed of two or more sublayers. In some of the drawings, two dimensions of a three-dimensional layer are depicted for illustrative purposes. However, those skilled in the art will recognize that a layer is three-dimensional in nature.

[0169] As used herein, the term "substantially" means that the modified characteristic (such as a verb or adjective modified by the term substantially) is not necessarily absolute but is close enough to obtain the advantage of the characteristic.

[0170] As used herein, the term "electrode" may refer to an electrical conductor, and in some cases, may serve as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, a wire, a conductive line, a conductive layer, etc., that provides an electrically conductive path between elements or components of a memory array.

[0171] The term "photolithography" as used herein may refer to a process of patterning with a photoresist material and exposing such material using electromagnetic radiation. For example, a photoresist material may be formed on a substrate material by, for example, spin coating the photoresist on the substrate material. A pattern may be created in the photoresist by exposing the photoresist to radiation. For example, the pattern may be defined by a photomask that spatially depicts where the radiation exposes the photoresist. For example, the exposed photoresist areas may then be removed by chemical treatment, leaving the desired pattern. In some cases, the exposed areas may remain, and the unexposed areas may be removed.

[0172] As used herein, the term "short" refers to a relationship between components in which a conductive path is established between the components by activating a single intermediate component between the two components in question. For example, a first component shorted to a second component may exchange signals with the second component when a switch between the two components is closed. Thus, shorting may be a dynamic operation that enables the flow of charge between components (or lines) in electronic communication.

[0173] The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0174] The switch assembly or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by a conductive material (e.g., a metal). The source and drain may be conductive and may include a heavily doped (e.g., degenerate) semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (e.g., most of the carriers are signals), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0175] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred to" or "superior to" other examples. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0176] In the accompanying drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0177] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0178] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0179] The techniques described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the function may be stored as one or more instructions or codes on a computer-readable medium or transmitted by a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or any combination of these. The features of the implementation functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations. Also, as used herein, included in the claims, the "or" used in the list of items (e.g., a list of items starting with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0180] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media may be any available media that can be accessed by a general or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or any other non-transitory media that can be used to carry or store the desired program code device in the form of an instruction or data structure and can be accessed by a general or special-purpose computer or a general or special-purpose processor. And, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, the coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0181] The description herein is provided to enable a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: receiving a command from a host device to perform an access operation on a memory unit of a memory device; determining, using a detection component of the memory device, that performing the access operation will violate a timing threshold associated with an operation of the memory device; transmitting, based at least in part on determining that the timing threshold will be violated, to the host device an indication that execution of the command on the memory device will violate the timing threshold; as well as Based at least in part on determining that the timing threshold will be violated, a group associated with the memory cells is locked to prevent additional operations from being performed on the group, wherein the indication transmitted to the host device is used to indicate that the group is locked.

2. The method according to claim 1, further comprising: Based at least in part on determining, using the detection component, that the timing threshold will be violated, refraining from performing the access operation, wherein transmitting the indication is based at least in part on refraining from performing the access operation.

3. The method of claim 1, further comprising: identifying the command received from the host device after receiving the command; and The timing threshold is selected from a set of timing thresholds based at least in part on the command, wherein determining whether the timing threshold will be violated is based at least in part on selecting the timing threshold.

4. The method of claim 3, wherein selecting the timing threshold comprises: A plurality of timing thresholds are selected from the set of timing thresholds based at least in part on the command, wherein determining whether the timing threshold will be violated includes determining whether at least one of the plurality of timing thresholds will be violated.

5. The method of claim 1, further comprising: Identifying that the memory device has completed a current access operation, wherein locking the group occurs after the current access operation is completed.

6. The method of claim 1, further comprising: Based at least in part on transmitting the indication, a message is received from the host device including information configured to unlock the group to enable additional operations to be performed on the group.

7. The method of claim 1, further comprising: The command is determined to be a training command, wherein receiving the command occurs during initialization of the memory device.

8. The method of claim 1, further comprising: Based at least in part on receiving the command, a state of the group associated with the memory unit is identified, wherein transmitting the indication to the host device is based at least in part on the state of the group when the command is received.

9. The method of claim 1, wherein the group comprises a group of one or more rows of memory cells, wherein at least one of the one or more rows includes the memory cell.

10. The method of claim 1, wherein the command comprises a row activate command, and wherein determining that the timing threshold will be violated comprises: It is determined that a row of the bank of the memory device is open, the bank is being precharged and a row precharge time (tRP) has not elapsed, or a row refresh cycle time (tRFC) associated with a refresh command has not elapsed, or any combination thereof.

11. The method of claim 1 , wherein the command comprises a row precharge command, and wherein determining that the timing threshold will be violated comprises: Determining that a row of the group of the memory device is not open, a row of the group is open and a row address enable time (tRAS) has not passed, a write recovery time (tWR) associated with a write command has not passed, a read to precharge time (tRTP) associated with a read command has not passed, or any combination thereof.

12. The method of claim 1 , wherein the command comprises a write command, and wherein determining that the timing threshold will be violated comprises: It is determined that the group of the memory device is idle or being precharged, that a row of the group is open and an activate-to-write delay time (tRCDWR) has not yet passed, a column-to-column delay time (tCCD) associated with a previous write command has not yet passed, a read-to-write time (tRTW) associated with a previous read command has not yet passed, or any combination thereof.

13. The method of claim 1 , wherein the command comprises a read command, and wherein determining that the timing threshold will be violated comprises: It is determined that the group of the memory device is idle or being precharged, the group is open and an activate to read delay time (tRCDRD) has not yet passed, a column to column delay time (tCCD) associated with a previous read command has not yet passed, a write to read time (tWTR) associated with a previous write command has not yet passed, or any combination thereof.

14. The method of claim 1 , wherein the command comprises a refresh command, and wherein determining that the timing threshold will be violated comprises: It is determined that a row of the bank of the memory device is open, the bank is being precharged and a row precharge time (tRP) has not yet elapsed, or any combination thereof.

15. The method of claim 1, further comprising: Based at least in part on determining, using the detection component, that the timing threshold will be violated, refraining from performing the access operation, wherein transmitting the indication occurs after refraining from performing the access operation. 16 . The method of claim 1 , wherein the command comprises a row activate command, a row precharge command, a write command, a read command, or a refresh command, or any combination thereof.

17. The method of claim 1 , wherein the timing thresholds comprise row cycle time (tRC), row address strobe time (tRAS), activate to read delay time (tRCDRD), activate to write delay time (tRCDWR), read to precharge time (tRTP), write recovery time (tWR), row precharge time (tRP), row refresh cycle time (tRFC), column to column delay time (tCCD), read to write time (tRTW), write to read time (tWTR), or any combination thereof.

18. The method of claim 1, wherein the memory device comprises a dynamic random access memory (DRAM) memory device.

19. An apparatus comprising: a memory cell array comprising one or more memory elements; a command decoder configured to receive a command from a host device to perform an access operation on a memory cell of the memory cell array; a detection component configured to determine whether execution of the access operation will violate a timing threshold associated with the memory unit, wherein based at least in part on the detection component determining that the timing threshold will be violated by execution of the access operation, the group associated with the memory unit is configured to lock out to prevent additional operations from being performed on the group; and A transmitter is configured to transmit an indication that the group is locked and that execution of the command will violate the timing threshold based at least in part on determining using the detection component that the timing threshold will be violated.

20. The apparatus of claim 19, further comprising: A selection component is configured to select the timing threshold from a set of timing thresholds based at least in part on the type of the command received from the host device, wherein the detection component is configured to determine whether the timing threshold will be violated based at least in part on the timing threshold selected by the selection component.

21. The apparatus of claim 19, wherein the detection component comprises: one or more analog timers, one or more digital counters, or any combination thereof configured to output one or more timings associated with the operation of the memory cell array, wherein the detection component is configured to compare at least one of the one or more timings associated with the operation of the memory cell array with the type of the command.

22. The apparatus of claim 21, wherein the detection component is further configured to cause the memory cell array to refrain from performing the access operation based at least in part on the detection component comparing the at least one timing associated with the operation of the memory cell array and the type of the command.

23. A method comprising: transmitting, from a host device, a command to perform an access operation on a memory unit of a memory device; and Based at least in part on a determination that a timing threshold associated with an operation of the memory device will be violated, receiving, by the host device, an indication that execution of the command on the memory device will violate the timing threshold, wherein based at least in part on the determination that the timing threshold will be violated, the indication is to instruct a group of the memory device associated with the memory unit to lock out from performing additional operations.

24. The method of claim 23, further comprising: Based at least in part on receiving the indication, the command that will violate the timing threshold is identified from a plurality of commands sent by the host device.

25. The method of claim 24, further comprising: A command-to-indication delay associated with a duration between when the host device transmits the command and when the indication is received is identified, wherein identifying the command associated with the indication is based at least in part on identifying the command-to-indication delay.

26. The method of claim 25, further comprising: The command-to-indication delay is stored for use when identifying the command associated with the indication.

27. The method of claim 24, further comprising: transmitting to the memory device a training command configured to identify a command associated with the memory device to indicate a delay; receiving an error signal from the memory device based at least in part on transmitting the training command; and Based at least in part on a difference between a first time the training command is transmitted and a second time the error signal is received, identifying the command-to-indication delay associated with a duration between when the host device transmits the command and when the indication is received, wherein identifying the command associated with the indication is based at least in part on identifying the command-to-indication delay.

28. The method of claim 23, further comprising: Based at least in part on receiving the indication, the command is resent, by the host device, to the memory device.

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