Method for manufacturing a semiconductor package

Abstract

A method for manufacturing a semiconductor package is disclosed, the method comprising: forming a release layer on a first carrier substrate, wherein the release layer comprises a first portion and a second portion, wherein the first portion has a first thickness and the second portion has a second thickness that is thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer comprises wiring and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate to the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching solder balls to the redistribution layer exposed by the removal of the barrier layer and the second portion of the release layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0018400, filed on February 14, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Exemplary embodiments of the present invention relate to a method for manufacturing semiconductor packages. Background Technology

[0003] As the realization of high-performance components has become feasible, semiconductor chip sizes have increased, and semiconductor package sizes have increased accordingly. Furthermore, the thickness of semiconductor packages has decreased, resulting in thinner electronic devices.

[0004] Semiconductor packaging is typically a process of encapsulating semiconductor chips (or bare semiconductor dies) to electrically connect them to electronic devices. A fan-out wafer-level packaging (FOWLP) type semiconductor package has been proposed, in which, as the size of the semiconductor chip decreases, the input / output terminals of the semiconductor package are placed outside the semiconductor chip using a redistribution layer. Because FOWLP type semiconductor packages have a relatively simple packaging process and can achieve small thicknesses, they can be relatively thin and possess excellent thermal and electrical characteristics. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor package is disclosed, the method comprising the steps of: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness and the second portion has a second thickness greater than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes a plurality of wirings and an insulating layer surrounding the plurality of wirings; mounting a semiconductor chip on the redistribution layer for electrical connection to the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate to the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching solder balls to the redistribution layer exposed by removing the second portion of the barrier layer and the release layer.

[0006] In an exemplary embodiment of the present invention, the barrier layer comprises a metallic material.

[0007] In an exemplary embodiment of the present invention, the metallic material includes copper (Cu).

[0008] In an exemplary embodiment of the present invention, the barrier layer comprises the same material as the plurality of wirings.

[0009] In an exemplary embodiment of the present invention, the step of forming a release layer includes: forming a first release layer having a first thickness on a first carrier substrate; and forming a second release layer on the first release layer, wherein the second release layer has a third thickness and includes an opening exposing at least a portion of the first release layer, wherein the opening overlaps with the first portion.

[0010] In an exemplary embodiment of the present invention, the third thickness ranges from about 3 μm to about 8 μm.

[0011] In an exemplary embodiment of the present invention, the step of removing the peeling layer includes using a laser.

[0012] In an exemplary embodiment of the present invention, the laser cannot enter the redistribution layer due to the blocking layer.

[0013] In an exemplary embodiment of the present invention, the step of removing a second portion of the barrier layer and the stripping layer exposes at least a portion of the plurality of wirings of the redistribution layer, and solder balls are electrically connected to the exposed plurality of wirings.

[0014] In an exemplary embodiment of the present invention, the release layer comprises the same material as the insulating layer.

[0015] In an exemplary embodiment of the present invention, the release layer comprises a photosensitive insulating material.

[0016] According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor package is disclosed, the method comprising the steps of: forming a first release layer on a first carrier substrate; forming a second release layer on the first release layer, wherein the second release layer includes an opening for exposing at least a portion of the first release layer; forming a barrier layer on the second release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes a plurality of wirings and an insulating layer surrounding the plurality of wirings; mounting a first semiconductor chip on the redistribution layer, wherein the first semiconductor chip is electrically connected to the redistribution layer; attaching a second carrier substrate to the first semiconductor chip; removing the first carrier substrate, the first release layer, and the second release layer using a laser; removing the barrier layer; and attaching solder balls to the location of the redistribution layer where the second release layer has been removed, wherein the first release layer and the second release layer comprise a photosensitive insulating material.

[0017] In an exemplary embodiment of the present invention, the first carrier substrate is a glass substrate.

[0018] In an exemplary embodiment of the present invention, the second peeling layer has a thickness ranging from about 3 μm to about 8 μm.

[0019] In an exemplary embodiment of the present invention, the barrier layer comprises a metallic material.

[0020] In an exemplary embodiment of the present invention, the method for manufacturing a semiconductor package further includes, after mounting a first semiconductor chip on a redistribution layer: forming a first molding layer on the redistribution layer, wherein the first molding layer at least partially surrounds the first semiconductor chip and includes a through-hole penetrating the first molding layer; and mounting a second semiconductor chip on the first molding layer, wherein a second carrier substrate is attached to the second semiconductor chip.

[0021] In an exemplary embodiment of the present invention, the second semiconductor chip is electrically connected to the redistribution layer via a through-hole.

[0022] In an exemplary embodiment of the present invention, the method for manufacturing a semiconductor package further includes, after mounting a first semiconductor chip on a redistribution layer: forming a first molding layer on the redistribution layer, wherein the first molding layer at least partially surrounds the first semiconductor chip; forming a connection substrate on an opposite side of the first semiconductor chip, wherein the connection substrate includes a plurality of subwires and a substrate layer at least partially surrounding the plurality of subwires; and mounting a package on the first molding layer, wherein the package includes a substrate, a second semiconductor chip mounted on the substrate, and a second molding layer at least partially surrounding the second semiconductor chip on the substrate, wherein a second carrier substrate is attached to the second molding layer, and the second semiconductor chip is electrically connected to the redistribution layer via the substrate and the connection substrate.

[0023] According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor package is disclosed, the method comprising the steps of: forming a first release layer on a first carrier substrate; forming a second release layer on the first release layer, wherein the second release layer includes a first opening for exposing at least a portion of an upper surface of the first release layer; forming a barrier layer on the second release layer, wherein the barrier layer extends along the upper surface of the second release layer and includes a metallic material; forming an electrode pad support layer on the barrier layer, wherein the electrode pad support layer exposes at least a portion of the barrier layer and includes a second opening not overlapping the first opening; forming a redistribution layer on the electrode pad support layer, wherein the redistribution layer includes a plurality of wirings and an insulating layer surrounding the plurality of wirings; mounting a semiconductor chip on the redistribution layer; forming a molding layer surrounding the semiconductor chip on the redistribution layer; attaching a second carrier substrate to the molding layer; removing the first carrier substrate, the first release layer, and the second release layer using a laser; removing the barrier layer; forming solder balls at locations where the second release layer has been removed; and removing the second carrier substrate, wherein the first release layer, the second release layer, and the insulating layer comprise a photosensitive insulating material.

[0024] In an exemplary embodiment of the present invention, the barrier layer comprises the same material as the plurality of wirings. Attached Figure Description

[0025] The above and other features of the present invention will become more apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0026] Figure 1 This is a diagram illustrating a semiconductor package manufactured by a method for manufacturing a semiconductor package, according to an exemplary embodiment of the concept of the present invention;

[0027] Figure 2 yes Figure 1 A magnified view of region S1;

[0028] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention.

[0029] Figure 13 and Figure 14 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor package according to an exemplary embodiment of the concept of the present invention;

[0030] Figure 15 , Figure 16 , Figure 17 and Figure 18 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention.

[0031] Figure 19 This is a diagram illustrating a semiconductor package manufactured by a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention; and

[0032] Figure 20 This is a diagram illustrating a semiconductor package manufactured by a method for manufacturing a semiconductor package according to an exemplary embodiment of the concept of the present invention. Detailed Implementation

[0033] Figure 1 This is a diagram illustrating a semiconductor package manufactured by a method for manufacturing a semiconductor package according to an exemplary embodiment of the concept of the present invention.

[0034] Reference Figure 1 A semiconductor package manufactured by a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention may include a redistribution layer 100, a first semiconductor chip 200, a first molding layer 300, and solder balls 500.

[0035] The redistribution layer 100 may include a first surface 100a and a second surface 100b facing each other. For example, the first surface 100a may be the upper surface of the redistribution layer 100 relative to the second direction D2, and the second surface 100b may be the lower surface of the redistribution layer 100 relative to the second direction D2.

[0036] The redistribution layer 100 may include an electrode pad 134, an electrode pad support layer 130, multiple wirings 136, 146, 156 and 174, multiple vias 142 and 152, and multiple insulating layers 132, 140, 150, 160 and 170.

[0037] The electrode pad support layer 130 may form the second surface 100b of the redistribution layer 100. For example, the lower surface of the electrode support layer 130 may be the lower surface 100b of the redistribution layer 100. The electrode pad support layers 130 may be spaced apart from each other in a first direction D1. The electrode pad support layer 130 may include an insulating material. The electrode pad support layer 130 may include, for example, a photosensitive insulating material (e.g., PID: photoimageable medium). The electrode pad support layer 130 may include, for example, epoxy resin or polyimide. However, the inventive concept is not limited thereto.

[0038] Electrode pads 134 may be formed on the second surface 100b of the redistribution layer 100. Electrode pads 134 may be included in the electrode pad support layer 130. The electrode pads 134 may be spaced apart in the electrode pad support layer 130 in a first direction D1. The lower surface of the electrode pads 134 may be located above the lower surface of the electrode pad support layer 130. Referring below... Figure 2 Provide a detailed description.

[0039] Electrode pad 134 and multiple wirings 136, 146, 156 and 174 may extend along a first direction D1. Electrode pad 134 and multiple wirings 136, 146, 156 and 174 may be spaced apart from each other in the first direction D1. Here, the first direction D1 may represent a direction substantially perpendicular to the second direction D2.

[0040] Multiple wirings 136, 146, 156, and 174 can be sequentially stacked on the electrode pad 134 from the second surface 100b to the first surface 100a of the redistribution layer 100. The wirings 136, 146, 156, and 174 can be spaced apart from each other in the second direction D2. For example, a first wiring 136 can be formed on the electrode pad 134, and a second wiring 146 can be formed on the first wiring 136. Additionally, a third wiring 156 can be formed on the second wiring 146, and a fourth wiring 174 can be formed on the third wiring 156. For example, the wirings 136, 146, 156, and 174 can be formed at different levels.

[0041] Multiple wirings 136, 146, 156, and 174 may include patterns that perform various functions. Multiple wirings 136, 146, 156, and 174 may include, for example, ground patterns, power patterns, signal patterns, etc. Signal patterns may input and output various electrical signals (such as data electrical signals), but may not input and output ground signals and power signals.

[0042] For example, the widths of the plurality of vias 142 and 152 may decrease from the first surface 100a toward the second surface 100b; however, the inventive concept is not limited thereto, and the widths of the plurality of vias 142 and 152 may be substantially the same. A plurality of wirings 136, 146, 156, and 174 may be electrically connected to each other through the plurality of vias 142 and 152. The plurality of vias 142 and 152 may interconnect the plurality of wirings 136, 146, 156, and 174 formed at different levels. For example, a first via 142 may penetrate a second insulating layer 140 to connect a first wiring 136 and a second wiring 146 to each other. A second via 152 may penetrate a third insulating layer 150 to connect a second wiring 146 and a third wiring 156 to each other.

[0043] Electrode pad 134, multiple wirings 136, 146, 156, and 174, and multiple vias 142 and 152 may comprise a conductive material. Electrode pad 134 may comprise the same material as the multiple wirings 136, 146, 156, and 174, and the multiple vias 142 and 152. Electrode pad 134, multiple wirings 136, 146, 156, and 174, and the multiple vias 142 and 152 may comprise, for example, but not limited to, copper (Cu). In another example, electrode pad 134, multiple wirings 136, 146, 156, and 174, and the multiple vias 142 and 152 may comprise at least one of aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof.

[0044] Multiple insulating layers 132, 140, 150, 160, and 170 may surround multiple wirings 136, 146, 156, and 174, as well as multiple vias 142 and 152. For example, the multiple wirings 136, 146, 156, and 174, as well as the multiple vias 142 and 152, may be formed within the multiple insulating layers 132, 140, 150, 160, and 170. For example, the first wiring 136 may be formed within the first insulating layer 132.

[0045] The plurality of insulating layers 132, 140, 150, 160, and 170 may comprise insulating materials. For example, the plurality of insulating layers 132, 140, 150, 160, and 170 may comprise the same material as the electrode pad support layer 130. For example, the plurality of insulating layers 132, 140, 150, 160, and 170 may comprise, for example, photosensitive insulating materials. The plurality of insulating layers 132, 140, 150, 160, and 170 may comprise, for example, epoxy resin or polyimide. However, the inventive concept is not limited thereto.

[0046] The multiple wirings 136, 146, 156 and 174, multiple vias 142 and 152, and multiple insulating layers 132, 140, 150, 160 and 170 shown in the attached figures are merely examples, and the number, location, thickness and / or arrangement of each of the multiple wirings 136, 146, 156 and 174, multiple vias 142 and 152, and multiple insulating layers 132, 140, 150, 160 and 170 are not limited thereto, but can be various.

[0047] A first semiconductor chip 200 may be mounted on a first surface 100a of a redistribution layer 100. The redistribution layer 100 may include a fan-out region (e.g., a first fan-out region) and another fan-out region (e.g., a second fan-out region). For example, the first fan-out region is stacked with the first semiconductor chip 200, and the other fan-out region is not stacked with the first semiconductor chip 200. The other fan-out region is the region other than the stacked region (e.g., the first fan-out region). For example, a semiconductor package according to an exemplary embodiment of the present invention may be a fan-out semiconductor package. Although a fan-out semiconductor package is shown in the accompanying drawings as an exemplary embodiment of the present invention, the present invention is not limited thereto and may be, for example, a wafer-level package (WLP).

[0048] The first semiconductor chip 200 can be a logic chip or a memory chip. The first semiconductor chip 200 can be, but is not limited to, an application processor (AP) such as a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), digital signal processor, encryption processor, microprocessor, and microcontroller, and can be a logic chip such as an analog-to-digital converter (ADC) or application-specific integrated circuit (ASIC). In another example, the first semiconductor chip 200 can be a memory chip such as volatile memory (e.g., DRAM) or non-volatile memory (e.g., ROM or flash memory). Additionally, the first semiconductor chip 200 can be configured by combining logic chips, combining memory chips, and combining logic chips and memory chips.

[0049] The first semiconductor chip 200 may include a first connection pad 210. The first connection pad 210 may be disposed on the lower surface of the first semiconductor chip 200. However, the inventive concept is not limited thereto, and the first connection pad 210 may protrude completely or partially from the first semiconductor chip 200 to the first surface 100a of the redistribution layer 100. The first connection pads 210 may be formed to be spaced apart from each other in a first direction D1.

[0050] The first connection pad 210 can be electrically connected to a circuit formed in the first semiconductor chip 200. The first connection pad 210 may include a conductive material. The first connection pad 210 may include a metallic material such as aluminum (Al).

[0051] A first connection terminal 180 may be formed on a first connection pad 210. The first connection terminal 180 may be disposed between a first surface 100a of the redistribution layer 100 and the first connection pad 210. The first connection terminal 180 may contact a fourth wiring 174 exposed on the first surface 100a of the redistribution layer 100. The first connection terminal 180 may contact the first connection pad 210. The first connection terminal 180 may electrically connect the first semiconductor chip 200 and the redistribution layer 100 to each other.

[0052] The first connection terminal 180 may be, for example, a solder ball, a solder block, or a combination thereof. Although the first connection terminal 180 is shown in the drawings as having a spherical shape, the inventive concept is not limited thereto. Although the first connection terminal 180 may include at least one of, for example, tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), and combinations thereof, the inventive concept is not limited thereto.

[0053] The first molding layer 300 may cover both the side surface and the top surface of the first semiconductor chip 200. The first molding layer 300 may at least partially surround the side surface and the top surface of the first semiconductor chip 200, and may be disposed between the first semiconductor chip 200 and the first surface 100a of the redistribution layer 100. The first molding layer 300 may surround the first connection terminal 180 and may fill the space between adjacent first connection terminals 180. The side surface of the first molding layer 300 and the side surface of the redistribution layer 100 may be coplanar.

[0054] Although the first molding layer 300 is shown in the accompanying drawing as covering the upper surface of the first semiconductor chip 200, the upper surface of the first molding layer 300 and the upper surface of the first semiconductor chip 200 may be coplanar. For example, the upper surface of the first molding layer 300 may be partially etched by a planarization process, thereby exposing the upper surface of the first semiconductor chip 200.

[0055] The first molding layer 300 may include, for example, an epoxy molding compound (EMC) or two or more silicon hybrid materials.

[0056] Solder balls 500 may be disposed on the second surface 100b of the redistribution layer 100. Solder balls 500 may protrude from the second surface 100b of the redistribution layer 100. Solder balls 500 may contact the electrode pads 134 exposed by the second surface 100b of the redistribution layer 100. Therefore, solder balls 500 may be electrically connected to the redistribution layer 100. Additionally, semiconductor packages may be electrically connected to external devices via solder balls 500.

[0057] Although the width of the solder ball 500 in the first direction D1 is shown in the accompanying drawing as being the same as the width of the electrode pad 134 in the first direction D1, the inventive concept is not limited thereto. For example, the width of the solder ball 500 in the first direction D1 may be greater than or less than the width of the electrode pad 134 in the first direction D1.

[0058] The number, shape, size, and arrangement of the solder balls 500 shown in the accompanying drawings are not limited to these, but can be quite varied. For example, the solder balls 500 may be substantially the same in size and shape as the first connection terminal 180, or may differ from each other as shown in the accompanying drawings. For example, the size of the solder balls 500 may be larger than the size of the first connection terminal 180.

[0059] Solder balls 500 may be disposed on electrode pad support layer 130. At least a portion of solder balls 500 may contact electrode pad support layer 130. For example, at least a portion of solder balls 500 may be disposed in redistribution layer 100.

[0060] Solder ball 500 may include, for example, but not limited to, at least one of tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), and combinations thereof.

[0061] Figure 2 yes Figure 1 A magnified view of region S1.

[0062] Reference Figure 2 Electrode pad 134 can be disposed on the first wiring 136. The height from the second surface 100b of the redistribution layer 100 to the electrode pad 134 in the second direction D2 can be a first height H1. The height from the second surface 100b of the redistribution layer 100 to the first wiring 136 in the second direction D2 can be a second height H2. The second height H2 can be larger than the first height H1. However, the inventive concept is not limited thereto. For example, the second height H2 can be the same as the first height H1, or the second height H2 can be smaller than the first height H1.

[0063] For example, the electrode pad 134 may protrude from the first wiring 136 toward the second surface 100b of the redistribution layer 100. The electrode pad 134 may not be coplanar with the second surface 100b of the redistribution layer 100, and the electrode pad 134 may be disposed above the second surface 100b of the redistribution layer 100 in the second direction D2.

[0064] The lower surface of the electrode pad support layer 130 may form the second surface 100b of the redistribution layer 100. The electrode pad support layer 130 may be adjacent to the side surface of the electrode pad 134, the lower surface of the first wiring 136, and the lower surface of the first insulating layer 132. For example, the electrode pad support layer 130 may have a second height H2 in the second direction D2.

[0065] The second surface 100b of the redistribution layer 100 may include at least one trench 100t. The trench 100t may be provided by the electrode pad support layer 130 and the electrode pad 134. The trench 100t may expose at least a portion of the electrode pad 134 and at least a portion of the electrode pad support layer 130. The depth of the trench 100t in the second direction D2 may be a first height H1.

[0066] Solder balls 500 can be disposed in trench 100t. Solder balls 500 can be disposed on electrode pads 134 exposed by trench 100t. Solder balls 500 can be adjacent to electrode pads 134.

[0067] The solder ball 500 may include regions disposed within the redistribution layer 100 and regions disposed outside the redistribution layer 100. Furthermore, at least a portion of the solder ball 500 may abut against the electrode pad support layer 130. The electrode pad support layer 130 may surround at least a portion of the solder ball 500. The solder ball 500 may include regions adjacent to the electrode pad support layer 130 and regions not adjacent to the electrode pad support layer 130.

[0068] Therefore, although the semiconductor package manufactured by the method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention is manufactured by, for example, a post-chip process described later, at least a portion of the solder balls 500 can be disposed within the redistribution layer 100. For example, since at least a portion of the solder balls 500 can be surrounded by the electrode pad support layer 130, the bonding reliability between the solder balls 500 and the electrode pads 134 can be increased or improved.

[0069] Figures 3 to 12 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. (Refer to...) Figures 3 to 12 A method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention is described.

[0070] Reference Figure 3 A method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention may include forming a first release layer 112 on a first carrier substrate 105.

[0071] The first carrier substrate 105 may be, for example, a glass substrate. Although the first carrier substrate 105 may include silicon, metal, plastic, ceramic, etc., the inventive concept is not limited thereto.

[0072] The first release layer 112 may be adjacent to the first carrier substrate 105. The first release layer 112 may be formed on the first carrier substrate 105. The thickness of the first release layer 112 in the second direction D2 may be a first thickness t1. For example, the first release layer 112 may be formed by vapor deposition or coating processes.

[0073] The first release layer 112 may include a photosensitive insulating material (e.g., a photoimageable medium: PID). The photosensitive insulating material can be subjected to photolithography and can be fabricated at the wafer level. Therefore, the first release layer 112 can be formed thinner, and the multiple wirings 136, 146, 156, and 174, as well as vias 142 and 152, which will be described later, can be formed with a finer pitch.

[0074] In an exemplary embodiment of the present invention, a first release layer 112 may be formed on a first carrier substrate 105 by means of an adhesive layer. For example, the adhesive layer may be further disposed between the first carrier substrate 105 and the first release layer 112. The adhesive layer may consist of a single layer or multiple layers. The adhesive layer may include, for example, a polymeric material of photothermal conversion (LTHC) that can be removed together with the first carrier substrate 105. In another example, the adhesive layer may include, for example, titanium (Ti).

[0075] Reference Figure 4 A second release layer 114 may be formed on the first release layer 112. The second release layer 114 may expose at least a portion of the first release layer 112. The second release layer 114 may include a first opening 114o that exposes at least a portion of the upper surface of the first release layer 112.

[0076] The second release layer 114 may include, for example, the same material as the first release layer 112. Therefore, a release layer 110 comprising a first region having a first thickness t1 and a second region having a third thickness t3 can be formed on the first carrier substrate 105. The release layer 110 may include the first release layer 112 and the second release layer 114. Here, the second thickness t2 may be a value obtained by adding the first thickness t1 and the third thickness t3.

[0077] The second release layer 114 may include a photosensitive insulating material. The second release layer 114 can be formed to have a third thickness t3 in the second direction D2 by, for example, vapor deposition or coating processes. Subsequently, the first opening 114o can be formed by exposure and development processes performed on the second release layer 114. Here, although the third thickness t3 can be, for example, in the range between about 3 μm and about 8 μm, the inventive concept is not limited thereto.

[0078] Reference Figure 5 A barrier layer 120 may be formed on the release layer 110. The barrier layer 120 may extend along the upper surface of the release layer 110. The barrier layer 120 may be conformally formed on the second release layer 114 and the first opening 114o. For example, the barrier layer 120 may cover the upper surface and side surfaces of the second release layer 114 and may cover the first opening 114o. However, the inventive concept is not limited thereto. For example, the barrier layer 120 may expose the upper surface of the first release layer 112 exposed by the first opening 114o by not covering the first opening 114o.

[0079] The barrier layer 120 may include a metallic material. The barrier layer 120 may include, for example, copper (Cu). In another example, the barrier layer 120 may include, but is not limited to, at least one of aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof.

[0080] The barrier layer 120 can be formed using methods such as physical vapor deposition (PVD), sputtering, and chemical vapor deposition (CVD), but is not limited to these methods.

[0081] Subsequently, referring to Figure 6 An electrode pad support layer 130 may be formed on the barrier layer 120. The electrode pad support layer 130 may expose at least a portion of the barrier layer 120. The electrode pad support layer 130 may include a second opening 130o that exposes at least a portion of the upper surface of the barrier layer 120. The second opening 130o may not overlap with the first opening 114o. For example, the second opening 130o may not be formed on the first opening 114o. For example, the electrode pad support layer 130 may be formed in the first opening 114o. The second opening 130o may expose the upper surface of the barrier layer 120 formed on the second release layer 114.

[0082] The electrode pad support layer 130 may include the same material as the release layer 110. The electrode pad support layer 130 may include, for example, a photosensitive insulating material.

[0083] Reference Figure 7 A first insulating layer 132 can be formed on the electrode pad support layer 130. The first insulating layer 132 may include the same material as the electrode pad support layer 130. The first insulating layer 132 can be patterned by photolithography.

[0084] Reference Figure 8 Electrode pads 134 and first wiring 136 can be formed on electrode pad support layer 130 and first insulating layer 132. For example, electrode pads 134 and first wiring 136 can be formed on barrier layer 120.

[0085] Electrode pad 134 and first wiring 136 may comprise the same material. Electrode pad 134 and first wiring 136 may comprise the same material as the barrier layer 120. For example, barrier layer 120 may comprise copper (Cu). For example, barrier layer 120 may be used as a seed layer to form electrode pad 134 and first wiring 136. In another example, electrode pad 134 and first wiring 136 may comprise, but are not limited to, at least one of aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof.

[0086] For example, the electrode pad 134 and the first wiring 136 can be formed by electroplating. The electrode pad 134 and the first wiring 136 can be formed simultaneously by an inlay process.

[0087] For example, the first wiring 136 can be partially etched using a chemical mechanical polishing (CMP) process. The first wiring 136 can be located at the same level as the first insulating layer 132. For example, the upper surface of the first wiring 136 and the upper surface of the first insulating layer 132 can be coplanar.

[0088] Reference Figure 9 A redistribution layer 100, comprising an electrode pad support layer 130, an electrode pad 134, a first wiring 136, and a first insulating layer 132, can be formed on the barrier layer 120. The redistribution layer 100 may include the electrode pad 134, multiple wirings 136, 146, 156, and 174, multiple vias 142 and 152, and multiple insulating layers 132, 140, 150, 160, and 170.

[0089] Electrode pad 134, multiple wirings 136, 146, 156, and 174, and multiple vias 142 and 152 may comprise the same material. Multiple insulating layers 132, 140, 150, 160, and 170 may comprise the same material as the electrode pad support layer 130. Multiple insulating layers 132, 140, 150, 160, and 170 may comprise, for example, a photosensitive insulating material. The multiple insulating layers 132, 140, 150, 160, and 170 may be patterned using a photolithography process.

[0090] Subsequently, a first semiconductor chip 200 can be mounted on the first surface 100a of the redistribution layer 100. A first connection terminal 180 can be provided between the redistribution layer 100 and the first semiconductor chip 200. The first connection terminal 180 can be disposed between the fourth wiring 174 and the first connection pad 210. The first connection terminal 180 can contact the fourth wiring 174 and the first connection pad 210. The first semiconductor chip 200 can be electrically connected to the redistribution layer 100 through the first connection terminal 180.

[0091] For example, a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention can be performed in a post-chip process in which a first semiconductor chip 200 is formed after the redistribution layer 100 is formed.

[0092] Subsequently, a first molding layer 300 may be formed to cover the first semiconductor chip 200. The first molding layer 300 may at least partially surround the side and top surfaces of the first semiconductor chip 200 and may be disposed between the first semiconductor chip 200 and the first surface 100a of the redistribution layer 100. The first molding layer 300 may surround the first connection terminal 180 and may fill the space between adjacent first connection terminals 180.

[0093] Although the first molding layer 300 is shown in the accompanying drawing as covering the upper surface of the first semiconductor chip 200, the upper surface of the first molding layer 300 and the upper surface of the first semiconductor chip 200 may be coplanar.

[0094] Reference Figure 10 The second carrier substrate 400 can be attached to the first molding layer 300. The second carrier substrate 400 can be disposed on the upper surface of the first molding layer 300. For example, the second carrier substrate 400 can be disposed on another surface of the first molding layer 300 opposite to the surface (e.g., the lower surface) of the first molding layer 300 disposed on the first surface 100a of the redistribution layer 100. In an exemplary embodiment of the present invention, an adhesive layer can be further formed between the second carrier substrate 400 and the first molding layer 300. The adhesive layer can include, for example, a photothermal conversion (LTHC) polymeric material that can be removed together with the second carrier substrate 400. Alternatively, the adhesive layer can include, for example, an epoxy resin-based heat-release material, an ultraviolet (UV) adhesive, etc.

[0095] The second carrier substrate 400 may include, for example, silicon, metal, glass, plastic, ceramic, etc. The second carrier substrate 400 may be a carrier comprising the same material as the first carrier substrate 105. For example, the second carrier substrate 400 may be adhesive tape.

[0096] The semiconductor package can then be inverted. Afterward, the first carrier substrate 105 can be removed from the semiconductor package. The first release layer 112 can be exposed. For example, the first carrier substrate 105 can be removed using a laser.

[0097] Reference Figure 11 It can remove the first peeling layer 112 and the second peeling layer 114.

[0098] Light or a laser can be irradiated onto the first release layer 112. The first release layer 112 and the second release layer 114 can be removed using a laser or light. For example, the first release layer 112 and the second release layer 114 can be removed by laser ablation.

[0099] Alternatively, the step of removing the first carrier substrate 105, the first release layer 112, and the second release layer 114 using a laser can be performed by using a barrier layer 120 as a stop layer. Furthermore, the barrier layer 120 prevents the laser from penetrating the redistribution layer 100, which includes the electrode pad 134, the electrode pad support layer 130, multiple wirings 136, 146, 156, and 174, multiple vias 142 and 152, and multiple insulating layers 132, 140, 150, 160, and 170, during laser irradiation. Therefore, the barrier layer 120 prevents the redistribution layer 100 from being damaged during the removal of the first carrier substrate 105, the first release layer 112, and the second release layer 114.

[0100] Reference Figure 12 The barrier layer 120 can be removed. Therefore, at least a portion of the electrode pad 134 can be exposed. For example, a trench 100t provided by the electrode pad support layer 130 and the electrode pad 134 can be formed. The trench 100t can be formed at the location where the second release layer 114 is removed. The trench 100t can be formed by removing the first release layer 112 and the second release layer 114.

[0101] Subsequently, referring to Figure 1 Solder balls 500 can be formed on the trench 100t. For example, solder balls 500 can be formed in the trench 100t. At least some of the solder balls 500 can contact the electrode pad support layer 130. Therefore, the bonding reliability between the solder balls 500 and the electrode pad 134 can be increased or improved.

[0102] Solder ball 500 may be adjacent to electrode pad 134 exposed by trench 100t. Solder ball 500 may be electrically connected to multiple wirings 136, 146, 156 and 174.

[0103] Subsequently, a sawing process is performed, and the second carrier substrate 400 is removed, thereby manufacturing... Figure 1 The semiconductor package shown.

[0104] Figure 13 and Figure 14 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. The main explanation will be related to... Figure 3 and Figure 4 The differences can be omitted, and any redundant descriptions can be left out.

[0105] Reference Figure 13 In an exemplary embodiment of the invention, a method for manufacturing a semiconductor package may be formed on a first carrier substrate 105, wherein a release layer 110 may be formed.

[0106] The release layer 110 may be adjacent to the first carrier substrate 105. The release layer 110 has a first portion 110_1 and a second portion 110_2. The first portion 110_1 has a first thickness t1, and the second portion 110_2 has a second thickness t2. Additionally, as an example, the release layer 110 has a plurality of second portions 110_2 disposed spaced apart from each other in a first direction D1. For example, the first portions 110_1 may be disposed between adjacent second portions 110_2, and the second portions 110_2 may be disposed between adjacent first portions 110_1.

[0107] The first thickness t1 can be less than the second thickness t2. For example, the second portion 110_2 can protrude from the upper surface of the first carrier substrate 105. The upper surface of the second portion 110_2 can be positioned above the upper surface of the first portion 110_1. Although the difference between the first thickness t1 and the second thickness t2 can be, for example, in the range of about 3 μm and about 8 μm, the inventive concept is not limited thereto. For example, the difference between the first thickness t1 and the second thickness t2 can be about 3 μm or about 8 μm. For example, the thickness difference would correspond to the thickness of the portion of the release layer 110 protruding from the first portion 110_1.

[0108] In an exemplary embodiment of the present invention, the second portion 110_2 may protrude from the upper surface of the first portion 110_1.

[0109] The release layer 110 may include a photosensitive insulating material. The release layer 110 may be formed by photolithography to include a first portion 110_1 and a second portion 110_2.

[0110] Reference Figure 14 A barrier layer 120 can be formed on the release layer 110. The barrier layer 120 can extend along the upper surface of the release layer 110 in a first direction D1. The barrier layer 120 can be conformally formed on the release layer 110. Subsequently, in sequential execution Figures 6 to 12 Following the process shown, it is possible to manufacture Figure 1 The semiconductor package shown.

[0111] Figures 15 to 18 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention.

[0112] Reference Figure 15 In a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention, the following steps are performed sequentially: Figures 3 to 9 Following the process shown, a through-hole 310 penetrating the first molding layer 300 in the second direction D2 can be formed. The through-hole 310 can be formed on a side surface of the first semiconductor chip 200. The through-hole 310 can be formed on the exposed fourth wiring 174. The through-hole 310 can be electrically connected to the fourth wiring 174.

[0113] The through-via 310 may include a conductive material. The through-via 310 may include, for example, the same material as the multiple wirings 136, 146, 156, and 174. The through-via 310 may include, for example, copper (Cu). In another example, the through-via 310 may include at least one of carbon (C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum (Al), and / or zirconium (Zr).

[0114] Reference Figure 16 A second semiconductor chip 600 can be mounted on the first semiconductor chip 200. The second semiconductor chip 600 can be a logic chip or a memory chip. The second semiconductor chip 600 may include a second connection pad 610. The second connection pad 610 can be disposed on the lower surface of the second semiconductor chip 600. The second connection pads 610 can be formed to be spaced apart from each other in the first direction D1.

[0115] The second connection pad 610 can be electrically connected to a circuit formed in the second semiconductor chip 600. The second semiconductor chip 600 may include a conductive material. The second semiconductor chip 600 may include a metallic material such as aluminum (Al).

[0116] A second connection terminal 380 can be formed between the through-hole 310 and the second connection pad 610. The second connection terminal 380 can electrically connect the second semiconductor chip 600 and the through-hole 310 to each other.

[0117] The second connection terminal 380 can be, for example, a solder ball, a solder block, or a combination thereof. Although the second connection terminal 380 is shown in the figure as having a spherical shape, the inventive concept is not limited thereto. The number, shape, size, and / or arrangement of the second connection terminals 380 shown in the figure are not limited thereto and can be various. For example, the second connection terminal 380 can have substantially the same size and shape as the first connection terminal 180, or it can have different sizes and shapes as shown in the figure.

[0118] Reference Figure 17 A second molding layer 700 may be formed on the first molding layer 300. For example, the second molding layer 700 may be formed around the upper surface of the first molding layer 300. As another example, the second molding layer 700 may cover the second connection terminal 380. The second molding layer 700 may include, for example, an epoxy molding compound (EMC) or a mixture of two or more silicon materials.

[0119] Subsequently, the second carrier substrate 400 can be attached to the second molding layer 700.

[0120] Then, in sequence Figures 10 to 12 Following the process shown, it is possible to manufacture Figure 18 The semiconductor package shown.

[0121] For example, the semiconductor package can be inverted. A laser can be used to remove the first carrier substrate 105, the first release layer 112, and the second release layer 114. Solder balls 500 can be formed at the location where the second release layer 114 has been removed.

[0122] Figure 19 This is a diagram illustrating a semiconductor package manufactured by a method for manufacturing a semiconductor package, according to an exemplary embodiment of the concept of the present invention.

[0123] Reference Figure 19 In a semiconductor package manufactured by a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention, the following steps are performed sequentially: Figures 3 to 9 , Figures 15 to 16 and Figure 1 The process shown is used to form a first package including a first semiconductor chip 200, and a second package 10 including a second semiconductor chip 15 can be formed on the first package.

[0124] The second package 10 may include a substrate 11, a second connecting pad 12, a third connecting terminal 13, an underfill material 14, a second semiconductor chip 15, and a second molding layer 16.

[0125] The substrate 11 can be, for example, a printed circuit board (PCB) substrate or a ceramic substrate. In another example, the substrate 11 can be an interposer.

[0126] The second connecting pad 12 may be disposed on the lower surface of the substrate 11. The second connecting pad 12 may be formed to be spaced apart from each other in the first direction D1. The second connecting pad 12 may be electrically connected to a circuit formed in the second semiconductor chip 15. The second semiconductor chip 15 may include a conductive material. The second semiconductor chip 600 may include a metallic material such as aluminum (Al).

[0127] A second connection terminal 380 may be formed between the through-hole 310 and the second connection pad 12. The second connection terminal 380 can electrically connect the second semiconductor chip 600 and the through-hole 310 to each other.

[0128] The second semiconductor chip 15 can be disposed on one surface of the substrate 11. The second semiconductor chip 15 can be a logic chip or a memory chip. A third connection terminal 13 can be formed between the substrate 11 and the second semiconductor chip 15. The third connection terminal 13 can be adjacent to conductive terminals exposed on the substrate 11 and conductive terminals exposed on the lower surface of the second semiconductor chip 15. The size of the third connection terminal 13 can be the same as the size of the first connection terminal 180, the second connection terminal 380, and the solder ball 500, or it can be different as shown in the figures. However, the inventive concept is not limited thereto. For example, the third connection terminal 13 can have a different size than the first connection terminal 180, the second connection terminal 380, and the solder ball 500.

[0129] The underfill material 14 can be formed in the empty space between the substrate 11 and the second semiconductor chip 15. The underfill material 14 can fill the space between adjacent third connection terminals 13. The underfill material 14 can protect the third connection terminals 13. The underfill material 14 can reduce the physical impact absorbed by the second semiconductor chip 15.

[0130] The second molding layer 16 may be formed on the substrate 11. The second molding layer 16 may at least partially surround the upper surface and side surface of the second semiconductor chip 15 and the side surface of the bottom filler material 14.

[0131] The second package 10 can be electrically connected to the first package including the first semiconductor chip 200 via the third connection terminal 13 and the through-hole 310.

[0132] Figure 20 This is a diagram illustrating a semiconductor package manufactured by a method for manufacturing a semiconductor package according to an exemplary embodiment of the concept of the present invention.

[0133] Reference Figure 20 In a semiconductor package manufactured by a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention, the following steps are performed sequentially: Figures 3 to 8 Following the process shown, an interconnect substrate can be formed on the first surface 100a of the redistribution layer 100. The interconnect substrate can be, for example, a PCB substrate. The interconnect substrate may include a substrate layer 320, sub-pads 312, sub-wiring 314, and sub-vias 316. For example, multiple interconnect substrates may be present.

[0134] Sub-pads 312 can be disposed on the upper and lower surfaces of the connecting substrate, respectively. Sub-wiring 314 can be placed between the substrate layers 320. Sub-vias 316 can penetrate the substrate layer 320 in the second direction D2. Sub-vias 316 can be disposed on the sub-pads 312 and sub-wiring 314. Sub-pads 312 and sub-wiring 314 can be electrically connected to each other through sub-vias 316.

[0135] Sub-pad 312, sub-wiring 314, and sub-via 316 may include conductive materials. Sub-pad 312, sub-wiring 314, and sub-via 316 may include at least one of, for example, aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof.

[0136] The first semiconductor chip 200 can be mounted between interconnect substrates. For example, the interconnect substrates can be formed on opposite sides of the first semiconductor chip 200. Alternatively, after the first semiconductor chip 200 is mounted on the redistribution layer 100, the interconnect substrates can be formed on the side surfaces of the first semiconductor chip 200.

[0137] Subsequently, a first molding layer 300 can be formed covering the connection substrate and the side and top surfaces of the first semiconductor chip 200. For example, a first package including the first semiconductor chip 200 can be formed. A second package 10 including a second semiconductor chip 15 can be formed on the first package. The second package 10 can be electrically connected to the first package including the first semiconductor chip 200 via a third connection terminal 13 and a connection substrate including a sub-pad 312, a sub-wiring 314, and a sub-via 316. Figure 19 The second package 10 has been explained, so no explanation of it will be provided.

[0138] Although the inventive concept has been specifically described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims.

Claims

1. A method for manufacturing a semiconductor package, the method comprising the following steps: A release layer is formed on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness and the second portion has a second thickness that is thicker than the first thickness; A barrier layer is formed on the peeling layer; A redistribution layer is formed on the barrier layer, wherein the redistribution layer includes multiple wirings and an insulating layer surrounding the multiple wirings; Semiconductor chips are mounted on the redistribution layer and electrically connected to the redistribution layer; A molding layer is formed on the redistribution layer to at least partially surround the semiconductor chip; The second carrier substrate is attached to the molding layer; Remove the first carrier substrate and the peeling layer; Remove the blocking layer; and Solder balls are attached to the redistribution layer exposed by removing the second part of the barrier layer and the stripper layer.

2. The method for manufacturing a semiconductor package according to claim 1, wherein, The barrier layer includes metallic materials.

3. The method for manufacturing a semiconductor package according to claim 2, wherein, Metallic materials include copper.

4. The method for manufacturing a semiconductor package according to claim 1, wherein, The barrier layer comprises the same material as the multiple wirings.

5. The method for manufacturing a semiconductor package according to claim 1, wherein, The steps for forming the release layer include: A first release layer having a first thickness is formed on a first carrier substrate; and A second release layer is formed on the first release layer, wherein the second release layer has a third thickness and includes an opening that exposes at least a portion of the first release layer. The opening overlaps with the first part.

6. The method for manufacturing a semiconductor package according to claim 5, wherein, The third thickness is in the range of 3μm to 8μm.

7. The method for manufacturing a semiconductor package according to claim 1, wherein, The steps to remove the peeling layer include using a laser.

8. The method for manufacturing a semiconductor package according to claim 7, wherein, The laser cannot enter the redistribution layer due to the blocking layer.

9. The method for manufacturing a semiconductor package according to any one of claims 1 to 8, wherein, The second step of removing the barrier layer and the stripping layer exposes at least a portion of the plurality of wirings in the redistribution layer, and The solder balls are electrically connected to the exposed wiring.

10. The method for manufacturing a semiconductor package according to any one of claims 1 to 8, wherein, The release layer consists of the same material as the insulating layer.

11. The method for manufacturing a semiconductor package according to any one of claims 1 to 8, wherein, The release layer includes photosensitive insulating material.

12. A method for manufacturing a semiconductor package, the method comprising the following steps: A first release layer is formed on the first carrier substrate; A second peeling layer is formed on the first peeling layer, wherein the second peeling layer includes an opening for exposing at least a portion of the first peeling layer; A barrier layer is formed on the second peeling layer; A redistribution layer is formed on the barrier layer, wherein the redistribution layer includes multiple wirings and an insulating layer surrounding the multiple wirings; A first semiconductor chip is mounted on the redistribution layer, wherein the first semiconductor chip is electrically connected to the redistribution layer; The second carrier substrate is attached to the first semiconductor chip; The first carrier substrate, the first release layer, and the second release layer are removed using a laser. Remove the blocking layer; and The solder balls were attached to the redistribution layer at the location where the second stripping layer had been removed. The first and second release layers comprise photosensitive insulating materials, and The barrier layer is formed on the upper and side surfaces of the second peeling layer, or on the upper and side surfaces of the second peeling layer and the opening.

13. The method for manufacturing a semiconductor package according to claim 12, wherein, The first carrier substrate is a glass substrate.

14. The method for manufacturing a semiconductor package according to claim 12, wherein, The second release layer has a thickness ranging from 3 μm to 8 μm.

15. The method for manufacturing a semiconductor package according to claim 12, wherein, The barrier layer includes metallic materials.

16. The method for manufacturing a semiconductor package according to any one of claims 12 to 15, the method further comprising, after mounting a first semiconductor chip on a redistribution layer: A first molding layer is formed on the redistribution layer, wherein, The first molding layer at least partially surrounds the first semiconductor chip and includes a through-hole penetrating the first molding layer; as well as The second semiconductor chip is mounted on the first molding layer. The second carrier substrate is attached to the second semiconductor chip.

17. The method for manufacturing a semiconductor package according to claim 16, wherein, The second semiconductor chip is electrically connected to the redistribution layer through a through-hole.

18. The method for manufacturing a semiconductor package according to any one of claims 12 to 15, the method further comprising, after mounting a first semiconductor chip on a redistribution layer: A first molding layer is formed on the redistribution layer, wherein, The first molding layer at least partially surrounds the first semiconductor chip; An interconnect substrate is formed on opposite sides of a first semiconductor chip, wherein the interconnect substrate includes a plurality of sub-wires and a substrate layer at least partially surrounding the plurality of sub-wires; and The package is mounted on a first molding layer, wherein the package includes a substrate, a second semiconductor chip mounted on the substrate, and a second molding layer on the substrate that at least partially surrounds the second semiconductor chip. The second carrier substrate is attached to the second molding layer, and The second semiconductor chip is electrically connected to the redistribution layer via a substrate and a connection substrate.

19. A method for manufacturing a semiconductor package, the method comprising the following steps: A first release layer is formed on the first carrier substrate; A second peeling layer is formed on the first peeling layer, wherein the second peeling layer includes a first opening for exposing at least a portion of the upper surface of the first peeling layer; A barrier layer is formed on the second release layer, wherein the barrier layer is formed on the upper surface and side surface of the second release layer or on the upper surface and side surface of the second release layer and the first opening, and comprises a metallic material; An electrode pad support layer is formed on the barrier layer, wherein the electrode pad support layer exposes at least a portion of the barrier layer and includes a second opening that does not overlap with the first opening; A redistribution layer is formed on the electrode pad support layer, wherein the redistribution layer includes multiple wirings and an insulating layer surrounding the multiple wirings; Semiconductor chips are mounted on a redistribution layer; A molding layer is formed around the semiconductor chip on the redistribution layer; The second carrier substrate is attached to the molding layer; The first carrier substrate, the first release layer, and the second release layer are removed using a laser. Remove the blocking layer; Solder balls are formed at the locations where the second peeling layer is removed; and Remove the second carrier substrate. The first release layer, the second release layer, and the insulating layer include photosensitive insulating material.

20. The method for manufacturing a semiconductor package according to claim 19, wherein, The barrier layer comprises the same material as the multiple wirings.

Images