Semiconductor device and manufacturing method

Abstract

The present disclosure relates to semiconductor devices and manufacturing methods. Disclosed are a semiconductor device having different gate structure configurations and a manufacturing method thereof. The semiconductor device includes: a fin structure disposed on a substrate; a nanostructured channel region disposed on the fin structure; and a gate-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes: a high-K (HK) gate dielectric layer having a metal-doped region, the metal-doped region having a dopant of a first metal material; a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer; a bimetallic nitride layer inserted between the HK gate dielectric layer and the pWFM layer; an n-type work function metal (nWFM) layer disposed on the pWFM layer; and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metal material, and the bimetallic nitride layer includes the first metal material and the second metal material.

Description

Technical Field

[0001] The present application relates to semiconductor devices and methods of manufacturing. Background Art

[0002] As semiconductor technology advances, the demand for higher memory capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field-effect transistors (MOSFETs), including planar MOSFETs and fin field-effect transistors (finFETs). This shrinkage increases the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate; a fin structure disposed on the substrate; a nanostructured channel region disposed on the fin structure; and a gate-surround GAA structure surrounding the nanostructured channel region, wherein the GAA structure comprises: a high-K HK gate dielectric layer having a metal-doped region, the metal-doped region having a dopant of a first metal material; a first work function metal WFM layer disposed on the HK gate dielectric layer, wherein the first WFM layer comprises a second metal material; a bimetallic nitride layer inserted between the HK gate dielectric layer and the first WFM layer, wherein the bimetallic nitride layer comprises the first metal material and the second metal material; a second WFM layer disposed on the first WFM layer; and a gate metal fill layer disposed on the second WFM layer.

[0004] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a substrate; a p-type FET having a first gate structure disposed on the substrate; and an n-type FET having a second gate structure disposed on the substrate, wherein the first gate structure and the second gate structure include: a high-K HK gate dielectric layer having a metal-doped region, the metal-doped region having a dopant of a first metal, an n-type work function metal nWFM layer disposed on the HK gate dielectric layer, and a gate metal fill layer disposed on the nWFM layer, and wherein the first gate structure includes a p-type work function metal pWFM layer and a bimetallic nitride layer inserted between the HK gate dielectric layer and the nWFM layer, the pWFM having a second metal, and the bimetallic nitride layer having the first metal and the second metal.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a nanostructured channel region on a fin structure; forming a gate opening surrounding the nanostructured channel region; depositing a high-K HK gate dielectric layer within the gate opening, wherein the HK gate dielectric layer comprises a first metal; forming a metal-doped region having a dopant of a second metal within the HK gate dielectric layer, wherein the second metal is different from the first metal; forming a bimetallic nitride layer on the HK gate dielectric layer; depositing a p-type work function metal pWFM layer on the bimetallic nitride layer, wherein the pWFM layer comprises a third metal different from the first metal and the second metal, and the bimetallic nitride layer comprises the second metal and the third metal; depositing an n-type work function metal nWFM layer on the pWFM layer; and depositing a gate metal fill layer on the nWFM layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1A 、 Figures 1B-1C and Figures 1D-1G Isometric views, cross-sectional views, and device characteristics of semiconductor devices having different gate structures according to some embodiments are shown.

[0008] Figure 2 is a flow chart of a method for fabricating semiconductor devices with different gate structures according to some embodiments.

[0009] Figures 3A-11B Cross-sectional views of semiconductor devices having different gate structures at various stages of their fabrication process are shown in accordance with some embodiments.

[0010] Figure 12 is a flow chart of a method for fabricating semiconductor devices with different gate structures according to some embodiments.

[0011] Figures 13A-17B Cross-sectional views of semiconductor devices having different gate structures at various stages of their fabrication process are shown in accordance with some embodiments.

[0012] Illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, a process for forming a first feature above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. As used herein, forming a first feature on a second feature means that the first feature is formed to be in direct contact with the second feature. In addition, the disclosure may repeat reference numbers / letters in various examples. This repetition itself does not indicate a relationship between the various embodiments and / or configurations discussed.

[0014] For ease of description, spatially relative terms, such as "below," "beneath," "below," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "exemplary," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the purview of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments (whether or not explicitly described).

[0016] It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, and thus the phraseology or terminology of this specification is to be interpreted by one or more persons skilled in the relevant art(s) based on the teachings herein.

[0017] As used herein, the term "high-k" refers to a high dielectric constant. In the field of semiconductor device structure and manufacturing process, high-k refers to a dielectric constant greater than the dielectric constant of SiO2 (eg, greater than 3.9).

[0018] As used herein, the term "low-k" refers to a low dielectric constant. In the field of semiconductor device structure and manufacturing process, low-k refers to a dielectric constant that is less than the dielectric constant of SiO2 (eg, less than 3.9).

[0019] As used herein, the term "p-type" defines a structure, layer, and / or region as being doped with a p-type dopant, such as boron.

[0020] As used herein, the term "n-type" defines a structure, layer, and / or region as being doped with an n-type dopant, such as phosphorus.

[0021] As used herein, the term "nanostructure" defines structures, layers, and / or regions as having horizontal dimensions (eg, along the X and / or Y axes) and / or vertical dimensions (eg, along the Z axis) less than, for example, 100 nm.

[0022] As used herein, the term "n-type work function metal (nWFM)" defines a metal or metal-containing material having a work function value that is closer to the conduction band energy of the material of the FET channel region than to the valence band energy. In some embodiments, the term "n-type work function metal (nWFM)" defines a metal or metal-containing material having a work function value less than 4.5 eV.

[0023] As used herein, the term "p-type work function metal (pWFM)" defines a metal or metal-containing material having a work function value that is closer to the valence band energy of the material of the FET channel region than to the conduction band energy. In some embodiments, the term "p-type work function metal (pWFM)" defines a metal or metal-containing material having a work function value equal to or greater than 4.5 eV.

[0024] In some embodiments, the terms "about" and "substantially" can refer to values that vary within 5% of the value of a given quantity (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms "about" and "substantially" can refer to percentages of values that would be interpreted by one or more persons skilled in the relevant art(s) in accordance with the teachings herein.

[0025] As used herein, the term "multi-threshold voltage (multi-Vt) device" defines a semiconductor device having two or more FETs, wherein each of the two or more FETs has a different threshold voltage from one another.

[0026] The fin structure disclosed herein can be patterned by any suitable method. For example, the fin structure can be patterned using one or more photolithography processes (including a double patterning process or a multi-patterning process). The double patterning process or the multi-patterning process can combine a photolithography process and a self-alignment process so that the pattern is created to have, for example, a smaller spacing than that obtainable using a single direct photolithography process in other ways. For example, a sacrificial layer is formed on top of a substrate and patterned using a photolithography process. A spacer is formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer can be used to pattern the fin structure.

[0027] The gate voltage (threshold voltage (Vt)) required to turn on a field effect transistor (FET) can depend on the effective work function (EWF) value of the semiconductor material of the FET channel region and / or the FET gate structure. For example, for an n-type FET (NFET), reducing the difference between the EWF value(s) of the NFET gate structure and the conduction band energy of the material of the NFET channel region (e.g., 4.1 eV for Si or 3.8 eV for SiGe) can reduce the NFET threshold voltage. For a p-type FET (PFET), reducing the difference between the EWF value(s) of the PFET gate structure and the valence band energy of the material of the PFET channel region (e.g., 5.2 eV for Si or 4.8 eV for SiGe) can reduce the PFET threshold voltage. The EWF value of the FET gate structure can depend on the thickness and / or material composition of each layer of the FET gate structure. Therefore, FETs with different threshold voltages can be manufactured by adjusting the thickness and / or material composition of the FET gate structure.

[0028] Due to the increasing demand for multifunctional portable devices, there is an increasing demand for FETs with different threshold voltages on the same substrate. One way to achieve such multi-threshold voltage devices can be to use different work function metal (WFM) layer thicknesses in the FET gate structure. However, different WFM layer thicknesses may be limited by the geometry of the FET gate structure. For example, in a gate-all-around (GAA) FET, the WFM layer thickness may be limited by the spacing between the nanostructured channel regions of the GAAFET. In addition, as FETs (e.g., GAA FETs and / or finFETs) continue to shrink, depositing different WFM layer thicknesses may also become increasingly difficult.

[0029] The present disclosure provides example multi-threshold voltage devices including FETs (e.g., GAA FETs) having threshold voltages different from each other, and provides example methods for forming such FETs on the same substrate. The example methods form PFETs having WFM layers of similar materials and thicknesses but having different threshold voltages on the same substrate. Compared to other methods of forming FETs with similar channel dimensions and threshold voltages on the same substrate, these example methods can be more cost-effective (e.g., approximately 20% to 30% cost reduction) and time-efficient (e.g., approximately 15% to 20% time reduction) in manufacturing reliable FET gate structures with different threshold voltages. In addition, compared to other methods of forming FETs with similar threshold voltages, these example methods can form FET gate structures with much smaller dimensions (e.g., thinner gate stacks).

[0030] In some embodiments, PFETs with different gate structure configurations but similar WFM layers can be selectively formed on the same substrate to achieve different threshold voltages. The different gate structures can have (i) metal-doped regions with different metal concentrations within a high-K (HK) gate dielectric layer and (ii) a dual-metal nitride layer with different metal concentrations between the HK gate dielectric layer and the WFM layer. The different metal concentrations produce gate structures with different EWF values and threshold voltages. In some embodiments, varying the metal concentration within a range of approximately 2 atomic percent to approximately 10 atomic percent can cause an approximately ±80 mV shift in the EWF value and an approximately ±50 mV shift in the threshold voltage. Therefore, adjusting the metal concentration within the HK gate dielectric layer and between the HK gate dielectric layer and the WFM layer can adjust the EWF value of the PFET gate structure, thereby adjusting the threshold voltage of the PFET without changing the material and / or thickness of the WFM layer.

[0031] refer to Figures 1A-1G A semiconductor device 100 having PFETs 102P1 - 102P4 and NFETs 102N1 - 102N4 is described in accordance with some embodiments. Figure 1A An isometric view of a semiconductor device 100 is shown, in accordance with some embodiments. Figure 1B and 1C shows a method according to some embodiments of the present invention along Figure 1A 1 and 2. Cross-sectional views of the semiconductor device 100 taken along respective lines AA and BB. Figures 1E-1G Device characteristics of semiconductor device 100 according to some embodiments are shown. Unless otherwise noted, the discussion of PFET 102P1 applies to 102P2-102P4, and the discussion of NFET 102N1 applies to NFETs 102N2-102N4. Unless otherwise noted, the discussion of elements of PFETs 102P1-102P4 and NFETs 102N1-102N4 with the same label applies to each other.

[0032] refer to Figures 1A-1C , the semiconductor device 100 may be formed on a substrate 106. The substrate 106 may be a semiconductor material, such as silicon, germanium (Ge), silicon-germanium (SiGe), a silicon-on-insulator (SOI) structure, and combinations thereof. Furthermore, the substrate 106 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0033] PFET 102P1 and NFET 102N1 may include: fin structures 108P-108N extending along the X-axis; epitaxial regions 110P-110N disposed on the respective fin structures 108P-108N; nanostructure channel regions 120P-120N disposed between the respective epitaxial regions 110P-110N; gate structures 112P-112N surrounding the respective nanostructure channel regions 120P-120N; an internal spacer 113; and a gate spacer 114.

[0034] In some embodiments, fin structures 108P-108N may include a material similar to substrate 106. Nanostructured channel regions 120P-120N may include a semiconductor material similar to or different from substrate 106, and may include semiconductor materials similar to or different from each other. In some embodiments, nanostructured channel region 120N may include Si, SiAs, silicon phosphide (SiP), SiC, or silicon carbon phosphide (SiCP), and nanostructured channel region 120P may include SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), or a III-V semiconductor compound. In some embodiments, nanostructured channel regions 120P-120N may each include Si, SiAs, SiP, SiC, SiCP, SiGe, SiGeB, GeB, SiGeSnB, or a III-V semiconductor compound. Although rectangular cross-sections of the nanostructured channel regions 120P- 120N are shown, the nanostructured channel regions 120P- 120N may have cross-sections of other geometric shapes, such as circular, elliptical, triangular, or polygonal.

[0035] Epitaxial regions 110P-110N may be grown on respective fin structures 108P-108N and may serve as source / drain (S / D) regions for PFET 102P1 and NFET 102N1. Epitaxial regions 110P-110N may comprise epitaxially grown semiconductor materials that are similar to or different from each other. In some embodiments, the epitaxially grown semiconductor material may comprise the same or different material as substrate 106. Epitaxial regions 110P and 110N may be p-type and n-type, respectively. In some embodiments, n-type epitaxial region 110N may comprise SiAs, SiC, or SiCP. P-type epitaxial region 110P may comprise SiGe, SiGeB, GeB, SiGeSnB, III-V semiconductor compounds, or combinations thereof.

[0036] The gate structures 112P-112N may be multilayer structures. The gate structures 112P-112N may surround the corresponding nanostructure channel regions 120P-120N, and the gate structures 112P-112N may be referred to as "gate-all-around (GAA) structures" or "horizontal gate-all-around (HGAA) structures." The PFET 102P1 and the NFET 102N1 may be referred to as "GAA PFET 102P1 and NFET 102N1." In some embodiments, the PFET 102P1 and the NFET 102N1 may be finFETs and have fin regions (not shown) instead of the nanostructure channel regions 120P-120N. Such finFETs 120P1-120N1 may have corresponding gate structures 112P-112N disposed on the fin regions.

[0037] The gate structures 112P-112N may include: (i) an interfacial oxide (IO) layer 127; (ii) HK gate dielectric layers 128P-128N; (iii) metal doped regions 128Pd-128Nd; (iv) an n-type WFM ("nWFM") layer 131; (vii) a gule layer 132; and (viii) a gate metal fill layer 133. The gate structure 112P may also include a dual metal nitride layer 129 and a p-type WFM ("pWFM") layer 130. Although Figures 1B-1C While all layers of the gate structure 112P are shown surrounding the nanostructured channel region 120P, the nanostructured channel region 120P may be surrounded by at least the IO layer 127 and the HK gate dielectric layer 128P to fill the space between adjacent nanostructured channel regions 120P. Thus, the nanostructured channel regions 120P may be electrically isolated from one another to prevent short circuits between the gate structure 112P and the S / D region 110P during operation of the PFET 102P1. Similarly, the nanostructured channel region 120N may be surrounded by at least the IO layer 127 and the HK gate dielectric layer 128N to electrically isolate the nanostructured channel region 120N from one another to prevent short circuits between the gate structure 112N and the S / D region 110N during operation of the NFET 102N1.

[0038] The IO layer 127 may be disposed on the nanostructured channel regions 120P-120N. In some embodiments, the IO layer 127 may include silicon oxide (SiO2), silicon germanium oxide (SiGeO x ) or germanium oxide (GeO x ), and a thickness ranging from about 0.5 nm to about 1.5 nm.

[0039] HK gate dielectric layers 128P-128N may be disposed on the IO layer 127. Each of the HK gate dielectric layers 128P-128N may have a thickness approximately 2 to 3 times that of the IO layer 127 (e.g., approximately 1 nm to approximately 3 nm), and may include: (i) a high-k dielectric material such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2); and (ii) a dielectric material having High-k dielectric materials of oxides of the following: lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu); or (iii) combinations thereof.

[0040] HK gate dielectric layers 128P-128N may include corresponding metal-doped regions 128Pd-128Nd. In some embodiments, the metal-doped regions 128Pd-128Nd may include the following dopants: (i) a metal from Group IIA (e.g., magnesium (Mg) or strontium (Sr)), Group IIIA (e.g., aluminum (Al)), Group IIIB (e.g., yttrium (Y)), or Group IVB (e.g., zirconium (Zr)) of the periodic table; (ii) a rare earth metal such as lanthanum (La), yttrium (Y), scandium (Sc), cerium (Ce), ytterbium (Yb), erbium (Er), dysprosium (Dy), and lutetium (Lu); or (iii) a combination thereof. In some embodiments, the metal-doped regions 128Pd-128Nd may include an Al dopant or a La dopant. In some embodiments, as a result of the fabrication process (e.g., method 200) for forming the PFET 102P1 and the NFET 102N1 as described in further detail below, the metal doped region 128Nd may not be present in the HK gate dielectric layer 128N (e.g., Figure 17B shown).

[0041] The dual-metal nitride layer 129 may be disposed on the HK gate dielectric layer 128P. In some embodiments, the dual-metal nitride layer 129 may include (i) a first metal that is the same as the dopant material included in the metal-doped region 128Pd, and (ii) a second metal that is the same as the metal included in the pWFM layer 130. In some embodiments, the pWFM layer 130 may include a metal material having a work function value that is closer to the valence band edge energy of the material of the nanostructured channel region 120P than to the conduction band edge energy. For example, the pWFM layer 130 may include a metal material that is substantially free of Al (e.g., lacks Al) and has a work function value equal to or greater than 4.5 eV (e.g., approximately 4.5 eV to approximately 5.5 eV), which may be closer to the valence band edge energy of the nanostructured channel region 120P (e.g., 5.2 eV for Si) than to the conduction band edge energy (e.g., 4.1 eV for Si).

[0042] In some embodiments, the pWFM layer 130 may include (i) a Ti-based nitride or alloy that is substantially free of Al (e.g., free of Al), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, titanium chromium (Ti-Cr) alloy, titanium cobalt (Ti-Co) alloy, titanium molybdenum (Ti-Mo) alloy, and titanium nickel (Ti-Ni) alloy; (ii) a Ta-based nitride or alloy that is substantially free of Al (e.g., free of Al), such as tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, tantalum copper (Ta-Cu) alloy, tantalum tungsten (Ta-W) alloy, tantalum platinum (Ta-Pt) alloy, tantalum molybdenum (Ta-Mo) alloy, and tantalum nickel (Ta-Ni) alloy; or (iii) a combination thereof. In some embodiments, the pWFM layer 130 may include a thickness ranging from about 1 nm to about 3 nm. A thickness within this range may allow the pWFM layer 130 to surround the nanostructured channel region 120P without being limited by the spacing between adjacent nanostructured channel regions 120P.

[0043] The work function value of the pWFM layer 130 can introduce an EWF value to the gate structure 112P of the PFET 102P1. By controlling the concentration of the metal dopant in the metal-doped region 128Pd and / or the concentration of the first metal in the bimetallic nitride layer 129, the EWF value of the gate structure 112P can be adjusted without changing the thickness of the pWFM layer 130. Furthermore, by controlling the concentration of the metal dopant and / or the first metal, PFETs 102P1-102P4 having similar pWFM layers 130 can be configured to have gate structures 112P with different EWF values. Because the EWF value of a gate structure corresponds to the threshold voltage of the FET, gate structures 112P with different EWF values can produce PFETs 102P1-102P4 with different threshold voltages on the same substrate 106.

[0044] In some embodiments, the EWF value of the gate structure 112P can be adjusted within a range of approximately ±80 mV by controlling the concentration of the metal dopant and / or the first metal. Adjusting the EWF value within a range of approximately ±80 mV can adjust the threshold of the gate structure 112P within a range of approximately ±50 mV. This adjustment range can be achieved by: the concentration of the first metal (e.g., Al) in the bi-metal nitride layer 129 is within a range of approximately 2 atomic % to approximately 10 atomic %, and / or the concentration ratio of the metal dopant (e.g., Al dopant) to the metal material ("HK metal," such as Hf) in the HK gate dielectric layer 128P is within a range of approximately 0.05 to approximately 0.5.

[0045] In some embodiments, the metal-doped region 128Pd may extend from the top surface of the HK gate dielectric layer 128P within the HK gate dielectric layer 128P by a distance D1 of approximately 0.1 nm to approximately 2 nm. In some embodiments, the bimetallic nitride layer 129 may have a thickness T1 of approximately 0.1 nm to approximately 1 nm, and the thickness T1 may be less than the distance D1. These ranges for the distance D1 and the thickness T1 are sufficient to control the respective concentrations of the metal dopant and the first metal. If the distance D1 is less than approximately 0.1 nm, the concentration ratio of the metal dopant to the HK metal in the metal-doped region 128Pd may not be within the range of approximately 0.05 to approximately 0.5, which may be insufficient to adjust the EWF value of the gate structure 112P. Similarly, if the thickness T1 is less than approximately 0.1 nm, the concentration of the first metal in the bimetallic nitride layer 129 may not be within the range of approximately 2 atomic % to approximately 10 atomic %, which may be insufficient to adjust the EWF value of the gate structure 112P. On the other hand, if the distance D1 and / or the thickness T1 is greater than the above range, the process time (eg, doping process time) increases, thereby correspondingly increasing the device manufacturing cost.

[0046] refer to Figures 1D-1EIn some embodiments, the concentration distribution of the metal dopant in the metal doping region 128Pd and the first metal in the double metal nitride layer 129 is along Figure 1B The line CC can be substantially constant. In some embodiments, as Figure 1D The concentrations of the metal dopant and the first metal may be equal to each other as shown, or as Figure 1E As shown, the concentration of the metal dopant can be greater than the concentration of the first metal. Figure 1F In some embodiments, the concentration distribution of the metal dopant and the first metal is along Figure 1B The line CC may be graded, and the concentration of the metal dopant may be greater than the concentration of the first metal.

[0047] refer to Figure 1G In some embodiments, the IO layer 127 includes silicon oxide (SiO2), the HK gate dielectric layer 128P includes hafnium oxide (HfO2) (with Al dopant in the metal-doped region 128Pd), the bimetallic nitride layer 129 includes titanium aluminum nitride (TiAlN), and the pWFM layer 130 includes TiN. Figure 1G Silicon, oxygen, hafnium, aluminum, titanium, and nitrogen atoms are shown along the layers in accordance with some embodiments. Figure 1B The concentration distribution of line CC. Figure 1G As shown, the aluminum concentration in the metal doped region 128Pd may be higher than the aluminum concentration in the double metal nitride layer 129 .

[0048] Return Reference Figures 1B-1C In some embodiments, the nWFM layer 131 may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), or a combination thereof. The adhesion layer 132 may include TiN, Ti, Co, or a combination thereof. The gate metal fill layer 133 may include a suitable conductive material, such as W, Ti, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), a metal alloy, and a combination thereof. The gate spacer 114 and the inner spacer 113 may form sidewalls of the gate structures 112P-112N. Each of the gate spacer 114 and the inner spacer 113 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, a low-k material, and a combination thereof.

[0049] The semiconductor device 100 may further include an isolation structure 104, an etch stop layer (ESL) 116, an interlayer dielectric layer (ILD) 118, and shallow trench isolation (STI) regions 138. The isolation structure 104 can electrically isolate the PFETs 102P1-102P4 and the NFETs 102N1-102N4 from each other. The ESL 116 can be configured to protect the gate structures 112P-112N and / or the S / D regions 110P-110N. In some embodiments, the isolation structure 104 and the ESL 116 may include insulating materials such as silicon oxide and silicon germanium oxide. The ILD layer 118 may be disposed on the ESL 116 and may include a dielectric material. The STI regions 138 may be configured to provide electrical isolation between the PFETs 102P1-102P4 and the NFETs 102N1-102N4 and may include an insulating material.

[0050] Figure 2 is a flow chart of an example method 200 for manufacturing a semiconductor device 100 according to some embodiments. For illustrative purposes, reference will be made to Figures 3A-11B An example manufacturing process for manufacturing the semiconductor device 100 is shown to describe Figure 2 The operation shown. Figures 3A-11B is a cross-sectional view of the semiconductor device 100 along lines AA and BB at various stages of fabrication according to some embodiments. Depending on the particular application, the operations may be performed in a different order, or not performed at all. It should be noted that the method 200 may not produce a complete semiconductor device 100. Therefore, it is understood that additional processes may be provided before, during, and after the method 200, and that some other processes may only be briefly described herein. Figures 3A-11B There are Figures 1A-1C Elements with the same tag as the elements in .

[0051] In operation 205, polysilicon structures and epitaxial regions are formed on the fin structures of the PFET and NFET. Figures 3A-3BAs shown, polysilicon structure 312 can be formed on superlattice structures 119P-119N, which are formed on fin structures 108P-108N. Superlattice structure 119P can include nanostructure regions 120P-122P arranged in an alternating configuration, and superlattice structure 119N can include nanostructure regions 120N-122N arranged in an alternating configuration. During subsequent processing, polysilicon structure 312 and nanostructure regions 122P-122N can be replaced in a gate replacement process to form gate structures 112P-112N. After forming inner spacers 113 and gate spacers 114, epitaxial regions 110P-110N can be selectively formed on portions of fin structures 108P-108N that are not underneath polysilicon structure 312. After forming the epitaxial regions 110P-110N, ESL 116 and ILD 118 may be formed to form Figures 3A-3B structure.

[0052] refer to Figure 2 In operation 210, a gate opening is formed on the fin structure. Figures 4A-4B As shown, gate openings 412A-412B may be formed on the fin structures 108P-108N. The formation of gate openings 412A-412B may include the following sequential operations: (i) Figures 3A-3B The polysilicon structure 312 is etched from the structure of Figures 3A-3B The nanostructured regions 122P-122N are etched into the structure.

[0053] refer to Figure 2 In operations 215-235, a gate-around (GAA) structure is formed in the gate opening. For example, based on operations 215-235, gate structures 112P-112N may be formed around nanostructure channel regions 120P-120N, as shown in FIG. Figures 5A-11B As stated.

[0054] refer to Figure 2 In operation 215, an interfacial oxide layer and a HK gate dielectric layer are deposited within the gate opening. Figures 5A-5B As shown, the IO layer 127 and the HK gate dielectric layer 128 may be deposited on Figures 4A-4B During subsequent processing, the HK gate dielectric layer 128 may be formed within the gate openings 412A-412B. Figures 1B-1CHK gate dielectric layer 128P-128N. In some embodiments, the IO layer 127 can be formed by exposing the nanostructured channel regions 120P-120N to an oxidizing environment. The oxidizing environment can include a combination of the following: ozone (O3); a mixture of ammonium hydroxide, hydrogen peroxide, and water ("SC1 solution"); and / or a mixture of hydrochloric acid, hydrogen peroxide, and water ("SC2 solution"). Deposition of the HK gate dielectric layer 128 can include depositing the HK dielectric material in an atomic layer deposition (ALD) process using hafnium chloride (HfCl4) as a precursor at a temperature of about 250°C to about 350°C. In some embodiments, the gate dielectric layer 128 can have a thickness of about 1 nm to about 3 nm to surround the nanostructured channel regions 120P-120N, without being constrained by the spacing between adjacent nanostructured channel regions 120P and between adjacent nanostructured channel regions 120N.

[0055] refer to Figure 2 In operation 220, a metal doped region is formed in the HK gate dielectric layer. Figures 7A-7B As shown, metal doped regions 128Pd-128Nd may be formed within the HK gate dielectric layer 128. The formation of the metal doped regions 128Pd-128Nd may include the following sequential operations: (i) impregnation with a metal precursor gas 538; Figures 5A-5B and (ii) impregnating the metal precursor gas 642 Figures 6A-6B In some embodiments, the impregnation process using the metal precursor gas 538 may include: using titanium tetrachloride (TiCl4) as the metal precursor gas 538 at a temperature of about 350° C. to about 500° C. and a pressure of about 500 standard cubic centimeters (sccm) to about 9000 sccm. Figures 5A-5B During the treatment with the metal precursor gas 538, the Figures 5A-5B A metal layer 640 having a thickness of about 0.1 nm to about 0.5 nm and having Ti is deposited on the structure. Figures 6A-6B shown.

[0056] In some embodiments, the impregnation process using the metal precursor gas 642 may include: using triethylaluminum (TEA) or trimethylaluminum (TMA) as the metal precursor gas 642 at a temperature of about 350° C. to about 500° C. and a pressure of about 2000 sccm to about 9000 sccm. Figures 6A-6BDuring the treatment with the metal precursor gas 642, (i) metal doped regions 128Pd-128Nd may be formed within the HK gate dielectric layer 128, (ii) the metal layer 640 may be converted to a metal layer 740 comprising TiAl, and (iii) a metal layer 744 comprising Al and having a thickness of approximately 0.1 nm to approximately 0.5 nm may be deposited on the metal layer 740. Figures 7A-7B shown.

[0057] refer to Figure 2 In operation 225, a double metal nitride layer and a pWFM layer are formed on the HK gate dielectric layer. Figures 8A-8B As shown, a double metal nitride layer 129 and a pWFM layer 130 may be formed on the HK gate dielectric layer 128. In some embodiments, the formation of the pWFM layer 130 may include depositing a TiN layer having a thickness of about 1 nm to about 3 nm in an ALD process using TiCl4 and ammonia (NH3) as precursors at a temperature of about 350° C. to about 475° C. In some embodiments, the ALD process for depositing the TiN layer may include about 30 cycles to about 90 cycles, wherein one cycle may include the following sequential time periods: (i) TiCl4 gas flow, (ii) TiCl4 gas purge process, (iii) NH3 gas flow, and (iv) NH3 gas purge process.

[0058] In some embodiments, the ALD process TiCl4 gas may react with the TiAl of the metal layer 740 to convert it into TiAlN of the double metal nitride layer 129A, and the ALD process NH3 gas may react with the Al of the metal layer 744 to convert it into TiAlN of the double metal nitride layer 129B. Therefore, during the ALD process for forming the pWFM layer 130, the double metal nitride layer 129 may be formed by converting the metal layers 740 and 744 into the corresponding double metal nitride layers 129A and 129B, as shown in FIG. Figures 8A-8B Operations 220 - 225 may be performed in-situ with the nitridation of metal layers 740 and 744 .

[0059] refer to Figure 2 In operation 230, portions of the bimetal nitride layer and the pWFM layer are selectively removed from the NFET. Figures 9A-9B As shown, portions of the dual metal nitride layer 129 and the pWFM layer 130 may be removed from the NFET 102N1. The selective removal process may include the following sequential operations: (i) patterning a masking layer 946 (e.g., a photoresist layer) on portions of the dual metal nitride layer 129 and the pWFM layer 130 on the PFET 102P1, as shown; Figures 9A-9BAs shown, (ii) a portion of the pWFM layer 130 is etched from the NFET 102N1, and (iii) a portion of the bimetallic layer 129 is etched from the NFET 102N1 to form Figure 9B In some embodiments, operation 230 may be an ex-situ operation.

[0060] refer to Figure 2 In operation 235, an nWFM layer, an adhesion layer, and a gate metal fill layer are formed on the pWFM layer of the PFET and on the HK dielectric layer of the NFET. Figures 10A-11B As shown, an nWFM layer 131, an adhesion layer 132, and a gate metal filling layer 133 may be formed. In some embodiments, the formation of the nWFM layer 131 may include depositing a TiAl layer having a thickness of about 1 nm to about 3 nm in an ALD process at a temperature of about 350° C. to about 475° C. using TiCl 4 and TEA or TMA as precursors. In some embodiments, the ALD process for depositing the TiAl layer may include about 4 cycles to about 12 cycles, wherein one cycle may include the following sequential time periods: (i) TiCl 4 gas flow, (ii) TiCl 4 gas purge process, (iii) TEA or TMA gas flow, and (iv) TEA or TMA gas purge process. After the nWFM layer 130 is formed, the adhesion layer 132 and the gate metal filling layer 133 may be deposited, as shown. Figures 10A-10B As shown, chemical mechanical polishing can then be performed to form Figures 11A-11B structure.

[0061] Figure 12 is a flow chart of an example method 1200 for manufacturing a semiconductor device 100 according to some embodiments. For illustrative purposes, reference will be made to Figures 13A-17B An example manufacturing process for manufacturing the semiconductor device 100 is shown to describe Figure 12 The operation shown. Figures 13A-17B is a cross-sectional view of the semiconductor device 100 along lines AA and BB at various stages of fabrication according to some embodiments. Depending on the particular application, the operations may be performed in a different order, or not performed at all. It should be noted that the method 1200 may not produce a complete semiconductor device 100. Therefore, it is understood that additional processes may be provided before, during, and after the method 1200, and that some other processes may only be briefly described herein. Figures 13A-17B There are Figures 1A-1C Elements with the same tag as the elements in .

[0062] refer to Figure 12 , similar to operations 205-215, operations 1205-1215 may be performed to form a Figures 5A-5B structure.

[0063] refer to Figure 12 In operation 1220, a metal doped region is selectively formed in a portion of the HK gate dielectric layer of the PFET, and a double metal nitride layer and a pWFM layer are selectively formed on the portion of the HK gate dielectric layer. Figures 13A-14B As shown, a metal doped region 128Pd may be selectively formed within a portion of the HK gate dielectric layer 128 of the PFET 102P1 ("HKPFET portion"), and a dual metal nitride layer 129 and a pWFM layer 130 may be selectively formed on the HK PFET portion. The selective formation process may include the following sequential operations: (i) patterning a masking layer 1246 (e.g., a photoresist layer) on a portion of the HK gate dielectric layer 128 of the NFET 102N1, as shown; Figures 13A-13B As shown, (ii) a metal doped region 128Pd is formed in the HKPFET portion, and (iii) a double metal nitride layer 129 and a pWFM layer 130 are formed on the HK PFET portion. The process for forming the metal doped region 128Pd may be similar to Figure 2 The process described in operation 220 of FIG. 1 and the process for forming the bimetal nitride layer 129 and the pWFM layer 130 may be similar to FIG. Figure 2 The process is described in operation 225.

[0064] refer to Figure 12 In operation 1225, an nWFM layer, an adhesion layer, and a gate metal fill layer are formed on the pWFM layer of the PFET and on the HK dielectric layer of the NFET. Figures 15A-17B As shown, a nWFM layer 131, an adhesive layer 132, and a gate metal filling layer 133 may be formed. Before forming the nWFM layer 131, the adhesive layer 132, and the gate metal filling layer 133, Figure 14B Remove the masking layer 1246 to form the structure Figure 15B After removing the masking layer 1246, Figure 2 The nWFM layer 131, the adhesion layer 132 and the gate metal filling layer 133 are formed in a similar process to the process described in operation 235 to form Figures 16A-16B The structure can then be subjected to a chemical mechanical polishing process to form Figures 17A-17B structure.

[0065] The present disclosure provides a multi-threshold voltage device including FETs (e.g., PFETs 102P1-102P4 and NFETs 102N1-102N4) having different threshold voltages from one another, and provides an example method for forming such FETs on the same substrate (e.g., substrate 106). The example method forms PFETs having WFM layers (e.g., pWFM layer 130) of similar material and thickness but different threshold voltages on the same substrate. In some embodiments, PFETs having different gate structure configurations but similar WFM layers can be selectively formed on the same substrate to achieve different threshold voltages from one another. The different gate structures can have (i) metal doped regions of different metal concentrations within a high-K (HK) gate dielectric layer and (ii) a dual metal nitride layer of different metal concentrations between the HK gate dielectric layer and the WFM layer. The different metal concentrations can result in gate structures having different EWF values and threshold voltages. In some embodiments, varying the metal concentration within a range of approximately 2 atomic % to approximately 10 atomic % can cause an approximately ±80 mV shift in the EWF value, and a ±50 mV shift in the threshold voltage of the masking layer. Therefore, adjusting the metal concentration within the HK gate dielectric layer and between the HK gate dielectric layer and the WFM layer can adjust the EWF value of the PFET gate structure, thereby adjusting the threshold voltage of the PFET without changing the material and / or thickness of the WFM layer.

[0066] In some embodiments, a semiconductor device includes: a substrate; a fin structure disposed on the substrate; a nanostructured channel region disposed on the fin structure; and a gate-around-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes: a high-K (HK) gate dielectric layer having a metal-doped region, the metal-doped region having a dopant of a first metal material; a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer; a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer; an n-type work function metal (nWFM) layer disposed on the pWFM layer; and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metal material, and the bimetallic nitride layer includes the first metal material and the second metal material.

[0067] In some embodiments, a semiconductor device includes: a substrate; a p-type FET having a first gate structure disposed on the substrate; and an n-type FET having a second gate structure disposed on the substrate. The first gate structure and the second gate structure include: a high-K (HK) gate dielectric layer having a metal-doped region, the metal-doped region having a dopant of a first metal; an n-type work function metal (nWFM) layer disposed on the HK gate dielectric layer; and a gate metal fill layer disposed on the nWFM layer. The first gate structure includes a p-type work function metal (pWFM) layer and a bimetallic nitride layer interposed between the HK gate dielectric layer and the nWFM layer. The pWFM has a second metal, and the bimetallic nitride layer has the first metal and the second metal.

[0068] In some embodiments, a method includes forming a nanostructured channel region on a fin structure; forming a gate opening surrounding the nanostructured channel region; depositing a high-K (HK) gate dielectric layer within the gate opening; forming a metal-doped region having a dopant of a second metal within the HK gate dielectric layer; forming a dual-metal nitride layer on the HK gate dielectric layer; depositing a p-type work function metal (pWFM) layer on the dual-metal nitride layer; depositing an n-type work function metal (nWFM) layer on the pWFM layer; and depositing a gate metal fill layer on the nWFM layer. The HK gate dielectric layer includes a first metal and a second metal different from the first metal. The pWFM layer includes a third metal different from the first and second metals, and the dual-metal nitride layer includes the second metal and the third metal.

[0069] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications in the present disclosure without departing from the spirit and scope of the present disclosure.

[0070] Example 1. A semiconductor device comprising: a substrate; a fin structure disposed on the substrate; a nanostructured channel region disposed on the fin structure; and a gate-surround GAA structure surrounding the nanostructured channel region, wherein the GAA structure comprises: a high-K HK gate dielectric layer having a metal-doped region, the metal-doped region having a dopant of a first metal material; a first work function metal WFM layer disposed on the HK gate dielectric layer, wherein the first WFM layer comprises a second metal material; a bimetallic nitride layer inserted between the HK gate dielectric layer and the first WFM layer, wherein the bimetallic nitride layer comprises the first metal material and the second metal material; a second WFM layer disposed on the first WFM layer; and a gate metal fill layer disposed on the second WFM layer.

[0071] Example 2. The semiconductor device of Example 1, wherein a concentration of the first metal material in the metal-doped region is greater than a concentration of the first metal material in the bi-metal nitride layer.

[0072] Example 3. The semiconductor device of Example 1, wherein a concentration of the second metallic material in the first WFM layer is greater than a concentration of the second metallic material in the bi-metal nitride layer.

[0073] Example 4. The semiconductor device of Example 1, wherein the first WFM layer is a p-type WFM layer, and the second WFM layer is an n-type WFM layer.

[0074] Example 5. The semiconductor device of Example 1, wherein a concentration profile of the first metal material in the double metal nitride layer has a decreasing slope from a bottom surface of the double metal nitride layer to a top surface of the double metal nitride layer.

[0075] Example 6. The semiconductor device of Example 1, wherein, in the bi-metal nitride layer, a concentration of the first metal material is greater than a concentration of the second metal material.

[0076] Example 7. The semiconductor device of Example 1, wherein a concentration of the first metal material in the bi-metal nitride layer is in a range of 2 atomic % to 10 atomic %.

[0077] Example 8. The semiconductor device of Example 1, wherein a concentration ratio of the first metal material in the metal doped region to the metal in the undoped region of the HK gate dielectric layer is in a range of 0.05 to 0.5.

[0078] Example 9. The semiconductor device of Example 1, wherein a thickness of the metal doped region is greater than a thickness of the bimetallic nitride layer.

[0079] Example 10. The semiconductor device of Example 1, wherein the first metal material comprises aluminum and the second metal material comprises titanium.

[0080] Example 11. A semiconductor device comprising: a substrate; a p-type FET having a first gate structure disposed on the substrate; and an n-type FET having a second gate structure disposed on the substrate, wherein the first gate structure and the second gate structure comprise: a high-K HK gate dielectric layer having a metal-doped region, the metal-doped region having a dopant of a first metal, an n-type work function metal nWFM layer disposed on the HK gate dielectric layer, and a gate metal fill layer disposed on the nWFM layer, and wherein the first gate structure comprises a p-type work function metal pWFM layer and a bimetallic nitride layer inserted between the HK gate dielectric layer and the nWFM layer, the pWFM having a second metal, and the bimetallic nitride layer having the first metal and the second metal.

[0081] Example 12. The semiconductor device of Example 11, wherein the first metal comprises aluminum.

[0082] Example 13. The semiconductor device of Example 11, wherein, in the bimetallic nitride layer, a concentration of the first metal is greater than a concentration of the second metal.

[0083] Example 14. The semiconductor device of Example 11, wherein a concentration of the first metal in the metal-doped region is greater than a concentration of the first metal in the bi-metal nitride layer.

[0084] Example 15. A method for manufacturing a semiconductor device, comprising: forming a nanostructured channel region on a fin structure; forming a gate opening around the nanostructured channel region; depositing a high-K HK gate dielectric layer within the gate opening, wherein the HK gate dielectric layer includes a first metal; forming a metal-doped region having a dopant of a second metal within the HK gate dielectric layer, wherein the second metal is different from the first metal; forming a bimetallic nitride layer on the HK gate dielectric layer; depositing a p-type work function metal pWFM layer on the bimetallic nitride layer, wherein the pWFM layer includes a third metal different from the first metal and the second metal, and the bimetallic nitride layer includes the second metal and the third metal; depositing an n-type work function metal nWFM layer on the pWFM layer; and depositing a gate metal fill layer on the nWFM layer.

[0085] Example 16. The method according to Example 15, wherein forming the metal-doped region includes: performing a first impregnation process on the HK gate dielectric layer using a precursor of the third metal; and after the first impregnation process, performing a second impregnation process on the HK gate dielectric layer using a precursor of the second metal.

[0086] Example 17. The method of Example 15, wherein forming the metal-doped region comprises doping a region of the HK gate dielectric layer with the second metal, and wherein the metal-doped region comprises a concentration ratio of the second metal to the first metal of 0.05 to 0.5.

[0087] Example 18. A method according to Example 15, wherein forming the dual metal nitride layer includes: depositing a first metal layer including the third metal on the HK gate dielectric layer; depositing a second metal layer on the first metal layer, wherein the second metal layer includes the second metal; and converting the first metal layer into a third metal layer during depositing the second metal layer, wherein the third metal layer includes the second metal and the third metal.

[0088] Example 19. The method of Example 15, wherein forming the bimetallic nitride layer comprises forming the bimetallic nitride layer wherein a concentration of the second metal is greater than a concentration of the third metal.

[0089] Example 20. The method of Example 15, wherein forming the bimetallic nitride layer comprises forming the bimetallic nitride layer wherein a concentration of the second metal is less than a concentration of the second metal in the metal-doped region.

Claims

1. A semiconductor device comprising: substrate; a fin structure disposed on the substrate; a nanostructured channel region disposed on the fin structure; as well as A gate-around GAA structure surrounds the nanostructure channel region, wherein the GAA structure includes: a high-K HK gate dielectric layer having a metal-doped region having a dopant of a first metal material; a first WFM layer disposed on the HK gate dielectric layer, wherein the first WFM layer comprises a second metal material; a double metal nitride layer interposed between the HK gate dielectric layer and the first WFM layer, wherein the double metal nitride layer comprises the first metal material and the second metal material, and wherein a concentration profile of the first metal material in the double metal nitride layer has a decreasing slope from a bottom surface of the double metal nitride layer to a top surface of the double metal nitride layer; a second WFM layer disposed on the first WFM layer; and A gate metal filling layer is disposed on the second WFM layer.

2. The semiconductor device according to claim 1, wherein The concentration of the first metal material in the metal-doped region is greater than the concentration of the first metal material in the bi-metal nitride layer.

3. The semiconductor device according to claim 1, wherein A concentration of the second metallic material in the first WFM layer is greater than a concentration of the second metallic material in the bi-metallic nitride layer.

4. The semiconductor device according to claim 1, wherein The first WFM layer is a p-type WFM layer, and the second WFM layer is an n-type WFM layer. The semiconductor device according to claim 1 , wherein In the bi-metal nitride layer, the concentration of the first metal material is greater than the concentration of the second metal material. The semiconductor device according to claim 1 , wherein: The concentration of the first metal material in the bi-metal nitride layer is in a range of 2 atomic % to 10 atomic %.

7. The semiconductor device according to claim 1, wherein A concentration ratio of the first metal material in the metal doped region to the metal in the undoped region of the HK gate dielectric layer is in a range of 0.05 to 0.

5.

8. The semiconductor device according to claim 1, wherein The thickness of the metal doping region is greater than the thickness of the bimetallic nitride layer.

9. The semiconductor device according to claim 1, wherein The first metal material includes aluminum, and the second metal material includes titanium.

10. A semiconductor device comprising: substrate; a p-type FET having a first gate structure disposed on the substrate; as well as An n-type FET having a second gate structure disposed on the substrate, Wherein, the first gate structure and the second gate structure include: a high K HK gate dielectric layer having a metal doped region having a dopant of a first metal, a nWFM layer disposed on the HK gate dielectric layer, and A gate metal filling layer is provided on the nWFM layer, and The first gate structure includes a pWFM layer and a bimetallic nitride layer inserted between the HK gate dielectric layer and the nWFM layer, the pWFM layer has a second metal, and the bimetallic nitride layer has the first metal and the second metal, wherein the concentration distribution of the first metal in the bimetallic nitride layer has a decreasing slope from the bottom surface of the bimetallic nitride layer to the top surface of the bimetallic nitride layer. The semiconductor device according to claim 10 , wherein: The first metal includes aluminum.

12. The semiconductor device according to claim 10, wherein In the bi-metal nitride layer, a concentration of the first metal is greater than a concentration of the second metal.

13. The semiconductor device according to claim 10, wherein A concentration of the first metal in the metal-doped region is greater than a concentration of the first metal in the bi-metal nitride layer.

14. A method for manufacturing a semiconductor device, comprising: forming a nanostructured channel region on the fin structure; forming a gate opening surrounding the nanostructure channel region; depositing a high-K HK gate dielectric layer within the gate opening, wherein the HK gate dielectric layer comprises a first metal; forming a metal-doped region having a dopant of a second metal within the HK gate dielectric layer, wherein the second metal is different from the first metal; forming a double metal nitride layer on the HK gate dielectric layer; depositing a pWFM layer on the bi-metal nitride layer, wherein the pWFM layer includes a third metal different from the first metal and the second metal, and the bi-metal nitride layer includes the second metal and the third metal; depositing an nWFM layer on the pWFM layer; and depositing a gate metal filling layer on the nWFM layer, Wherein, forming the metal-doped region comprises: performing a first dipping process on the HK gate dielectric layer with a precursor of the third metal; and After the first dipping process, a second dipping process is performed on the HK gate dielectric layer using a precursor of the second metal.

15. The method according to claim 14, wherein Forming the metal doped region further includes doping a region of the HK gate dielectric layer with the second metal, and wherein the metal doped region includes a concentration ratio of the second metal to the first metal of 0.05 to 0.

5.

16. The method according to claim 14, wherein Forming the bimetallic nitride layer includes: depositing a first metal layer including the third metal on the HK gate dielectric layer; depositing a second metal layer on the first metal layer, wherein the second metal layer comprises the second metal; and The first metal layer is converted into a third metal layer during deposition of the second metal layer, wherein the third metal layer includes the second metal and the third metal.

17. The method according to claim 14, wherein: Forming the double metal nitride layer includes forming the double metal nitride layer in which a concentration of the second metal is greater than a concentration of the third metal.

18. The method according to claim 14, wherein Forming the double metal nitride layer includes forming the double metal nitride layer in which a concentration of the second metal is less than a concentration of the second metal in the metal-doped region.

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