Vertical 2-transistor memory cell

Abstract

Some embodiments include apparatus and methods of forming the apparatus. One of the apparatus and methods includes a memory cell having a first transistor and a second transistor positioned above a substrate. The first transistor includes a channel region. The second transistor includes a channel region positioned above and electrically separated from the channel region of the first transistor. The memory cell includes a memory element positioned on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor and electrically coupled to a channel of the second transistor.

Description

[0001] Priority application

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 62 / 785,119, filed on December 26, 2018, which is incorporated herein by reference in its entirety. Background Art

[0003] Memory devices are widely used in computers and many other electronic items to store information. Memory devices are generally classified into two types: volatile memory devices and non-volatile memory devices. Examples of volatile memory devices include dynamic random access memory (DRAM) devices. Examples of non-volatile memory devices include flash memory devices (e.g., flash memory sticks). Memory devices generally have many memory cells that store information. In volatile memory devices, if the supply power is disconnected from the memory device, the information stored in the memory cells is lost. In non-volatile memory devices, the information stored in the memory cells is retained even if the supply power is disconnected from the memory device.

[0004] The description herein relates to volatile memory devices. Most conventional volatile memory devices store information in the form of electric charge in a capacitor structure contained in a memory cell. As the demand for device storage density increases, many conventional techniques provide ways to reduce the size of the memory cell in order to increase the device storage density for a given device area. However, if the memory cell size shrinks to a certain size, then physical limitations and manufacturing constraints may set challenges for such conventional techniques. Unlike some conventional memory devices, the memory devices described herein include features that may overcome the challenges faced by conventional techniques. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A block diagram is shown of an apparatus in the form of a memory device including volatile memory cells according to some embodiments described herein.

[0006] Figure 2 A schematic diagram showing a portion of a memory device including a memory array of 2-transistor (2T) memory cells according to some embodiments described herein.

[0007] Figure 3 A diagram showing example voltages used during a read operation of a memory device according to some embodiments described herein Figure 2 Memory device.

[0008] Figure 4 A diagram showing example voltages used during a write operation of a memory device according to some embodiments described herein Figure 2 Memory device.

[0009] Figure 5 Demonstration according to some embodiments described herein may be Figure 2 A schematic diagram of a portion of a memory device of a variation of a memory device.

[0010] Figures 6 to 30 Different views of elements during the process of forming a memory device according to some embodiments of the present invention are shown.

[0011] Figure 31 to Figure 35 Different views of elements during the process of forming another memory device are shown according to some embodiments of the present invention.

[0012] Fig.36A , Fig.36B and Fig.36C Different views of the structure of a memory device including multiple stacks of memory cells according to some embodiments described herein are shown. DETAILED DESCRIPTION

[0013] The memory devices described herein include volatile memory cells, wherein each of the memory cells may include two transistors (2T memory cells). One of the two transistors has a charge storage structure that may form a memory element of the memory cell to store information. The memory devices described herein may have a structure that allows the size of the memory device to be relatively smaller than that of similar conventional memory devices (e.g., a 4F2 cell footprint). Figure 1 to Figure 35 Other improvements and benefits of the described memory device and variations thereof are discussed.

[0014] Figure 1 A block diagram of an apparatus in the form of a memory device 100 including volatile memory cells is shown according to some embodiments described herein. The memory device 100 includes a memory array 101, which may contain memory cells 102. The memory device 100 is a volatile memory device (e.g., a DRAM device) such that the memory cells 102 are volatile memory cells. Therefore, if the supply power (e.g., the supply voltage Vcc) is disconnected from the memory device 100, the information stored in the memory cells 102 may be lost (e.g., invalid). Hereinafter, Vcc is mentioned to represent some voltage level, however, it is not limited to the supply voltage (e.g., Vcc) of the memory device (e.g., memory device 100). For example, if the memory device (e.g., memory device 100) has an internal voltage generator (e.g., Vcc) that generates an internal voltage based on Vcc, the internal voltage may be lost. Figure 1 Not shown), then such internal voltage can be used instead of Vcc.

[0015] In the physical structure of the memory device 100, each of the memory cells 102 may include transistors (e.g., two transistors) vertically formed in different levels (e.g., stacked on top of each other in different layers) above a substrate (e.g., a semiconductor substrate) of the memory device 100. The structure of the memory array 101 including the memory cells 102 may include the following reference Figures 2 to 35 Describes the structure of the memory array and memory cells.

[0016] like Figure 1 , memory device 100 can include access lines 104 (e.g., “word lines”) and data lines (e.g., bit lines) 105. Memory device 100 can use signals on access lines 104 (e.g., word line signals) to access memory cells 102 and data lines 105 to provide information (e.g., data) to be stored (e.g., written) in memory cells 102 or read (e.g., sensed) from memory cells 102.

[0017] The memory device 100 may include an address register 106 to receive address information ADDR (e.g., row address signals and column address signals) on a line (e.g., address line) 107. The memory device 100 may include a row access circuit (e.g., X-decoder) 108 and a column access circuit (e.g., Y-decoder) 109 operable to decode the address information ADDR from the address register 106. Based on the decoded address information, the memory device 100 may determine which memory cells 102 are to be accessed during a memory operation. The memory device 100 may perform a write operation to store information in the memory cells 102, and perform a read operation to read (e.g., sense) information in the memory cells 102 (e.g., previously stored information). The memory device 100 may also perform an operation (e.g., a refresh operation) to refresh (e.g., keep valid) the value of the information stored in the memory cells 102. Each of memory cells 102 may be configured to store information that may represent a single bit of at most one bit (e.g., having a binary zero (“0”) or a binary one (“1”)) or more than one bit (e.g., a plurality of bits having a combination of at least two binary bits).

[0018] Memory device 100 may receive supply voltages on lines 130 and 132, respectively, including supply voltages Vcc and Vss. Supply voltage Vss may operate at ground potential (e.g., having a value of substantially zero volts). Supply voltage Vcc may include an external voltage supplied to memory device 100 from an external power source such as a battery or an alternating current to direct current (AC-DC) converter circuit.

[0019] like Figure 1, the memory device 100 may include a memory control unit 118 that includes circuits (e.g., hardware components) to control memory operations (e.g., read and write operations) of the memory device 100 based on control signals on lines (e.g., control lines) 120. Examples of signals on lines 120 include a row access select signal RAS*, a column access select signal CAS*, a write enable signal WE*, a chip select signal CS*, a clock signal CK, and a clock enable signal CKE. These signals may be part of the signals provided to the DRAM device.

[0020] like Figure 1 , memory device 100 can include lines (e.g., global data lines) 112 that can carry signals DQ0-DQN. In a read operation, the value of the information (read from memory cell 102) provided to line 112 (in the form of signals DQ0-DQN) (e.g., a "0" or a "1") can be based on the value of the signal on data line 105. In a write operation, the value of the information (to be stored in memory cell 102) provided to data line 105 (e.g., a "0" or a "1") can be based on the value of the signals DQ0-DQN on line 112.

[0021] Memory device 100 may include sense circuits 103, select circuits 115, and input / output (I / O) circuits 116. Column access circuits 109 may selectively activate signals on lines (e.g., select lines) based on address signals ADDR. Select circuits 115 may respond to signals on lines 114 to select signals on data lines 105. The signals on data lines 105 may represent the value of information to be stored in memory cell 102 (e.g., during a write operation) or the value of information to be read (e.g., sensed) from memory cell 102 (e.g., during a read operation).

[0022] I / O circuitry 116 may be operable to provide information read from memory cell 102 to line 112 (e.g., during a read operation) and to provide information from line 112 (e.g., provided by an external device) to data line 105 for storage in memory cell 102 (e.g., during a write operation). Line 112 may include a node within memory device 100 or a pin (or solder ball) on a package in which memory device 100 may reside. Other devices external to memory device 100 (e.g., a hardware memory controller or a hardware processor) may communicate with memory device 100 via lines 107, 112, and 120.

[0023] The memory device 100 may include other components that are not shown to help focus on the embodiments described herein. The memory device 100 may be configured to include a memory device having the following references Figures 2 to 35 At least a portion of a memory device with associated structure and operation is described.

[0024] One of ordinary skill in the art will recognize that the memory device 100 may include other components, some of which are not shown. Figure 1 In order not to obscure the example embodiments described herein. At least a portion of the memory device 100 (eg, a portion of the memory array 101) may include the same Fig.35 Similar or identical structure and operation to any of the memory devices described.

[0025] Figure 2 A schematic diagram showing a portion of a memory device 200 including a memory array 201 according to some embodiments described herein. The memory device 200 may correspond to Figure 1 For example, the memory array 201 may be formed Figure 1 A portion of the memory array 101. Figure 2 , memory device 200 may include memory cells 210-215, which are volatile memory cells (eg, DRAM cells). For simplicity, similar or identical elements among memory cells 210-215 are given the same labels.

[0026] Each of the memory cells 210 to 215 may include two transistors T1 and T2. Therefore, each of the memory cells 210 to 215 may be referred to as a 2T memory cell (e.g., a 2T gain cell). Each of the transistors T1 and T2 may include a field effect transistor (FET). The transistor T1 may include a charge storage-based structure (e.g., based on a floating gate). Figure 2 As shown in FIG. 1 , each of the memory cells 210-215 may include a charge storage structure 202, which may include a floating gate (e.g., floating gate 202) of transistor T1. The charge storage structure 202 may form a memory element of a corresponding memory cell among the memory cells 210-215. The charge storage structure 202 may store charge. The value (e.g., "0" or "1") of the information stored in a particular memory cell among the memory cells 210-215 may be based on the amount of charge in the charge storage structure 202 of that particular memory cell.

[0027] like Figure 2 , the transistor T2 (e.g., the channel region of transistor T2) of a particular memory cell among the memory cells 210-215 may be electrically coupled to (e.g., directly coupled to) the charge storage structure 202 of that particular memory cell. Thus, a circuit path (e.g., a current path) may be formed directly between the transistor T2 of the particular memory cell and the charge storage structure 202 of that particular memory cell during operation (e.g., a write operation) of the memory device 200.

[0028] The memory cells 210 to 215 may be arranged in a memory cell group 201. 0 and 201 1 middle. Figure 2 Two memory cell groups (eg, 201 0 and 201 1 ) as an example. However, the memory device 200 may include more than two memory cell groups. 0 and 201 1 The memory cell group 201 may include the same number of memory cells. 0 The memory cell group 201 may include memory cells 210, 212, and 214. 1 Memory cells 211 , 213 , and 215 may be included. Figure 2 Display memory cell group 201 0 and 201 1 As an example, three memory cells in each of the memory cell groups 201 are shown. 0 and 201 1 The number of memory cells in may be different from three.

[0029] The memory device 200 may perform a write operation to store information in the memory cells 210 to 215, and perform a read operation to read (e.g., sense) information from the memory cells 210 to 215. The memory device 200 may be configured to operate as a DRAM device. However, unlike some conventional DRAM devices that store information in a structure such as a container of a capacitor, the memory device 200 may store information in the form of charge in a charge storage structure 202 (which may be a floating gate structure). As mentioned above, the charge storage structure 202 may be a floating gate (e.g., floating gate 202) of the transistor T1. Therefore, the memory device 200 may be referred to as a floating gate-based DRAM device.

[0030] like Figure 2 , memory device 200 may include access lines (eg, word lines) 241, 242, and 243 that may carry respective signals (eg, word line signals) WL1, WL2, and WL3. Access lines 241, 242, and 243 may be used to access memory cell group 201. 0 and 201 1Both. Each of the access lines 241, 242, and 243 may be structured as at least one conductive line (one conductive line or multiple conductive lines that may be electrically coupled to each other (e.g., shorted)). The access lines 241, 242, and 243 may be selectively activated (e.g., activated one at a time) during an operation (e.g., a read or write operation) of the memory device 200 to access one or more selected memory cells among the memory cells 210 to 215. The selected cells may be referred to as target cells. In a read operation, information may be read from the one or more selected memory cells. In a write operation, the information may be stored information in the one or more selected memory cells.

[0031] In the memory device 200, a single access line (e.g., a single word line) may be used to control (e.g., turn on or off) the transistors T1 and T2 of the corresponding memory cells during a read or write operation of the memory device 200. Two separate access lines may be used to control the corresponding transistors T1 and T2 during access to the corresponding memory cells during read and write operations. However, using a single access line (e.g., a common access line) in the memory device 200 to control both the transistors T1 and T2 of the corresponding memory cells may save space and simplify the operation of the memory device 200.

[0032] In memory device 200, the gate of each of transistors T1 and T2 may be part of a corresponding access line (eg, a corresponding word line). Figure 2 As shown in , the gate of each of the transistors T1 and T2 of the memory cell 210 can be part of the access line 241. The gate of each of the transistors T1 and T2 of the memory cell 211 can be part of the access line 241.

[0033] The gate of each of the transistors T1 and T2 of the memory cell 212 may be part of the access line 242. The gate of each of the transistors T1 and T2 of the memory cell 213 may be part of the access line 242.

[0034] The gate of each of the transistors T1 and T2 of the memory cell 214 may be part of the access line 243. The gate of each of the transistors T1 and T2 of the memory cell 215 may be part of the access line 243.

[0035] The memory device 200 may include data lines (e.g., read bit lines) 221, 221', 221, 222, and 222' that may carry corresponding signals (e.g., read bit line signals) BL1, BL1*, BL2, and BL2*, and data lines (e.g., write bit lines) 221W and 222W that may carry corresponding signals (e.g., write bit line signals) BL1W and BL2W. Each of the data lines 221, 221', 222, 222', 221W, and 222W may be structured as a conductive line. During a read operation, the memory device 200 may use the data lines 221 and 221' to obtain data from the memory cell group 201. 0 The selected memory cell of the memory cell group 201 is read (eg, sensed) and the data lines 222 and 222′ are used to read the selected memory cell of the memory cell group 201. 1 During a write operation, the memory device 200 may use the data line 221W to provide the data to be stored in the memory cell group 201. 0 The information in the selected memory cell is provided using the data line 222W to be stored in the memory cell group 201 1 The information in the selected memory cell.

[0036] The memory device 200 may include a read path (eg, a circuit path). Information read from a selected memory cell during a read operation may be obtained via the read path coupled to the selected memory cell. 0 In the example of FIG. 2 , the read path of a particular memory cell (eg, 210, 212, or 214) may include a current path (eg, a read current path) through the channel region of the transistor T1 of that particular memory cell and the data lines 221 and 221′. 1 In the embodiment, the read path of a particular memory cell (e.g., 221, 213, or 215) may include a current path (e.g., a read current path) through the channel region of transistor T1 of that particular memory cell and data lines 222 and 222'. Since transistor T1 may be used for the read path to read information from the corresponding memory cell during a read operation, transistor T1 may be referred to as a read transistor and the channel region of transistor T1 may be referred to as a read channel region.

[0037] The memory device 200 may include a write path (eg, a circuit path). Information to be stored in a selected memory cell during a write operation may be provided to the selected memory cell via the write path coupled to the selected memory cell. 0In [the figure], the write path of a specific memory cell may include a current path (e.g., a write current path) through the channel region of transistor T2 of that specific memory cell and data line 221W. In memory cell group 201 1 In [the figure], the write path of a specific memory cell (e.g., 221, 213, or 215) may include a current path (e.g., a write current path) through the channel region of transistor T2 of that specific memory cell and data line 222W. Since transistor T2 can be used in the write path to store information in the corresponding memory cell during a write operation, transistor T2 can be referred to as a write transistor and the channel region of transistor T1 can be referred to as a write channel region.

[0038] Each of transistors T1 and T2 may have a threshold voltage (Vt). Transistor T1 has a threshold voltage Vt1. Transistor T2 has a threshold voltage Vt2. The values of threshold voltages Vt1 and Vt2 may be different (unequal values). For example, the value of threshold voltage Vt2 may be greater than the value of threshold voltage Vt1. The difference between the values of threshold voltages Vt1 and Vt2 allows the reading (e.g., sensing) of the information stored in charge storage structure 202 in transistor T1 on the read path without affecting (e.g., without turning on) transistor T2 on the write path (e.g., the path through transistor T2). This can prevent charge leakage from charge storage structure 202 via transistor T2 of the write path.

[0039] In the structure of memory device 200, transistors T1 and T2 can be formed (e.g., engineered) such that the threshold voltage Vt1 of transistor T1 can be less than zero volts (e.g., Vt1 < 0V) regardless of the value (e.g., “0” or “1”) of charge storage structure 202 that stores information in transistor T1, and Vt1 < Vt2. When information having a value “0” is stored in charge storage structure 202, charge storage structure 202 can be in state “0”. When information having a value “1” is stored in charge storage structure 202, charge storage structure 202 can be in state “1”. Thus, in this structure, the relationship between the values of threshold voltages Vt1 and Vt2 can be expressed as follows: Vt1 for state “0” < Vt1 for state “1” < 0V, and Vt2 = 0V (or alternatively Vt2 > 0V).

[0040] In an alternative structure of memory device 200, transistors T1 and T2 can be formed (e.g., engineered) such that Vt1 for state “0” < Vt1 for state “1”, where Vt1 for state “0” < 0V (or alternatively Vt1 for state “0” = 0V), Vt1 for state “1” > 0V, and Vt1 < Vt2.

[0041] In another alternative configuration, transistors T1 and T2 can be formed (e.g., engineered) such that Vt1 (for state "0") < Vt1 (for state "1"), where Vt1 for state "0" = 0V (or alternatively Vt1 for state "0" > 0V), and Vt1 < Vt2.

[0042] During a read operation of memory device 200, only one memory cell of the same memory cell group can be selected one at a time to read information from the selected memory cell. For example, memory cells 210, 212, and 214 of memory cell group 201 0 can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells 210, 212, and 214 in this example). In another example, memory cells 212, 213, and 215 of memory cell group 201 1 can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells 221, 213, and 215 in this example).

[0043] During a read operation, different memory cell groups (e.g., memory cell group 201 0 and 201 1 ) sharing the same access line (e.g., access lines 241, 242, or 243) can be selected in parallel (or alternatively sequentially). For example, memory cells 210 and 211 can be selected in parallel during a read operation to read (e.g., read in parallel) information from memory cells 210 and 211. Memory cells 212 and 213 can be selected in parallel during a read operation to read (e.g., read in parallel) information from memory cells 212 and 213. Memory cells 214 and 215 can be selected in parallel during a read operation to read (e.g., read in parallel) information from memory cells 214 and 215.

[0044] The value of the information read from the selected memory cell of memory cell group 201 0 during a read operation can be determined based on the value of the current detected (e.g., sensed) from the read path (described above) of transistors T1 and data lines 221 and 221' including the selected memory cell (e.g., memory cells 210, 212, or 214). The value of the information read from the selected memory cell of memory cell group 201 1 during a read operation can be determined based on the value of the current detected (e.g., sensed) from the read path of transistors T1 and data lines 222 and 222' including the selected memory cell (e.g., memory cells 211, 213, or 215).

[0045] Memory device 200 may include detection circuitry (not shown) operable during a read operation to detect (e.g., sense) a current on a read path including data lines 221 and 221' (e.g., current I1, not shown), and to detect a current on a read path including data lines 222 and 222' (e.g., current I2, not shown). The value of the detected current may be based on the value of the information stored in the selected memory cell. For example, depending on the value of the information stored in memory cell group 201, the current I2 may be detected by the memory cell group 201. 0 The value of the current detected between the data lines 221 and 221' (eg, the value of the current I1) may be zero or greater than zero depending on the value of the information stored in the selected memory cell of the memory cell group 201. 1 The value of the detected current between data lines 222 and 222' (e.g., the value of current I2) may be zero or greater than zero depending on the value of the information in the selected memory cell. The memory device 200 may include a circuit (not shown) that converts the value of the detected current into the value of the information stored in the selected memory cell (e.g., "0", "1", or a combination of multi-bit values).

[0046] During a write operation of the memory device 200, only one memory cell of the same memory cell group may be selected one at a time to store information in the selected memory cell. For example, the memory cell group 201 may be selected one at a time during a write operation. 0 210, 212, and 214 to store information in a selected memory cell (e.g., one of the memory cells 210, 212, and 214 in this example). In another example, the memory cell group 201 may be selected one at a time during a write operation. 1 212, 213, and 215 to store information in a selected memory cell (eg, one of memory cells 211, 213, and 215 in this example).

[0047] During a write operation, different groups of memory cells (eg, memory cell group 201) sharing the same access line (eg, access line 241, 242, or 243) may be selected in parallel (or alternatively may be selected sequentially). 0 and 201 1). For example, memory cells 210 and 211 may be selected in parallel during a write operation to store information (e.g., stored in parallel) in memory cells 210 and 211. Memory cells 212 and 213 may be selected in parallel during a write operation to store information (e.g., stored in parallel) in memory cells 212 and 213. Memory cells 214 and 215 may be selected in parallel during a write operation to store information (e.g., stored in parallel) in memory cells 214 and 215.

[0048] To be stored in memory cell group 201 during a write operation 0 The information in the selected memory cell of the memory cell group 201 may be provided via a write path including data line 221W and transistor T2 of the selected memory cell (eg, memory cell 210, 212, or 214). 1 The information in the selected memory cell of may be provided via a write path including data line 222W and transistor T2 of the selected memory cell (e.g., memory cell 212, 213, or 215). As described above, the value (e.g., a binary value) of the information stored in a particular memory cell among the memory cells 210-215 may be based on the amount of charge in the charge storage structure 202 of that particular memory cell.

[0049] In a write operation, the amount of charge in the charge storage structure 202 of the selected memory cell may be changed (to reflect the value of the information stored in the selected memory cell) by applying a voltage to a write path including the transistor T2 of that particular memory cell and a data line (e.g., data line 221W or 222W) coupled to that particular memory cell. For example, if the information to be stored in the selected memory cell among the memory cells 210, 212, and 214 has one value (e.g., “0”), a voltage having one value (e.g., 0V) may be applied to the data line 221W (e.g., 0V is provided to the signal BL1). In another example, if the information to be stored in the selected memory cell among the memory cells 210, 212, and 214 has another value (e.g., “1”), a voltage having another value (e.g., a positive voltage) may be applied to the data line 221 (e.g., a positive voltage is provided to the signal BL1). Thus, information may be stored (eg, directly stored) in the charge storage structure 202 of a particular memory cell by providing the information to be stored (eg, in the form of a voltage) on the write path (which includes transistor T2) of that particular memory cell.

[0050] Figure 31 shows a flowchart including example voltages V0, V1, V2, and V3 used during a read operation of the memory device 200 according to some embodiments described herein. Figure 2 A memory device 200 is provided. Figure 3 The example assumes that memory cell 210 is a selected memory cell (e.g., a target memory cell) during a read operation to read (e.g., sense) information stored (e.g., previously stored) in memory cell 210. Memory cells 221 to 215 are assumed to be unselected memory cells. This means that in Figure 3 When information is read from memory cell 210 in the example of , memory cells 221 to 215 are not accessed and information stored in memory cells 221 to 215 is not read.

[0051] exist Figure 3 , voltages V0, V1, V2, V3, V4, and V5 may represent different voltages applied to corresponding access lines 241, 242, and 243 and data lines 221, 221', 221W, 222, 222', and 222W during a read operation of memory device 200. As an example, voltages V0, V1, V2, V3, V4, and V5 may have values ​​of 0V (e.g., ground), 0.5V, 0V, 0.5V, 0V, and 2V, respectively. These values ​​are example values. Different values ​​may be used.

[0052] like Figure 3 As shown in , each of the data lines 222 and 222' may have a voltage V4 applied to it or be placed in a "FLOAT" condition. Placing a particular conductive line (e.g., data line 222 or 222') in a FLOAT condition during a particular operation may include allowing the potential on that particular conductive line to vary or "float" (e.g., by not coupling that particular conductive line to a fixed potential (e.g., ground or other voltage)). Figure 3 In the instance read operation of Figure 3 Each of the data lines 222 and 222' in the memory cell 210 can be placed in a FLOAT condition by, for example, decoupling each of the data lines 222 and 222' from ground or from a fixed positive voltage source. This allows the potential on each of the data lines 222 and 222' to change (e.g., "float") during an operation to read information from the memory cell 210 (the selected memory cell in this example).

[0053] exist Figure 3In the read operation shown in , voltage V1 may have a value (voltage value) to turn on transistor T1 of memory cell 210 (the selected memory cell in this example) and turn off (or remain off) transistor T2 of memory cell 210. This allows information to be read from memory cell 210. Voltages V0 and V2 may have values ​​such that transistors T1 and T2 of each of memory cells 221 to 215 (unselected memory cells in this example) are turned off (e.g., remain off). Voltage V3 may have a value such that a current (e.g., a read current) may be formed on a read path including data lines 221 and 221' and transistor T1 of memory cell 210. This allows current to be detected on a read path coupled to memory cell 210. A detection circuit (not shown) of memory device 200 may be operable to convert the value of the detected current (during reading of information from a selected memory cell) into a value of information read from the selected memory cell (e.g., "0", "1", or a combination of multi-bit values). In Figure 3 In the example of , the value of the detected current on the data lines 221 and 221 ′ may be converted into the value of information read from the memory cell 210 .

[0054] exist Figure 3 , the voltages applied to the respective access lines 241, 242, and 243 may cause the transistors T1 and T2 of each of the memory cells 221 to 215, except for the transistor T1 of the memory cell 210, to be turned off (or remain turned off). Depending on the value of the threshold voltage Vt1 of the transistor T1 of the memory cell 210, the transistor T1 of the memory cell 210 may or may not be turned on. For example, if the transistor T1 of each of the memory cells (e.g., 210 to 215) of the memory device 200 is configured (e.g., structured) such that the threshold voltage of the transistor T1 is less than zero (e.g., Vt1<0V) regardless of the value (e.g., state) of the information stored in the respective memory cell 210, then the transistor T1 of the memory cell 210 in this example may be turned on and conduct current between the data lines 221 and 221′ (via the transistor T1 of the memory cell 210). The memory device 200 may determine the value of information stored in the memory cell 210 based on the value of the current between the data lines 221 and 221'. As described above, the memory device 200 may include a detection circuit that measures the value of the current between the data lines 221 and 221' (or between the data lines 222 and 222) during a read operation.

[0055] Figure 4 1 shows a flowchart including example voltages V5, V6, V7, and V8 used during a write operation of the memory device 200 according to some embodiments described herein. Figure 2 A memory device 200 is provided. Figure 4Assume that memory cells 210 and 211 are selected memory cells (eg, target memory cells) during a write operation to store information in memory cells 210 and 211. Assume that memory cells 212 to 215 are unselected memory cells. This means that when information is stored in Figure 4 When the memory cells 210 and 211 in the example of FIG. 1 are accessed, the memory cells 212 to 215 are not accessed and the stored information is not stored in the memory cells 212 to 215.

[0056] exist Figure 4 , voltages V5, V6, V7, and V8 may represent different voltages applied to corresponding access lines 241, 242, and 243 and data lines 221W and 222W during a write operation of memory device 200. As an example, voltages V5 and V6 may have values ​​of 2.5V and 0V, respectively. Depending on the value of information stored in memory cells 210 and 211 (e.g., "0" or "1"), the value of each of voltages V7 and V8 may be less than, equal to, or greater than the value of voltage V5. The specific values ​​of voltages used in this specification are merely example values. Different values ​​may be used.

[0057] Depending on the value of the information stored in the memory cells 210 and 211 (e.g., "0" or "1"), the values ​​of the voltages V7 and V8 may be the same or different. For example, if the memory cells 210 and 211 are to store information having the same value, the values ​​of the voltages V7 and V8 may be the same (e.g., V7=V8). As an example, if the information to be stored in each memory cell 210 and 211 is "0", then V7=V8=0V, ​​and V5=2.5V, and if the information to be stored in each memory cell 210 and 211 is "1", then V7=V8=1V to 3V, and V5=2.5V.

[0058] In another example, if memory cells 210 and 211 are to store information having different values, the values ​​of voltages V7 and V8 may be different (e.g., V7≠V8). As an example, if "0" and "1" to be stored in memory cell 210 are to be stored in memory cell 211, then V7=0V, V8=1V to 3V, and V5=2.5V. As another example, if "1" and "0" to be stored in memory cell 210 are to be stored in memory cell 211, then V7=1V to 3V, V8=0V, ​​and V5=2.5V.

[0059] A range of voltages of 1 V to 3 V is used here as an example. Different ranges of voltages may be used. In addition, instead of 0 V, a positive voltage (e.g., V7>0 V or V8>0 V) may be applied to a particular write data line (e.g., data line 221W or 222W) for storing information having a value of "0" to a memory cell (e.g., memory cell 210 or 211) coupled to that particular write data line.

[0060] exist Figure 4 In a write operation of the memory device 200 of FIG. 1 , the voltage V6 may have a value such that the transistors T1 and T2 of each of the memory cells 212 to 215 (unselected memory cells in this example) are turned off (e.g., remain turned off). The voltage V5 may have a value to turn on the transistors T2 of each of the memory cells 210 and 211 (selected memory cells in this example) and form a write path between the charge storage structure 202 of the memory cell 210 and the data line 221W, and a write path between the charge storage structure 202 of the memory cell 211 and the data line 222W. A current (e.g., a write current) may be formed between the charge storage structure 202 of the memory cell 210 and the data line 221W. This current may affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory device 210 to reflect the value of the information to be stored in the memory cell 210. A current (e.g., another write current) may be formed between the charge storage structure 202 of the memory cell 211 and the data line 222W. This current may affect (eg, change) the amount of charge on the charge storage structure 202 of the memory device 211 to reflect the value of the information to be stored in the memory cell 211 .

[0061] exist Figure 4 In the example write operation of , the value of voltage V7 may cause the charge storage structure 202 of memory cell 210 to discharge or charge, so that the resulting charge on the charge storage structure 202 of memory cell 210 (e.g., the charge remaining after the discharge or charge action) may reflect the value of the information stored in memory cell 210. Similarly, the value of voltage V8 in this example may cause the charge storage structure 202 of memory cell 211 to discharge or charge, so that the resulting charge on the charge storage structure 202 of memory cell 211 (e.g., the charge remaining after the discharge or charge action) may reflect the value of the information stored in memory cell 211.

[0062] Figure 4The example write operation of assumes that memory cells 210 and 211 are selected (e.g., selected in parallel) to store (e.g., store in parallel) information. In another write operation, memory cell 210 or memory cell 211 may be selected to store information. For example, in another write operation, memory cell 210 may be selected and memory cells 211 to 215 may be unselected memory cells. In such a write operation, voltage V8 may be applied with a voltage (e.g., a write inhibit voltage (e.g., V8=V5)) such that memory cell 211 is inhibited from storing information when information is stored in memory cell 210 (the selected memory cell). Similarly, if memory cell 211 is selected to store information and memory cells 210 and 212 to 215 are unselected memories, voltage V7 may be applied with a voltage (e.g., a write inhibit voltage (e.g., V7=V5)) such that memory cell 210 is inhibited from storing information when information is stored in memory cell 211 (the selected memory cell).

[0063] References Figures 2 to 4 The described memory device 200 may have the following reference Figures 6 to 30 The structure of the memory device 600 described above (eg, a 2-T memory structure) is shown in FIG. Figure 31 to Figure 35 The structure of the memory device 3100 is described (eg, a 2-T memory structure).

[0064] Figure 5 Schematic diagram showing a portion of a memory device 500 including a memory array 501' according to some embodiments described herein. The memory device 500 may be the memory device described above with reference to Figures 2 to 4 Variations of the described memory device 200. Therefore, for simplicity, similar or identical elements between the memory devices 200 and 500 are given the same reference labels and their descriptions are not repeated.

[0065] The difference between memory devices 200 and 500 includes multiple access lines in memory device 500, which memory device 500 can use to separately control (e.g., turn on or off) transistors T1 and T2 of each of the memory cells in memory device 500. Figure 5As shown in , the memory device 500 may include access lines 241R and 241W (which may receive corresponding signals WL1R and WL1W) that control transistors T1 and T2, respectively, of each of the memory cells 210 and 211; access lines 242R and 242W (which may receive corresponding signals WL2R and WL2W) that control transistors T1 and T2, respectively, of each of the memory cells 212 and 213; and access lines 243R and 243W (which may receive corresponding signals WLnR and WLnW) that control transistors T1 and T2, respectively, of each of the memory cells 214 and 215.

[0066] Depending on which memory cells 210-215 are selected during a particular read operation, access lines 241R, 242R, and 243R may be selectively activated during a read operation of memory device 500. Access lines 241W, 242W, and 243W may be deactivated during a read operation of memory device 500. During a read operation of memory device 500, access lines 241R, 242R, and 243R may have Figure 3 The voltages provided to the access lines 241, 242 and 243 respectively are similar (or consistent) voltages.

[0067] Depending on which memory cells 210-215 are selected during a particular write operation, access lines 241W, 242W, and 243W may be selectively activated (or alternatively activated in parallel) during a write operation of memory device 500. Access lines 241R, 242R, and 243R may be deactivated during a write operation of memory device 500. During a write operation of memory device 500, access lines 241W, 242W, and 243W may have the same Figure 4 The voltages provided to the access lines 241, 242 and 243 respectively are similar (or consistent) voltages.

[0068] The memory device 500 may have the following reference Figures 6 to 30 The structure of the memory device 600 described above (eg, a 2-T memory structure) is shown in FIG. 5 . Alternatively, the memory device 500 may have the structure shown in FIG. 5 . Figure 31 to Figure 35 The structure of the memory device 3100 is described (eg, a 2-T memory structure).

[0069] Figures 6 to 30 Different views of elements during the process of forming memory device 600 according to some embodiments of the present invention are shown. Some or all of the processes for forming memory device 600 may be used to form the memory device 600 described above with reference to FIG. Figures 2 to 5 A memory device 200 is described.

[0070] Figure 6Memory device 600 is shown after dielectric material 690, conductive material 619', material 610, conductive material 624, and dielectric material 616 are formed in the Z direction in respective levels (e.g., layers) over substrate 699. The Z direction (e.g., vertical direction) is a direction perpendicular to (e.g., outward from) substrate 699. The Z direction is also perpendicular to the X direction (e.g., a direction parallel to a surface of substrate 699).

[0071] Dielectric material 690, conductive material 624, material 610, conductive material 619', and dielectric material 616 may be formed one material after another over substrate 699 in a sequential manner. For example, Figure 6 The process used may include forming (e.g., depositing) a dielectric material 690 above a substrate, forming (e.g., depositing) a conductive material 619' above the dielectric material 690, forming (e.g., depositing) a material 610 above the conductive material 619', forming (e.g., depositing) a conductive material 624 above the dielectric material 610, and forming (e.g., depositing) a dielectric material 616 above the conductive material 624.

[0072] The substrate 699 may be a semiconductor substrate (eg, a silicon-based substrate) or other types of substrates. The dielectric material 690 may include an oxide material (eg, silicon dioxide SiO 2 ). Conductive materials 619' and 624 may include metal, conductively doped polysilicon, or other conductive materials. Material 610 may include metal or semiconductor material (e.g., silicon, polysilicon (doped or undoped polysilicon), germanium, SiGe, or other semiconductor material). Dielectric material 616 may include oxide material (e.g., silicon dioxide SiO 2 The dielectric material 616 may include an oxide material (eg, silicon dioxide SiO 2 ).

[0073] Figure 7 Memory device 600 is shown after forming openings (e.g., trenches) 731 and 732 and data lines (e.g., read data lines) 620', 621', and 622'. Forming openings 731 and 732 can include removing (e.g., by patterning) portions of each of dielectric material 616, conductive material 624, material 610, and conductive material 619' at the locations of openings 731 and 732 and leaving remaining portions of these materials, such as Figure 7 For example, portions 610A, 610B, and 610C are Figure 6 The remainder of material 610. Figure 7 Parts 620A, 621A and 622A are Figure 6The remaining portion of the conductive material 624. Portions 616A, 616B and 616C are Figure 6 The remaining portion of the dielectric material 616.

[0074] Forming data lines 620', 621' and 622' ( Figure 7 ) may include removing conductive material 619' at the locations of openings 731 and 732 ( Figure 6 ) and leaving the remaining portion of the conductive material 619' to form the corresponding data lines 620', 621' and 622'. Each of the data lines 620', 621' and 622' is a conductive line (e.g., a conductive region) and has a direction perpendicular to the X direction and the Z direction (e.g., the Y direction, Figure 7 Length on the plate (not marked).

[0075] like Figure 7 As shown, data lines 620', 621' and 622' are electrically separated from each other (in the X direction). Data lines 621' and 622' may represent Figure 2 The data line 620' may be a structure of the data lines 221' and 222' of the memory device 200 shown in FIG. Figure 2 The data line of the memory device 200 ( Figure 2 Another data line of the memory device 700 having a structure not shown in FIG.

[0076] Figure 7 Also shown are signals (eg, bit line signals) BL0*, BL1*, and BL2* that can represent signals applied to data lines 620', 621', and 622', respectively. Memory device 600 can have read operations similar or consistent with those of memory device 200. Figure 7 The signals BL1* and BL2* in Figure 2 1 and 2. The memory device 200 in FIG. Figure 7 The signal BL0* in can also represent Figure 2 A signal (e.g., a bit line signal, Figure 2 not shown).

[0077] Figure 8 Memory device 600 is shown after dielectric materials 815A, 815B, 815C, and 815D (815A-815D) and materials 802A, 802B, 802C, and 802D are formed in respective openings 731 and 732. Forming dielectric materials 815A-815D may include forming (e.g., depositing) an initial dielectric material (e.g., silicon dioxide) in openings 731 and 732, then removing (e.g., by etching) a portion of the initial dielectric material and leaving the initial dielectric material having a dielectric state. Figure 8Portions of dielectric material 815A to 815D of the structure shown in FIG.

[0078] Materials 802A-802D may be formed after dielectric materials 815A-815D are formed. For example, forming materials 802A-802D may include forming (e.g., depositing) an initial material (e.g., polysilicon, metal, or one or more materials that can trap charge) in openings 731 and 732, then removing (e.g., by etching) a portion of the initial material and leaving the initial material formed with a dielectric material 815A-815D. Figure 8 Portions of materials 802A to 802D of the structure shown.

[0079] Fig. 9 Memory device 600 is shown after dielectric materials 915 and 916 are formed (eg, filled) in respective openings 731 and 732. Fig. 9 2A to 802D may be subsequently structured to form charge storage structures (eg, memory elements) of respective memory cells 209′, 210′, and 211′ of memory device 600. Memory cells 210′ ​​and 211′ may represent Figure 2 Memory cells 210 and 211. Memory cell 209' may represent Figure 2 The additional memory cell of the memory device 200 ( Figure 2 ), where such additional memory cells may share access line 241 with memory cells 211 and 212 of memory device 200.

[0080] Each of the materials 610A, 620B, and 610C may be subsequently processed (eg, structured) to form a transistor (eg, transistor T1, T2) of a corresponding memory cell 209', 210', or 211' of the memory device 900. Fig.12 ) of a channel region (e.g., a read channel region).

[0081] Each of memory cells 209', 201', and 211' may have a charge storage structure including two portions formed from two respective portions of materials 802A to 802D. Materials 802B and 802C may subsequently be processed (e.g., structured) to form two respective portions of the charge storage structure of memory cell 210' (one from material 802B and the other from material 802C). Material 802A may form a portion (e.g., half) of the charge storage structure of memory cell 209'. Material 802D may form a portion (e.g., half) of the charge storage structure of memory cell 211'. Each of memory cells 209' and 211' may have a charge storage structure including two portions (similar to the two portions formed from materials 802B and 802C of the charge storage structure of memory cell 210'). However, for simplicity, another portion of the charge storage structure of memory cell 209' (e.g., the portion to the left of material 610A) is not shown. Fig. 9 , and another portion of the charge storage structure of the memory cell 211′ (eg, the portion to the right of the material 610C) is not shown. Fig. 9 middle.

[0082] Fig.10 Show relative to Fig. 9 FIG. 6 is a top view of the memory device 600 in the XY direction. For simplicity, the Fig.10 Description of the components shown in Fig. 9 to describe). Fig.10 , elements of memory device 600 may include strips (e.g., lines) of material having a length extending in the Y direction. Subsequent processes of forming memory device 600 may include removing (e.g., cutting (e.g., etching) in the Z direction) material at locations 1061, 1062, 1063, and 1064 (1061-1064) down to data lines 620', 621', and 622' ( Fig. 9 )(stop at the data lines 620', 621' and 622'). Therefore, the data lines 620', 621' and 622' (which have a length extending in the Y direction) will remain to continuously extend in the Y direction.

[0083] exist Fig.10, after removing portions of the material at locations 1061-1064, portions 616A1, 616A2, and 616A3 (at locations 1071, 1072, and 1073, respectively) will be the remaining portions of portion 616A; portions 616B1, 616B2, and 616B3 (at locations 1071, 1072, and 1073, respectively) will be the remaining portions of portion 616B; and portions 616C1, 616C2, and 616C3 (at locations 1071, 1072, and 1073, respectively) will be the remaining portions of portion 616C. Another view of memory device 600 along line 11-11 is shown at Fig.11 middle.

[0084] Fig.11 The openings (eg, trenches) 1061A, 1062A, 1063A, and 1064A (1061A to 1064A) are shown formed at locations 1061, 1062, 1063, and 1064, respectively. Fig.10 ) relative to the YZ direction Fig.10 A side view of line 11-11. Fig.11 , structures (e.g., material) at locations 1061-1064 are removed, stopping at data line 621' (e.g., down to data line 621') so that material of data line 621' is not removed. Openings 1061A-1064A may be formed by removing portions of each of the material at locations 1061-1064 (as mentioned above). Fig.11 In the Y direction, the portions 610B1, 610B2 ​​and 610B3 are the portions 610B ( Fig. 9 ) of the remaining part: the Y-direction parts 621A1, 6212A2 and 621A3 are part 621A ( Fig. 9 ) of the remaining portion; and portions 616B1, 616B2 and 616B3 in the Y direction are portions 616B ( Fig. 9 and Fig.10 )'s remainder. Fig.11 The material of the memory device 600 in the substrate 699 may include structures (eg, protrusions (eg, islands)) 1101, 1102, and 1103 extending outward from the substrate 699. Each of the structures 1101, 1102, and 1103 may be part of a memory cell in a subsequent process of forming the memory device 600.

[0085] Fig.121. The structure of the present invention is shown after dielectric material (e.g., gate oxide) 1215, conductive lines (e.g., conductive regions) 1201, 1202, 1203, 1204, 1205, and 1206 (1201-1206), and dielectric materials 1216, 1217, 1218, and 1219 (1216-1219) are formed in respective openings 1061A-1064A. Fig.11 Memory device 600. Each of dielectric materials 1215 and 1216 to 1219 may include silicon dioxide or other dielectric materials. Each of conductive lines 1201 to 1206 may include metal, conductively doped polysilicon, or other conductive materials.

[0086] Conductive lines 1201-1206 may form part of access lines (eg, word lines) to access memory cells 210', 212', and 214' of memory device 600. Memory cells 210', 212', and 214' may represent Figure 2 Memory cells 210, 212, and 214 of the memory device 200.

[0087] exist Fig.12 , conductive lines 1201 and 1202 may form part of an access line (eg, a word line) to access memory cell 210′ ​​and other memory cells (eg, Fig.12 Such other memory cells may be positioned in the same row as memory cell 210' in the X direction (e.g., memory cells 209' and 211', Fig.13 ).

[0088] exist Fig.12 middle, Fig.12 Conductive lines 1203 and 1204 in can form part of access lines (eg, word lines) to access memory cell 212 ′ and other memory cells (not shown) of memory device 600 . Fig.12 The conductive lines 1205 and 1206 in can form part of access lines (eg, word lines) to access the memory cell 214 ′ and other memory cells (not shown) of the memory device 600 .

[0089] Therefore, if Fig.12 , conductive line 1201 may have a portion adjacent to one side (e.g., the right side in the Y direction) of the channel region (e.g., portion 610B1) of memory cell 210'. Conductive line 1202 may have a portion adjacent to the other side (e.g., the left side (opposite to the right side) in the Y direction) of the channel region (e.g., portion 610B1) of memory cell 210'.

[0090] Similarly, conductive lines 1203 and 1204 may have respective portions (e.g., respective conductive regions) adjacent to respective sides (opposite sides) in the Y direction of the channel region (e.g., read channel region) of memory cell 212'. Conductive lines 1205 and 1206 may have respective portions (e.g., respective conductive regions) adjacent to respective sides (opposite sides) in the Y direction of the channel region (e.g., read channel region) of memory cell 214'. Another view of memory device 600 along line 13-13 is shown in FIG. Fig.13 middle.

[0091] Fig.13 Shows the XZ direction along Fig.12 A side view of line 13-13. Fig.13 , conductive lines 1201 and 1202 are partially shown to avoid blocking portions of other elements of memory device 600. Fig.13 As shown in , each of the conductive lines may have a length in the X direction, a width in the Z direction, and a thickness in the Y direction (e.g., less than the width) ( Fig.12 ).

[0092] exist Fig.13 In the dielectric part, parts 616A1, 616B1 and 616C1 are respectively Fig.10 The portions 616A, 616B and 616C are Fig.11 After removing (e.g., cutting) a portion of each of portions 616A, 616B, and 616C during the process (and after conductive lines 1201 to 1206 are formed at Fig.12 the remainder of the process before).

[0093] The portions (conductive portions) 620A1, 621A1 and 622A1 are Fig.10 The parts 620A, 621A and 622A are in Fig.11 After removing (e.g., cutting) a portion of each of portions 620A, 621A, and 622A during the process (and after conductive lines 1201 to 1206 are formed at Fig.12 the remainder of the process before).

[0094] Parts (dielectric parts) 915A and 916A are Fig.10 The dielectric materials 915 and 916 are Fig.11 After removing (e.g., cutting) portions of each of dielectric materials 915 and 916 during the process (and after conductive lines 1201 to 1206 are formed at Fig.12 the remainder of the process before).

[0095] Parts 815A1, 815B1, 815C1 and 815D1 are Fig.10 Materials 815A, 815B, 815C and 815D are Fig.11 After removing (e.g., cutting) portions of each of materials 815A, 815B, 815C, and 815D during the process (and after conductive lines 1201 to 1206 are formed at Fig.12 the remainder of the process before).

[0096] Parts 610A1, 610B1 and 610C1 are Fig.10 The portions 610A, 610B and 610C are Fig.11 After removing (e.g., cutting) a portion of each of portions 610A, 610B, and 610C during the process (and after conductive lines 1201 to 1206 are formed at Fig.12 The remainder of the process before. Fig.13 In the embodiment, portion 610B1 may form a channel region (eg, a read channel region) of transistor T1 of memory cell 210 ′. Fig.13 The transistor T1 can be represented by Figure 2 The transistor T1 of the memory cell 210 of the memory device 200 is Fig.13 , Part 610A1( Fig.13 ) may form a channel region (eg, a read channel region) of transistor T1 of memory cell 209'. Portion 610C1 may form a channel region (eg, a read channel region) of transistor T1 of memory cell 211'. Each of portions 610A, 610B, and 610C may include a Figure 6 A block of material (eg, metal or polysilicon) is formed as part of material 610 during the process.

[0097] exist Fig.13 In the example, parts 802A1, 802B1, 802C1 and 802D1 are Fig.10 The materials 802A, 802B, 802C and 802D (hidden under the dielectric materials 915 and 916) are Fig.11 After removing (e.g., cutting) portions of each of materials 802A, 802B, 802C, and 802D during the process (and after conductive lines 1201 to 1206 are formed at Fig.12 the remainder of the process before).

[0098] exist Fig.13 middle, Fig.13 The portions 802B1 and 802C1 in FIG. 2 may form a charge storage structure (eg, a memory element) of the memory cell 210 ′. The charge storage structure (eg, portions 802B1 and 802C2) of the memory cell 210 ′ may represent Figure 2The charge structure 202 of the memory cell 210 of the memory device 200 is shown in FIG. Fig.13 As shown in , the charge storage structure of the memory cell 210′ ​​may have a portion (e.g., portion 802B1) adjacent to one side (e.g., the left side in the X direction) of the channel region (e.g., portion 610B1) of the memory cell 210′, and another portion (e.g., portion 802C1) adjacent to the other side (e.g., the right side (opposite to the left side) in the X direction) of the channel region (e.g., portion 610B1) of the memory cell 210′.

[0099] Portion 802A1 may form part (e.g., half) of a charge storage structure (e.g., memory element) of memory cell 209'. The charge storage structure of memory cell 209' may have a portion (e.g., portion 802B1) adjacent to one side (e.g., right side in the X direction) of a channel region (e.g., portion 610A1) of memory cell 209'.

[0100] Portion 802D1 may form part (e.g., half) of a charge storage structure (e.g., memory element) of memory cell 211'. The charge storage structure of memory cell 211' may have a portion (e.g., portion 802D1) adjacent to one side (e.g., left side in the X direction) of a channel region (e.g., portion 610C1) of memory cell 211'.

[0101] exist Fig.13 , conductive lines 1201 and 1202 may be part of an access line (e.g., word line) 1241R (which may receive a signal (e.g., word line signal) WL1R) to access memory cells 209′, 210′, and 211′ of memory device 600 during operation of memory device 600. For example, the signal (e.g., WL1R) on conductive lines 1201 and 1202 may be used to control (e.g., turn on or off) transistor T1 of memory cell 210′.

[0102] Therefore, if Fig. 27 As shown in Fig. 27 Access line 1241R of memory device 600 in can include conductive lines 1201 and 1202 having respective portions positioned adjacent respective sides of a channel region (eg, a read channel region) of a respective memory cell (eg, 209, 210', or 211').

[0103] For example, the conductive line 1201 may have a portion adjacent to one side (e.g., the front side in the Y direction) of the channel region (e.g., the portion 610A1) of the memory cell 209'. The conductive line 1202 may have a portion adjacent to the other side (e.g., the back side (opposite to the front side) in the Y direction) of the channel region (e.g., the portion 610A1) of the memory cell 209'.

[0104] Conductive line 1201 may have a portion adjacent to one side (e.g., front side in the Y direction) of the channel region (e.g., portion 610B1) of memory cell 210'. Conductive line 1202 may have a portion adjacent to the other side (e.g., back side (opposite to the front side) in the Y direction) of the channel region (e.g., portion 610B1) of memory cell 210'.

[0105] Conductive line 1201 may have a portion adjacent to one side (e.g., front side in the Y direction) of the channel region (e.g., portion 610C1) of memory cell 211'. Conductive line 1202 may have a portion adjacent to the other side (e.g., back side (opposite to the front side) in the Y direction) of the channel region (e.g., portion 610C1) of memory cell 211'.

[0106] form Fig.13 The process of forming the memory device 600 in FIG. 6 may include forming a conductive connector 1201′ (which may include a conductive material (eg, metal)) that electrically couples the conductive lines 1201 and 1202 to each other. Similarly, the process of forming the memory device 600 may include forming a conductive connector 1201′ (which may include a conductive material (eg, metal)) that electrically couples the conductive lines 1201 and 1202 to each other. Fig.12 ) are electrically coupled to each other (not shown), and conductive connections (not shown) are formed to electrically couple conductive lines 1205 and 1206 ( Fig.12 ) are electrically coupled to each other (not shown).

[0107] Fig.14 Memory device 600 is shown after removing portions 616A1 , 616B1 , and 616C1 and after removing portions of each of portions 915A and 916A. Fig.14 The process in may include a planarization process (eg, a chemical mechanical polishing (CMP) process) that removes portions 616A1 , 616B1 , and 616C1 and removes a portion (eg, a top portion) of each of portions 915A and 916A.

[0108] Fig.15 Memory device 600 is shown after forming conductive material 1521 and dielectric material 1515. Material 1515 may include an oxide material (eg, silicon dioxide SiO 2). Conductive material 1521 may include metal, conductively doped polysilicon, or other conductive materials, which may be the same material as portions 621A1, 621A2, and 621A3.

[0109] Fig.16 Memory device 600 is shown after forming openings (e.g., trenches) 1631 and 1632 by removing portions of conductive material 1521 and portions of dielectric material 1515 at the locations of openings 1631 and 1632. The remaining portions of dielectric material 1515 include portions 1515A, 151B, and 1515C. The remaining portions of conductive material 1521 form portions that may represent Figure 2 The data lines 221 and 222 of the memory device 200 are data lines 1521BL0, 1521BL1, and 1521BL2.

[0110] Fig.16 Memory device 600 is shown after dielectric materials 1715 and 1716 are formed in openings 1631 and 1632, respectively. Materials 1715 and 1716 may include oxide materials (e.g., silicon dioxide SiO 2 ). Another view of the memory device 600 along line 18-18 is shown at Fig.18 middle.

[0111] Fig.18 Show relative to Fig.17 A top view of the memory device 600 along line 18-18 in the XY direction. Fig.18 As shown in FIG. 1 , each of the data lines 1521BL0, 1521BL1, and 1521BL2 can be structured as a conductive line having a length in the Y direction, which is the same direction as the length of each of the data lines 620', 621', and 622' below the corresponding data lines 1521BL0, 1521BL1, and 1521BL2 (in the Z direction). Fig.18 Also shown are relative locations of memory cells 209', 210, 211', 212', and 214' positioned below respective data lines 1521BL0, 1521BL1, and 1521BL2 (in the Z direction) and between data lines 1521BL0, 1521BL1, and 1521BL2 and data lines 620', 621', and 622' of memory device 600.

[0112] Fig.19Memory device 600 is shown after one or more materials 1920 are formed (e.g., deposited) over portions 1515A, 1515B, 1515C and over dielectric materials 1715 and 1716. Material 1920 may include a semiconductive material. The semiconductive material may include an oxide material. Examples of oxide materials include semiconductive oxide materials, transparent conductive oxide materials, and other oxide materials.

[0113] As an example, the material 1920 may include at least one of the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Silicon Oxide (IGSO), Indium Oxide (InO x ,In 2 O 3 ), tin oxide (SnO 2 )、TiOx、ZnOx x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), Indium Gallium Zinc Oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum oxide, tin, indium, zinc (Al x Sn y In z Zn a O d ), Silicon Indium Zinc Oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Snz O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a )、Zirconium oxide zinc tin (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

[0114] The materials listed above are examples of materials 520 and 521. However, other materials (eg, relatively high bandgap materials) other than the materials listed above may be used.

[0115] The use of the above-listed materials in memory device 200 provides improvements and benefits to memory device 200 over some other materials. For example, during a read operation to read information from a selected memory cell (e.g., memory cell 210 or 211), charge from the charge storage structure 202 of the selected memory cell may leak from the selected memory cell (e.g., to transistor T2). Using the above-listed materials for the channel region of transistor T2 (e.g., material 520 or 521) may reduce or prevent such leakage. This improves the accuracy of the information read from the selected memory cell and improves the retention of information stored in the memory cells of the memory devices described herein (e.g., memory device 200).

[0116] Fig. 20 Shown in the removal of material 1920 ( Fig.19 ), portions of materials 1715 and 1716, portions of each of portions 915A and 915B, and portions of each of dielectric materials 815A1, 815B1, 815C1, and 815D1 to form openings (e.g., trenches) 2031 and 2032. Portions 1920B1, 1920B2, and 1920B3 are the remaining portions of material 1920 after removing portions of material 1902 (at the locations of openings 2031 and 2032). Fig. 20 The process also includes exposing portions 802A1 , 802B1 , 802C2 , and 802D1 at corresponding openings 2031 and 2032 .

[0117] Fig.21 Memory device 600 is shown after forming dielectric material 2115. Dielectric material 2115 may include an oxide material (eg, silicon dioxide SiO 2 ).

[0118] Fig. 22Memory device 600 is shown after forming conductive materials 2202A, 2202B, 2202C, and 2202D. Conductive materials 2202A, 2202B, 2202C, and 2202D may include metal or other conductive materials. As shown in 21, conductive materials 2202B and 2202C may contact portion 1920B. Conductive materials 2202B and 2202C may also contact portions 802B1 and 802C1, respectively. Thus, materials 2202B and 2202C may electrically couple portion 1920B to portions 802B1 and 802C1. Similarly, conductive material 2202A may contact portion 1902A and portion 802A1 and electrically couple portion 1920A to portion 802A1. Conductive material 2202D may contact portion 1902D and portion 802D1 and electrically couple portion 1902D to portion 801D1.

[0119] Fig.23 Memory device 600 is shown after forming dielectric materials 2315 and 2316. Materials 2315 and 2316 may include oxide materials (e.g., silicon dioxide SiO 2 ).

[0120] Fig.24 Show relative to Fig.23 FIG. 6 is a top view of the memory device 600 in the XY direction. For simplicity, the Fig.24 Description of the components shown in Fig.23 to describe). Fig.24 , elements of memory device 600 may include strips (e.g., lines) of material having a length extending in the Y direction. Subsequent processes of forming memory device 600 may include removing (e.g., cutting (e.g., etching) in the Z direction) material at locations 2461, 2462, 2463, and 2464 (2461-2464) down to the level of dielectric materials 1515A, 1515B, and 1515C and at data lines 1521BL0, 1521BL1, and 1521BL2 ( Fig.23 ). Therefore, the data lines 1521BL0, 1521BL1, and 1521BL2 (which have a length extending in the Y direction) will remain to extend continuously in the Y direction.

[0121] exist Fig.24, after removing portions of the material at locations 2461-2464, portions 1920A1, 1920A2, and 1920A3 will be the remaining portions of material 1920A; portions 1920B1, 1920B2, and 1920B3 will be the remaining portions of material 1920B; and portions 1920C1, 1920C2, and 1920C3 will be the remaining portions of material 1920C. Another view of memory device 600 along line 25-25 is shown at Fig.25 middle.

[0122] Fig.25 The openings (eg, grooves) 2461A, 2462A, 2463A, and 2464A (2461A to 2464A) are shown formed at locations 2461, 2462, 2463, and 2464, respectively. Fig.24 ) relative to the YZ direction Fig.24 A side view of line 25-25 of FIG. Fig.25 , structures (e.g., materials) at locations 2461-1064 are removed, stopping at data line 1521BL1 (e.g., down to data line 1521BL1) so that material of data line 1521BL1 is not removed. Openings 2461A-2464A may be formed by removing portions of each of the materials at locations 2461-2464 (as mentioned above). Fig.25 In the Y direction, portions 1515B1, 1515B2, and 1515B3 are portions 1515B ( Fig.23 ), and portions 1920B1, 1920B2, and 1920B3 in the Y direction are portions 1920B ( Fig.24 )'s remainder. Fig.25 The material of memory device 600 in the substrate 699 may include structures (e.g., protrusions (e.g., islands)) 2501, 2502, and 2503 extending outward from substrate 699. Each of structures 2501, 2502, and 2503 may be part of a memory cell in a subsequent process of forming memory device 600.

[0123] Fig.26Memory device 600 is shown after dielectric material (e.g., gate oxide) 2615, conductive lines (e.g., conductive regions) 2601, 2602, 2603, 2604, 2605, and 2606 (2601-2606), and dielectric materials 2616, 2617, 2618, and 2619 (2616-2619) are formed in respective openings 2461A-2464A. Each of dielectric materials 2615 and 2616-2619 may include silicon dioxide or other dielectric materials. Each of conductive lines 2601-2606 may include metal, conductively doped polysilicon, or other conductive materials. Conductive lines 2601-2606 may form access lines (e.g., word lines) to access memory cells (e.g., memory cells 210', 212', and 214' of memory device 600). As mentioned above, the memory cells 210', 212', and 214' of the memory device 600 may include Figure 2 Memory cells 210, 212, and 214 of the memory device 200.

[0124] exist Fig.26 , conductive lines 2601 and 2602 may form part of access lines (e.g., word lines) to access memory cell 210' and other memory cells of memory device 600. Such other memory cells may be positioned in the same row as memory cell 210' in the X direction (e.g., memory cells 209' and 211', Fig. 27 ). Fig.26 The conductive lines 2603 and 2604 in can form part of an access line (eg, a word line) to access the memory cell 212 ′ and other memory cells of the memory device 600 . Fig.26 The conductive lines 2605 and 2606 in 2700 may form part of an access line (eg, word line) 2741 to access the memory cell 214 ′ and other memory cells of the memory device 600 .

[0125] Therefore, if Fig.26 , conductive line 2601 may have a portion adjacent to one side (e.g., the right side in the Y direction) of the channel region (e.g., portion 1920B1) of memory cell 210'. Conductive line 2602 may have a portion adjacent to the other side (e.g., the left side (opposite to the right side) in the Y direction) of the channel region (e.g., portion 1920B1) of memory cell 210'.

[0126] Similarly, conductive lines 2603 and 2604 may have respective portions (e.g., respective conductive regions) adjacent to respective sides (opposite sides) in the Y direction of the channel region (e.g., read channel region) of memory cell 212'. Conductive lines 2605 and 2606 may have respective portions (e.g., respective conductive regions) adjacent to respective sides (opposite sides) in the Y direction of the channel region (e.g., read channel region) of memory cell 214'. Another view of memory device 600 along line 27-27 is shown in FIG. Fig. 27 middle.

[0127] Fig. 27 Shows the XZ direction along Fig.26 A side view of line 27-27. Fig. 27 , conductive lines 2601 and 2602 are partially shown to avoid blocking portions of other elements of memory device 600. Fig. 27 As shown in FIG. , each of conductive lines 2601 and 2602 may have a length in the X direction, a width in the Z direction, and a thickness in the Y direction (e.g., less than the width) ( Fig.26 ).

[0128] exist Fig. 27 In the embodiment, the conductive parts 2202A1, 2202B1, 2202C1 and 2202D1 are Fig.24 The conductive materials 2202A, 2202B, 2202C and 2202D are Fig.25 After removing (e.g., cutting) a portion of each of the conductive materials 2202A, 2202B, 2202C, and 2202D during (and after Fig.26 2601 to 2606 are formed in the process of forming the remaining portion of the conductive lines 2601 to 2606. As shown in 27, portions 2202B1 and 2202C1 can contact portion 1920B1 and portions 802B1 and 802C1, respectively, so that portions 2202B1 and 2202C1 form a conductive coupling that electrically couples portion 1920B1 to portions 802B1 and 802C1. Conductive material 2202A1 can contact portions 1920A1 and 802A1 and form a conductive coupling that electrically couples portion 1920A1 to portion 802A1. Conductive material 2202D1 can contact portions 1920D1 and 802D1 and form a conductive coupling that electrically couples portion 1920D1 to portion 802D1.

[0129] Parts (dielectric part) 2315A and 2316A are Fig.24 The dielectric materials 2315 and 2316 are Fig.25 After removing (e.g., cutting) portions of each of dielectric materials 2315 and 2316 during the process (and after conductive lines 2601 to 2606 are formed at Fig.26 the remainder of the process before).

[0130] Parts 1920A1, 1920B1 and 1920C1 are Fig.24 Parts 1920A, 1920B and 1920C in Fig.25 After removing (e.g., cutting) a portion of each of portions 1920A, 1920B, and 1920C during the process (and after conductive lines 2601 to 2606 are formed at Fig.26 the remainder of the process before).

[0131] exist Fig. 27 In the embodiment, portion 1920B1 may form a channel region (eg, a write channel region) of transistor T2 of memory cell 210'. Fig. 27 The transistor T2 can be expressed as Figure 2 The transistor T2 of the memory cell 210 of the memory device 200. The portion 1920A1 ( Fig.13 ) may form a channel region (eg, a write channel region) of transistor T2 of memory cell 209'. Portion 1920C1 may form a channel region (eg, a write channel region) of transistor T2 of memory cell 211'. Each of portions 1920A, 1920B, and 1920C may include a Fig.19 A portion of a piece of material (eg, semiconductor material) is formed during a process of forming material 1920 .

[0132] exist Fig. 27 , conductive lines 2601 and 2602 may be part of access line (e.g., word line) 1241W (which may receive signal (e.g., word line signal) WL1W) to access memory cells 209′, 210′, and 211′ of memory device 600 during operation of memory device 600. For example, the signal (e.g., WL1W) on conductive lines 2601 and 2602 may be used to control (e.g., turn on or off) transistor T2 of memory cell 210′.

[0133] form Fig. 27 The process of forming the memory device 600 in FIG. 6 may include forming a conductive connector 2601′ (which may include a conductive material (eg, metal)) that electrically couples the conductive lines 2601 and 2602 to each other. Similarly, the process of forming the memory device 600 may include forming a conductive connector 2601′ (which may include a conductive material (eg, metal)) that electrically couples the conductive lines 2601 and 2602 to each other. Fig.12 ) are electrically coupled to each other (not shown), and conductive connections (not shown) are formed to electrically couple conductive lines 2605 and 2606 ( Fig.12 ) are electrically coupled to each other (not shown).

[0134] Therefore, if Fig. 27 As shown in Fig. 27 Access line 1241W of memory device 600 in can include conductive lines 2601 and 2602 having respective portions positioned adjacent respective sides of a channel region (eg, a write channel region) of a respective memory cell (eg, 209, 210', or 211').

[0135] For example, conductive line 2601 may have a portion adjacent to one side (e.g., front side in the Y direction) of the channel region (e.g., portion 1920A1) of memory cell 209'. Conductive line 2602 may have a portion adjacent to the other side (e.g., back side (opposite to the front side) in the Y direction) of the channel region (e.g., portion 1920A1) of memory cell 209'.

[0136] Conductive line 2601 may have a portion adjacent to one side (e.g., front side in the Y direction) of the channel region (e.g., portion 1920B1) of memory cell 210'. Conductive line 2602 may have a portion adjacent to the other side (e.g., back side (opposite to the front side) in the Y direction) of the channel region (e.g., portion 1920B1) of memory cell 210'.

[0137] Conductive line 2601 may have a portion adjacent to one side (e.g., front side in the Y direction) of the channel region (e.g., portion 1920C1) of memory cell 211'. Conductive line 2602 may have a portion adjacent to the other side (e.g., back side (opposite to the front side) in the Y direction) of the channel region (e.g., portion 1920C1) of memory cell 211'.

[0138] form Fig. 27 The process of the memory device 600 in can also include forming a conductive connection 2701' (which can include a conductive material (e.g., a metal)) that electrically couples the connections 2601' and 1201' to each other. Thus, the conductive lines 1201, 1202, 2601, and 2602 can be electrically coupled to each other so that the transistors T1 and T2 of the memory cell 210' can share the same access line (e.g., a combination of access lines 1241R and 1241W), which includes the conductive lines 1201, 1202, 2601, and 2602. Thus, in Fig. 27, signals WL1R and WL1W may be the same signal because conductive lines 1201, 1202, 2601, and 2602 are electrically coupled to each other (via conductive connections 1201', 2601', and 2701). In alternative structures of memory device 600, conductive connection 2701' may be omitted (e.g., not formed). In such alternative structures of memory device 600, signals WL1R and WL1W are different signals and may be activated at different times. For example, in such alternative structures of memory device 600, signal WL1R may be activated (and signal WL1W deactivated) during a read operation to control transistor T1 of memory cell 210'. In another example, signal WL1W may be activated (and signal WL1R deactivated) during a write operation to control transistor T2 of memory cell 210'.

[0139] Fig.28 Memory device 600 is shown after forming conductive material 2829. Conductive material 2829 may include metal or other conductive material.

[0140] Fig.29 Memory device 600 is shown after forming openings 2931 and 2932 and data lines (e.g., write data lines) 2920W, 2921W, and 2922W. Forming data lines 2920W, 2921W, and 2922W may include removing portions of conductive material 2829 at the locations of openings 2931 and 2932. The remaining portions of conductive material 2829 form conductive lines (e.g., conductive regions), which are data lines 2920W, 2921W, and 2922W. Each of data lines 2920W, 2921W, and 2922W may have a length in the Y direction. As shown in FIG. Fig.29 As shown in FIG. 1 , data lines 2920W, 2921W, and 2922W may contact (may be electrically coupled to) corresponding portions (eg, write channel regions) 1902A1, 1902B1, or 1902C1. Data lines 2921W and 2922W may represent Figure 2 The data lines 221W and 222W of the memory device 200 are shown in FIG.

[0141] Fig.30 Memory device 600 is shown after dielectric material 3015 is formed on other elements of memory device 600. The process of forming memory device 600 may include other processes not described in this specification in order to not obscure the embodiments described herein.

[0142] like Fig.30, memory device 600 may include memory cells 209', 210', and 211', which may include a transistor (e.g., transistor T1) and a corresponding channel region (e.g., a read channel region) formed by portions 610A1, 610B1, and 610C1; a transistor (e.g., transistor T2) and a corresponding channel region (e.g., a write channel region) formed by portions 1920A1, 1920B1, and 1920C1; and a transistor (e.g., transistor T3) and a corresponding channel region (e.g., a write channel region) formed by portions 802A1, 802B1, 802C1, and 802D1. A charge storage structure (e.g., a memory element) is formed, wherein portions 802B1 and 802C1 may form a charge storage structure of transistor T1 of memory cell 210'; and conductive couplings 2202A1, 2202B1, 2202C1, and 2202D1 electrically couple a channel region (e.g., portions 1920A1, 1920B1, and 1920C1) of transistor T2 to corresponding charge storage structures (e.g., portions 802A1, 802B1, 802C1, and 802D1).

[0143] Fig.30 The memory device 600 may include data lines (e.g., read data lines) 1521BL0, 1521BL1, and 1521BL2; and data lines (e.g., write data lines) 2920W, 2921W, and 2922W. The memory device 600 may include conductive lines 1201, 1202, 2601, and 2602 that may be electrically coupled to each other to form an access line (e.g., a single access line) to control two transistors (e.g., T1 and T2) in each of the memory cells 209', 210', and 211'. In the above reference Figures 6 to 30 Other elements of memory device 600 are described.

[0144] Figure 31 to Figure 35 Different views of elements during a process of forming another memory device 3100 according to some embodiments of the present invention are shown. Some or all of the processes for forming memory device 600 may be used to form the memory device 3100 described above with reference to FIG. Figures 2 to 5 A memory device 200 is described.

[0145] The process of forming the memory device 3100 may be similar to that described above with reference to Figures 6 to 30 Some of the processes described to form memory device 600 are similar or identical. Therefore, for simplicity, the processes to form similar or identical elements between memory devices 600 and 3100 are not repeated.

[0146] Fig.31Memory device 3100 is shown after conductive material 3121, dielectric material 690, conductive material 619', material 610, conductive material 624, and dielectric material 616 are formed in the Z direction in respective levels (eg, layers) over substrate 699. Conductive material 3121 may include metal, conductively doped polysilicon, or other conductive materials.

[0147] Fig.32 Memory device 3100 is shown after forming openings (eg, trenches) 3231 and 3232 and data lines (eg, read data lines) 620 ′, 621 ′, and 622 ′.

[0148] Fig.33 Memory device 3100 is shown after dielectric materials 815A, 815B, 815C, and 815D (815A-815D), materials 802A, 802B, 802C, and 802D, and conductive materials 3321A and 3321B are formed in respective openings 3231 and 3232. Fig.33 , conductive materials 3321A and 3321B may be formed such that conductive materials 3321A and 3321B may contact (e.g., may be electrically coupled to) conductive material 3121. Conductive material 3121 may be a conductive region (or alternatively a conductive line) formed over (e.g., formed in or on) substrate 699. Thus, conductive materials 3321A and 3321B may contact a conductive region (conductive material 3121) formed under (below) memory cells 209', 210', and 211' and over at least a portion of substrate 699. Conductive material 3121 may be coupled to a ground connection (not shown) of memory device 600.

[0149] Fig.34 Memory device 3100 is shown after dielectric materials 915 and 916 are formed (eg, filled) in respective openings 3231 and 3232. Fig.34 The structure shown in the figure is used to form a portion of a corresponding memory cell of the memory device 3100. The subsequent process can be the same as that described above with reference to Figures 10 to 30 The process of forming memory device 600 is similar or identical as described.

[0150] Fig.35 Memory device 3100 is shown after forming other components. Fig.35 As shown in FIG. 1 , the elements of the memory device 3100 may be connected to Fig.30 The components of the memory device 600 are similar or identical. Fig.30 ) and the memory device 3100 ( Fig.35 ) includes the differences formed in Fig.33The inclusion of conductive structures 3321A1 and 3321B1 as part of conductive materials 3321A and 3321B, respectively, during the process. Fig.35 As shown in FIG. 3 , conductive structure 3321A can be adjacent portion 802A1 (a portion of a memory element) of memory cell 209′ and adjacent portion 802B1 (a portion of a memory element) of memory cell 210′. Conductive structure 3321B can be adjacent portion 802C1 (another portion of a memory element) of memory cell 210′ ​​and adjacent portion 802D1 (a portion of a memory element) of memory cell 211′.

[0151] Compared with the memory device 600, Fig.35 Including conductive structures 3321A1 and 3321B1 in memory device 3100 can reduce electrical coupling between charge storage structures of adjacent memory cells (e.g., between charge storage structures of memory cells 209' and 210', and between charge storage structures of memory cells 210' and 211'). The reduced coupling in memory device 3100 can result in a relatively larger voltage range for the read window of each of the memory cells of memory device 3500 as compared to memory device 600.

[0152] Fig.36A , Fig.36B and Fig.36C Different views of the structure of a memory device 3600 including multiple stacks of memory cells are shown according to some embodiments described herein. Fig.36A An exploded view (eg, in the Z direction) of memory device 3600 is shown. Fig.36B Side views (eg, cross-sectional views) in the X-direction and the Z-direction of the memory device 360 ​​are shown. Fig.36C Side views (eg, cross-sectional views) in the Y-direction and the Z-direction of the memory device 3600 are shown.

[0153] like Fig.36A As shown in FIG. 3 , the memory device 3600 may include a stack (a stack of memory cells) 3605 0 、3605 1 、3605 2 and 3605 3 , the stacks are shown separated from each other in the exploded view to help facilitate easy viewing of the stack structure of the memory device 3600. In fact, the stack 3605 0 、3605 1 、3605 2 and 3605 3The stacks may be attached to each other in an arrangement where one stack may be formed (eg, stacked) on top of another stack on a substrate (eg, a semiconductor (eg, silicon) substrate) 3699. Fig.36A As shown in the figure, stack 3605 0 、3605 1 、3605 2 and 3605 3 It can be formed in the Z direction perpendicular to the substrate 3699 (for example, formed vertically in the Z direction relative to the substrate 3699).

[0154] like Fig.36A As shown in the figure, stack 3605 0 、3605 1 、3605 2 and 3605 3 Each of the stacks 3605 may have memory cells arranged in the X direction and the Y direction (eg, arranged in rows in the X direction and arranged in columns in the Y direction). 0 May include memory unit 3610 0 、3611 0 ,3612 0 and 3613 0 (eg, arranged in rows), memory cells 3620 0 ,3621 0 ,3622 0 and 3623 0 (eg, arranged in rows) and memory cells 3630 0 ,3631 0 ,3632 0 and 3633 0 (eg, arranged in rows).

[0155] Stack 3605 1 May include memory unit 3610 1 、3611 1 ,3612 1 and 3613 1 (eg, arranged in rows), memory cells 3620 1 ,3621 1 ,3622 1 and 3623 1 (eg, arranged in rows) and memory cells 3630 1 ,3631 1 ,3632 1 and 3633 1 (eg, arranged in rows).

[0156] Stack 3605 2May include memory unit 3610 2 、3611 2 ,3612 2 and 3613 2 (eg, arranged in rows), memory cells 3620 2 ,3621 2 ,3622 2 and 3623 2 (eg, arranged in rows) and memory cells 3630 2 ,3631 2 ,3632 2 and 3633 2 (eg, arranged in rows).

[0157] Stack 3605 3 May include memory unit 3610 3 、3611 3 ,3612 3 and 3613 3 (eg, arranged in rows), memory cells 3620 3 ,3621 3 ,3622 3 and 3623 3 (eg, arranged in rows) and memory cells 3630 3 ,3631 3 ,3632 3 and 3633 3 (eg, arranged in rows).

[0158] like Fig.36A As shown in the figure, stack 3605 0 、3605 1 、3605 2 and 3605 3 The stack 3605 may be positioned (eg, formed vertically in the Z direction) on the levels (eg, portions) 3650, 3651, 3652, and 3653 of the memory device 3600, respectively. 0 、3605 1 、3605 2 and 3605 3 The arrangement forms a 3-dimensional (3D) structure of the memory cells of the memory device 3600, wherein different levels of the memory cells of the memory device 3600 may be positioned (e.g., formed) in different levels (e.g., different vertical portions) 3650, 3651, 3652, and 3653 of the memory device 3600.

[0159] The stack 3605 can be formed one stack at a time 0 、3605 1、3605 2 and 3605 3 For example, you can click on stack 3605 0 、3605 1 、3605 2 and 3605 3 The order of forming stack 3605 0 、3605 1 、3605 2 and 3605 3 (For example, first form stack 3605 1 And finally form a stack 3605 3 In this example, another stack (e.g., stack 3605) may be used. 0 ) after the formation of a memory cell or in another stack (e.g., stack 3605 2 ) is formed before forming a stack (eg, stack 3605 1 Alternatively, stack 3605 may be formed in parallel (eg, simultaneously) 0 、3605 1 、3605 2 and 3605 3 , so that stacks 3605 can be formed in parallel 0 、3605 1 、3605 2 and 3605 3 For example, memory cells in levels 3650, 3651, 3652, and 3653 of memory device 3600 may be formed in parallel.

[0160] Stack 3605 0 、3605 1 、3605 2 and 3605 3 The structure of each memory cell may include the above reference Figure 1 to Figure 35 The structure of the memory cell described. For example, stack 3605 0 、3605 1 、3605 2 and 3605 3 The structure of the memory cell of may include the structure of the memory cell of the memory devices 600 and 3100 .

[0161] The memory device 3600 may include data lines (eg, bit lines) and access lines (eg, word lines) to access the stack 3605. 0 、3605 1 、3605 2 and 3605 3For simplicity, Fig.36A The data lines and access lines of the memory cells are omitted. However, the data lines and access lines of the memory device 3600 may be similar to those described above with reference to Figure 1 to Figure 35 Data lines and access lines of a memory device are described.

[0162] Fig.36A As an example, a system including four stacks (e.g., 3605 0 、3605 1 、3605 2 and 3605 3 ) of the memory device 3600. However, the number of stacks may be different from four. Fig.36A A stack 3605 is shown as an example of a level (eg, layer) including memory cells. 0 、3605 1 、3605 2 and 3605 3 However, at least one of the stacks (e.g., stack 3605 0 、3605 1 、3605 2 and 3605 3 One or more of) may have two (or more) levels of memory cells. Fig.36A An example is shown, in which stack 3605 0 、3605 1 、3605 2 and 3605 3 Each of includes four memory cells in the X direction (eg, in a row) and three memory cells in the Y direction (eg, in a column). However, the number of memory cells in a row, in a column, or both may vary.

[0163] The description of apparatus (e.g., memory devices 100, 200, 500, 600, 3100, and 3600) and methods (e.g., the operation of memory devices 100, 200, and 500 and methods of forming memory devices 600 and 3100) is intended to provide a general understanding of the structure of various embodiments and is not intended to provide a complete description of all elements and features of apparatus that may utilize the structure described herein. An apparatus herein refers to, for example, a device (e.g., any one of memory devices 100, 200, 500, 600, 3100, and 3600) or a system (e.g., an electronic article that may include any one of memory devices 100, 200, 500, 600, 3100, and 3600).

[0164] References Figure 1 to Figure 35Any of the described components may be implemented in a number of ways, including via software simulation. Thus, the apparatus (e.g., memory devices 100, 200, 500, 600, 3100, and 3600) or portions of each of these memory devices described above may be characterized herein as one or more "modules". Such modules may include hardware circuits, single and / or multi-processor circuits, memory circuits, software program modules and objects, and / or firmware, and combinations thereof, as required and / or appropriate for the particular implementation of the various embodiments. For example, these modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and range simulation package, a capacitance-inductance simulation package, a power / heat dissipation simulation package, a signal transmission-reception simulation package, and / or a combination of software and hardware to operate or simulate the operation of the various potential embodiments.

[0165] The memory devices described herein (e.g., memory devices 100, 200, 500, 600, 3100, and 3600) may be included in devices (e.g., electronic circuits) such as high-speed computers, communication and signal processing circuits, single or multi-processor modules, single or multiple embedded processors, multi-core processors, message information switches, and application-specific modules including multi-layer, multi-chip modules. These devices may further be included as subcomponents within a variety of other devices (e.g., electronic systems) such as televisions, cellular phones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, etc.

[0166] References Figure 1 to Figure 35 The described embodiments include devices and methods of forming the devices. One of the devices includes a memory cell including a first transistor and a second transistor positioned above a substrate. The first transistor includes a channel region. The second transistor includes a channel region positioned above the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element positioned on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor and electrically coupled to the channel of the second transistor. Other embodiments including additional devices and methods are described.

[0167] In the detailed description and claims, the terms "on," one "on" another, used with respect to two or more elements (e.g., materials), mean at least some contact between the elements (e.g., between the materials). The term "over" means that the elements (e.g., materials) are in close proximity, but may have one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Neither "on" nor "over" implies any directionality as used herein unless so stated.

[0168] In the detailed description and claims, a list of items joined by the term "at least one of" may mean any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" means only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0169] In the detailed description and claims, a list of items joined by the term "one of" may mean only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means only A (not including B) or only B (not including A). In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" means only A; only B; or only C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0170] The above description and drawings illustrate some embodiments of the subject matter of the present invention to enable those skilled in the art to practice the embodiments of the subject matter of the present invention. Other embodiments may incorporate structural, logical, electrical, process and other changes. Examples represent possible variations only. Portions and features of some embodiments may be included in those portions and features of other embodiments, or replace those portions and features. After reading and understanding the above description, those skilled in the art will understand many other embodiments.

Claims

1. A method of forming a memory device, comprising: forming a first transistor of a memory cell over a substrate, including forming a channel region of the first transistor; forming a memory element of the memory cell on at least one side of the channel region of the first transistor such that the memory element is electrically separated from the channel region of the first transistor; and Forming a second transistor of the memory cell includes forming a channel region of the second transistor such that the channel region of the second transistor is electrically coupled to the memory element.

2. The method of claim 1 , wherein forming the memory element comprises: forming a first portion of the memory element on a first side of the channel region of the first transistor; and A second portion of the memory element is formed on a second side of the channel region of the first transistor.

3. The method according to claim 1, further comprising: A conductive coupling is formed such that the conductive coupling contacts the channel region of the second transistor and the memory element.

4. The method of claim 3, wherein forming the conductive coupling comprises: forming a first portion of the conductive coupling such that the first portion of the conductive coupling contacts the channel region of the second transistor and contacts a first portion of the memory element; and A second portion of the conductive coupling is formed such that the second portion of the conductive coupling contacts the channel region of the second transistor and contacts a second portion of the memory element. The method of claim 1 , wherein the memory element comprises polysilicon. The method of claim 1 , wherein the channel region of the first transistor comprises polysilicon. The method of claim 1 , wherein the channel region of the second transistor comprises an oxide material.

8. The method of claim 1, wherein the channel region of the second transistor comprises at least one of: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Silicon Oxide (IGSO), Indium Oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), Indium Gallium Zinc Oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum oxide, tin, indium, zinc (Al x Sn y In z Zn a O d ), Silicon Indium Zinc Oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a )、Zirconium oxide zinc tin (Zr x Zn y Sn z O a ) and indium gallium silicon oxide (InGaSiO).

9. The method according to claim 1, further comprising: forming a first data line between the channel region of the first transistor and the substrate; and A second data line is formed over the channel region of the first transistor such that the channel region of the first transistor contacts the first data line and the second data line.

10. The method according to claim 9, further comprising: A third data line is formed over the channel region of the second transistor.

11. A method of forming a memory device, comprising: forming a memory cell over a substrate, comprising forming a first transistor of the memory cell over a substrate and forming a second transistor of the memory cell over the first transistor, the first transistor comprising a first material, and the second transistor comprising a second material formed over the first material of the first transistor; forming a first conductive line having a portion adjacent to a first side of the first material; forming a first additional conductive line having a portion adjacent to the second side of the first material; forming a second conductive line having a portion adjacent to the first side of the second material; and A second additional conductive line is formed having a portion adjacent to the second side of the second material.

12. The method according to claim 11, further comprising: A third conductive line is formed over the substrate and between the first transistor and the substrate, wherein the third conductive line has a length in a first direction, and each of the first conductive line, the first additional conductive line, the second conductive line, and the second additional conductive line has a length in a second direction.

13. The method of claim 11 , wherein forming the memory cell comprises forming a memory element of the memory cell, wherein the first side and the second side of the first material are opposite to each other in a first direction, the memory element comprises a first portion adjacent to a third side of the first material and a second portion adjacent to a fourth side of the first material, and the third side and the fourth side of the first material are opposite to each other in a second direction. The method of claim 11 , wherein the second material comprises gallium phosphide (GaP). The method of claim 11 , wherein the first material comprises one of polysilicon and metal.

16. The method according to claim 11, further comprising: forming a first conductive connection such that the first conductive connection is electrically coupled to the first conductive line and the first additional conductive line; and A second conductive connection is formed such that the second conductive connection is electrically coupled to the second conductive line and the second additional conductive line.

17. The method according to claim 11, further comprising: A third conductive connection is formed such that the third conductive connection is electrically coupled to the first conductive line, the first additional conductive line, the second conductive line, and the second additional conductive line.

18. A method of forming a memory device, comprising: forming a conductive region over the substrate; forming a first memory cell over the conductive region, including forming a first transistor of the first memory cell and forming a second transistor of the first memory cell over the first transistor of the first memory cell; forming a second memory cell over the conductive region, including forming a first transistor of the second memory cell and forming a second transistor of the second memory cell over the first transistor of the second memory cell; forming a third memory cell over the conductive region, including forming a first transistor of the third memory cell and forming a second transistor of the third memory cell over the first transistor of the third memory cell; forming a first conductive structure between the first memory cell and the second memory cell, the first conductive structure contacting the conductive region; and A second conductive structure is formed between the second memory cell and the third memory cell, the second conductive structure contacting the conductive region.

19. The method according to claim 18, further comprising: The memory element of each of the first memory cell, the second memory cell and the third memory cell is formed such that: The first conductive structure is adjacent to a first portion of the memory element of the first memory cell and adjacent to a portion of the memory element of the second memory cell; and The second conductive structure is adjacent to a second portion of the memory element of the first memory cell and adjacent to a portion of the memory element of the third memory cell.

20. The method of claim 18, further comprising: A first conductive line is formed, so that the first conductive line comprises: a first portion adjacent to a side of the first transistor of the first memory cell; a second portion adjacent to a side of the first transistor of the second memory cell; and a third portion adjacent to a side of the first transistor of the third memory cell; A second conductive line is formed, so that the second conductive line comprises: a first portion adjacent to a side of the second transistor of the first memory cell; a second portion adjacent to a side of the second transistor of the second memory cell; and A third portion is adjacent to a side of the second transistor of the third memory cell.

21. A memory device comprising: a first transistor of a memory cell positioned above the substrate, the first transistor comprising a first region; a second transistor of the memory cell, the second transistor comprising a second region positioned above and electrically separated from the first region of the first transistor; a memory element of the memory cell positioned on at least one side of the first region of the first transistor and electrically separated from the first region; and A conductive coupling contacts the second region and the memory element.

22. The memory device of claim 21, wherein the first region comprises a block of semiconductor material.

23. The memory device of claim 21, wherein the first region comprises a block of metal.

24. The memory device of claim 21, wherein the memory element comprises polysilicon.

25. The memory device of claim 21, wherein the conductive coupling comprises metal.

26. The memory device of claim 21, wherein the second region comprises a bulk of oxide material.

27. The memory device of claim 21, wherein the second region comprises a block of oxide material and the memory element comprises a block of polysilicon contacting the block of oxide material.

28. The memory device of claim 21, wherein the second region comprises at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxynitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), oxide Zirconium indium zinc (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), indium tin zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

29. The memory device of claim 21, further comprising: a first data line contacting the first region of the first transistor; a second data line contacting the first region of the first transistor; and A third data line contacts the second region of the first transistor.

30. The memory device of claim 29, further comprising: a first access line adjacent to the first region of the first transistor; and A second access line is adjacent to the second region of the second transistor.

31. A memory device comprising: a conductive region located above the substrate; a first memory cell positioned above the conductive region, the first memory cell comprising a first transistor and a second transistor positioned above the first transistor; a second memory cell positioned above the conductive region, the second memory cell comprising a first transistor and a second transistor positioned above the first transistor of the second memory cell; a third memory cell positioned above the conductive region, the third memory cell comprising a first transistor and a second transistor positioned above the first transistor of the third memory cell; a first conductive structure located between the first memory cell and the second memory cell, the first conductive structure contacting the conductive region; and A second conductive structure is located between the second memory cell and the third memory cell, and the second conductive structure contacts the conductive region.

32. The memory device of claim 31 , wherein each of the first memory cell, the second memory cell, and the third memory cell comprises a memory element, and wherein: The first conductive structure is located between the memory element of the first memory cell and the memory element of the second memory cell; and The second conductive structure is located between the memory element of the second memory cell and the memory element of the third memory cell.

33. The memory device of claim 31, wherein the second transistor of each of the first memory cell, the second memory cell, and the third memory cell includes a channel region electrically coupled to a memory element of a corresponding memory cell of the first memory cell, the second memory cell, and the third memory cell.

34. The memory device of claim 33, wherein the first transistor of each of the first memory cell, the second memory cell, and the third memory cell comprises a channel region, and the memory element of each of the first memory cell, the second memory cell, and the third memory cell comprises: a first portion adjacent to a first side of the channel region of a corresponding memory cell of the first memory cell, the second memory cell, and the third memory cell, and A second portion is adjacent to a second side of the channel region of a corresponding memory cell of the first memory cell, the second memory cell, and the third memory cell. 35 . The memory device of claim 34 , wherein the channel region of the first transistor and the channel region of the second transistor of each of the first memory cell, the second memory cell, and the third memory cell have different materials.

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