Image sensor

Abstract

An image sensor is provided, comprising a first substrate and a second substrate, the first substrate comprising a plurality of pixels and a plurality of vertical signal lines and a plurality of first wiring layers, and the second substrate comprising a plurality of second wiring layers. The first substrate and the second substrate are fixed together between the plurality of first wiring layers and the plurality of second wiring layers. A first solder pad is provided between one of the plurality of first wiring layers and one of the plurality of second wiring layers, and a second solder pad is provided between another first wiring layer of the plurality of first wiring layers and another second wiring layer of the plurality of second wiring layers. A first through hole and a second through hole connect the first solder pad to the one of the plurality of first wiring layers and the one of the plurality of second wiring layers.

Description

Technical Field

[0001] This application claims the benefit of Japanese Patent Application JP 2019-036818, filed February 28, 2019, which is hereby incorporated by reference herein in its entirety.

[0002] The present invention relates to a solid-state imaging device and an imaging system. In particular, the present invention relates to a solid-state imaging device and an imaging system in which noise is caused by dark current. Background Art

[0003] In order to reduce the size and area of ​​the circuits used for each semiconductor substrate, conventional techniques for stacking and bonding multiple semiconductor substrates have been used in solid-state imaging devices. For example, a solid-state imaging device has been proposed in which copper electrode pads are exposed on the bonding surfaces of a pair of semiconductor substrates and the electrode pads are bonded to each other for electrical conduction (for example, see Japanese Patent Application Laid-Open No. 2012-164870). The method of bonding copper electrode pads to each other as described above is called Cu (copper)-Cu bonding. In addition, in the above-mentioned solid-state imaging device, the pads that are not used for electrical conduction are called dummy pads, which are provided on the bonding surfaces below the multiple pixel circuits.

[0004] List of citations

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application No. 2012-164870 Summary of the Invention

[0007] Technical problem to be solved by the invention

[0008] In the above-mentioned prior art, in addition to the electrode pads, dummy pads are also bonded to each other to improve bonding strength. However, a difference in dark current occurs between the pixel circuits on the electrode pads and the pixel circuits on the dummy pads, which leads to the following problems: noise is generated in the image data due to this difference, and image quality is reduced. The reason for the above-mentioned difference in dark current is probably due to the difference in the amount of hydrogen supplied to the pixel circuits on the electrode pads and the pixel circuits on the dummy pads.

[0009] In view of the above circumstances, it is desirable to suppress degradation in image quality of image data in a solid-state imaging device in which a plurality of semiconductor substrates are stacked and dummy pads are provided.

[0010] Solutions to technical problems

[0011] According to a first aspect of the present invention, an image sensor is provided, comprising a first substrate and a second substrate, the first substrate comprising a plurality of pixels, a plurality of vertical signal lines, and a plurality of first wiring layers, the plurality of first wiring layers being located on one side of the first substrate; and the second substrate comprising a plurality of second wiring layers, the plurality of second wiring layers being located on one side of the second substrate. The first and second substrates are fixed together between the plurality of first wiring layers and the plurality of second wiring layers. A first pad is provided between one of the plurality of first wiring layers and one of the plurality of second wiring layers, and a second pad is provided between another first wiring layer of the plurality of first wiring layers and another second wiring layer of the plurality of second wiring layers. A first through-hole is connected to the one of the plurality of first wiring layers and the first pad provided on the first substrate, and a second through-hole is connected to the one of the plurality of second wiring layers and the first pad provided on the second substrate. The first pad provided on the first substrate and the first pad provided on the second substrate are connected to each other. A third through-hole is connected to another first wiring layer among the plurality of first wiring layers, and a fourth through-hole is connected to another second wiring layer among the plurality of second wiring layers. At least one of the third through-hole and the fourth through-hole connects the second pad to at least one of the another first wiring layer among the plurality of first wiring layers and the another second wiring layer among the plurality of second wiring layers. The first pad provides an electrical connection between the one first wiring layer among the plurality of first wiring layers and the one second wiring layer among the plurality of second wiring layers, the first pad is electrically connected to one vertical drive line among the plurality of vertical drive lines, and the second pad is not electrically connected to the plurality of vertical signal lines.

[0012] Furthermore, in the first aspect, the first substrate further includes a pixel circuit and the second substrate further includes a subsequent circuit.

[0013] Furthermore, in the first aspect, the pixel signal from the pixel circuit is transmitted from the pixel circuit to the subsequent circuit.

[0014] Furthermore, in the first aspect, the dummy pad is electrically floating.

[0015] Furthermore, in the first aspect, the dummy pad is connected to a fixed potential.

[0016] Furthermore, in the first aspect, the first pad is an electrode pad and the second pad is a dummy pad.

[0017] Furthermore, in the first aspect, the number of the first through holes and the second through holes is equal to the number of the third through holes and the fourth through holes.

[0018] Furthermore, in the first aspect, the number of the first through holes and the second through holes is greater than the number of the third through holes and the fourth through holes.

[0019] Furthermore, in the first aspect, the number of the first through holes and the second through holes is smaller than the number of the third through holes and the fourth through holes.

[0020] Furthermore, in the first aspect, the third through-hole and the fourth through-hole connect the second pad with the other one of the plurality of first wiring layers and the other one of the plurality of second wiring layers.

[0021] Furthermore, in the first aspect, the third through hole connects the second pad and the other first wiring layer among the plurality of first wiring layers.

[0022] Furthermore, in the first aspect, the sizes of the first through hole and the second through hole are different from the sizes of the third through hole and the fourth through hole.

[0023] Furthermore, in the first aspect, the cross-sectional shape of the first through hole, the second through hole, the third through hole, and the fourth through hole is rectangular, circular, or elliptical.

[0024] Furthermore, in the first aspect, the number of the third through holes is different from the number of the fourth through holes.

[0025] According to a second aspect of the present invention, an image sensor is provided, comprising a first substrate and a second substrate disposed below the first substrate. The first substrate comprises: a first bonding region comprising an electrode pad; and a second bonding region comprising a dummy pad. A plurality of first through-holes extend from the first bonding region of the first substrate and connect to the electrode pad, and a plurality of second through-holes extend from the second bonding region of the first substrate and connect to the dummy pad. The number of the plurality of first through-holes is greater than the number of the plurality of second through-holes.

[0026] Furthermore, in the second aspect, the electrode pad provides electrical connection between the first substrate and the second substrate.

[0027] Furthermore, in the second aspect, the electrode pad is provided in the first bonding region.

[0028] Furthermore, in the second aspect, the dummy pad is provided in the second bonding region.

[0029] Furthermore, in the second aspect, the dummy pad is electrically floating.

[0030] Furthermore, in the second aspect, the dummy pad is connected to a fixed potential.

[0031] According to a third aspect of the present invention, an image sensor is provided, comprising a first substrate and a second substrate disposed below the first substrate. The first substrate comprises a pair of first bonding regions having electrode pads and at least one second bonding region disposed between the pair of first bonding regions and having dummy pads. A plurality of first through-holes extend from the pair of first bonding regions of the first substrate and are connected to the electrode pads, and a plurality of second through-holes extend from the at least one second bonding region of the first substrate and are connected to the dummy pads.

[0032] Furthermore, in the third aspect, the at least one second bonding region is provided in a central portion of the first substrate.

[0033] Furthermore, in the third aspect, the image sensor further includes another second bonding region provided above one of the pair of first bonding regions and still another second bonding region provided below the other of the pair of first bonding regions.

[0034] Furthermore, in the third aspect, the second substrate includes a plurality of pairs of circuit components.

[0035] Furthermore, in the third aspect, the plurality of pairs of circuit components are arranged such that the first circuit component and the second circuit component in one pair of circuit components are reversed in order in another adjacent pair of circuit components. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] [ Figure 1 ]

[0037] Figure 1 is a block diagram showing a configuration example of an imaging system according to a first embodiment of the present invention.

[0038] [ Figure 2 ]

[0039] Figure 2 is a diagram showing an example of a stacked structure of the solid-state imaging device according to the first embodiment of the present invention.

[0040] [ Figure 3 ]

[0041] Figure 3 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present invention.

[0042] [ Figure 4 ]

[0043] Figure 4 1 is a plan view showing an example of a bonding surface of the light receiving substrate in the first embodiment of the present invention.

[0044] [ Figure 5 ]

[0045] Figure 5 is a circuit diagram showing a configuration example of a pixel circuit on a vertical signal line (VSL) bonding area in the first embodiment of the present invention.

[0046] [ Figure 6 ]

[0047] Figure 6 is a circuit diagram showing a configuration example of a pixel circuit in a dummy area in the first embodiment of the present invention.

[0048] [ Figure 7 ]

[0049] Figure 7 is a plan view showing an example of a VSL bonding region and a dummy region in the first embodiment of the present invention.

[0050] [ Figure 8 ]

[0051] Figure 8 is an example of a cross-sectional view of the solid-state imaging device according to the first embodiment of the present invention.

[0052] [ Figure 9 ]

[0053] Figure 9 is an example of a cross-sectional view of a solid-state imaging device according to a comparative example.

[0054] [ Figure 10A ]

[0055] Figure 10A It is an enlarged view showing an example of the vicinity of the joining surface in the first embodiment of the present invention.

[0056] [ Figure 10B ]

[0057] Figure 10B is an enlarged view showing an example of the vicinity of the joining surface in the comparative example.

[0058] [ Figure 11A ]

[0059] Figure 11A is a diagram showing an example of image data in the first embodiment of the present invention.

[0060] [ Figure 11B ]

[0061] Figure 11B is a diagram showing an example of image data in a comparative example.

[0062] [ Figure 12 ]

[0063] Figure 12 : is a plan view showing an example of a VSL bonding region and a dummy region in a first modification example according to the first embodiment of the present invention.

[0064] [ Figure 13 ]

[0065] Figure 13 : is a plan view showing an example of a VSL bonding region and a dummy region in a second modification example according to the first embodiment of the present invention.

[0066] [ Figure 14 ]

[0067] Figure 14 is an example of a cross-sectional view of a solid-state imaging device in a second modification example according to the first embodiment of the present invention.

[0068] [ Figure 15 ]

[0069] Figure 15 : is a plan view showing an example of a VSL bonding region and a dummy region in a third modification example of the first embodiment of the present invention.

[0070] [ Figure 16 ]

[0071] Figure 16 is an example of a cross-sectional view of a solid-state imaging device according to a third modification example of the first embodiment of the present invention.

[0072] [ Figure 17 ]

[0073] Figure 17 is a plan view showing an example of a VSL bonding region and a dummy region in the second embodiment of the present invention.

[0074] [ Figure 18A ]

[0075] Figure 18A is a plan view showing an example of a dummy region in a modification of the second embodiment of the present invention.

[0076] [ Figure 18B ]

[0077] Figure 18Bis a plan view showing an example of a dummy region in a modification of the second embodiment of the present invention.

[0078] [ Figure 18C ]

[0079] Figure 18C is a plan view showing an example of a dummy region in a modification of the second embodiment of the present invention.

[0080] [ Figure 19 ]

[0081] Figure 19 : is a plan view showing an example of a VSL bonding region and a dummy region in the third embodiment of the present invention.

[0082] [ Figure 20 ]

[0083] Figure 20 is an example of a cross-sectional view of a solid-state imaging device according to a third embodiment of the present invention.

[0084] [ Figure 21 ]

[0085] Figure 21 : is a plan view showing an example of a VSL bonding region and a dummy region in the fourth embodiment of the present invention.

[0086] [ Figure 22 ]

[0087] Figure 22 is an example of a cross-sectional view of a solid-state imaging device according to a fifth embodiment of the present invention.

[0088] [ Figure 23 ]

[0089] Figure 23 is an example of a cross-sectional view of a solid-state imaging device according to a sixth embodiment of the present invention.

[0090] [ Figure 24 ]

[0091] Figure 24 is an example of a cross-sectional view of a solid-state imaging device according to a seventh embodiment of the present invention.

[0092] [ Figure 25 ]

[0093] Figure 25 is an example of a cross-sectional view of a solid-state imaging device according to an eighth embodiment of the present invention.

[0094] [ Figure 26 ]

[0095] Figure 26is an example of a cross-sectional view of a solid-state imaging device according to a ninth embodiment of the present invention.

[0096] [ Figure 27 ]

[0097] Figure 27 is a plan view showing an example of a bonding surface of a light receiving substrate according to a tenth embodiment of the present invention.

[0098] [ Figure 28 ]

[0099] Figure 28 is a diagram illustrating the configuration of a solid-state imaging device according to an eleventh embodiment of the present invention.

[0100] [ Figure 29 ]

[0101] Figure 29 It is a diagram illustrating circuits provided on a light-receiving substrate and a circuit substrate in the eleventh embodiment of the present invention.

[0102] [ Figure 30 ]

[0103] Figure 30 is a plan view showing an example of an optical bonding surface in an eleventh embodiment of the present invention.

[0104] [ Figure 31 ]

[0105] Figure 31 is a diagram showing a circuit configuration of a solid-state imaging device according to an eleventh embodiment of the present invention.

[0106] [ Figure 32 ]

[0107] Figure 32 is an example of a cross-sectional view of a solid-state imaging device according to a twelfth embodiment of the present invention.

[0108] [ Figure 33 ]

[0109] Figure 33 is an example of a cross-sectional view of a solid-state imaging device according to a thirteenth embodiment of the present invention.

[0110] [ Figure 34 ]

[0111] Figure 34 is an example of a perspective view of a solid-state imaging device according to a fourteenth embodiment of the present invention.

[0112] [ Figure 35 ]

[0113] Figure 35is a plan view showing an example of a bonding surface of a light receiving substrate in a fourteenth embodiment of the present invention.

[0114] [ Figure 36 ]

[0115] Figure 36 is another example of a perspective view of the solid-state imaging device according to the fourteenth embodiment of the present invention.

[0116] [ Figure 37 ]

[0117] Figure 37 is a plan view showing another example of the bonding surface of the light receiving substrate in the fourteenth embodiment of the present invention.

[0118] [ Figure 38 ]

[0119] Figure 38 is another example of a perspective view of the solid-state imaging device according to the fourteenth embodiment of the present invention.

[0120] [ Figure 39 ]

[0121] Figure 39 is another example of a perspective view of the solid-state imaging device according to the fourteenth embodiment of the present invention.

[0122] [ Figure 40A ]

[0123] Figure 40A It is an enlarged view showing an example of the vicinity of the joining surface in the embodiment of the present invention.

[0124] [ Figure 40B ]

[0125] Figure 40B is an enlarged view showing an example of the vicinity of the joining surface in the comparative example.

[0126] [ Figure 41 ]

[0127] Figure 41 is an example of a cross-sectional view of a solid-state imaging device according to a fifteenth embodiment of the present invention.

[0128] [ Figure 42 ]

[0129] Figure 42 is an example of a cross-sectional view of a solid-state imaging device according to a sixteenth embodiment of the present invention.

[0130] [ Figure 43 ]

[0131] Figure 43is another example of a cross-sectional view of the solid-state imaging device according to the sixteenth embodiment of the present invention.

[0132] [ Figure 44 ]

[0133] Figure 44 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0134] [ Figure 45 ]

[0135] Figure 45 1 and 2 are diagrams illustrating examples of installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0136] Hereinafter, embodiments for carrying out the present invention (hereinafter, referred to as embodiments) will be described. The description will be made in the following order.

[0137] 1. First Embodiment (Example in which hydrogen is uniformly supplied through vias)

[0138] 2. Second Embodiment (Example in which a through hole is connected to a portion of a dummy pad and hydrogen is uniformly supplied)

[0139] 3. Third Embodiment (Example in which hydrogen is uniformly supplied through a plurality of through holes having different cross-sectional areas)

[0140] 4. Fourth embodiment (example in which hydrogen is uniformly supplied through circular through-holes)

[0141] 5. Fifth Embodiment (Example in which hydrogen is uniformly supplied to a circuit through a through-hole)

[0142] 6. Sixth Embodiment (Example in which Hydrogen is Uniformly Supplied Through Through-Hole on the Light Receiving Side and the Circuit Side)

[0143] 7. Seventh Embodiment (Example in which hydrogen is uniformly supplied through the medium and through-holes)

[0144] 8. Eighth Embodiment (Example in which hydrogen is uniformly supplied through through-holes penetrating the joint surface)

[0145] 9. Ninth Embodiment (Example in which hydrogen is uniformly supplied also to regions other than the pixel region through through-holes)

[0146] 10. Tenth Embodiment (Example in which a dummy pad is provided in a pixel region and hydrogen is uniformly supplied through a through hole)

[0147] 11. Eleventh Embodiment (Example in which analog-to-digital conversion is performed on each region and hydrogen is uniformly supplied through through-holes)

[0148] 12. Twelfth Embodiment (Example in which Hydrogen is Uniformly Supplied Through Through-Hole in a Three-Layer Stack Structure Including a Memory Substrate)

[0149] 13. Thirteenth Embodiment (Example in which Hydrogen is Uniformly Supplied Through Through-Hole in a Three-Layer Stacked Structure Including a Pixel Substrate)

[0150] 14. Fourteenth Embodiment (Example in which a plurality of vertical drive circuits are provided and hydrogen is uniformly supplied through through-holes)

[0151] 15. Fifteenth Embodiment (Example in which an electrode pad is provided in a region other than a pixel array unit and hydrogen is uniformly supplied through a through hole)

[0152] 16. Sixteenth Embodiment (Example in which hydrogen is uniformly supplied through through-holes in a three-layer stacked structure)

[0153] 17. Application examples of mobile objects.

[0154] <1. First Implementation Method>

[0155] "Configuration Example of Imaging Device"

[0156] Figure 1 1 is a block diagram illustrating an example configuration of an imaging system 100 according to a first embodiment of the present invention. Imaging system 100 is used to acquire image data through imaging and includes an optical unit 110, a solid-state imaging device 200, and a digital signal processing (DSP) circuit 120. Furthermore, imaging system 100 includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. Imaging system 100 can be considered to be a camera installed in a smartphone or an in-vehicle camera, for example.

[0157] The optical unit 110 collects light from the subject and guides the collected light to the solid-state imaging device 200. The solid-state imaging device 200 generates image data by photoelectric conversion and supplies the generated image data to the DSP circuit 120 via the signal line 209.

[0158] The DSP circuit 120 performs predetermined signal processing on the image data. The DSP circuit 120 outputs the processed image data to the frame memory 160 or the like through the bus 150. Note that the DSP circuit 120 is an example of a signal processing circuit.

[0159] The display unit 130 displays image data. For example, a liquid crystal panel or an organic electroluminescent (EL) panel can be considered as the display unit 130. The operation unit 140 generates an operation signal according to a user operation.

[0160] The bus 150 is a common path used by the optical unit 110 , the solid-state imaging device 200 , the DSP circuit 120 , the display unit 130 , the operation unit 140 , the frame memory 160 , the storage unit 170 , and the power supply unit 180 to transmit / receive data to / from each other.

[0161] The frame memory 160 holds image data. The storage unit 170 stores various types of data such as image data. The power supply unit 180 supplies power to the solid-state imaging device 200, the DSP circuit 120, the display unit 130, and the like.

[0162] "Configuration Example of Solid-State Imaging Device"

[0163] Figure 2 1 is a diagram showing an example of a stacked structure of a solid-state imaging device 200 according to the first embodiment of the present invention. The solid-state imaging device 200 includes a circuit substrate 202 and a light receiving substrate 201 stacked on the circuit substrate 202 .

[0164] Hereinafter, a predetermined axis parallel to the substrate planes of the light receiving substrate 201 and the circuit substrate 202 is defined as the X axis, and an axis perpendicular to the substrate planes is defined as the Z axis.

[0165] A plurality of vertical signal lines VSL are arranged along the Y-axis direction on the light receiving substrate 201. The vertical signal lines VSL are electrically connected to the circuit in the circuit substrate 202 via through-holes by Cu-Cu bonding.

[0166] Figure 3 1 is a block diagram illustrating a configuration example of a solid-state imaging device 200 according to a first embodiment of the present invention. The solid-state imaging device 200 includes a vertical drive circuit 210, a timing control circuit 220, a north horizontal drive circuit 231, a north column signal processing circuit 241, a pixel array unit 250, a south column signal processing circuit 242, and a south horizontal drive circuit 232. Furthermore, the solid-state imaging device 200 includes a power supply circuit 270 and an output unit 280.

[0167] A plurality of pixel circuits 260 are arranged in a two-dimensional grid in the pixel array unit 250. Hereinafter, a group of pixel circuits 260 arranged in the X-axis direction is referred to as a "row," and a group of pixel circuits 260 arranged on the Y-axis is referred to as a "column."

[0168] The pixel circuits 260 each generate a pixel signal by photoelectrically converting incident light.

[0169] The vertical drive circuit 210 sequentially selects and drives rows, and causes each row to output a pixel signal. The pixel circuit 260 in one of the odd or even rows (e.g., the odd row) outputs a pixel signal to the north column signal processing circuit 241, and the other pixel circuit 260 (e.g., the pixel circuit in the even row) outputs a pixel signal to the south column signal processing circuit 242.

[0170] The timing control circuit 220 controls the operation timing of each of the vertical driving circuit 210 , the north horizontal driving circuit 231 , the north column signal processing circuit 241 , the south column signal processing circuit 242 , and the south horizontal driving circuit 232 .

[0171] The north column signal processing circuit 241 performs signal processing such as analog-to-digital (AD) conversion and correlated double sampling (CDS) on pixel signals from corresponding rows (e.g., odd-numbered rows) for each column. The north column signal processing circuit 241 outputs the processed pixel signals to the output unit 280 under the control of the north horizontal drive circuit 231.

[0172] The south column signal processing circuit 242 performs signal processing such as AD conversion and CDS processing on pixel signals from corresponding rows (e.g., even-numbered rows) for each column, and outputs the processed pixel signals to the output unit 280 under the control of the south horizontal drive circuit 232.

[0173] The north horizontal driving circuit 231 controls the north column signal processing circuit 241 to sequentially output pixel signals in the corresponding row. The south horizontal driving circuit 232 controls the south column signal processing circuit 242 to sequentially output pixel signals in the corresponding row.

[0174] The power supply circuit 270 supplies power to the pixel array unit 250 etc. The output unit 280 outputs image data in which pixel signals are arranged.

[0175] Furthermore, a pixel array unit 250 is arranged on the light receiving substrate 201 , and circuits other than the pixel array unit 250 such as a vertical driving circuit 210 are provided on the circuit substrate 202 . Figure 3 The dotted lines in FIG. 2 represent the interface between the substrates. Note that while pixel array unit 250 is configured on light-receiving substrate 201 and other circuits are configured on circuit substrate 202, the circuits to be configured on the respective substrates are not limited to this configuration. For example, even components such as comparators in north column signal processing circuit 241 and south column signal processing circuit 242 may be configured on light-receiving substrate 201.

[0176] In addition, although the north column signal processing circuit 241 and the south column signal processing circuit 242 are arranged, only one of the circuits may be configured. In this case, only one of the north horizontal driving circuit 231 and the south horizontal driving circuit 232 is configured.

[0177] Figure 4 1 is a plan view showing an example of the bonding surface of the light receiving substrate 201 in the first embodiment of the present invention. Hereinafter, the surface opposite to the bonding surface of the two surfaces of the light receiving substrate 201 is referred to as the "light receiving surface." The plurality of pixel circuits 260 described above are arranged on the light receiving surface.

[0178] On the bonding surface of the light receiving substrate 201, drive line bonding areas 311 and 312, power line bonding areas 313 and 316, VSL bonding area 314, and dummy areas 321 and 322 are provided. The VSL bonding area 314 can be arranged at the center. In other words, the VSL bonding area 314 can be arranged between the dummy areas 321 and 322. In addition, with the light receiving surface side as the upper side, the VSL bonding area 314 and the dummy areas 321 and 322 are arranged below the pixel array unit 250. The circuit substrate 202 ( Figure 2 The configuration of the bonding surface of the light receiving substrate 201 is the same as that of the bonding surface of the light receiving substrate 201.

[0179] In the VSL bonding area 314, for example, a plurality of electrode pads 431 each formed of copper are arranged. The electrode pads 431 are configured below different pixel circuits 260. In addition, the electrode pads 431 are connected to the vertical signal line and the power supply line through through holes, respectively. In addition, the electrode pads 431 are bonded to the electrode pad on the circuit substrate 202 side, and the light receiving substrate 201 and the circuit substrate 202 are electrically connected to each other through the electrode pads. The north column signal processing circuit 241 and the south column signal processing circuit 242 are connected to the electrode pad 431 of the VSL bonding area 314. Note that the material of the electrode pad is not limited to copper, and other metal materials such as gold, conductive materials, etc. can be used. In addition, although the diameter of the through hole is smaller than 1 / 4 of the electrode pad when viewed from the X-axis direction, Figure 4 The diameter of the through hole may be greater than, equal to, or smaller than the diameter of the pad as viewed from the X-axis direction and the Y-axis direction.

[0180] A plurality of electrode pads are also formed in the drive line bonding regions 311 and 312 , and each electrode pad is connected to a drive line through a through-hole. Note that the drive line is a signal line for transmitting a drive signal for driving the pixel circuit 260 .

[0181] A plurality of electrode pads are also formed in the power line bonding regions 313 and 316 , and the respective electrode pads are connected to the power line and the ground line through vias.

[0182] A plurality of dummy pads 441, each formed of copper, are arranged in each of the dummy regions 321 and 322. The dummy pads 441 are arranged below different pixel circuits 260. In addition, although the dummy pads 441 are bonded to the dummy pads on the circuit substrate 202 side, unlike the electrode pads 431, the dummy pads 441 are not used for electrical connection between the light receiving substrate 201 and the circuit substrate 202. The dummy pads are connected to lines other than VSL (e.g., VDD, grounding) or are electrically floating. In other words, the dummy pads 441 are not used for electrical connection. However, by bonding the dummy pads 441 to each other in addition to the electrode pads 431, the bonding strength can be improved and the warping of the substrate can be suppressed.

[0183] "Configuration example of pixel circuit"

[0184] Figure 5 2 is a circuit diagram showing a configuration example of a pixel circuit 260 on the VSL junction region 314 in the first embodiment of the present invention. The pixel circuit 260 includes a photoelectric conversion device 261, a transfer transistor 262, a reset transistor 263, a floating diffusion 264, an amplification transistor 265, and a selection transistor 266.

[0185] Furthermore, a pair of vertical signal lines VSL are connected along the Y-axis direction for each column on the light-receiving surface of the pixel array unit 250. One of the pair of vertical signal lines VSL is connected to odd-numbered rows, and the other of the pair of vertical signal lines VSL is connected to even-numbered rows. Furthermore, drive lines 217 to 219 are connected along the X-axis direction for each row on the light-receiving surface of the pixel array unit 250.

[0186] The photoelectric conversion device 261 generates charges by photoelectrically converting incident light. The transfer transistor 262 transfers the charges from the photoelectric conversion device 261 to the floating diffusion layer 264 according to the drive signal TRG. The drive signal TRG is supplied from the vertical drive circuit 210 via the drive line 218.

[0187] The reset transistor 263 performs initialization by taking out charges from the floating diffusion 264 according to the driving signal RST. The driving signal RST is supplied from the vertical driving circuit 210 through the driving line 217.

[0188] The floating diffusion layer 264 accumulates electric charges and generates a voltage corresponding to the amount of electric charges. The amplifier transistor 265 amplifies the voltage of the floating diffusion layer 264.

[0189] The selection transistor 266 outputs the amplified voltage signal as a pixel signal to the north column signal processing circuit 241 or the south column signal processing circuit 242 via the vertical signal line VSL according to the drive signal SEL. The drive signal SEL is supplied from the vertical drive circuit 210 via the drive line 219 .

[0190] Furthermore, the pixel circuit 260 on the VSL bonding region 314 is connected to the electrode pad 431 via a vertical signal line VSL and a through-hole. The electrode pad 431 is bonded to the electrode pad 432 on the circuit substrate 202 side. One of the pair of vertical signal lines VSL is connected to the north column signal processing circuit 241 via the pad and the through-hole, and the other vertical signal line VSL is connected to the south column signal processing circuit 242. Note that when only one of the north column signal processing circuit 241 and the south column signal processing circuit 242 is provided, only one vertical signal line VSL is connected to each column.

[0191] Furthermore, a connection point between a power supply line 279 for supplying a power supply voltage VDD and the pixel circuit 260 is connected to the power supply circuit 270 on the circuit substrate 202 side through a through hole, an electrode pad 431 , and an electrode pad 432 .

[0192] Figure 6 is a circuit diagram showing an example configuration of the pixel circuit 260 on the dummy region 322 in the first embodiment of the present invention. A through-hole is arranged at the connection node between the pixel circuit 260 and the vertical signal line VSL on or above the dummy region 322. However, unlike the through-hole in the VSL bonding region 314, the through-hole in the dummy region 322 is not electrically connected to the circuit substrate 202.

[0193] In addition, the pixel circuit 260 on the dummy area 322 is connected to the dummy pad 441 through the power supply line 279 and the through hole. The dummy pad 441 is bonded to the dummy pad 442 on the circuit substrate 202 side. Note that the configuration of the pixel circuit 260 is not limited to Figure 5 or Figure 6 For example, a selection transistor is not necessarily provided in the pixel circuit 260 .

[0194] Figure 7 3 is a plan view showing an example of the VSL bonding area 314 and the dummy area 322 in the first embodiment of the present invention. In the VSL bonding area 314, a plurality of electrode pads 431 are arranged, and a predetermined number (e.g., four) of through-holes 423 are connected to the electrode pads 431. Note that the number of through-holes 423 of each electrode pad 431 is not limited to four.

[0195] Meanwhile, a plurality of dummy pads 441 are arranged in dummy region 322, and different numbers (eg, two) of vias 424 are connected to the respective dummy pads 441. The number of vias 424 is different from that of electrode pad 431.

[0196] In addition, the number of through holes used for connection is the same for all dummy pads 441. In addition, the cross-sectional area and cross-sectional shape of each of through holes 423 and 424 are the same. For example, the cross-sectional shape of each through hole is rectangular.

[0197] When multiple films are stacked on the light receiving substrate 201, the films themselves may contain hydrogen in some cases. Furthermore, hydrogen may be mixed in during the hydrogen sintering process in some cases. Depending on the circumstances, the number of through holes in the electrode pad 431 or the dummy pad 441 is adjusted so that the amount of hydrogen supplied to each of the multiple pixel circuits 260 is uniform.

[0198] Figure 8 is an example of a cross-sectional view of the solid-state imaging device 200 according to the first embodiment of the present invention. Figure 8 The cross-section is along Figure 7 FIG. 1 is a cross-sectional view of the solid-state imaging device 200 cut along line segment Y1 - Y2 .

[0199] In the light receiving substrate 201, with the light receiving surface side as the upper side, a wiring layer 420 is provided above the electrode pad 431. The wiring layer 420 includes a single insulating film or multiple insulating films, and a single wiring layer or multiple wiring layers. In the area where the electrode pads are not bonded to each other, the upper insulating film and the lower insulating film are connected to each other. In addition, in the wiring layer 420, metal wirings 421 such as vertical signal lines and power lines are connected along the Y-axis direction, and transistors 417 such as transfer transistors are arranged. In addition, the vertical signal lines and the like are connected to each other with the electrode pad 431 through through-holes 423. In addition, a photodiode 415 is formed above the through-hole 423, and a color filter 413 is formed above the photodiode 415. An on-chip lens 411 is formed above the color filter 413. The photodiode 415 and the transistor 417 constitute the pixel circuit 260. The wiring layer 420 includes multiple metal wirings 421 and 422. The plurality of metal wirings 421 are connected to each other through a through-hole 423, and the plurality of metal wirings 422 are connected to each other through a through-hole 424. In addition, the wiring layer 450 includes a plurality of metal wirings 451 and 452. The plurality of metal wirings 451 are connected to each other through a through-hole 453, and the plurality of metal wirings 452 are connected to each other through a through-hole 454.

[0200] At the same time, a wiring layer 420 is also provided above the dummy pad 441. In the wiring layer 420, metal wiring 422 such as a power line is connected along the Y-axis direction or the X-axis direction, and a transistor 418 such as a transfer transistor is provided. In addition, the power line and the dummy pad 441 are connected to each other through a through hole 424. In addition, a photodiode 416 is formed above the through hole 424, and a color filter 414 is formed above the photodiode 416. An on-chip lens 412 is formed above the color filter 414. The photodiode 416 and the transistor 418 constitute the pixel circuit 260.

[0201] In the circuit substrate 202, with the light receiving surface side as the upper side, a wiring layer 450 is provided below the electrode pad 432. In the wiring layer 450, metal wiring 451 is wired, and a transistor 455 is provided. A through hole 453 is connected to the electrode pad 432. In addition, a subsequent circuit 461 such as an A / D converter (ADC) in the column signal processing circuit 241 is provided below the through hole 453. The through hole 453 connects the electrode pad 432 and the circuit such as the subsequent circuit 461 to each other.

[0202] At the same time, a wiring layer 450 is also provided below the dummy pad 442. In the wiring layer 450, metal wiring 452 is routed, and a transistor 456 and a through-hole 454 are provided. However, the through-hole 454 is not connected to the dummy pad 442. In addition, a subsequent circuit 462 such as an ADC in the north column signal processing circuit 241 is provided below the through-hole 454.

[0203] As described above, a plurality of pixel circuits 260 are arranged on the light receiving surface opposite to the bonding surface of the two surfaces of the light receiving substrate 201. During the process (hydrogen sintering process, etc.) when the light receiving substrate 201 and the circuit substrate 202 are bonded to each other, hydrogen or the like may be mixed in near the bonding surface in some cases. As disclosed in Japanese Patent Application Laid-Open No. 2001-267547, it is known that hydrogen or the like terminates dangling bonds of silicon. Due to this characteristic, when hydrogen or the like is supplied to the semiconductor device (photoelectric conversion device or transistor) in the pixel circuit 260, dark current generated in the pixel circuit 260 is suppressed according to the amount of hydrogen or the like supplied.

[0204] like Figure 8As shown, through-hole 423 connects electrode pad 431 and pixel circuit 260 above electrode pad 431, and transmits pixel signals through through-hole 423. Through-hole 424 connects dummy pad 441 and pixel circuit 260 above dummy pad 441. In other words, through-hole 423 connects pixel circuit 260 above electrode pad 431 and VSL bonding area 314 on the bonding surface through electrode pad 431, and through-hole 424 connects pixel circuit 260 above dummy pad 441 and dummy area 322 on the bonding surface through dummy pad 441.

[0205] Due to the process during bonding, hydrogen is contained near the bonding surface. Therefore, hydrogen is supplied to the pixel circuit 260 above the electrode pad 431 through the through hole 423, and hydrogen is also supplied to the pixel circuit 260 above the dummy pad 441 through the through hole 424. Therefore, the amount of hydrogen supplied to each of the multiple pixel circuits 260 is constant, and the amount of dark current generated in each circuit is constant. In addition, by also connecting the through hole 424 to the dummy pad 441, the uniformity of the opening of the through hole can be improved, and process variations can be suppressed. In addition, plasma damage can be suppressed and the yield can be improved.

[0206] In addition, if no through-hole is provided, the electrode pad for dummy bonding is floating. By additionally arranging through-holes, it is possible to connect the electrode pad for dummy bonding (e.g., dummy pad 441) to, for example, a fixed potential (VDD), an arbitrary potential, a ground potential (GND), etc. Therefore, it is possible to stabilize the potential of the electrode for dummy bonding and improve electrical characteristics. Examples of methods for connecting the electrode pad for dummy bonding to a fixed potential, an arbitrary potential, or a ground potential include methods for directly connecting a through-hole to the potential. In addition, by additionally arranging through-holes, it is possible to connect the electrode pad to other wirings through the through-holes. By connecting the wiring connected to the contact terminal opposite to the electrode pad in the contact terminal of the through-hole to an arbitrary potential, it is possible to connect the electrode pad to the potential through the through-hole.

[0207] Note that light receiving substrate 201 is an example of a first semiconductor substrate, and circuit substrate 202 is an example of a second semiconductor substrate. Pixel circuit 260 is an example of a first circuit. Subsequent circuit 461 is an example of a second circuit. Electrode pad 431 is an example of a first electrode pad. Dummy pad 441 is an example of a second electrode pad. Electrode pad 432 is an example of a third electrode pad, and dummy pad 442 is an example of a fourth electrode pad. Wiring layer 420 is an example of a first wiring layer, and wiring layer 450 is an example of a second wiring layer. Through hole 423 is an example of a first through hole, and through hole 453 is an example of a second through hole. Through hole 424 is an example of a third through hole.

[0208] Furthermore, although hydrogen is assumed to be an atom that terminates dangling bonds of silicon, atoms other than hydrogen may have the property of terminating dangling bonds of silicon in some cases. Therefore, the number of through-holes can be adjusted to uniformly supply atoms other than hydrogen that terminate dangling bonds of silicon. Examples of atoms that terminate dangling bonds of silicon include hydrogen (H), fluorine (F), nitrogen (N), oxygen (O), and carbon (C). Other examples of such atoms include, but are not limited to, elements from Groups 13 to 17.

[0209] Next, a comparative example in which the through hole 424 is not connected to the dummy pad 441 will be described.

[0210] Figure 9 : is an example of a cross-sectional view of a solid-state imaging device according to a comparative example. Figure 9 As shown in , when through-hole 424 is not connected to dummy pad 441, the amount of hydrogen supplied to pixel circuit 260 above dummy pad 441 is reduced compared to the amount of hydrogen supplied to pixel circuit 260 above electrode pad 431. Therefore, the amount of hydrogen supplied to each of the plurality of pixel circuits 260 is non-uniform, and differences may occur in the amount of dark current generated in each circuit. Consequently, noise is generated due to the differences in dark current, which degrades the image quality of the image data.

[0211] Figure 10A and Figure 10B are enlarged views showing examples of the vicinity of the joining surface in the first embodiment of the present invention or the comparative example, respectively. Figure 10A It is an enlarged view showing an example of the vicinity of the joining surface in the first embodiment of the present invention. Figure 10B is an enlarged view showing an example of the vicinity of the joining surface in the comparative example.

[0212] like Figure 10A As shown, a silicon nitride (SiN) film 471 is formed on the bonding surface on the light receiving side in order to suppress warping of the light receiving substrate 201. The electrode pad 431 is formed by breaking through the SiN film 471. In other words, the electrode pad 431 penetrates the SiN film 471.

[0213] Similarly, a SiN film 472 is formed on the bonding surface on the circuit side, and the electrode pad 432 is formed by breaking through the SiN film 472 .

[0214] As disclosed in Japanese Patent Application Laid-Open No. 2018-078305, SiN films 471 and 472 are used to suppress warping. However, as disclosed in Japanese Patent Application Laid-Open No. 2004-165236, SiN films 471 and 472 each have a property of blocking hydrogen. Figure 10BIf the SiN film 472 shown is not broken, hydrogen may not be supplied to the pixel circuit 260 and dark current may not be sufficiently suppressed. Therefore, when forming a SiN film, it is advantageous for the electrode pad to break through the SiN film.

[0215] Figure 11A and Figure 11B are diagrams showing examples of image data in the first embodiment of the present invention or a comparative example, respectively. Figure 11A is a diagram showing image data 500 obtained by performing imaging in a dark state in the first embodiment of the present invention. Figure 11B is a diagram showing an example of image data 501 obtained by imaging in a dark state in a comparative example in which a through-hole is not connected to a dummy pad.

[0216] In the case where the through hole is connected to the dummy pad, hydrogen is also supplied to the pixel circuit 260 above the dummy pad through the through hole. Therefore, the amount of hydrogen supplied to each of the plurality of pixel circuits 260 is uniform and the amount of dark current generated in each circuit is uniform. Figure 11A As shown, stripes do not appear on the image data 500, which enables improvement in image quality.

[0217] Meanwhile, in the case where the through hole is not connected to the dummy pad, hydrogen is not supplied to the pixel circuit 260 above the dummy pad. Therefore, the amount of hydrogen supplied to each of the plurality of pixel circuits 260 is non-uniform, and the amount of dark current generated in each circuit is non-uniform. Figure 11B As shown, stripe noise occurs in the VSL joint region 314 of the image data 501, which degrades the image quality.

[0218] As described above, according to the first embodiment of the present invention, since the through hole 424 connects the pixel circuit 260 and the dummy region 322 on the bonding surface to each other through the dummy pad 441, it is possible to make uniform the amount of hydrogen supplied to each of the plurality of pixel circuits 260. Therefore, the amount of dark current generated becomes uniform, and the image quality of image data can be improved.

[0219] "First Modification"

[0220] In the first embodiment described above, the amount of hydrogen supplied is made uniform by using two through-holes in the dummy pad 441. However, when the number of through-holes is two, the amount of hydrogen supplied may be excessive in some cases. The solid-state imaging device 200 according to the first modification of the first embodiment differs from the solid-state imaging device 200 according to the first embodiment in that the number of through-holes in the dummy pad 441 is reduced to reduce the amount of hydrogen supplied.

[0221] Figure 12 This is a plan view illustrating an example of a VSL bonding region 314 and a dummy region 322 in a first modification of the first embodiment of the present invention. The solid-state imaging device 200 according to the first modification of the first embodiment differs from the solid-state imaging device according to the first embodiment in that the number of through-holes in the dummy pad 441 is one. By reducing the number of through-holes in the dummy pad 441 by one, the amount of hydrogen supplied to the pixel circuit 260 above the dummy pad 441 can be reduced.

[0222] According to the first modification of the first embodiment of the present invention, since the number of through holes of dummy pad 441 is reduced, the amount of hydrogen to be supplied to pixel circuit 260 above dummy pad 441 can be reduced.

[0223] "Second Modification"

[0224] In the first embodiment described above, the amount of hydrogen supplied is made uniform by using two through-holes in the dummy pad 441. However, when the number of through-holes is two, the amount of hydrogen supplied may be insufficient in some cases. The solid-state imaging device 200 according to the second modified example of the first embodiment differs from the solid-state imaging device according to the first embodiment in that the number of through-holes in the dummy pad 441 is increased to increase the amount of hydrogen supplied.

[0225] Figure 13 3 is a plan view showing an example of a VSL bonding region 314 and a dummy region 322 in a second modification example of the first embodiment of the present invention.

[0226] Figure 14 is an example of a cross-sectional view of a solid-state imaging device 200 according to a second modification example of the first embodiment of the present invention.

[0227] like Figure 13 and Figure 14 As shown in FIG. 1 , the solid-state imaging device 200 according to the second modification of the first embodiment is different from the solid-state imaging device according to the first embodiment in that the number of through-holes in the dummy pad 441 is four, which is the same as the number of through-holes in the electrode pad 431. By increasing the number of through-holes in the dummy pad 441, the amount of hydrogen to be supplied to the pixel circuit 260 above the dummy pad 441 can be increased.

[0228] Note that the number of through holes of each dummy pad 441 is not limited to one, two, or four, and may be three.

[0229] As described above, according to the second modification of the first embodiment of the present invention, since the number of through holes of dummy pad 441 is increased, the amount of hydrogen to be supplied to pixel circuit 260 above dummy pad 441 can be increased.

[0230] "Third Modification"

[0231] In the second modification of the first embodiment, the number of through-holes in the dummy pad 441 has been increased to four. However, when the number of through-holes is four, the amount of hydrogen may be insufficient in some cases. The solid-state imaging device 200 according to the third modification of the first embodiment differs from the solid-state imaging device according to the second modification of the first embodiment in that the number of through-holes in the dummy pad 441 is further increased.

[0232] Figure 15 3 is a plan view showing an example of a VSL bonding region 314 and a dummy region 322 in a third modification example of the first embodiment of the present invention.

[0233] Figure 16 is an example of a cross-sectional view of a solid-state imaging device 200 according to a third modification example of the first embodiment of the present invention.

[0234] like Figure 15 and Figure 16 As shown in FIG. 1 , the solid-state imaging device 200 according to the third modification of the first embodiment differs from the solid-state imaging device according to the first embodiment in that the number of through holes in the dummy pad 441 is nine. By increasing the number of through holes in the dummy pad 441, the amount of hydrogen supplied to the pixel circuit 260 above the dummy pad 441 can be increased.

[0235] Note that the number of through holes per dummy pad 441 is not limited to four or nine, and may be five to eight.

[0236] As described above, according to the third modification of the first embodiment of the present invention, since the number of through holes of dummy pad 441 is further increased, the amount of hydrogen to be supplied to pixel circuit 260 above dummy pad 441 can be further increased.

[0237] <2. Second Implementation Plan>

[0238] In the first embodiment described above, the number of through holes connected to the dummy pads 441 is the same for all dummy pads 441. However, in some cases, depending on the position of the dummy pads, it is not necessary to provide through holes. The solid-state imaging device 200 according to the second embodiment differs from the solid-state imaging device according to the first embodiment in that dummy pads connected to through holes and dummy pads not connected to through holes are arranged.

[0239] Figure 173 is a plan view showing an example of a VSL bonding region 314 and a dummy region 322 in a second embodiment of the present invention. The dummy region 322 in the second embodiment differs from the dummy region 322 in the first embodiment in that a plurality of dummy pads 441 and a plurality of dummy pads 442 are arranged.

[0240] It is not necessary to supply hydrogen to each of the dummy pads 441 arranged at their respective positions, and no through-holes are connected to these dummy pads. At the same time, it is necessary to supply hydrogen to each of the dummy pads 442 arranged at their respective positions, and the number of through-holes for the dummy pads is four, etc. By adjusting the number of through-holes as described above, the amount of hydrogen to be supplied can be made uniform.

[0241] Note that the dummy pad 441 is an example of a first dummy pad, and the dummy pad 442 is an example of a second dummy pad.

[0242] As described above, according to the second embodiment of the present invention, since the dummy pads 441 not connected to the through-holes and the dummy pads 442 connected to the through-holes are arranged, the amount of hydrogen to be supplied can be adjusted and made uniform.

[0243] Modification Example

[0244] In the second embodiment described above, dummy pads not connected to through-holes and dummy pads connected to through-holes are arranged. However, there is a possibility that the amount of hydrogen supplied to the dummy pads not connected to through-holes is insufficient. The solid-state imaging device 200 according to the modified example of the second embodiment differs from the solid-state imaging device according to the second embodiment in that two or more types of dummy pads having different numbers of through-holes are arranged.

[0245] 18A to 18C 1 and 2 are plan views respectively showing examples of dummy regions 321 , 322 , and 323 in a modification of the second embodiment of the present invention. Figure 18A is a plan view showing an example of the dummy region 321 . Figure 18B 3 is a plan view showing an example of the dummy region 322 . Figure 18C 3 is a plan view showing an example of the dummy region 323 .

[0246] The number of through holes per dummy pad is adjusted to make the amount of hydrogen to be supplied uniform. Figure 18A As shown, dummy pads 441 and 442 are arranged in dummy region 321. The number of vias connected to dummy pad 441 is, for example, four, and the number of vias connected to dummy pad 442 is different from the number of vias connected to dummy pad 441 (for example, one).

[0247] Note that the dummy pad 441 is an example of a first dummy pad, and the dummy pad 442 is an example of a second dummy pad.

[0248] like Figure 18B As shown, dummy pads 443 and dummy pads 444 are arranged in dummy region 322. The number of through-holes connected to dummy pad 443 is, for example, one, and the number of through-holes connected to dummy pad 444 is different from the number of through-holes connected to dummy pad 443 (for example, two).

[0249] like Figure 18C As shown, dummy pads 445 and 446 are arranged in dummy region 323. No through-hole is connected to dummy pad 445, and the number of through-holes connected to dummy pad 446 is, for example, one.

[0250] As described above, according to the modification of the second embodiment of the present invention, since a plurality of types of dummy pads connected with different numbers of through holes are arranged, the amount of hydrogen to be supplied can be made uniform by adjusting the number of through holes.

[0251] <3. Third Implementation Plan>

[0252] In the first embodiment described above, the cross-sectional area of ​​the through-hole 423 of the electrode pad 431 and the cross-sectional area of ​​the through-hole 424 of the dummy pad 441 are the same. In this configuration, in some cases, the amount of hydrogen supplied to the through-holes is uneven. The solid-state imaging device 200 according to the third embodiment differs from the solid-state imaging device according to the first embodiment in that the cross-sectional area of ​​the through-hole 423 of the electrode pad 431 and the cross-sectional area of ​​the through-hole 424 of the dummy pad 441 are different.

[0253] Figure 19 3 is a plan view showing an example of the VSL bonding region 314 and the dummy region 322 in the third embodiment of the present invention.

[0254] Figure 20 is an example of a cross-sectional view of a solid-state imaging device 200 according to the third embodiment of the present invention.

[0255] like Figure 19 and Figure 20 As shown, the cross-sectional area of ​​through-hole 423 of electrode pad 431 is different from the cross-sectional area of ​​through-hole 424 of dummy pad 441. For example, the cross-sectional area of ​​through-hole 424 is larger than the cross-sectional area of ​​through-hole 423. In addition, the number of through-holes of electrode pad 431 is four, and the number of through-holes of dummy pad 441 is one. The number and cross-sectional area of ​​each of through-holes 423 and through-hole 424 are adjusted so that the amount of hydrogen to be supplied is uniform.

[0256] As described above, according to the third embodiment of the present invention, since the cross-sectional areas of the through hole 423 of the electrode pad 431 and the through hole 424 of the dummy pad 441 are different, the supply amount of hydrogen can be made uniform by adjusting the cross-sectional areas.

[0257] <4. Fourth Implementation Plan>

[0258] In the first embodiment described above, a through hole having a rectangular cross-sectional shape has been used. The cross-sectional shape of the through hole is not limited to a rectangular shape and may be a circular shape. The solid-state imaging device 200 according to the fourth embodiment differs from the solid-state imaging device according to the first embodiment in that a through hole having a circular cross-sectional shape is used.

[0259] Figure 21 3 is a plan view showing an example of a VSL bonding region 314 and a dummy region 322 in a fourth embodiment of the present invention. The through-holes 423 and 424 in the fourth embodiment differ from those in the first embodiment in that both have circular cross-sectional shapes. Note that the cross-sectional shape of the through-holes is not limited to a circular or rectangular shape. For example, the cross-sectional shape of the through-holes may be an elliptical shape.

[0260] As described above, according to the fourth embodiment of the present invention, since the cross-sectional shape of the through-hole is a circular shape, the dark current can be made uniform by supplying hydrogen through the circular through-hole.

[0261] <5. Fifth Implementation Plan>

[0262] In the first embodiment described above, the dark current of each of the plurality of pixel circuits 260 on the light receiving side is made uniform. In some cases, the dark current of the plurality of circuits on the circuit side (e.g., ADC) is non-uniform. The solid-state imaging device 200 according to the fifth embodiment differs from the solid-state imaging device according to the first embodiment in that the through-holes and dummy pads on the circuit side are connected to each other to make the dark current on the circuit side uniform.

[0263] Figure 22 is an example of a cross-sectional view of a solid-state imaging device 200 according to a fifth embodiment of the present invention. The solid-state imaging device 200 according to the fifth embodiment differs from the solid-state imaging device according to the first embodiment in that the through hole 424 is not connected to the dummy pad 441 on the light-receiving side, and the through hole 454 is connected to the dummy pad 442 on the circuit side. It is assumed that even when the through hole 424 is not connected to the dummy pad 441 on the light-receiving side, the dark current on the light-receiving side is uniform.

[0264] As described above, multiple circuits, such as subsequent circuits 461 and 462, are arranged on the plane opposite the bonding surface of the two surfaces of circuit substrate 202. Via 453 connects subsequent circuit 461 to electrode pad 432, and via 454 connects subsequent circuit 462 to dummy pad 442. Subsequent circuits 461 and 462 are, for example, ADCs. Therefore, the amount of hydrogen supplied to each of subsequent circuits 461 and 462, etc., can be made uniform, and the amount of dark current on the circuit side can be made uniform.

[0265] As described above, according to the fifth embodiment of the present invention, since the through hole 454 on the circuit side connects the subsequent circuit 462 and the dummy pad 442 to each other, it is possible to make the amount of hydrogen to be supplied to each of the plurality of circuits on the circuit side uniform. Therefore, the amount of dark current generated becomes uniform, and the image quality of the image data can be improved.

[0266] <6. Sixth Implementation Plan>

[0267] In the first embodiment described above, the dummy pads on the circuit side are not connected to the through-holes. In this configuration, there is a possibility that the amount of hydrogen supplied may be insufficient. The solid-state imaging device 200 according to the sixth embodiment differs from the solid-state imaging device according to the first embodiment in that through-holes are further connected to the dummy pads on the circuit side to increase the amount of hydrogen to be supplied.

[0268] Figure 23 is an example of a cross-sectional view of a solid-state imaging device 200 according to a sixth embodiment of the present invention. The solid-state imaging device 200 according to the sixth embodiment differs from the solid-state imaging device according to the first embodiment in that a through-hole 454 is also connected to a dummy pad 442 on the circuit side. However, the through-hole 454 is not connected to the power supply circuit 270, and the dummy pads 441 and 442 are not used for electrical connection.

[0269] like Figure 23 As shown, by connecting the through-hole not only to the dummy pad 441 on the light-receiving side but also to the dummy pad 442 on the circuit side, hydrogen in the circuit substrate 202 can also be supplied to the pixel circuit 260 above the circuit substrate 202. Therefore, compared with the case where the through-hole is connected only to the dummy pad 441 on the light-receiving side, the amount of hydrogen to be supplied can be increased.

[0270] Note that the dummy pad 441 is an example of a dummy pad on the light receiving side, and the dummy pad 442 is an example of a dummy pad on the circuit side. Furthermore, the through hole 454 is an example of a fourth through hole.

[0271] As described above, according to the sixth embodiment of the present invention, since the via is also connected to the dummy pad 442 on the circuit side, the amount of hydrogen for supply can be increased compared to the case where the via is connected only to the dummy pad 441 on the light receiving side.

[0272] <7. Seventh Implementation Plan>

[0273] In the first embodiment described above, the through hole 424 is directly connected to the dummy pad 441. However, since hydrogen vaporizes, it is possible to supply hydrogen through a hollow path. The solid-state imaging device 200 according to the seventh embodiment differs from the solid-state imaging device according to the first embodiment in that hydrogen is supplied through a hollow path.

[0274] Figure 24 is an example of a cross-sectional view of a solid-state imaging device 200 according to a seventh embodiment of the present invention. The solid-state imaging device 200 according to the seventh embodiment differs from the solid-state imaging device according to the first embodiment in that a through-hole 424 and a dummy pad 441 are connected to each other via a cavity 425, which serves as a hollow path. In other words, the through-hole 424 connects the bonding surface and the pixel circuit 260 to each other via the air (a medium carrying hydrogen) in the cavity 425 and the dummy pad 441. Therefore, the length of the through-hole 424 can be shortened by an amount corresponding to the length of the cavity 425. Note that the cavity 425 can be filled with a filler such as an organic substance, as long as the filler is a medium capable of carrying hydrogen.

[0275] As described above, according to the seventh embodiment of the present invention, since the through hole 424 connects the bonding surface and the pixel circuit 260 to each other through the cavity 425 and the dummy pad 441 , the length of the through hole 424 can be shortened by an amount corresponding to the cavity 425 .

[0276] <8. Eighth Implementation Plan>

[0277] In the first embodiment described above, a pad is provided on the bonding surface for each pixel circuit 260, and the pads are bonded to each other. However, if the bonding position accuracy is sufficiently high, it is not necessary to provide a pad. The solid-state imaging device 200 according to the eighth embodiment differs from the solid-state imaging device according to the first embodiment in that hydrogen is supplied through a through-hole penetrating the bonding surface, which eliminates the need for a pad.

[0278] Figure 25 is an example of a cross-sectional view of a solid-state imaging device 200 according to an eighth embodiment of the present invention. In the eighth embodiment, a through-hole 424 on the light-receiving side is connected to a through-hole 454 on the circuit side without passing through a dummy pad. Note that one end of through-hole 424 is connected to the power supply line on the light-receiving side, but the other end of through-hole 424 is not connected to the circuit. This through-hole is not used for electrical connection.

[0279] Furthermore, the through-hole 423 on the light-receiving side is connected to the through-hole 453 on the circuit side without passing through the electrode pad.

[0280] Since the through-holes are provided in each of the dummy region 322 and the VSL junction region 314 , hydrogen can be uniformly supplied to the plurality of pixel circuits 260 through the through-holes.

[0281] As described above, according to the eighth embodiment of the present invention, since the through-holes on the light-receiving side and the through-holes on the circuit side are directly connected to each other, the amount of hydrogen to be supplied can be made uniform without using a pad.

[0282] <9. Ninth Implementation Plan>

[0283] In the first embodiment described above, the dummy pads 441 and the through-holes 424 are arranged in the pixel region where the pixel circuit 260 is arranged. However, the dummy pads 441 and the through-holes 424 may be arranged in regions other than the pixel region. The solid-state imaging device 200 according to the ninth embodiment differs from the solid-state imaging device according to the first embodiment in that the dummy pads 441 and the through-holes 424 are also arranged in regions other than the pixel region.

[0284] Figure 26 : is an example of a cross-sectional view of a solid-state imaging device according to a ninth embodiment of the present invention. The configuration of the pixel region in the ninth embodiment is similar to that in the first embodiment. Figure 26 As shown, the solid-state imaging device 200 according to the ninth embodiment is different from the solid-state imaging device according to the first embodiment in that dummy pads 441 and through holes 424 are also arranged in a region other than the pixel region.

[0285] As described above, in the ninth embodiment of the present invention, the dummy pads 441 and the through holes 424 are arranged in the region other than the pixel region.

[0286] <10. Tenth Implementation Plan>

[0287] Although the VSL bonding region 314 is arranged in the pixel region in which the pixel circuit 260 is arranged in the first embodiment described above, the present invention is not limited to this configuration. The solid-state imaging device 200 according to the tenth embodiment differs from the solid-state imaging device according to the first embodiment in that the VSL bonding region 314 is arranged in a region outside the pixel region.

[0288] Figure 27This is a plan view showing an example of the bonding surface of the light receiving substrate in the tenth embodiment of the present invention. The bonding surface of the light receiving substrate 201 according to the tenth embodiment includes power line / drive line bonding areas 317 and 318, VSL bonding areas 314 and 315, and a dummy area 321. Furthermore, the dummy area 321 is arranged below the pixel array unit 250 (pixel area), with the light receiving surface side as the upper side. The configuration of the bonding surface of the circuit substrate 202 is the same as that of the bonding surface of the light receiving substrate 201.

[0289] In addition, the VSL bonding regions 314 and 315 are disposed outside the pixel region.

[0290] As described above, in the tenth embodiment of the present invention, the VSL bonding regions 314 and 315 are provided outside the pixel region.

[0291] <11. Eleventh Implementation Plan>

[0292] In the first embodiment described above, AD conversion is performed for each column. However, AD conversion may be performed for each region including a plurality of pixel circuits 260. The solid-state imaging device 200 according to the eleventh embodiment differs from the solid-state imaging device 200 according to the first embodiment in that AD conversion is performed for each region.

[0293] Figure 28 This figure shows the configuration of a solid-state imaging device 200 according to the eleventh embodiment of the present invention. This embodiment of the present invention can be applied to a stacked imaging device. This stacked imaging device has a configuration in which a chip with a signal processing circuit is used instead of a supporting substrate for the pixel portion, and the pixel portion is overlaid on this chip. This configuration enables miniaturization of the imaging device.

[0294] like Figure 28 As shown, on the light receiving substrate 10, pixels 21 are arranged in a matrix and a pixel driving circuit 22 for driving each pixel 21 is arranged. On the lower substrate 11, ADCs (A / D converters) 31 are arranged in a matrix at positions corresponding to the pixels 21. Figure 28 In the illustrated example, a configuration is shown in which 2×2=4 pixels are used as one block (region) and one ADC 31 processes four pixels 21 corresponding to one block. In this configuration, the ADCs 31 operate in parallel, and each ADC 31 performs AD conversion while scanning four pixels.

[0295] The circuit substrate 11 is also equipped with an output circuit 32, a sense amplifier 33, a V scanning circuit 34, a timing generation circuit 35, and a DAC (D / A converter). The output from the ADC 31 is output to the outside via the sense amplifier 33 and the output circuit 32. The pixel drive circuit 22 and the V scanning circuit 34 perform processing related to reading from the pixel 21, and this processing is controlled by the timing generated by the timing generation circuit 35. In addition, the DAC 36 is a circuit that generates a ramp signal.

[0296] The ramp signal is a signal for supplying to the comparator of the ADC 31. Figure 29 The internal configuration of the ADC 31 will be described. Figure 29 3 is a block diagram showing the configuration of pixels 21 corresponding to one block (region) and ADC 31. Signals from each pixel 21 corresponding to one block including 2×2=4 pixels are compared by comparator 51 of ADC 31 with the ramp voltage of the ramp signal.

[0297] The ramp voltage is a voltage that gradually decreases from a predetermined voltage. When the ramp voltage starts to decrease and intersects the signal from the pixel 21 (when the voltage of the signal from the pixel 21 and the ramp voltage become the same voltage), the output of the comparator 51 is reversed. The output of the comparator 51 is input to the latch circuit 52. The code value indicating the time at this time is input to the latch circuit 52, and the code value when the output of the comparator 51 is reversed is held in the latch circuit 52 and subsequently read from the latch circuit 52.

[0298] Figure 30 1 is a plan view showing an example of the bonding surface of the light receiving substrate in the eleventh embodiment of the present invention. On the bonding surface, pads are arranged for each block (region) with the same number of pixels. When 2×2 pixels are used as one region, four pads are arranged. One of the four pads is an electrode pad 431 and the other three are dummy pads 441.

[0299] Figure 31 3 is a circuit diagram showing an imaging device including the ADC 31. Figure 31 In the figure, it is shown that Figure 29 The light receiving substrate 10 and the circuit substrate 11 are shown. The light receiving substrate 10 includes a pixel 21, and the circuit of the pixel 21 has the following Figure 31 Now, a structure in which four pixels share one floating diffusion (FD) will be described as an example.

[0300] Photodiodes (PD) 101-1 to 101-4 as photoelectric conversion units are connected to transfer transistors (Trf) 102-1 to 102-4, respectively. Hereinafter, when the photodiodes 101-1 to 101-4 do not need to be distinguished individually, they are simply referred to as photodiodes 101. Other parts will be similarly abbreviated.

[0301] The transfer transistors 102-1 to 102-4 are connected to a floating diffusion (FD) 103. The transfer transistor 102 transfers the signal charge photoelectrically converted and accumulated by the photodiode 101 to the floating diffusion 103 at the timing when a transfer pulse is supplied.

[0302] The floating diffusion 103 functions as a charge-voltage conversion unit that converts signal charge into a voltage signal. The drain and source of the reset transistor (Rst) 104 are connected to the pixel power supply of the power supply voltage Vdd and the floating diffusion 103, respectively. Before transferring the signal charge from the photodiode 101 to the floating diffusion 103, the reset transistor 104 applies a reset pulse RST to the gate and resets the voltage of the floating diffusion 103 to the reset voltage.

[0303] The gate and drain of the amplifier transistor (Amp) 105 are connected to the floating diffusion 103 and the pixel power supply of the power supply voltage Vdd, respectively. The amplifier transistor 105 outputs the voltage of the floating diffusion 103 reset by the reset transistor 104 as a reset level, and outputs the voltage of the floating diffusion 103 after the signal charge is transferred by the transfer transistor 102 as a signal level.

[0304] A combination of the amplification transistor 105 and the load MOS 121 provided on the lower substrate 11 functions as a source follower, and transmits an analog signal representing the voltage of the floating diffusion 103 to the comparator 51 of the lower substrate 11 .

[0305] The comparator 51 may include a differential amplifier circuit. The comparator 51 includes: a differential transistor pair unit including transistors 141 and 144; a load transistor pair unit including transistors 142 and 143 serving as an output load of the differential transistor pair unit and arranged on the power supply side; and a current source unit 145 that supplies a constant operating current and is arranged on the ground (GND) side.

[0306] The sources of the transistors 141 and 144 are commonly connected to the drain of the transistor of the current source unit 145. The drains of the corresponding transistors 142 and 143 of the load transistor pair unit are connected to the drains (output terminals) of the transistors 141 and 144.

[0307] The output of the differential transistor cell (the drain of transistor 144 in the illustrated example) is fully amplified by buffer 146 and then output to latch circuit 52 .

[0308] A pixel signal transmitted from the pixel 21 is supplied to the gate (input terminal) of the transistor 141 , and a ramp signal from the DAC 36 is supplied to the gate (input terminal) of the transistor 144 .

[0309] The latch circuit 52 includes ten latch columns 161-1 to 161-10. Codes D0 to D9 (hereinafter referred to as code values ​​D) are input to the latch columns 161-1 to 161-10, respectively. The code values ​​D0 to D9 are code values ​​indicating the current time.

[0310] Each latch column 161 is a dynamic circuit for miniaturization. In addition, the output from the comparator 51 is input to the gate of the transistor 171 for turning on and off each latch column 161. In this latch circuit 52, the code value when the output of the comparator 51 is inverted is held, and then the code value is read and output to the sense amplifier 33 ( Figure 28 ).

[0311] In this structure, the pixels 21 are arranged on the light receiving substrate 10, and the circuit is configured on the circuit substrate 11. The light receiving substrate 10 and the circuit substrate 11 can be bonded to each other by, for example, Cu-Cu bonding. For Cu-Cu bonding, the technology disclosed in Japanese Patent Application Laid-Open No. 2011-54637, previously filed by the present applicant, can be used.

[0312] In the eleventh embodiment of the present invention, since AD ​​conversion is performed for each region as described above, the reading speed of image data can be increased compared with the first embodiment in which AD conversion is performed for each column.

[0313] <12. Twelfth Implementation Plan>

[0314] In the first embodiment described above, the solid-state imaging device 200 has a two-layer stacked structure in which the circuit is arranged on the light receiving substrate 201 and the circuit substrate 202. However, the solid-state imaging device 200 may have a three-layer stacked structure. The solid-state imaging device 200 according to the twelfth embodiment differs from the solid-state imaging device according to the first embodiment in that the solid-state imaging device 200 has a three-layer stacked structure.

[0315] Figure 321 is an example of a cross-sectional view of a solid-state imaging device 200 according to a twelfth embodiment of the present invention. In the twelfth embodiment, a memory substrate 203 is interposed between a light receiving substrate 201 and a circuit substrate 202. Dummy pads and electrode pads are used for Cu-Cu connections between the light receiving substrate 201 and the memory substrate 203. A memory for storing image data is also arranged on the memory substrate 203.

[0316] As described above, in the twelfth embodiment of the present invention, the three-layer stacked structure is applied.

[0317] <13. Thirteenth Implementation Plan>

[0318] In the first embodiment described above, the solid-state imaging device 200 has a two-layer stacked structure in which the circuit is arranged on the light receiving substrate 201 and the circuit substrate 202. However, the solid-state imaging device 200 may have a three-layer stacked structure. The solid-state imaging device 200 according to the thirteenth embodiment differs from the solid-state imaging device according to the first embodiment in that the solid-state imaging device 200 has a three-layer stacked structure.

[0319] Figure 33 is an example of a cross-sectional view of a solid-state imaging device 200 according to the thirteenth embodiment of the present invention. In the thirteenth embodiment, a pixel substrate 204 is inserted between a light receiving substrate 201 and a circuit substrate 202. Dummy pads and electrode pads are used for Cu-Cu connection between the pixel substrate 204 and the circuit substrate 202. In addition, a photodiode and an optical system (such as a photodiode 415, a color filter 413, and an on-chip lens 411) above the photodiode are arranged on the light receiving substrate 201. The photodiode is connected to the circuit substrate 202 by a plurality of channels. Figure 33 The wiring shown is connected to transistors and the like.

[0320] As described above, in the thirteenth embodiment of the present invention, the three-layer structure is applied.

[0321] <14. Fourteenth Implementation Plan>

[0322] In the first embodiment described above, only one vertical drive circuit is arranged in the solid-state imaging device 200. However, more vertical drive circuits may be arranged. The solid-state imaging device 200 according to the fourteenth embodiment of the present invention differs from the solid-state imaging device according to the first embodiment in that a plurality of vertical drive circuits are arranged.

[0323] Figure 341 is an example of a perspective view of a solid-state imaging device 200 according to a fourteenth embodiment of the present invention. In the circuit substrate 202 of the fourteenth embodiment, vertical drive circuits 211 to 214, a plurality of AD units 243, and a plurality of storage units 244 are arranged. In addition, the AD unit 243 and the storage unit 244 form a pair of circuit components. Figure 34 As shown, the storage unit 244-a and the AD unit 243-a form a circuit component pair. Similarly, the adjacent circuit component pair includes the AD unit 243-b and the storage unit 244-b. Since the vertical signal line VSL needs to be connected to the AD unit 243 first and then to the storage unit 244, the storage unit 244-a and the AD unit 243-a are reversed in the adjacent circuit component pair (i.e., the AD unit 243-b and the storage unit 244-b). Figure 36 、 38 The same structure is also applicable to the AD unit 243 and the storage unit 244 shown in FIG. 39. In the fourteenth embodiment, other circuit components such as a control circuit or a processing circuit (not shown) may be arranged in the circuit substrate 202. In addition, the surface between the light receiving substrate 201 and the circuit substrate 202 represents a joint surface. The plan view of the joint surface is similar to Figure 4 Floor plan shown.

[0324] A predetermined number of ADCs are provided in the AD unit 243. A predetermined number of memories for holding digital signals from the AD unit 243 are provided in the memory unit 244. As the memory, an SRAM (Static Random Access Memory) or the like is used.

[0325] like Figure 34 As shown, by arranging the VSL bonding region 314 at the center of the solid-state imaging device 200, the capacitance difference between the end and the center can be reduced, and the appearance of shadows can be suppressed. Furthermore, fluctuations in device characteristics can be suppressed. Furthermore, by increasing the number of vertical drive circuits to four, high-speed and complex driving can be performed.

[0326] Figure 35 14 is a plan view showing another example of the bonding surface of the light receiving substrate 201 in the fourteenth embodiment of the present invention. Figure 35 As shown, the VSL bonding regions 314 and 315 may be disposed at the center, and the dummy region 323 may be disposed between the VSL bonding regions 314 and 315 .

[0327] Figure 36 corresponds to Figure 35 Stereoscopic image.

[0328] Figure 3714 is a plan view showing another example of the bonding surface of the light receiving substrate 201 in the fourteenth embodiment of the present invention. Figure 37 As shown, you can Figure 35 Each region in the dummy region 321-1 is divided into two. For example, the dummy region 321-1, the VSL bonding region 314-1, the dummy region 323-1, the VSL bonding region 315-1, and the dummy region 322-1 can be arranged in the order described between the drive line bonding regions 311-1 and 311-2. In addition, the dummy region 321-2, the VSL bonding region 314-2, the dummy region 323-2, the VSL bonding region 315-2, and the dummy region 322-2 can be arranged in the order described between the drive line bonding regions 312-1 and 312-2.

[0329] Figure 38 corresponds to Figure 37 Stereoscopic image.

[0330] Figure 39 FIG is another example of a perspective view of a solid-state imaging device according to a fourteenth embodiment of the present invention. Figure 39 As shown, two vertical driving circuits can also be configured.

[0331] Now, a supplementary description will be given of the bonding surface on which the dummy pads in the first embodiment are arranged. Figure 40A and Figure 40B They are enlarged views showing examples of the vicinity of the bonding surface on which the dummy pad is arranged in the embodiment of the present invention and in the comparative example, respectively. Figure 40A It is an enlarged view showing an example of the vicinity of the joining surface in the first embodiment of the present invention. Figure 40B : is an enlarged view showing an example of the vicinity of the joint surface in the comparative example. Figure 40A As shown, similarly to the electrode pads, the dummy pads are also formed by breaking through the SiN film 471. This also applies to the second embodiment and subsequent embodiments.

[0332] As described above, in the fourteenth embodiment of the present invention, since the vertical driving circuits 211 to 214 are arranged, high-speed driving and complicated driving can be performed.

[0333] <15. Fifteenth Implementation Plan>

[0334] In the first embodiment described above, the electrode pads are arranged in the pixel array unit 250. However, the electrode pads may be arranged in a region outside the pixel array unit 250. The fifteenth embodiment differs from the first embodiment in that the electrode pads are also arranged in a region outside the pixel array unit 250.

[0335] Figure 411 is an example of a cross-sectional view of a solid-state imaging device 200 according to a fifteenth embodiment of the present invention. In the solid-state imaging device 200 according to the fifteenth embodiment, electrode pads 431 and 432 are also arranged in a region outside the pixel array unit 250. For example, a signal line can be drawn from the pixel array unit 250 to a region for wiring outside the pixel array unit 250.

[0336] As described above, in the fifteenth embodiment of the present invention, electrode pads are also arranged in the region other than the pixel array unit 250 .

[0337] <16. Sixteenth Implementation Plan>

[0338] In the first embodiment described above, the solid-state imaging device 200 has a two-layer stacked structure in which the circuit is arranged in the light receiving substrate 201 and the circuit substrate 202. However, the solid-state imaging device 200 may also have a three-layer stacked structure. The solid-state imaging device 200 according to the sixteenth embodiment differs from the solid-state imaging device according to the first embodiment in that it has a three-layer stacked structure.

[0339] Figure 42 16 is an example of a cross-sectional view of a solid-state imaging device 200 according to a sixteenth embodiment of the present invention. In the sixteenth embodiment, a memory substrate 203 is interposed between a light receiving substrate 201 and a circuit substrate 202. Figure 42 As shown, the substrates are connected to each other through Cu-Cu bonding and TSVs (Through Silicon Vias). For example, the light receiving substrate 201 and the memory substrate 203 are bonded to each other through Cu-Cu bonding. The circuit substrate 202 and the light receiving substrate 201 are connected through TSVs 481, and the circuit substrate 202 and the memory substrate 203 are connected through TSVs 482.

[0340] Figure 43 16 is another example of a cross-sectional view of the solid-state imaging device 200 according to the sixteenth embodiment of the present invention. Figure 43 As shown, substrates can be bonded to each other only by Cu-Cu bonding without TSVs.

[0341] As described above, in the sixteenth embodiment of the present invention, a three-layer stacked structure is applied and substrates are connected to each other through TSV or the like.

[0342] <17. Application Examples of Mobile Objects>

[0343] The technology according to the present invention (the present technology) can be applied to various products. For example, the technology according to the present invention can be implemented as a device installed on any type of mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobile device, an airplane, an unmanned aerial vehicle, a ship, and a robot.

[0344] Figure 44 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present invention can be applied.

[0345] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 44 In the illustrated example, vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, as a functional configuration of integrated control unit 12050, a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated.

[0346] Drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, drive system control unit 12010 functions as a control device for the following devices: a drive force generating device, such as an internal combustion engine or a drive motor, that generates the vehicle's drive force; a drive force transmission mechanism that transmits the drive force to the wheels; a steering mechanism that adjusts the vehicle's steering angle; and a braking device that generates the vehicle's braking force.

[0347] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, or various lights such as headlights, backup lights, brake lights, turn signals, and fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a mobile device that replaces a key, or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door locks, power windows, lights, and the like.

[0348] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 can detect objects such as people, vehicles, obstacles, signs, and characters on the road surface, or detect the distance to such objects.

[0349] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as information about the measured distance. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0350] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 that detects the driver's condition. For example, the driver status detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or determine whether the driver is dozing off.

[0351] The microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on information about the interior or exterior of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, following driving based on following distance, speed maintenance driving, vehicle collision warning, and vehicle lane departure warning.

[0352] In addition, by controlling the driving force generating device, steering mechanism, or braking device, etc. based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, the microcomputer 12051 is able to perform collaborative control aimed at achieving automatic driving, etc., wherein the automatic driving enables the vehicle to travel autonomously without relying on the driver's operation.

[0353] Furthermore, based on the information about the exterior of the vehicle acquired by the exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam, for example, based on the position of a preceding vehicle or an oncoming vehicle detected by the exterior information detection unit 12030.

[0354] The audio and video output unit 12052 transmits an output signal of at least one of audio and video to an output device capable of visually or auditorily notifying the passengers of the vehicle or the outside of the vehicle. Figure 44 In the example of FIG, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0355] Figure 45 It is a schematic diagram illustrating an example of the installation position of the imaging unit 12031.

[0356] exist Figure 45 , the imaging unit 12031 includes an imaging unit 12101 , an imaging unit 12102 , an imaging unit 12103 , an imaging unit 12104 and an imaging unit 12105 .

[0357] Imaging units 12101, 12102, 12103, 12104, and 12105 are located, for example, on the front nose, side mirrors, rear bumper, and rear doors of vehicle 12100, as well as on the upper portion of the windshield inside the vehicle. Imaging unit 12101 located on the front nose and imaging unit 12105 located on the upper portion of the windshield inside the vehicle primarily capture images of the front of vehicle 12100. Imaging units 12102 and 12103 located on the side mirrors primarily capture images of both sides of vehicle 12100. Imaging unit 12104 located on the rear bumper or rear door primarily captures images of the rear of vehicle 12100. Imaging unit 12105 located on the upper portion of the windshield inside the vehicle primarily detects vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0358] By the way, Figure 45Examples of the imaging ranges of imaging units 12101 through 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, located at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located at the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, located at the rear bumper or rear door. For example, a bird's-eye view image of vehicle 12100 viewed from above can be obtained by superimposing image data captured by imaging units 12101 through 12104.

[0359] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0360] For example, based on the distance information acquired from imaging units 12101 to 12104, microcomputer 12051 can determine the distances of various three-dimensional objects within imaging ranges 12111 to 12114 and the temporal changes in these distances (relative speed to vehicle 12100), thereby extracting the closest three-dimensional object, particularly one on the travel path of vehicle 12100 and traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h), as the leading vehicle. Furthermore, microcomputer 12051 can pre-set a following distance to maintain ahead of the leading vehicle and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Consequently, it is possible to perform coordinated control such as autonomous driving, which aims to enable the vehicle to travel autonomously without relying on driver input.

[0361] For example, based on the distance information acquired from imaging units 12101 and 12104, microcomputer 12501 can classify 3D object data regarding 3D objects into 3D object data for two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other 3D objects, extract the classified 3D object data, and use the extracted 3D object data for automatic obstacle avoidance. For example, microcomputer 12051 classifies obstacles around vehicle 12100 into those that are visually recognizable by the driver of vehicle 12100 and those that are difficult for the driver of vehicle 12100 to visually recognize. Microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is equal to or greater than a set value, and therefore a collision is possible, microcomputer 12051 issues a warning to the driver via audio speaker 12061 or display unit 12062, and the drive system control unit 12010 executes forced deceleration or evasive steering. Microcomputer 12051 can thus assist in driving to avoid collisions.

[0362] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether a pedestrian exists in images captured by the imaging units 12101 to 12104. For example, this identification of a pedestrian may be performed by extracting feature points from images captured by the imaging units 12101 to 12104, which are infrared cameras; and performing pattern matching on a series of feature points representing the outline of an object to determine whether the pedestrian is a pedestrian. If the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio and video output unit 12052 controls the display unit 12062 to display a square outline superimposed on the identified pedestrian for emphasis. Furthermore, the audio and video output unit 12052 may control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0363] An example of a vehicle control system to which the technology according to the present invention can be applied has been described above. The technology according to the present invention can be applied to the imaging unit 12031 of the above-mentioned structure, for example. Specifically, Figure 1 The imaging system 100 shown in FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present invention to the imaging unit 12031, it is possible to reduce noise caused by dark current to generate an image that is easier to view. Therefore, it is possible to reduce the fatigue of the driver.

[0364] Note that the above embodiments each illustrate examples for implementing the present technology, and that the subject matter in the embodiments corresponds to the inventions defined in the claims. Similarly, the inventions defined in the claims and the subject matter with the same names as these in the embodiments correspond to each other. However, the present technology is not limited to the embodiments described, and can be implemented by making various modifications to the embodiments without departing from the essence of the present technology.

[0365] It should be noted that the effects described herein are merely examples and are not restrictive, and other effects may be produced.

[0366] It should be noted that the present technology can adopt the following configurations.

[0367] (1) A solid-state imaging device comprising:

[0368] a first semiconductor substrate including a plurality of photoelectric conversion units and a first wiring layer; and

[0369] a second semiconductor substrate including a second wiring layer and a signal processing circuit;

[0370] The first wiring layer includes a first electrode pad, a first through-hole connected to the first electrode pad, and a second electrode pad,

[0371] The second wiring layer includes a third electrode pad, a fourth electrode pad, and a second through-hole connected to the third electrode pad.

[0372] the first wiring layer or the second wiring layer includes a third through hole connected to one of the second electrode pad and the fourth electrode pad,

[0373] A portion of the first electrode pad and a portion of the third electrode pad are bonded to each other,

[0374] a portion of the second electrode pad and a portion of the fourth electrode pad are joined to each other,

[0375] A pixel signal generated by at least one of the plurality of photoelectric conversion units is transmitted to the signal processing circuit via the first through-hole, the first electrode pad, the third electrode pad, and the second through-hole,

[0376] The second electrode pad or the fourth electrode pad connected to the third through-hole is electrically connected to an arbitrary potential through the third through-hole.

[0377] (2) The solid-state imaging device according to (1) above, wherein

[0378] The first semiconductor substrate further includes a transfer transistor and a floating diffusion.

[0379] (3) The solid-state imaging device according to (2) above, wherein

[0380] The first semiconductor substrate further includes a reset transistor and an amplifying transistor.

[0381] (4) The solid-state imaging device according to any one of (1) to (3) above, wherein:

[0382] The signal processing circuit includes an analog-to-digital signal conversion circuit.

[0383] (5) The solid-state imaging device according to any one of (1) to (4) above, wherein:

[0384] The first wiring layer includes a third through hole for connecting to the second electrode pad, and

[0385] The second wiring layer includes a fourth through hole for connecting to the fourth electrode pad.

[0386] (6) A solid-state imaging device comprising:

[0387] a plurality of first circuits provided on a first semiconductor substrate bonded to a second semiconductor substrate at a bonding surface including atoms terminating dangling bonds of silicon;

[0388] a second circuit disposed on the second semiconductor substrate;

[0389] a first through hole connecting a portion of the plurality of first circuits and a predetermined bonding area on the bonding surface to each other;

[0390] a second through-hole connecting the second circuit and the bonding area; and

[0391] A third through hole connects the other first circuit and a dummy region, which is a region on the bonding surface different from the bonding region, to each other.

[0392] (7) The solid-state imaging device according to (6) above, wherein

[0393] The electrode pad is arranged on the bonding area,

[0394] The dummy pad is configured on the dummy area.

[0395] The first through hole connects a portion of the plurality of first circuits and the bonding area through the electrode pad, and

[0396] The third through hole connects the other first circuits and the dummy area through the dummy pad.

[0397] (8) The solid-state imaging device according to (7) above, wherein

[0398] A predetermined number of the first through holes are connected to the electrode pad, and the third through holes include a third through hole connected to the dummy pad, the number of the third through holes connected to the pad being different from the predetermined number.

[0399] (9) The solid-state imaging device according to (7) above, wherein

[0400] A predetermined number of the first through holes are connected to the electrode pad, and the third through holes include a third through hole connected to the dummy pad, the number of the third through holes connected to the pad being the predetermined number.

[0401] (10) The solid-state imaging device according to (7) above, wherein

[0402] The dummy pads include a first dummy pad not connected to the third through hole, and a second dummy pad connected to the third through hole.

[0403] (11) The solid-state imaging device according to (7) above, wherein

[0404] The dummy pads include a first dummy pad and a second dummy pad connected to different numbers of the third through holes.

[0405] (12) The solid-state imaging device according to any one of (7) to (11) above, wherein:

[0406] A cross-sectional area of ​​the third through hole is different from a cross-sectional area of ​​the first through hole.

[0407] (13) The solid-state imaging device according to any one of (7) to (12) above, wherein:

[0408] Each of the first through-hole and the third through-hole has a circular cross-sectional shape or a rectangular cross-sectional shape.

[0409] (14) The solid-state imaging device according to any one of (7) to (13) above, wherein:

[0410] The third via connects the other first circuits and the dummy region to each other through a predetermined medium carrying atoms and the dummy pad.

[0411] (15) The solid-state imaging device according to any one of (7) to (14) above, wherein:

[0412] Each of the plurality of first circuits is a pixel circuit that generates a predetermined pixel signal,

[0413] The second circuit processes the pixel signal, and

[0414] The first semiconductor substrate is a light receiving substrate.

[0415] (16) The solid-state imaging device according to (15) above, further comprising:

[0416] The fourth through hole,

[0417] The second semiconductor substrate is a circuit substrate,

[0418] The dummy pads include light-receiving-side dummy pads arranged on the light-receiving substrate and circuit-side dummy pads arranged on the circuit substrate.

[0419] The third through hole is connected to the light receiving side dummy pad, and

[0420] The fourth through hole is connected to the circuit-side dummy pad.

[0421] (17) The solid-state imaging device according to (6) above, wherein

[0422] The second circuit is a pixel circuit that generates a predetermined pixel signal,

[0423] Each of the plurality of first circuits processes the pixel signal, and

[0424] The first semiconductor substrate is a circuit substrate.

[0425] (18) The solid-state imaging device according to (6) above, further comprising:

[0426] a fourth through hole connected to the third through hole without passing through a dummy pad,

[0427] The first through hole and the second through hole are connected to each other without passing through the electrode pad.

[0428] (19) The solid-state imaging device according to (6) above, further comprising:

[0429] a silicon nitride film formed on the bonding region and the dummy region;

[0430] an electrode pad penetrating the silicon nitride film formed in the bonding region; and

[0431] A dummy pad penetrates the silicon nitride film formed in the dummy region.

[0432] (20) An imaging system comprising:

[0433] a plurality of first circuits provided on a first semiconductor substrate bonded to a second semiconductor substrate at a bonding surface including atoms terminating dangling bonds of silicon;

[0434] a second circuit disposed on the second semiconductor substrate;

[0435] a first through hole connecting a portion of the plurality of first circuits and a predetermined bonding area on the bonding surface to each other;

[0436] a second through hole connecting the second circuit and the bonding area;

[0437] a third through hole connecting the other first circuit and a dummy region to each other, the dummy region being a region on the bonding surface different from the bonding region; and

[0438] A signal processing circuit performs predetermined signal processing on the signal generated by the second circuit.

[0439] (21) An image sensor comprising:

[0440] a first substrate comprising a plurality of pixels, a plurality of vertical signal lines, and a plurality of first wiring layers, wherein the plurality of first wiring layers are located on one side of the first substrate;

[0441] The second substrate includes a plurality of second wiring layers, wherein the plurality of second wiring layers are located on one side of the second substrate.

[0442] wherein the first substrate and the second substrate are fixed together between the plurality of first wiring layers and the plurality of second wiring layers;

[0443] a first pad provided between one of the plurality of first wiring layers and one of the plurality of second wiring layers;

[0444] a second pad provided between another first wiring layer among the plurality of first wiring layers and another second wiring layer among the plurality of second wiring layers;

[0445] a first through hole connecting the one first wiring layer among the plurality of first wiring layers and the first pad provided on the first substrate;

[0446] a second through hole connecting the one second wiring layer among the plurality of second wiring layers and the first pad provided on the second substrate;

[0447] wherein the first pad disposed on the first substrate and the first pad disposed on the second substrate are connected to each other;

[0448] a third through hole connecting the other first wiring layer among the plurality of first wiring layers; and

[0449] a fourth through hole connecting the other second wiring layer among the plurality of second wiring layers,

[0450] wherein at least one of the third through hole and the fourth through hole connects the second pad to at least one of the other first wiring layer among the plurality of first wiring layers and the other second wiring layer among the plurality of second wiring layers;

[0451] wherein the first pad provides electrical connection between the one of the plurality of first wiring layers and the one of the plurality of second wiring layers, and the first pad is electrically connected to one of the plurality of vertical drive lines, and

[0452] The second pad is not electrically connected to the plurality of vertical signal lines.

[0453] (22) The image sensor according to (21) above, wherein the first substrate further includes a pixel circuit and the second substrate further includes a subsequent circuit.

[0454] (23) The image sensor according to (22) above, wherein a pixel signal from the pixel circuit is transmitted from the pixel circuit to the subsequent circuit.

[0455] (24) The image sensor according to any one of (21) to (22) above, wherein the dummy pad is electrically floating.

[0456] (25) The image sensor according to any one of (21) to (22) above, wherein the dummy pad is connected to a fixed potential.

[0457] (26) The image sensor according to any one of (21) to (22) above, wherein the first pad is an electrode pad and the second pad is a dummy pad.

[0458] (27) The image sensor according to any one of (21) to (26) above, wherein the number of the first through holes and the second through holes is equal to the number of the third through holes and the fourth through holes.

[0459] (28) The image sensor according to any one of (21) to (26) above, wherein the number of the first through holes and the second through holes is greater than the number of the third through holes and the fourth through holes.

[0460] (29) The image sensor according to any one of (21) to (26) above, wherein the number of the first through holes and the second through holes is smaller than the number of the third through holes and the fourth through holes.

[0461] (30) An image sensor according to any one of (21) to (26) above, wherein the third through hole and the fourth through hole connect the second pad to the other first wiring layer among the multiple first wiring layers and the other second wiring layer among the multiple second wiring layers.

[0462] (31) The image sensor according to any one of (21) to (26) above, wherein:

[0463] The third through hole connects the second pad and the other first wiring layer among the plurality of first wiring layers.

[0464] (32) The image sensor according to any one of (21) to (26) above, wherein the sizes of the first through hole and the second through hole are different from the sizes of the third through hole and the fourth through hole.

[0465] (33) An image sensor according to any one of (21) to (32) above, wherein the cross-sectional shape of the first through hole, the second through hole, the third through hole, and the fourth through hole is rectangular, circular, or elliptical.

[0466] (34) The image sensor according to any one of (21) to (26) above, wherein the number of the third through holes is different from the number of the fourth through holes.

[0467] (35) An image sensor comprising:

[0468] a first substrate;

[0469] a second substrate disposed below the first substrate,

[0470] The first substrate includes a first bonding area and a second bonding area, the first bonding area includes an electrode pad, and the second bonding area includes a dummy pad;

[0471] a plurality of first through holes extending from the first bonding area of ​​the first substrate and connected to the electrode pads; and

[0472] a plurality of second through-holes extending from the second bonding area of ​​the first substrate and connected to the dummy pads;

[0473] The number of the first through holes is greater than the number of the second through holes.

[0474] (36) The image sensor according to (35) above, wherein the electrode pad provides electrical connection between the first substrate and the second substrate.

[0475] (37) The image sensor according to any one of (35) to (36) above, wherein the electrode pad is provided in the first bonding region.

[0476] (38) The image sensor according to any one of (35) to (37) above, wherein the dummy pad is provided in the second bonding region.

[0477] (39) The image sensor according to any one of (35) to (38) above, wherein the dummy pad is electrically floating.

[0478] (40) The image sensor according to any one of (35) to (38) above, wherein the dummy pad is connected to a fixed potential.

[0479] (41) An image sensor comprising:

[0480] a first substrate;

[0481] a second substrate disposed below the first substrate,

[0482] The first substrate includes a pair of first bonding areas and at least one second bonding area, the pair of first bonding areas include electrode pads, and the at least one second bonding area is disposed between the pair of first bonding areas and includes a dummy pad;

[0483] a plurality of first through holes extending from the pair of first bonding regions of the first substrate and connected to the electrode pads; and

[0484] A plurality of second through-holes extend from the at least one second bonding region of the first substrate and are connected to the dummy pads.

[0485] (42) The image sensor according to (41) above, wherein the at least one second bonding region is provided in a central portion of the first substrate.

[0486] (43) The image sensor according to any one of (41) to (42) above further includes another second bonding area arranged above one of the pair of first bonding areas and another second bonding area arranged below the other of the pair of first bonding areas.

[0487] (44) The image sensor according to any one of (41) to (43) above, wherein the second substrate includes a plurality of pairs of circuit components.

[0488] (45) The image sensor according to (44) above, wherein the plurality of pairs of circuit components are arranged so that the first circuit component and the second circuit component in one pair are reversed in order in another adjacent pair of circuit components.

[0489] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may occur within the scope of the appended claims or the equivalents thereof depending on design requirements and other factors.

[0490] Reference Signs List

[0491] 100 Imaging System

[0492] 110 optical unit

[0493] 120 DSP circuit

[0494] 130 display units

[0495] 140 operating units

[0496] 150 bus

[0497] 160 frame memory

[0498] 170 storage units

[0499] 180 Power Supply Unit

[0500] 200 Solid-state imaging device

[0501] 201 light receiving substrate

[0502] 202 circuit board

[0503] 210 vertical drive circuit

[0504] 220 Timing Control Circuit

[0505] 231 North horizontal drive circuit

[0506] 232 South horizontal drive circuit

[0507] 241 North column signal processing circuit

[0508] 242 South column signal processing circuit

[0509] 250 pixel array unit

[0510] 260 pixel circuit

[0511] 261 Photoelectric conversion devices

[0512] 262 pass transistor

[0513] 263 Reset transistor

[0514] 264 floating diffusion layer

[0515] 265 Amplifier Transistor

[0516] 266 Select transistor

[0517] 270 Power Circuit

[0518] 280 output units

[0519] 311, 312, 311-1, 311-2, 312-1, 312-2 driving line bonding area

[0520] 313, 316 Power line connection area

[0521] 314, 315, 314-1, 314-2, 315-1, 315-2 VSL junction area

[0522] 321 to 323, 321-1, 321-2, 322-1, 322-2, 323-1, 323-2 Dummy areas

[0523] 411, 412 On-chip lens

[0524] 413, 414 color filters

[0525] 415, 416 photodiodes

[0526] 417, 418, 455, 456 transistors

[0527] 420 wiring layer

[0528] 421, 422, 451, 452 metal wiring

[0529] 423, 424, 453, 454 through holes

[0530] 425 cavity

[0531] 431, 432 electrode pads

[0532] 441 to 446 dummy pads

[0533] 450 wiring layer

[0534] 461, 462 Subsequent circuits

[0535] 471, 472 SiN (silicon nitride) film

[0536] 12031 Imaging Department

Claims

1. An image sensor, comprising: a first substrate comprising a plurality of pixels, a plurality of vertical signal lines, and a plurality of first wiring layers, wherein the plurality of first wiring layers are located on one side of the first substrate; The second substrate includes a plurality of second wiring layers, wherein the plurality of second wiring layers are located on one side of the second substrate. wherein the first substrate and the second substrate are fixed together between the plurality of first wiring layers and the plurality of second wiring layers; a first pad provided between one of the plurality of first wiring layers and one of the plurality of second wiring layers; a second pad provided between another first wiring layer among the plurality of first wiring layers and another second wiring layer among the plurality of second wiring layers; a first through hole connecting the one first wiring layer among the plurality of first wiring layers and the first pad provided on the first substrate; a second through hole connecting the one second wiring layer among the plurality of second wiring layers and the first pad provided on the second substrate; wherein the first pad disposed on the first substrate and the first pad disposed on the second substrate are connected to each other; a third through hole connecting the other first wiring layer among the plurality of first wiring layers; and a fourth through hole connecting the other second wiring layer among the plurality of second wiring layers, wherein at least one of the third through hole and the fourth through hole connects the second pad to at least one of the other first wiring layer among the plurality of first wiring layers and the other second wiring layer among the plurality of second wiring layers; wherein the first pad provides electrical connection between the first wiring layer in the plurality of first wiring layers and the second wiring layer in the plurality of second wiring layers, and the first pad is electrically connected to a vertical driving line in the plurality of vertical driving lines, wherein the second pad is not electrically connected to the plurality of vertical signal lines, and The first pad and the second pad are formed by penetrating a SiN film formed on a bonding surface of the first substrate and the second substrate.

2. The image sensor according to claim 1, wherein The first substrate further includes pixel circuitry and the second substrate further includes subsequent circuitry.

3. The image sensor according to claim 2, wherein: A pixel signal from the pixel circuit is transmitted from the pixel circuit to the subsequent circuit.

4. The image sensor according to any one of claims 1 to 3, wherein: The second pad is electrically floating.

5. The image sensor according to any one of claims 1 to 3, wherein: The second pad is connected to a fixed potential.

6. The image sensor according to any one of claims 1 to 3, wherein: The first pad is an electrode pad and the second pad is a dummy pad.

7. The image sensor according to any one of claims 1 to 3, wherein: The number of the first through holes and the second through holes is equal to the number of the third through holes and the fourth through holes.

8. The image sensor according to any one of claims 1 to 3, wherein: The number of the first through holes and the second through holes is greater than the number of the third through holes and the fourth through holes.

9. The image sensor according to any one of claims 1 to 3, wherein: The number of the first through holes and the second through holes is smaller than the number of the third through holes and the fourth through holes.

10. The image sensor according to any one of claims 1 to 3, wherein: The third through hole and the fourth through hole connect the second pad with the other first wiring layer among the plurality of first wiring layers and the other second wiring layer among the plurality of second wiring layers.

11. The image sensor according to any one of claims 1 to 3, wherein: The third through hole connects the second pad and the other first wiring layer among the plurality of first wiring layers.

12. The image sensor according to any one of claims 1 to 3, wherein: The sizes of the first through hole and the second through hole are different from the sizes of the third through hole and the fourth through hole.

13. The image sensor according to any one of claims 1 to 3, wherein: The cross-sectional shapes of the first through hole, the second through hole, the third through hole and the fourth through hole are rectangular, circular or elliptical.

14. The image sensor according to any one of claims 1 to 3, wherein: The number of the third through holes is different from the number of the fourth through holes.

15. An image sensor comprising: a first substrate; a second substrate disposed below the first substrate, The first substrate includes a first bonding area and a second bonding area, the first bonding area includes an electrode pad, and the second bonding area includes a dummy pad; a plurality of first through holes extending from the first bonding area of ​​the first substrate and connected to the electrode pads; and a plurality of second through-holes extending from the second bonding area of ​​the first substrate and connected to the dummy pads; wherein the number of the plurality of first through holes is greater than the number of the plurality of second through holes, The electrode pads and the dummy pads are formed by penetrating a SiN film formed on a bonding surface of the first substrate and the second substrate.

16. The image sensor according to claim 15, wherein: The electrode pad provides electrical connection between the first substrate and the second substrate.

17. The image sensor according to claim 15, wherein: The electrode pad is disposed in the first bonding region.

18. The image sensor according to claim 15, wherein: The dummy pad is disposed in the second bonding region.

19. The image sensor according to any one of claims 15 to 18, wherein: The dummy pad is electrically floating.

20. The image sensor according to any one of claims 15 to 18, wherein: The dummy pad is connected to a fixed potential.

21. An image sensor comprising: a first substrate; a second substrate disposed below the first substrate, The first substrate includes a pair of first bonding areas and at least one second bonding area, the pair of first bonding areas include electrode pads, and the at least one second bonding area is disposed between the pair of first bonding areas and includes a dummy pad; a plurality of first through holes extending from the pair of first bonding regions of the first substrate and connected to the electrode pads; and a plurality of second through holes extending from the at least one second bonding area of ​​the first substrate and connected to the dummy pads, The electrode pads and the dummy pads are formed by penetrating a SiN film formed on a bonding surface of the first substrate and the second substrate.

22. The image sensor according to claim 21, wherein The at least one second bonding region is disposed at a central portion of the first substrate. 23 . The image sensor according to claim 21 , further comprising another second bonding region disposed above one of the pair of first bonding regions and still another second bonding region disposed below the other of the pair of first bonding regions.

24. The image sensor according to any one of claims 21 to 23, wherein: The second substrate includes a plurality of pairs of circuit components.

25. The image sensor according to claim 24, wherein The pairs of circuit assemblies are arranged such that the first circuit assembly and the second circuit assembly in one pair are reversed in order in another adjacent pair of circuit assemblies.

Images