Method of manufacturing a semiconductor device

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device. After forming a MISFET on a substrate including a semiconductor substrate, an insulating layer, and a semiconductor layer, an interlayer insulating film and a first insulating film are formed on the substrate. Also, after forming an opening in each of the first insulating film and the interlayer insulating film, a second insulating film is formed at each of a bottom of the opening and a side surface of the opening, and also on an upper surface of the first insulating film. Furthermore, each of the second insulating film formed at the bottom of the opening and the second insulating film formed on the upper surface of the first insulating film is removed by etching. Thereafter, the inside of the opening is etched under a condition that each of the first insulating film and the second insulating film is etched less than the insulating layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a method of manufacturing a semiconductor device, and the present application can be appropriately applied to a method of manufacturing a semiconductor device using, for example, an SOI substrate.

[0002] BACKGROUND To manufacture a semiconductor device, after a semiconductor element such as an MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on a semiconductor substrate, a multilayer wiring structure including a plurality of interlayer insulating films and a plurality of wiring layers is formed on the semiconductor substrate. There is a technique of using an SOI substrate as a semiconductor substrate.

[0003] The disclosed technology is listed below.

[0004] [Patent Literature 1] Japanese Unexamined Patent Application Publication No. 2013-219181

[0005] Patent Literature 1 discloses a technique relating to a semiconductor device using an SOI substrate. SUMMARY

[0006] It is desirable to improve the reliability of a semiconductor device manufactured by using an SOI substrate. It is also desirable to reduce the manufacturing cost of a semiconductor device manufactured by using an SOI substrate.

[0007] Other objects and novel features will become apparent from the description and drawings.

[0008] According to one embodiment, a method of manufacturing a semiconductor device includes the steps of: (a) providing a substrate including a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a semiconductor layer formed on the insulating layer, and a gate electrode formed on the semiconductor layer via a gate insulating film. Also, the method includes: (b) after the step (a), forming an epitaxial layer on the semiconductor layer located on both sides of the gate electrode by an epitaxial growth method. Also, the method includes: (c) after the step (b), forming a metal silicide layer in the epitaxial layer by silicidation of the epitaxial layer. Also, the method includes: (d) after the step (c), forming an interlayer insulating film on the substrate to cover the gate electrode and the metal silicide layer. Also, the method includes: (e) after the step (d), forming a first insulating film on the interlayer insulating film. Also, the method includes: (f) after the step (e), forming an opening at a portion of each of the first insulating film and the interlayer insulating film which overlaps with the metal silicide layer. Also, the method includes: (g) after the step (f), forming a second insulating film at each of a bottom of the opening and a side surface of the opening and on an upper surface of the first insulating film. Also, the method includes: (h) after the step (g), each of the second insulating film formed at the bottom of the opening and the second insulating film formed on the upper surface of the first insulating film is removed by etching. Also, the method includes: (i) after the step (h), etching inside the opening in a state where an upper surface of the interlayer insulating film is covered with the first insulating film and a side surface of the opening is covered with the second insulating film as a side surface of the interlayer insulating film. Also, the method includes: (j) after the step (i), forming a plug composed of a conductive material inside the opening. Further, the step (i) is performed under a condition where each of the first insulating film, the second insulating film, and the metal silicide layer is etched less than the insulating layer. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a process flow chart showing a part of a manufacturing process of a semiconductor device according to one embodiment;

[0010] Figure 2 is a cross-sectional view in a manufacturing process of a semiconductor device according to one embodiment;

[0011] Figure 3 is a cross-sectional view in a manufacturing process of a semiconductor device following Figure 2 ;

[0012] Figure 4 is a cross-sectional view in a manufacturing process of a semiconductor device following Figure 3 ;

[0013] Figure 5 is a cross-sectional view in a manufacturing process of a semiconductor device following Figure 4 ;

[0014] Figure 6 is a cross-sectional view of a semiconductor device manufacturing process next Figure 5

[0015] Figure 7 is a cross-sectional view of a semiconductor device manufacturing process next Figure 6

[0016] Figure 8 is a cross-sectional view of a semiconductor device manufacturing process next Figure 7

[0017] Figure 9 is a cross-sectional view of a semiconductor device manufacturing process next Figure 8

[0018] Figure 10 is a cross-sectional view of a semiconductor device manufacturing process next Figure 9

[0019] Figure 11 is a cross-sectional view of a semiconductor device manufacturing process next Figure 10

[0020] Figure 12 is a cross-sectional view of a semiconductor device manufacturing process next Figure 11

[0021] Figure 13 is a cross-sectional view of a semiconductor device manufacturing process next Figure 12

[0022] Figure 14 is a cross-sectional view of a semiconductor device manufacturing process next Figure 13

[0023] Figure 15 is a cross-sectional view of a semiconductor device manufacturing process next Figure 14

[0024] Figure 16 is a cross-sectional view of a semiconductor device manufacturing process next Figure 15

[0025] Figure 17 is a cross-sectional view of a semiconductor device manufacturing process next Figure 16

[0026] Figure 18 is a cross-sectional view of a semiconductor device manufacturing process next Figure 17

[0027] Figure 19 is a cross-sectional view of a semiconductor device manufacturing process next Figure 18 ​​​​​​​​​​​​​cross-sectional views in a manufacturing process of a semiconductor device;

[0028] Figure 20 are cross-sectional views in a manufacturing process of a semiconductor device; Figure 19

[0029] Figure 21 are cross-sectional views in a manufacturing process of a semiconductor device according to the inspection example;

[0030] Figure 22 are cross-sectional views in a manufacturing process of a semiconductor device; Figure 21

[0031] Figure 23 are cross-sectional views in a manufacturing process of a semiconductor device; Figure 22

[0032] Figure 24 are cross-sectional views in a manufacturing process of a semiconductor device; Figure 23

[0033] Figure 25 is a process flow diagram showing a part of a manufacturing process of a semiconductor device according to another embodiment;

[0034] Figure 26 are cross-sectional views in a manufacturing process of a semiconductor device according to another embodiment;

[0035] Figure 27 are cross-sectional views in a manufacturing process of a semiconductor device; Figure 26

[0036] Figure 28 are cross-sectional views in a manufacturing process of a semiconductor device. Figure 27 DETAILED DESCRIPTION

[0037] ​​​​​​In the following embodiments, when necessary, for the convenience, description will be made by being divided into a plurality of parts or embodiments, but unless specifically described, the following embodiments are not independent of each other, and one embodiment relates to a modified example, details, supplementary description, etc. of part or all of the other embodiments. In the following embodiments, the number of elements, etc. (including the number of elements, numerical values, amounts, ranges, etc.) are not limited to a specific number, but can be not less than or equal to the specific number, unless the number is specifically indicated and is fundamentally limited to the specific number. Furthermore, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not essential, unless specifically indicated and are fundamentally considered to be obviously necessary. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, etc., it is assumed that the shape, etc. are substantially similar or similar to the shape, etc., unless specifically indicated and are fundamentally considered to be obviously similar, etc. The above applies to numerical values and ranges as well.

[0038] Embodiments will be described in detail below based on each drawing. In all the drawings for explaining the embodiments, the members having the same function are denoted by the same reference numerals, and repetitive description thereof is omitted. In the following embodiments, description of the same or similar parts will not be repeated in principle unless specifically necessary.

[0039] In the drawings used in the embodiments, hatching can be omitted even in the case of a sectional view to make the drawing easier to see. Furthermore, even in the case of a plan view, hatching can be used to make the drawing easier to see.

[0040] (First Embodiment)

[0041] <Manufacturing Process of Semiconductor Device>

[0042] A manufacturing process of a semiconductor device of the present first embodiment will be described with reference to the drawings. Figure 1 is a process flow chart showing a part of the manufacturing process of the semiconductor device according to the present first embodiment. Figures 2 to 21 is a sectional view in the manufacturing process of the semiconductor device according to the present first embodiment. Figure 1 is Figures 13 to 19 is a process flow chart of the step shown in

[0043] First, as shown in Figure 2 , an SOI (SOI: Silicon on Insulator) substrate 1 is prepared (provided).

[0044] The SOI substrate 1 has a semiconductor substrate SB as a support substrate, an insulating layer (buried insulating film) BX formed on a main surface of the semiconductor substrate SB, and a semiconductor layer SM formed on an upper surface of the insulating layer BX.

[0045] The semiconductor substrate SB is a supporting substrate for the insulating layer BX and the structure above the insulating layer BX, but it is also a semiconductor substrate. The semiconductor substrate SB is preferably a single-crystal silicon substrate, and is made of, for example, p-type single-crystal silicon. For example, the semiconductor substrate SB can be formed from single-crystal silicon with a resistivity of about 1 Ωcm to 10 Ωcm. The thickness of the semiconductor substrate SB can be, for example, about 700 μm to 1000 μm. The insulating layer BX is preferably a silicon oxide film, and the thickness of the insulating layer BX can be, for example, about 10 nm to 30 nm. When the insulating layer BX is a silicon oxide film, the insulating layer BX can be considered as a BOX (buried oxide) layer. The semiconductor layer SM is made of single-crystal silicon, etc. For example, the semiconductor layer SM can be formed from single-crystal silicon with a resistivity of about 1 Ωcm to 10 Ωcm. The thickness of the semiconductor layer SM is thinner than the thickness of the supporting semiconductor substrate SB, and the thickness of the semiconductor layer SM can be, for example, about 20 nm to 50 nm. The SOI substrate 1 is formed from the semiconductor substrate SB, the insulating layer BX, and the semiconductor layer SM.

[0046] In SOI substrate 1, the main surface of semiconductor substrate SB that contacts insulating layer BX is called the upper surface of semiconductor substrate SB, and the main surface of semiconductor substrate SB opposite to the upper surface is called the rear surface of semiconductor substrate SB. In SOI substrate 1, the main surface of insulating layer BX on the side that contacts semiconductor substrate SB is called the lower surface of insulating layer BX, and the main surface of semiconductor layer SM on the side that contacts semiconductor layer SM is called the upper surface of insulating layer BX. The upper and lower surfaces of insulating layer BX are surfaces opposite to each other. The main surface of semiconductor layer SM on the side that contacts insulating layer BX is called the lower surface of semiconductor layer SM, and the main surface of semiconductor layer SM on the side opposite to the lower surface is called the upper surface of semiconductor layer SM.

[0047] Although SOI substrate 1 can be fabricated using methods such as SIMOX (a method of isolation by oxygen implantation), lamination, or smart lift-off processes, the fabrication method of SOI substrate 1 is not limited to these.

[0048] Next, as Figure 3 As shown, a device isolation region ST is formed. The device isolation region ST penetrates the semiconductor layer SM and the insulating layer BX to reach the semiconductor substrate SB, and the bottom surface of the device isolation region ST is located at the middle of the thickness of the semiconductor substrate SB. That is, the height of the bottom surface of the isolation region ST is lower than the height of the bottom surface of the insulating layer BX (the interface between the insulating layer BX and the semiconductor substrate SB).

[0049] The separation region ST can be formed, for example, by a shallow trench isolation method as described below. That is, a photoresist pattern (not shown) is formed on the upper surface of the semiconductor layer SM using a photolithography technique, and then the semiconductor layer SM, the insulating layer BX, and the semiconductor substrate SB are etched using the photoresist pattern as an etching mask, thereby forming a device separation trench TR. The trench TR can be formed by using the insulating film formed above the semiconductor layer SM as an etching mask. The trench TR penetrates the semiconductor layer SM and the insulating layer BX, the bottom surface of the trench TR reaches the semiconductor substrate SB, and the bottom surface of the trench TR is located in the middle of the thickness of the semiconductor substrate SB. Then, an insulating film (silicon oxide film) for forming the element separation region ST is formed on the SOI substrate 1 to fill the inside of the trench TR, and then the insulating film (insulating film for forming the element separation region ST) outside the trench TR is removed by using a chemical mechanical polishing (CMP) method or the like. Thus, the element separation region ST made of the insulating film, preferably silicon oxide film, buried in the trench TR can be formed. At the stage of preparing the SOI substrate 1, the semiconductor layer SM is formed on the entire surface of the upper surface of the semiconductor substrate SB via the insulating layer BX, but when the element separation region ST is formed, the semiconductor layer SM is divided into a plurality of regions (active regions) surrounded by the element separation region ST, respectively.

[0050] Next, a photoresist pattern (not shown) formed on the SOI substrate 1 can be used as a mask (ion implantation block mask) to perform ion implantation to adjust the threshold value of the semiconductor substrate SB of the SOI substrate 1. The ion implantation is performed to control the threshold voltage of the MISFET to be formed later on the semiconductor layer SM. By this ion implantation, in the semiconductor substrate SB, impurities are introduced into a region adjacent to the insulating layer BX to form a semiconductor region.

[0051] Next, a semiconductor device such as a MISFET is formed on the semiconductor layer SM.

[0052] By forming the element separation region ST, in a plan view, the semiconductor layer SM is divided into a plurality of regions (active regions) surrounded by the element separation region ST, and the MISFET is formed in the semiconductor layer SM of the active region. In a plan view, the semiconductor layer SM of each active region is surrounded by the element separation region ST, and its lower surface is adjacent to the insulating layer BX. Thus, the semiconductor layer SM of each active region is surrounded by the element separation region ST and the insulating layer BX.

[0053] The process of forming the MISFET will be described in detail below.

[0054] First, after cleaning the surface of the semiconductor layer SM by performing a cleaning process (wet etching process for cleaning) if necessary, a gate insulating film GF is formed on the surface of the semiconductor layer SM. The gate insulating film GF is formed of a silicon oxide film or the like, and can be formed by a thermal oxidation method or the like.

[0055] Next, on the main surface of the SOI substrate 1, i.e., on the gate insulating film GF and the isolation region ST, a silicon film such as a doped polysilicon film is formed as a conductive film for forming a gate electrode GE. In addition, an insulating film such as a silicon nitride film (insulating film for forming a cover insulating film CP) is formed on the silicon film. Then, the stacked film of the silicon film and the insulating film thereon is patterned by photolithography and dry etching to form thereon the gate electrode GE and the cover insulating film CP. The gate electrode GE is formed on the semiconductor layer SM via the gate insulating film GF. The cover insulating film CP has substantially the same planar shape as the gate electrode GE. A portion of the gate insulating film GF not covered by the gate electrode GE can be removed by dry etching at the time of patterning the silicon film or by wet etching thereafter. This step is shown in Figure 4 .

[0056] Here, the stacked structure of the gate electrode GE and the cover insulating film CP thereon is hereinafter referred to as a laminate LT.

[0057] Next, as shown in Figure 5 , a side wall spacer SW1 is formed as a side wall insulating film on the side surfaces of the laminate LT. The formation step of the side wall spacer SW1 can be performed as follows.

[0058] First, a multilayer film including an insulating film IL1 and an insulating film IL2 on the insulating film IL1 is formed on the entire main surface of the SOI substrate 1 including the isolation region ST to cover the laminate LT. The insulating film IL1 and the insulating film IL2 are made of different materials, preferably, the insulating film IL1 is made of a silicon oxide film and the insulating film IL2 is made of a silicon nitride film. Then, the stacked film of the insulating film IL1 and the insulating film IL2 is etched back by an anisotropic etching technique to form the side wall spacer SW1 on both side surfaces of the laminate LT. This step is shown in Figure 5 . The side wall spacer SW1 is formed of the stacked film of the insulating film IL1 and the insulating film IL2.

[0059] Next, as shown in Figure 6As shown, a semiconductor layer EP is formed on the semiconductor layer SM of the SOI substrate 1 by epitaxial growth. The semiconductor layer EP is an epitaxial layer formed by epitaxial growth and is made of, for example, single-crystal silicon. Since the semiconductor layer EP is formed by epitaxial growth, the crystal structure of the semiconductor layer EP reflects the crystal structure of the underlying semiconductor layer SM, and the crystal structure of the semiconductor layer EP is the same as that of the semiconductor layer SM. The thickness of the semiconductor layer EP can be, for example, about 20 nm to 50 nm.

[0060] Since the semiconductor layer EP is formed by epitaxial growth, an epitaxial layer (semiconductor layer EP) is selectively grown on the exposed surface (Si surface) of the semiconductor layer SM, and no epitaxial layer is grown on the insulating film. Therefore, the semiconductor layer EP is selectively grown on the exposed surface of the semiconductor layer SM that is not covered by the stack body LT and the sidewall spacers SW1. Thus, as... Figure 6 As shown in region 1A, a semiconductor layer EP (epitaxial layer) is formed on the semiconductor layer SM. The semiconductor layer EP (epitaxial layer) is located on both sides of the structure formed by the stacked body LT and sidewall spacers SW1 on the semiconductor layer SM. Since the upper surface of the gate electrode GE is covered by the insulating film CP and the side surface of the gate electrode GE is covered by the sidewall spacers SW1, the epitaxial layer EP is not formed on the gate electrode GE. Furthermore, since the device isolation region ST is made of an insulator (insulating film), no epitaxial layer (semiconductor layer EP) is formed on the device isolation region ST.

[0061] Here, when forming a semiconductor layer EP by epitaxial growth, it may not be possible to successfully form an epitaxial layer EP on a semiconductor layer SM. Figure 6 Region 1A illustrates the successful formation of an epitaxial layer (semiconductor layer EP) on the semiconductor layer SM, and Figure 6 Region 1B illustrates a case where an epitaxial layer (semiconductor layer EP) was not successfully formed on the semiconductor layer SM. Therefore, although the structures of Region 1A and Region 1B are similar... Figures 1 to 5 The same in, but in Figure 6 In region 1A, an epitaxial layer (semiconductor layer EP) is formed on the semiconductor layer SM, while... Figure 6 In region 1B, the epitaxial layer (semiconductor layer EP) is not formed on the semiconductor layer S.

[0062] However, initially, as in region 1A, the manufacturing process is controlled to form the epitaxial layer EP on the semiconductor layer SM. Therefore, ideally, when performing the epitaxial growth process, structures such as region 1A are obtained, and structures such as region 1B are not generated. However, due to various reasons, the epitaxial layer EP may not be successfully formed on the semiconductor layer SM, and structures such as region 1B may occur. During the epitaxial growth process, it cannot be confirmed whether structures such as region 1B have occurred; therefore, the following steps are the same regardless of whether the structure of region 1B has occurred.

[0063] Next, as Figure 7 As shown, the insulating film IL2 constituting the sidewall spacer SW1 is etched away. Since the insulating film IL2 is etched and removed under conditions where it is etched less than the insulating film IL1, the insulating film IL1 constituting the sidewall spacer SW1 is almost completely etched and remains. Furthermore, since the insulating film IL2 is formed of the same material as the covering insulating film CP, the covering insulating film CP can also be removed by etching at this time. If the covering insulating film CP is removed, a metal silicide layer SL, described later, can be formed on the gate electrode GE.

[0064] Next, as Figure 8 As shown, n-type impurity ions, such as phosphorus (P) or arsenic (As), are implanted into regions of the semiconductor layers SM and EP of the SOI substrate 1 on both sides of the gate electrode GE, thereby forming an n-type semiconductor region (extended region) EX. In the ion implantation used to form the n-semiconductor region EX, the gate electrode GE and the insulating film IL1 extending on the side surface of the gate electrode GE can be used as ion implantation barrier masks. Figure 8 In the image, the region where impurities are implanted via ion implantation is shown by shaded dots.

[0065] Next, as Figure 9 As shown, a sidewall separator SW2 is formed on the side surface of the gate electrode GE as a sidewall insulating film.

[0066] The formation of the sidewall spacer SW2 can be performed as follows: An insulating film (e.g., a silicon nitride film) for forming the sidewall spacer SW2 is formed on the entire main surface of the SOI substrate 1, including the isolation region ST, to cover the gate electrode GE and the insulating film IL1. Then, the insulating film is etched back using an anisotropic etching technique, thereby forming the sidewall spacer SW2 on the side surface of the gate electrode GE. The sidewall spacer SW2 is formed on both side surfaces of the gate electrode GE, with the insulating film IL1 inserted between them.

[0067] Next, as Figure 10As shown, n-type impurity ions, such as phosphorus (P) or arsenic (As), are implanted into regions of the semiconductor layers SM and EP of the SOI substrate 1 on both sides of the gate electrode GE and the sidewall spacer SW2 to form an n+ type semiconductor region (source / drain region) SD. Figure 10 In the image, the region where impurities are implanted via ion implantation is shown by shaded dots.

[0068] In ion implantation for forming the n+ semiconductor region SD, the gate electrode GE and the sidewall spacers SW2 on both sides of the gate electrode GE can be used as ion implantation barrier masks. The n+ semiconductor region SD has a higher impurity concentration than the n- semiconductor region EX.

[0069] like Figure 10 As shown, in either region 1A or 1B, an n-type semiconductor region EX is formed in the semiconductor layer SM on both sides of the gate electrode GE to adjacent the channel forming region (the region directly below the gate electrode GE). That is, the n-type semiconductor region EX is formed in the semiconductor layer SM, and specifically, the n-type semiconductor region EX is formed in the portion of the semiconductor layer SM located below the insulating film IL1 and the sidewall spacer SW2.

[0070] like Figure 10 As shown, in region 1A, an n+ type semiconductor region SD is formed in semiconductor layers SM and EP at a position separated from and adjacent to the n-type semiconductor region EX by the channel formation region. Since semiconductor layer EP is not formed in region 1B, an n+ type semiconductor region SD is formed in semiconductor layer SM at a position separated from and adjacent to the n-type semiconductor region EX by the channel formation region. That is, in region 1A, the n+ type semiconductor region SD is formed above semiconductor layers EP and SM on both sides of the gate electrode GE, and semiconductor layer SM is below semiconductor layer EP; while in region 1B, the n+ type semiconductor region SD is formed in semiconductor layer SM on both sides of the gate electrode GE.

[0071] The semiconductor layer SM located below the gate electrode GE serves as the channel formation region, in which the MISFET channel is formed. The n-type semiconductor region EX and the n+ type semiconductor region SD form the source / drain regions of the LDD structure, i.e., the semiconductor regions used for the source or drain.

[0072] Next, activation annealing is performed, which is a heat treatment used to activate impurities introduced into the n+ type semiconductor region SD, n- type semiconductor region EX, etc. When the ion-implanted region is amorphous, it can be crystallized during this activation annealing.

[0073] Next, a low-resistance metal silicide layer SL is formed on the n+ semiconductor region SD and the gate electrode GE using self-aligned silicide technology.

[0074] Specifically, the metal silicide layer SL can be formed as follows: That is, as... Figure 11 As shown, a metal film ME for forming a metal silicide layer SL is formed on the entire main surface of an SOI substrate 1, including an isolation region ST, to cover the gate electrode GE, sidewall spacers SW2, and n+ semiconductor region SD. The metal film ME is made of, for example, a cobalt film, a nickel film, a nickel-platinum alloy film, etc. The thickness of the metal film ME can be, for example, about 10 nm to 50 nm. Then, a heat treatment is performed on the SOI substrate 1 to react the upper portions of each of the n+ semiconductor region SD and the gate electrode GE with the metal film ME. Thus, a metal silicide layer SL is formed in the upper portions of each of the n+ semiconductor region SD and the gate electrode GE, respectively. The metal silicide layer SL is the reaction layer between the semiconductor layer and the metal film ME. Thereafter, the unreacted metal film ME is removed, and the cross-sectional view of this stage is shown in... Figure 12 As shown in the figure, by forming a metal silicide layer SL, the diffusion resistance and contact resistance of the gate electrode GE and the n+ type semiconductor region SD can be reduced.

[0075] Here, the metal silicide layer SL for the gate electrode is referred to as metal silicide layer SL1, and has the reference symbol SL1, while the metal silicide layer SL for the source / drain region is referred to as metal silicide layer SL2, and has the reference symbol SL2. Metal silicide layer SL1 for the gate electrode is formed in the upper portion of the gate electrode GE, and metal silicide layer SL2 for the source / drain region is formed in the upper portion of the n+ semiconductor region SD. In region 1A, the semiconductor layer EP or semiconductor layers EP and SM react with the metal film ME to form metal silicide layer SL2 by silicideing the semiconductor layer EP or semiconductor layers EP and SM. In region 1B, the semiconductor layer SM reacts with the metal film ME to form metal silicide layer SL2 by silicideing the semiconductor layer SM.

[0076] In this way, semiconductor devices such as MISFETs (transistors) can be formed.

[0077] Here, the thickness of the metal silicide layer SL2 formed in region 1B is thinner than the thickness of the metal silicide layer SL2 formed in region 1A. That is, when the metal silicide layer SL is formed using self-aligned silicide technology, a metal silicide layer SL2 with the desired thickness can be formed in region 1A, but the thickness of the metal silicide layer SL2 in region 1B becomes thinner than the desired thickness. This is because, since the metal silicide layer SL2 is the reaction layer between the semiconductor layer and the metal film ME, if the thickness of the semiconductor layer below the metal film ME is small before heat treatment, the thickness of the metal silicide layer SL2 formed by heat treatment will also be small. Therefore, when the semiconductor layer EP is formed on the semiconductor layer SM by epitaxial growth in region 1A, the metal silicide layer SL2 can ensure the predetermined thickness, but when the epitaxial layer EP is not successfully formed on the semiconductor layer SM in region 1B, the thickness of the metal silicide layer SL2 formed by self-aligned silicide technology decreases.

[0078] Next, as Figure 13 As shown, in Figure 1 In step S1, an insulating film NT1 is formed on the entire main surface of the SOI substrate 1, including the isolation region ST, to cover the gate electrode GE, the sidewall spacers SW2, and the metal silicide layers SL1 and SL2. Then, in Figure 1 In step S2, an interlayer insulating film OX is formed on the insulating film NT1. After forming the interlayer insulating film OX, the upper surface of the interlayer insulating film OX can be polished by CMP method as needed.

[0079] The insulating film NT1 and the interlayer insulating film OX are made of different materials. The insulating film NT1 is preferably made of silicon nitride, and the interlayer insulating film OX is preferably made of silicon oxide. The thickness of the insulating film NT1 (silicon nitride film) is less than the thickness of the interlayer insulating film OX (silicon oxide film). The thickness of the interlayer insulating film OX can be, for example, about 600 nm to 800 nm, and the thickness of the insulating film NT1 can be, for example, about 10 nm to 30 nm. When the interlayer insulating film OX is etched to form a contact hole, the insulating film NT1 can be used as an etch stop film. Both the insulating film NT1 and the interlayer insulating film OX can be formed by, for example, chemical vapor deposition (CVD). Alternatively, the insulating film NT1 can be omitted. The interlayer insulating film OX is formed on the entire main surface of the SOI substrate 1, including the isolation region ST, to cover the gate electrode GE, the sidewall spacers SW2, and the metal silicide layers SL1 and SL2.

[0080] Next, as Figure 14 As shown, an insulating film NT2 is formed on the interlayer insulating film OX. Figure 1 Step S3 in the process.

[0081] The insulating film NT2 is made of a material other than that of the interlayer insulating film OX, and is preferably made of a silicon nitride film. The insulating film NT2 and the insulating film NT1 are preferably made of the same material. The thickness of the insulating film NT2 (the silicon nitride film) is smaller than the thickness of the interlayer insulating film OX (the silicon oxide film). The thickness of the insulating film NT2 can be, for example, about 20 nm to 40 nm. When the insulating film NT1 is formed, the thickness of the insulating film NT2 (the film thickness formed) is preferably thicker than the thickness of the insulating film NT1 (the film thickness formed). The insulating film NT2 can be formed by, for example, a CVD method or the like.

[0082] Next, a photoresist pattern PR is formed on the insulating film NT2 by photolithography. This step is shown in Figure 14 . The photoresist pattern PR has an opening at a position where the photoresist pattern PR forms a contact hole, that is, at a position where the photoresist pattern PR overlaps the n+ semiconductor region SD in a plan view.

[0083] Next, as shown in Figure 15 , an opening OP is formed in the insulating film NT2 by etching (preferably dry etching) the insulating film NT2 using the photoresist pattern PR as an etching mask (step S4 in Figure 1 ). The opening OP penetrates the insulating film NT2, and the interlayer insulating film OX is exposed at the bottom of the opening OP. At this stage, the opening OP does not penetrate the interlayer insulating film OX. Since the etching in step S4 is performed under a condition that the insulating film NT2 is more easily etched than the interlayer insulating film OX, that is, under a condition that the etching rate of the insulating film NT2 is higher than the etching rate of the interlayer insulating film OX, the insulating film NT2 is selectively etched, and the interlayer insulating film OX functions as an etching stopper film. The opening OP is formed at a position aligned with the opening of the photoresist pattern PR. In a plan view, the opening OP is formed at a position overlapping the n+ semiconductor region SD, and thus, in a plan view, the opening OP is formed at a position overlapping the metal silicide layer SL2.

[0084] Next, the interlayer insulating film OX exposed at the bottom of the opening OP is etched (preferably dry etched) using the photoresist pattern PR as an etching mask, thereby forming an opening OP in the interlayer insulating film OX (step S5 in Figure 1 ). Thus, the opening OP penetrates the insulating film NT2 and the interlayer insulating film OX, and the insulating film NT1 is exposed at the bottom of the opening OP. At this stage, the opening OP does not penetrate the insulating film NT1. Figure 15This stage is illustrated. Since the etching in step S5 is performed under conditions where the interlayer insulating film OX is more easily etched than the insulating film NT1, i.e., under conditions where the etching rate of the interlayer insulating film OX is higher than that of the insulating film NT1, the interlayer insulating film OX is selectively etched, and the insulating film NT1 serves as an etch stop film. Afterwards, the photoresist pattern PR is removed by ashing or the like.

[0085] Next, as Figure 16 As shown, an insulating film NT3 is formed on the insulating film NT2. Figure 1 In step S6), the insulating film NT3 includes the bottom (bottom surface) of the opening OP and the side surface (inner wall) of the opening OP.

[0086] The insulating film NT3 is preferably made of the same material as the insulating film NT2, and is preferably a silicon nitride film. The thickness of the insulating film NT3 (silicon nitride film) is less than the thickness of the interlayer insulating film OX (silicon oxide film). The thickness of the insulating film NT3 can be, for example, about 5 nm to 10 nm. The insulating film NT3 can be formed by, for example, CVD. A laminated film consisting of the insulating film NT2 and the insulating film NT3 formed on the insulating film NT2 is formed on the upper surface of the interlayer insulating film OX. In addition, the insulating film NT3 is formed on the side surface of the opening OP, which is the side surface of the interlayer insulating film OX. Furthermore, since the insulating film NT3 is formed in the state where the insulating film NT1 is exposed at the bottom of the opening OP, the insulating film NT3 is formed on the insulating film NT1 at the bottom of the opening OP.

[0087] Next, as Figure 17 As shown, the insulating film NT3 formed at the bottom of the opening OP and the insulating film NT1 formed at the bottom of the opening OP are etched away. Figure 1 Step S7). In S7, the insulating film NT3 and the insulating film NT1 formed at the bottom of the opening OP are removed by etching, thereby exposing the metal silicide layer SL2 at the bottom of the opening OP. Thus, a contact hole CT is formed as a through-hole to the metal silicide layer SL2. The contact hole CT is formed by the opening OP, and the inner wall (side surface) of the contact hole CT is formed by the surface of the insulating film NT3, which is retained in a layered manner on the side surface of the opening OP. Therefore, the radius of the contact hole CT is smaller than the thickness of the insulating film NT3, which is retained in a layered manner on the side surface of the opening OP, compared to the radius of the opening OP. The etching in S7 is performed under the condition that the metal silicide layer SL (SL2) and the insulating layer BX are etched less than the insulating films NT3 and NT1.

[0088] The etching in step S7 is preferably dry etching, and particularly anisotropic dry etching is preferred. Thus, in the etching in S7, the insulating film NT3 formed at the side surface of the opening OP is hardly etched. Therefore, at the stage when the etching of step S7 is completed, the insulating film NT3 remains on the side surface of the opening OP of the interlayer insulating film OX in a layered form. In addition, the etching of step S7 is started while the multilayer film of the insulating film NT2 and the insulating film NT3 is formed on the upper surface of the interlayer insulating film OX. Thus, when the insulating film NT3 formed at the bottom of the opening OP is removed by etching in step S7, the insulating film NT3 among the insulating films NT2 and NT3 formed on the upper surface of the interlayer insulating film OX is also removed by the etching in step S7. Further, since the insulating film NT1 at the bottom of the opening OP is removed by etching in step S7, a part of the thickness of the insulating film NT2 on the upper surface of the interlayer insulating film OX is also removed by the etching in step S7. However, the thickness of the insulating film NT3 to be formed in step S6 is preferably set so that the insulating film NT3 remains on the upper surface of the interlayer insulating film OX in a layered form at the completion of the etching in step S7. In this regard, the film thickness of the insulating film NT2 is preferably thicker than the film thickness of the insulating film NT1. Thus, the entire insulating film NT3, and a part of the thickness of the insulating film NT2 among the insulating films NT2 and NT3 on the upper surface of the interlayer insulating film OX are removed by the etching in S7, but the insulating film NT2 remains on the upper surface of the interlayer insulating film OX in a layered state.

[0089] Thus, when step S7 is performed, the insulating films NT1, NT3 at the bottom of the opening OP are removed to expose the metal silicide layer SL, the insulating film NT3 remains on the side surface of the opening OP of the interlayer insulating film OX in a layered state, and the insulating film NT2 remains on the upper surface of the interlayer insulating film OX in a layered state. Since the side surface of the opening OP of the interlayer insulating film OX is covered with the insulating film NT3, and the upper surface of the interlayer insulating film OX is covered with the insulating film NT2, it is possible to prevent the interlayer insulating film OX from being exposed at the completion of the etching of S7.

[0090] Here, in the region 1B, not only the insulating films NT1, NT3 at the bottom of the opening OP are removed by the etching in step S7, but also the metal silicide layer SL is etched and removed, and the insulating layer BX is likely to be exposed (see the region 1B in FIG. 6). Figure 17 The reason for this is that the thickness of the metal silicide SL2 formed by the self-aligned silicide technique in the region 1B becomes thinner than the intended thickness.

[0091] That is, the etching in step S7 is performed to remove the insulating films NT1, NT3 at the bottom of the opening OP to expose the metal silicide layer SL2, but if the removal of the insulating films NT1, NT3 on the metal silicide layer SL2 is insufficient, the reliability of the electrical connection between the plug PG and the metal silicide layer SL2 to be formed later decreases. For this reason, in the etching in S7, it is necessary to set the etching conditions (etching duration, etc.) under the premise that over-etching is performed to some extent so that the insulating films NT1 and NT3 at the bottom of the opening OP can be sufficiently removed (i.e., so that a remaining portion of the insulating films NT1 and NT3 does not occur). Therefore, in the etching of step S7, the metal silicide layer SL2 exposed at the bottom of the opening OP is also etched to some extent. Therefore, the etching conditions (etching duration, etc.) of S7 are set so that the etching amount (etching thickness) of the metal silicide layer SL2 is smaller than the thickness of the metal silicide layer SL2 formed by the self-aligned silicide technique. Therefore, even if the metal silicide layer SL2 exposed at the bottom of the opening OP is etched in step S7, the etching amount (etching thickness) of the metal silicide layer SL2 will be smaller than the thickness of the metal silicide layer SL2 so that the metal silicide layer SL2 remains in a layered state at the bottom of the opening OP, and the contact hole CT does not need to penetrate the metal silicide layer SL2 (see Figure 17 Region 1A).

[0092] However, when the thickness of the metal silicide layer SL2 becomes thinner than the expected thickness at the time of forming the metal silicide layer SL2, the entire thickness of the metal silicide layer SL2 at the bottom of the opening OP is etched in step S7, and the contact hole CT can penetrate the metal silicide layer SL2 to expose the insulating layer BX at the bottom of the contact hole CT.

[0093] Therefore, when the epitaxial layer EP is appropriately formed on the semiconductor layer SM as in Region 1A, the thickness of the metal silicide layer SL2 increases, so, as shown in Region 1A of Figure 17 On the other hand, when the epitaxial layer (semiconductor layer EP) is not successfully formed on the semiconductor layer SM as in Region 1B, the thickness of the metal silicide layer SL2 decreases, so, as shown in Region 1B of Figure 17

[0094] ​Thus, when a large number of MISFETs are formed, in most of the MISFETs, the metal silicide layer SL2 having a predetermined thickness is formed, and the contact hole CT does not penetrate the metal silicide layer SL2, but in some of the MISFETs, the thickness of the metal silicide layer SL2 is reduced, and the contact hole CT penetrates the metal silicide layer SL2, and the insulating layer BX can be exposed at the bottom of the contact hole CT. Figure 17 A cross-sectional view of the region 1A and a cross-sectional view of the region 1B are shown. In the region 1A, the epitaxial layer EP is accurately formed on the semiconductor layer SM, the metal silicide layer SL2 having a predetermined thickness is formed, and the contact hole CT does not penetrate the metal silicide layer SL2. On the other hand, in the region 1B, the epitaxial layer (semiconductor layer EP) is not successfully formed on the semiconductor layer SM, the thickness of the metal silicide layer SL2 formed by the self-aligned silicide technique is reduced, the contact hole CT penetrates the metal silicide layer SL2, and the insulating layer BX is exposed at the bottom of the contact hole CT.

[0095] Thus, there is a possibility that the portion having the structure of the region 1A and the portion having the structure of the region 1B are mixed.

[0096] Then, in the present first embodiment, after the etching in the step S7, as shown in Figure 18 in the step S8 of Figure 1 The etching step capable of selectively etching the insulating layer BX is executed in the step S8. Hereinafter, the etching step of the step S8 will be referred to as the etching step of the step S8. The contact hole CT (the opening OP) is etched by the etching process of the step S8.

[0097] The etching step of the step S8 is executed under the condition that the insulating films NT2 and NT3 are etched less than the insulating layer BX, that is, under the condition that the etching rate of each of the insulating films NT2 and NT3 is lower than the etching rate of the insulating layer BX. In other words, the etching step of the step S8 is executed under the condition that the insulating layer BX is more easily etched than the insulating films NT2 and NT3, that is, under the condition that the etching rate of the insulating layer BX is higher than the etching rate of each of the insulating films NT2 and NT3.

[0098] Figure 18 A stage at which the etching process of the step S8 is completed is shown. At the stage at which the etching process of the step S8 is completed, as shown in Figure 18As illustrated, since the side surface of the opening OP as the side surface of the interlayer insulating film OX is covered with the insulating film NT3 and the upper surface of the interlayer insulating film OX is covered with the insulating film NT2, the interlayer insulating film OX is not exposed. Therefore, the etching step of step S8 is performed in a state where the side surface of the opening OP as the side surface of the interlayer insulating film OX is covered with the insulating film NT3 and the upper surface of the interlayer insulating film OX is covered with the insulating film NT2. That is, the etching process of step S8 can be performed in a state where the interlayer insulating film OX is not exposed. As described above, the etching step of step S8 is performed in a condition where each of the insulating films NT2 and NT3 is etched less than the insulating film BX. Therefore, in the etching step of step S8, the insulating films NT2 and NT3 are hardly etched, and the insulating film NT3 on the side surface of the opening OP as the side surface of the interlayer insulating film OX and the insulating film NT2 on the upper surface of the interlayer insulating film OX can function as films for preventing the interlayer insulating film OX from being etched. Therefore, in the etching step of step S8, it is possible to etch the insulating layer BX while suppressing or preventing the interlayer insulating film OX from being etched.

[0099] In particular, when the insulating layer BX and the interlayer insulating film OX are made of the same material, preferably silicon oxide, if the insulating film NT3 on the side surface of the opening OP of the interlayer insulating film OX and the insulating film NT2 on the upper surface of the interlayer insulating film OX are not present, when the insulating layer BX is removed in the etching step of step S8, the interlayer insulating film OX is also etched in a large amount. If the interlayer insulating film OX is etched, the shape of the contact hole can change and the flatness of the upper surface of the interlayer insulating film OX can deteriorate, thereby a problem can occur when the plug PG is formed later or when the wiring M1 is formed later. Therefore, it is desirable to prevent the interlayer insulating film OX from being etched when the insulating layer BX is removed as much as possible in the etching process of step S8.

[0100] On the contrary, in the present first embodiment, in the etching step S8, since the insulating film NT3 on the side surface of the opening OP of the interlayer insulating film OX and the insulating film NT2 on the upper surface of the interlayer insulating film OX can function as films for preventing the interlayer insulating film OX from being etched, etching of the interlayer insulating film OX can be suppressed or prevented. Therefore, it is possible to prevent the change in the shape of the contact hole and the deterioration in the flatness of the upper surface of the interlayer insulating film OX due to etching of the interlayer insulating film OX, thereby it is possible to prevent a problem from occurring when the plug PG is formed later or when the wiring M1 is formed later. Therefore, it is possible to improve the reliability of the semiconductor device. Therefore, by applying the present first embodiment, when the insulating layer BX and the interlayer insulating film OX are made of the same material, preferably silicon oxide, the effect is very significant.

[0101] More preferably, at the stage where the etching process in step S8 is completed, the side surface of the opening OP of the interlayer insulating film OX is covered by the insulating film NT3 and the upper surface of the interlayer insulating film OX is covered by the insulating film NT2, thereby preventing the interlayer insulating film OX from being etched during the etching process in step S8. Therefore, the thickness of each of the insulating films NT2 and NT3 is preferably set such that at the stage where the etching process in step S8 is completed, the side surface of the opening OP of the interlayer insulating film OX is covered by the insulating film NT3, and the upper surface of the interlayer insulating film OX is covered by the insulating film NT2. The radius of the opening OP is larger than the thickness of the insulating film NT3 compared to the required radius of the contact hole CT, and the insulating film NT3 remains on the side surface of the opening OP after etching step S8.

[0102] Furthermore, since the etching step in step S8 is performed under the condition that the insulating layer BX is easier to etch than the insulating films NT2 and NT3, when the insulating layer BX is exposed at the bottom of the contact hole CT as in region 1B, the insulating layer BX at the bottom of the contact hole CT can be removed to expose the semiconductor substrate SB. That is, in region 1B, the contact hole CT penetrates the insulating layer BX to reach the semiconductor substrate SB, and the semiconductor substrate SB at the bottom of the contact hole CT is exposed.

[0103] In this first embodiment, in etching step S8, the entire thickness of the insulating layer BX is set to an etching amount (etch thickness) that allows the insulating layer BX to be etched. That is, as in Figure 17 In region 1B, at the stage where etching in step S7 is completed, when the insulating layer BX is exposed at the bottom of the contact hole CT, the conditions of the etching process in step S8 (e.g., etching duration) are set such that the entire thickness of the insulating layer BX at the bottom of the contact hole CT is etched and the contact hole CT penetrates the insulating layer BX when the etching process in step S8 is performed. Specifically, when the thickness of the insulating layer BX is T1 in the stage of preparing the SOI substrate 1, the etching step of step S8 is performed under the condition that the insulating layer BX with a thickness of T1 can be etched.

[0104] As in Figure 17 In region 1B, at the stage where etching is completed in step S7, when the insulating layer BX is exposed at the bottom of the contact hole CT, it is preferable to set a slight over-etch in the etching step S8 so that the contact hole CT can always penetrate the insulating layer BX in the etching step S8. However, if the over-etch setting value in the etching step S8 is too large, as in Figure 17In the region 1A, when the metal silicide layer SL2 remains in a layered state at the bottom of the contact hole CT, the etching amount of the metal silicide layer SL2 increases, but it is not desirable for the etching amount of the metal silicide layer SL2 to increase. Therefore, it is preferable that the setting value of the over-etching in the etching step of step S8 not be too large. Therefore, it is preferable that the setting value of the over-etching in the etching step of step S8 be set to about 10% of the thickness T1 of the insulating layer BX. For example, when the thickness of the insulating layer BX is T1 at the stage of preparing the SOI substrate 1, it is preferable that the etching step of step S8 be performed under conditions in which an insulating layer BX having a thickness of T1 x 1.1 can be etched. To give an example of a specific numerical value, when the insulating layer BX is a silicon oxide film having a thickness of 15 nm at the stage of preparing the SOI substrate 1, it is preferable that the etching step of step S8 be performed under conditions in which a silicon oxide film having a thickness of 16.5 nm can be etched.

[0105] In the etching process step of step S8, wet etching or dry etching can be used. In the case of wet etching, hydrofluoric acid (an aqueous solution of hydrofluoric acid, diluted hydrofluoric acid) can be suitable for the etchant. In the case of dry etching, a fluorocarbon compound (a fluorocarbon compound gas) can be suitable for the etching gas.

[0106] In addition, in the region 1A, since the etching processing of step S8 is performed while the metal silicide layer SL2 is exposed at the bottom of the contact hole CT, it is desirable to suppress the etching of the metal silicide layer SL2 in the etching process of step S8 as much as possible. Therefore, the etching step of step S8 is performed under conditions in which the metal silicide layer SL2 (SL) is hardly etched as compared with the insulating layer BX, that is, under conditions in which the etching rate of the metal silicide layer SL2 (SL) is smaller (lower) than the etching rate of the insulating layer BX.

[0107] In the etching step S8, it is desirable to set the etching conditions such that the etching selectivity of the insulating layer with respect to the metal silicide layer SL2 and the insulating films NT2 and NT3 is as high as possible. The etching selectivity ratio of the insulating layer BX with respect to the metal silicide layer SL2 (SL) and the insulating films NT2, NT3 corresponds to the ratio of the etching rate of the insulating layer BX to the etching rate of each of the metal silicide layer SL2 (SL) and the insulating films NT2, NT3. Since wet etching tends to increase the etching selectivity of the insulating layer with respect to the metal silicide layer SL2, it is more preferable to use wet etching in the etching step S8. In particular, wet etching using hydrofluoric acid can etch silicon dioxide with high selectivity. Therefore, the insulating layer BX is formed of silicon oxide, and wet etching using hydrofluoric acid is applied to the etching step of step S8, so that it is possible to suppress the etching of the metal silicide layer SL2 in the region 1A while etching the insulating layer BX in the region 1B selectively.

[0108] Silicon oxide has higher etch selectivity than silicon nitride and the like. Therefore, compared to step S7 for etching the insulating films NT3 and NT1, the etching thickness of the metal silicide layer SL2 can be reduced in step S8 for etching the insulating layer BX made of silicon oxide. Therefore, in the etching step of step S8, the amount of etching of the metal silicide layer SL2 at the bottom of the contact hole CT in region 1A is reduced, and it is possible to prevent the contact hole CT from penetrating the metal silicide layer SL2.

[0109] When wet etching is applied to the etching process of S8, damage caused by dry etching can be prevented from being applied to the metal silicide layer SL2 in region 1A.

[0110] On the other hand, when dry etching is applied to the etching step of step S8, etching of the side surface of the insulating layer BX can be suppressed.

[0111] After the etching in step S7 is completed, as Figure 17 As shown, in region 1A, the metal silicide layer SL2 is exposed at the bottom of the contact hole CT, while the contact hole CT does not penetrate the metal silicide layer SL2. In region 1B, the contact hole CT penetrates the metal silicide layer SL2, and the insulating layer BX is exposed at the bottom of the contact hole CT. At the stage where the etching process in step S8 is completed, as... Figure 18 As shown, in region 1A, the metal silicide layer SL2 is exposed at the bottom of the contact hole CT, and the contact hole CT does not penetrate the metal silicide layer SL2. However, in region 1B, the contact hole CT penetrates the metal silicide layer SL2 and the insulating layer BX, and the semiconductor substrate SB is exposed at the bottom of the contact hole CT.

[0112] When multiple SOI substrates 1 flow through the production line to perform semiconductor device manufacturing processes on the respective SOI substrates 1, at the etching completion stage in step S7, not only do they include... Figure 17 The structure of region 1A exists, but Figure 17 The structure of region 1B is absent in the SOI substrate 1, and there is also... Figure 17 The structure of region 1A and Figure 17 The SOI substrate 1 with the structure coexisting in region 1B. However, it is difficult to confirm whether the corresponding SOI substrate 1 has a structure that exists during the etching completion stage of S7. Figure 17 The structure of region 1B is shown. Therefore, in this first embodiment, the etching process of step S8 is performed at the stage where etching is completed in step S7, and... Figure 17 The presence or absence of a structure in region 1B is irrelevant. Therefore, even at the stage where etching is completed in step S7... Figure 17 If the structure of region 1B exists, then during the etching process in step S8, this part will inevitably become... Figure 18The structure of region 1B in the middle. Therefore, at the stage where etching is completed in step S8, not only is there the structure of region 1B in the middle. Figure 18 The structure of region 1A exists, but Figure 18 The structure of region 1B in the SOI substrate 1 is absent, and there is also... Figure 18 The structure of region 1A in the middle and Figure 18 SOI substrate 1 with structure coexisting in region 1B.

[0113] After the etching step in step S8, as Figure 19 As shown, a plug PG made of conductive material is formed inside the contact hole CT (opening OP). Figure 1 Step S1). The plug PG can be formed, for example, as follows.

[0114] First, a conductive film for forming the plug PG is formed on the interlayer insulating film OX (insulating film NT2), including inside the contact hole CT. The conductive film is a laminate of a barrier conductive film and a tungsten film. Then, the unnecessary conductive film (the conductive film for forming the plug PG) outside the contact hole CT is removed by CMP, etching back, etc., leaving the conductive film (the conductive film for forming the plug PG) inside the contact hole CT. Therefore, a plug PG made of the conductive film retained in the contact hole CT can be formed. The plug PG is buried in the contact hole CT.

[0115] A plug PG for the source / drain region is provided to provide a predetermined potential to the source / drain region (here, the n+ semiconductor region SD) via a metal silicide layer SL2. Therefore, initially, the plug PG for the source / drain region is arranged on the metal silicide layer SL2, and the bottom surface of the plug PG for the source / drain region contacts the upper surface of the metal silicide layer SL2, such that the plug PG for the source / drain region and the metal silicide layer SL2 should be electrically connected to each other, and region 1A has this configuration. In region 1A, the plug PG for the source / drain region does not contact the semiconductor substrate SB. On the other hand, in region 1B, the lower surface of the plug PG for the source / drain region contacts the semiconductor substrate SB, and the plug PG for the source / drain region and the semiconductor substrate SB are electrically connected to each other.

[0116] Next, as Figure 20 As shown, an insulating film ZM is formed on an interlayer insulating film OX (insulating film NT2) that conceals a plug PG. Then, after forming a wiring trench in a predetermined area of ​​the insulating film ZM, wiring M1 is buried in the wiring trench using a single damascene technique. Wiring M1 is, for example, copper wiring with copper as the main component, i.e., buried copper wiring. The upper surface of the plug PG contacts the wiring M1, thereby electrically connecting the plug PG and the wiring M1 to each other.

[0117] After that, the wiring of the second layer and subsequent layers is formed by a dual damascene method or the like, but illustration and explanation thereof are omitted here. The wiring M1 and the wiring on the upper layer of the wiring M1 are not limited to damascene wiring, but can be formed by patterning a conductive film for wiring, and can be, for example, tungsten wiring or aluminum wiring.

[0118] In this way, the SOI substrate 1 is subjected to wafer processing. The wafer processing is also referred to as pre-processing. Here, the wafer processing generally refers to a process of forming various elements, interconnection layers, and pad electrodes on a main surface of a semiconductor wafer (here, the SOI substrate 1); forming a surface protective film; and then enabling electrical testing of each of a plurality of chip regions formed on the semiconductor wafer (here, the SOI substrate 1) by a probe or the like. The chip region of the semiconductor wafer (here, the SOI substrate 1) corresponds to a region of the semiconductor wafer (here, the SOI substrate 1) from which one semiconductor chip is obtained.

[0119] Thereafter, by performing a probe test (so-called wafer test) using the pads, the respective chip regions of the semiconductor wafer (here, the SOI substrate 1) can be electrically tested. The results of the probe test can be used to improve yield and reliability by selecting whether each chip region of the semiconductor wafer (here, the SOI substrate 1) is a non-defective chip or a defective chip, or by feeding back data of the measurement results of the probe test to each manufacturing process.

[0120] In the region 1A, the plug PG for the source / drain region is not electrically connected to the semiconductor substrate SB, whereas in the region 1B, the plug PG for the source / drain region is electrically connected to the semiconductor substrate SB, and thus it is possible to determine in the probe test whether the plug PG for the source / drain region is electrically connected to the semiconductor substrate SB. That is, in the probe test, it is possible to determine whether there is a structure such as the region 1B in the probe test. Therefore, it is possible to select a chip region in which there is a structure such as the region 1B (a structure in which the plug PG for the source / drain region is electrically connected to the semiconductor substrate SB) as a defective chip region.

[0121] Thereafter, by performing a cutting process, the SOI substrate 1 is cut (diced) and divided (singulated) into a plurality of semiconductor chips. That is, the SOI substrate 1 is cut along the scribe line region. Thus, the semiconductor chips are obtained from the chip regions of the SOI substrate 1.

[0122] As described above, the semiconductor device of the present first embodiment is manufactured.

[0123] Note that the test for determining whether a structure such as region 1B, a structure in which a plug PG for a source / drain region is electrically connected to a semiconductor substrate SB, exists or not can not be performed in a probe test, but on a semiconductor chip that is singulated by dicing or a semiconductor package in which a semiconductor chip is packaged.

[0124] In the present first embodiment, although an n-channel MISFET is formed as the MISFE, a p-channel MISFET can be formed by inverting the conductivity type, or both an n-channel MISFET and a p-channel MISFET can be formed.

[0125] <Research Background>

[0126] Figures 21 to 24 is a main part cross-sectional view of an inspection example that the present inventors have researched in a manufacturing process of a semiconductor device. Until Figure 13 the step shown, the manufacturing process of the semiconductor device of the inspection example is also the same as the manufacturing process of the semiconductor device of the above-described present first embodiment, and thus a repetitive description thereof is omitted here.

[0127] After the interlayer insulating film OX is formed to obtain Figure 13 the structure shown, as Figure 21 shown, in the inspection example, a photoresist pattern PR 101 is formed on the interlayer insulating film OX using a photolithography technique. Figure 21 Region 1C shown is a region corresponding to region 1A of Figure 13 , and Figure 21 Region 1D shown is a region corresponding to region 1B of Figure 13 . Then, as Figure 22 shown, the interlayer insulating film OX and the insulating film NT1 are sequentially etched, preferably dry-etched, using the photoresist pattern PR 101 as an etching mask, thereby forming a contact hole CT 101 that penetrates the interlayer insulating film OX and the insulating film NT1. At this time, first, the interlayer insulating film OX is etched under a condition in which the interlayer insulating film OX is more easily etched than the insulating film NT1, and the contact hole CT 101 is formed in the interlayer insulating film OX. Then, the insulating film NT1 exposed at the bottom of the contact hole CT 101 is etched under a condition in which the insulating film NT1 is more easily etched than the interlayer insulating film OX, thereby forming the contact hole CT 101 that penetrates the interlayer insulating film OX and the insulating film NT1. At the bottom of the contact hole CT 101, the metal silicide layer SL2 is exposed (see region 1C in Figure 22 ).

[0128] Next, as Figure 23As shown, a plug PG 101 made of conductive material is formed in the contact hole CT 101. Since the specific method for forming the plug PG 101 is similar to the method for forming the plug PG described above, its description is omitted here.

[0129] Next, as Figure 24 As shown, an insulating film ZM and wiring M1 are also formed in the test example. Subsequently, in the case of the test example, a second and subsequent conductor layer are also formed, but illustrations and explanations are omitted here.

[0130] In the formation step of contact hole CT 101, although the metal silicide layer SL2 is initially in Figure 22 The bottom of contact hole CT 101 in region 1C is exposed, but etching should stop before contact hole CT 101 penetrates the metal silicide layer SL2. However, as in Figure 22 In region 1D, the contact hole CT 101 may penetrate the metal silicide layer SL2, and the insulating layer BX may be exposed at the bottom of the contact hole CT 101. This phenomenon may occur when the thickness of the metal silicide SL2 formed by the self-aligned silicide technique becomes thinner than expected.

[0131] That is, in region 1C, because the epitaxial layer (semiconductor layer EP) is accurately formed on the semiconductor layer SM, the thickness of the metal silicide layer SL2 increases, and the contact hole CT 101 does not penetrate the metal silicide layer SL2, as in Figure 22 In region 1C. On the other hand, in region 1D, since the epitaxial layer (semiconductor layer EP) was not successfully formed on the semiconductor layer SM, the thickness of the metal silicide layer SL2 is reduced, and the contact hole CT 101 penetrates the metal silicide layer SL2, as shown in... Figure 22 In region 1D, and the insulating layer BX may be exposed at the bottom of contact hole CT 101. Therefore, when forming a large number of MISFETs, in most MISFETs, contact hole CT 101 is as follows: Figure 22 In region 1C, the metal silicide layer SL2 will not penetrate, but in some MISFETs, the contact hole CT 101, as in... Figure 22 In region 1D, the metal silicide layer SL2 penetrates, and the insulating layer BX may be exposed at the bottom of the contact hole CT 101. In region 1D, when the contact hole CT 101 is formed, a portion of the thickness of the insulating layer BX is also etched, and the thickness of the insulating layer BX remaining at the bottom of the contact hole CT 101 may be thinner than the thickness of the insulating layer BX in other regions.

[0132] Therefore, when Figure 23When the plug PG 101 is formed as shown, in region 1C, the plug PG 101 for the source / drain region is disposed on the metal silicide layer SL2, and the bottom surface of the plug PG for the source / drain region contacts the upper surface of the metal silicide layer SL2, thereby electrically connecting the plug PG 101 for the source / drain region and the metal silicide layer SL2. On the other hand, in region 1D, the plug PG 101 for the source / drain region penetrates the metal silicide layer SL2, and the lower surface of the plug PG 101 for the source / drain region contacts the insulating layer BX. The thickness of the insulating layer BX below the plug PG 101 may be thinner than the thickness of the insulating layer BX in other regions.

[0133] If in Figure 23 Manufacturing a semiconductor device with the structure shown in region 1D (i.e., the structure in which the lower surface of the plug PG 101 is in contact with the insulating layer BX) reduces the reliability of the semiconductor device. For example, in region 1D, if the plug PG 101 and the semiconductor substrate SB are opposite each other via the insulating layer BX, and if the insulating layer BX between the plug PG 101 and the semiconductor substrate SB is thin, the breakdown voltage between the plug PG 101 and the semiconductor substrate SB will be reduced. Therefore, leakage current may occur between the plug PG 101 and the semiconductor substrate SB. Furthermore, if the insulating layer BX between the plug PG 101 and the semiconductor substrate SB breaks down during the use of the semiconductor device, a short circuit will occur between the plug PG 101 and the semiconductor substrate SB. However, it is necessary to prevent the short circuit between the plug PG 101 and the semiconductor substrate SB during the use of the semiconductor device.

[0134] Therefore, it is expected that the testing process will determine Figure 23 Does the structure of region 1D shown (i.e., the structure where the lower surface of plug PG 101 contacts the insulating layer BX) exist? If determined during the testing process... Figure 23 The structure of region 1D shown (i.e., the structure in which the lower surface of plug PG 101 contacts the insulating layer BX) exists, and if Figure 23 The structure of region 1D shown can be selected as a defective product, so that the structure of region 1D will not cause problems in the process of using semiconductor devices, thereby improving the reliability of semiconductor devices.

[0135] However, it is not easy to determine in the testing process. Figure 23 Does the structure of region 1D shown exist? This is because it does. Figure 23 The MISFET in region 1D shown operates almost normally in the short term. Within it exists... Figure 23In the MISFET of the structure of the region 1D shown in which the lower surface of the plug PG 101 is in contact with the insulating layer BX, even if the plug normally operates in the short term, it is desirable to distinguish (select) the plug in the test process because defects such as a leakage or a dielectric breakdown can occur in the long term, but it is difficult to distinguish (select) the plug in the test process because the plug almost normally operates in the short term. If a load test in which an electrical test is performed is performed in a state in which stress is applied, it is possible to determine Figure 23 whether or not the structure of the region 1D shown exists, but in this case, one semiconductor device (semiconductor chip) requires a stress load for a long time (for example, about several minutes), and the time required for the test process becomes long, and the cost required for the test process becomes high.

[0136] <Main features and effects>

[0137] In the present first embodiment, the insulating film NT1, NT3 at the bottom of the opening OP is removed by etching to expose the metal silicide layer SL2 in step S7, and then the etching step in step S8 is performed as one of the main features of the metal silicide layer OP. The etching step of step S8 is an etching step capable of selectively etching the insulating layer BX. Therefore, at the stage at which the etching of step S7 is completed, as in the region 1B shown in Figure 17 In the region 1B shown in FIG. 6, when the contact hole CT penetrates the metal silicide layer SL2 and the insulating layer BX is exposed at the bottom of the contact hole CT, in the etching step of step S8, the insulating layer BX at the bottom of the contact hole CT can be removed, and the semiconductor substrate SB can be exposed at the bottom of the contact hole CT. That is, at the stage at which the etching of step S7 is completed, as in the region 1B shown in Figure 17 In the region 1B shown in FIG. 6, when the contact hole CT penetrates the metal silicide layer SL2 and the insulating layer BX is exposed at the bottom of the contact hole CT, in the etching step of step S8, the insulating layer BX at the bottom of the contact hole CT can be removed, and the semiconductor substrate SB can be exposed at the bottom of the contact hole CT. That is, at the stage at which the etching of step S7 is completed, as in the region 1B shown in

[0138] Since it is difficult to confirm Figure 17 whether or not the structure of the region 1B shown exists at the stage at which the etching of step S7 is completed in the respective SOI substrates 1, in the present first embodiment, the etching step of step S8 is performed regardless of whether or not the structure of the region 1B shown exists at the stage at which the etching of step S7 is completed. Figure 17 Therefore, even if the structure of the region 1B shown exists at the stage at which the etching of step S7 is completed, the portion inevitably becomes the structure of the region 1B shown in which the semiconductor substrate SB is exposed at the bottom of the contact hole CT when the etching step of step S8 is performed. Figure 17 Therefore, even if the structure of the region 1B shown exists at the stage at which the etching of step S7 is completed, the portion inevitably becomes the structure of the region 1B shown in which the semiconductor substrate SB is exposed at the bottom of the contact hole CT when the etching step of step S8 is performed. Figure 18

[0139] ​Therefore, when the plug PG is formed, in region 1A, the plug PG for the source / drain region does not penetrate the metal silicide layer SL2 and is not conductive with the semiconductor substrate SB. However, in region 1B, the plug PG for the source / drain region penetrates the metal silicide layer SL2 and the insulating layer BX and is conductive with the semiconductor substrate SB. It is easy to determine whether the plug PG for the source / drain region is electrically connected to the semiconductor substrate SB during a test process (e.g., probe testing). For example, if a potential difference is established between the plug PG for the source / drain region and the semiconductor substrate SB to check whether current flows between the plug PG for the source / drain region and the semiconductor substrate SB, it can be determined whether the plug PG for the source / drain region is electrically connected to the semiconductor substrate SB. Therefore, the test for determining whether the plug PG for the source / drain region is electrically connected to the semiconductor substrate SB can be easily performed in a short time.

[0140] In it Figure 24 In the MISFET with the structure shown in region 1D, even if the plug operates normally in the short term, it is desirable to distinguish the plug during the test process because defects such as leakage or dielectric breakdown may occur in the long term. However, it is difficult to distinguish the plug during the test process because the plug operates almost normally in the short term. On the other hand, in this first embodiment, when as in Figure 17 When the insulating layer BX in region 1B is exposed at the bottom of the contact hole CT by etching in step S7, as... Figure 18 In region 1B, the insulating layer BX at the bottom of the contact hole CT is forcibly removed by the etching step in step S8, and the contact hole CT is forced to reach the semiconductor substrate SB.

[0141] Therefore, since the plug PG formed in the contact hole CT in region 1B inevitably comes into contact with the semiconductor substrate SB, it is possible to determine whether the plug PG and the semiconductor substrate SB are conductive if it is determined whether they have conductivity. Figure 19 The presence of a portion of the structure in region 1B (where the plug PG contacts the semiconductor substrate SB) can be determined easily and quickly in a testing process (e.g., probe testing). Figure 19 The presence or absence of a portion of the structure in region 1B (where the plug PG contacts the semiconductor substrate SB) allows for a reduction in the time and cost of the testing process. Furthermore, as in Figure 23 In region 1D, the plugs used for the source / drain regions can be prevented from contacting the insulating layer BX, and the portion opposite to the semiconductor substrate SB can be prevented from forming through the insulating layer BX. Therefore, the reliability of the semiconductor device can be improved.

[0142] In addition, as another main feature of the present first embodiment, in a case where the upper surface of the interlayer insulating film OX is covered with the insulating film NT2 and the side surface of the opening OP of the interlayer insulating film OX is covered with the insulating film NT3, step S8 is executed. The etching step of step S8 is executed under a condition that the insulating film NT2 and the insulating film NT3 are hardly etched compared with the insulating film BX. Thus, in the etching step of step S8, it is possible to suppress or prevent the interlayer insulating film OX from being etched while allowing the insulating layer BX to be etched. Thus, it is possible to prevent the shape change of the contact hole CT and the reduction of the flatness of the upper surface of the interlayer insulating film OX caused by the etching of the interlayer insulating film OX, and thereby it is possible to prevent a problem from occurring when the plug PG is formed later or when the wire M1 is formed later. Thus, it is possible to improve the reliability of the semiconductor device.

[0143] In particular, when the insulating layer BX and the interlayer insulating film OX are made of the same material, preferably silicon oxide, if the insulating film NT3 on the side surface of the opening OP of the interlayer insulating film OX and the insulating film NT2 on the upper surface of the interlayer insulating film OX are not present, the interlayer insulating film OX is also etched in large amount when the insulating layer BX is removed in the etching step of step S8. In the present first embodiment, even when the insulating layer BX and the interlayer insulating film OX are made of the same material, preferably silicon oxide, it is possible to selectively etch the insulating layer BX while suppressing or preventing the etching of the interlayer insulating film OX in the etching step S8.

[0144] (Second Embodiment)

[0145] The manufacturing process of the semiconductor device according to the present second embodiment will be described with reference to Figures 25 to 28 FIG. 10.

[0146] Figure 1 is a process flowchart showing a part of the manufacturing process of the semiconductor device according to the present second embodiment and corresponding to Figures 26 to 28 FIG. 9. Figure 15 is a cross-sectional view in the manufacturing process of the semiconductor device according to the present second embodiment.

[0147] Until the structure shown in Figures 2 to 14 is obtained, the manufacturing process of the semiconductor device of the present second embodiment is basically the same as the manufacturing process of the first embodiment described above (the steps shown in Figure 14 ), and thus a repeated description thereof is omitted here.

[0148] After the structure of Figure 15 is obtained, in the first embodiment described above, the insulating film NT2 and the interlayer insulating film OX are sequentially etched with the photoresist pattern PR as an etching mask to form the opening OP that penetrates the insulating film NT2 and the interlayer insulating film OX, and the etching is completed in the step of exposing the insulating film NT1 at the bottom of the opening OP, that is, the structure of Figure 16The structural stage. Afterwards, such as... Figure 15 As shown, an insulating film NT3 is formed.

[0149] On the other hand, in this second embodiment, the structure is obtained in the same manner as shown in the first embodiment described above. Figure 26 Following the structure shown, as Figure 25 As shown, the insulating film NT1 exposed at the bottom of the opening OP is removed by etching using a photoresist pattern PR as an etching mask. Figure 22 Step S5a). That is, in this second embodiment, by sequentially performing the etching in step S4, the etching in step S5, and the etching in step S5a, the opening OP penetrates the insulating films NT2, OX, and NT1, and the metal silicide layer SL2 is exposed at the bottom of the opening OP (see step S5a). Figure 26 (Region 1A in the text). The etching in step S5a is performed under conditions where the insulating film NT1 is more easily etched than the metal silicide layer SL (SL2), the interlayer insulating film OX, and the insulating layer BX. The etching in step S5a is preferably dry etching, and particularly preferably anisotropic dry etching. Afterward, the photoresist pattern PR is removed by ashing or the like.

[0150] Here, although the metal silicide layer SL2 is as in Figure 26 In region 1A, the initial exposure is at the bottom of the opening OP, but the etching in S5a should terminate before the opening OP penetrates the metal silicide layer SL2. However, not only is the insulating film NT1 at the bottom of the opening OP removed, but the metal silicide layer SL is also etched and removed in step S5a, as in Figure 22 In region 1B, opening OP can penetrate the metal silicide layer SL2, and insulating layer BX can be exposed at the bottom of opening OP. This is because when contact hole CT 101 penetrates... Figure 27 The reason is the same as for the metal silicide layer SL2 in region 1D, and in the above test example, the insulating layer BX is exposed at the bottom of the contact hole CT 101. Similar to the first embodiment described above, in this second embodiment, it is also possible to mix the portion having the structure of region 1A and the portion having the structure of region 1B.

[0151] Next, as Figure 25 As shown, in Figure 25In step S6a, the insulating film NT3 is formed on the insulating film NT2, including the bottom surface and the side surface of the opening OP. The second embodiment is also the same as the above-described first embodiment in the formation method of the insulating film NT3, the material constituting the insulating film NT3, the thickness of the insulating film NT3, and the like. On the upper surface of the interlayer insulating film OX, the laminated film of the insulating film NT2 and the insulating film NT3 is formed, and on the side surface of the opening OP of the interlayer insulating film OX, the insulating film NT3 is formed. Further, in the region 1A, since the insulating film NT3 is formed in a state where the metal silicide layer SL2 is exposed at the bottom of the opening OP, the insulating film NT3 is formed on the metal silicide layer SL2 at the bottom of the opening OP. Also, in the region 1B, since the insulating film NT3 is formed in a state where the insulating layer BX is exposed at the bottom of the opening OP, the insulating film NT3 is formed on the insulating layer BX at the bottom of the opening OP.

[0152] Next, in operation S7a, Figure 28 In operation S7a, the insulating film NT3 at the bottom of the opening OP is etched away. In the region 1A, the insulating film NT3 at the bottom of the opening OP is removed, and the metal silicide SL2 is exposed at the bottom of the opening OP. Also, in the region 1B, the insulating film NT3 at the bottom of the opening OP is removed, and the insulating film BX is exposed at the bottom of the opening OP. Thus, the contact hole CT is formed. The contact hole CT is formed from the opening OP, and the inner wall (side surface) of the contact hole CT is formed from the surface of the insulating film NT3 which is left on the side surface of the opening OP in a layered manner. Thus, the radius of the contact hole CT is smaller than the radius of the opening OP by the thickness of the insulating film NT3 which is left on the side surface of the opening OP in a layered manner. The etching in S7a is performed under conditions in which the metal silicide layer SL (SL2) and the insulating layer BX are more difficult to etch than the insulating film NT3.

[0153] The etching in step S7a is preferably dry etching, and particularly preferably anisotropic dry etching. Thus, at the stage when the etching of step S7a is completed, the insulating film NT3 is left on the side surface of the opening OP of the interlayer insulating film OX in the form of a layer. Further, since the insulating film NT3 at the bottom of the opening OP is removed by etching in step S7a, the insulating film NT3 among the insulating films NT2, NT3 on the upper surface of the interlayer insulating film OX is also removed by the etching in step S7a. However, preferably, at the stage when the etching in step S7a is completed, the thickness of the insulating film NT3 formed in step S6 is set so that the insulating film NT3 is left on the upper surface of the interlayer insulating film OX in a layered manner.

[0154] Thus, when the etching step S7a is performed, in the region 1A, Figure 28In region 1A, the insulating film NT1 at the bottom of the opening OP is removed to expose the metal silicide layer SL. The insulating film NT3 remains in a layered state on the side surface of the opening OP of the interlayer insulating film OX, and the insulating film NT2 remains in a layered state on the upper surface of the interlayer insulating film OX. Additionally, during etching step S7a, in... Figure 28 In region 1B, the insulating film NT1 at the bottom of the opening OP is removed to expose the insulating layer BX, the insulating film NT3 is retained in a layered state on the side surface of the opening OP of the interlayer insulating film OX, and the insulating film NT2 is retained in a layered state on the upper surface of the interlayer insulating film OX. Figure 28 In either region 1A or 1B, since the side surface of the opening OP of the interlayer insulating film OX is covered by the insulating film NT3 and the upper surface of the interlayer insulating film OX is covered by the insulating film NT2, it is possible to prevent the interlayer insulating film OX from being exposed during the etching stage of S7a.

[0155] In this second embodiment, the thickness of the insulating film NT2 formed in step S3 can be reduced compared to the first embodiment described above. However, in both the first and second embodiments, at the stage where etching is complete in S7, the upper surface of the interlayer insulating film OX is covered by the insulating film NT2.

[0156] In this second embodiment Figure 17 The structure is similar to that in the first embodiment described above. Figure 28 The structure. That is, Figure 17 The structure of region 1A in the middle is similar to Figure 28 The structure of region 1A in the middle, and Figure 17 The structure of region 1B in the middle is similar to Figure 28 The structure of region 1B in the image. Therefore, in this second embodiment, the method used to obtain the image after etching step S7a is as follows. Figures 18 to 20 The process of the structure is similar to step S8 and its subsequent steps in the first embodiment described above (i.e., ​ The etching process is the same as the steps described above, but its repetition is omitted here.

[0157] In this second embodiment, essentially the same effects as in the first embodiment described above can be achieved. However, in this second embodiment, the insulating film NT1 at the bottom of the opening OP is removed by etching in step S5a, followed by the formation of the insulating film NT3, and then the insulating film NT3 at the bottom of the opening OP is removed by etching in step S7a. In the first embodiment, after the formation of the insulating film NT3, both the insulating films NT3 and NT1 at the bottom of the opening OP are removed by etching in step S7. Therefore, compared to this second embodiment, the first embodiment can reduce the number of steps and shorten the manufacturing time of the semiconductor device.

[0158] The application made by the present inventors has been described in detail above on the basis of embodiments, but the present application is not limited to the above-described embodiments, and needless to say, various modifications can be made without departing from the gist thereof.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: (a) Providing a substrate, the substrate comprising a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a semiconductor layer formed on the insulating layer, and a gate electrode formed on the semiconductor layer via a gate insulating film; (b) After step (a), an epitaxial layer is formed on the semiconductor layer located on both sides of the gate electrode by an epitaxial growth method; (c) After step (b), a metal silicide layer is formed in the epitaxial layer by silicide formation; (d) After step (c), an interlayer insulating film is formed on the substrate to cover the gate electrode and the metal silicide layer; (e) After step (d), a first insulating film is formed on the interlayer insulating film; (f) After step (e), an opening is formed at the portion of each of the first insulating film and the interlayer insulating film that overlaps with the metal silicide layer; (g) After step (f), a second insulating film is formed at each of the bottom of the opening and the side surfaces of the opening, and on the upper surface of the first insulating film; (h) After step (g), each of the following is removed by etching: the second insulating film formed at the bottom of the opening, and the second insulating film formed on the upper surface of the first insulating film; (i) After step (h), the interior of the opening is etched in the following state: the upper surface of the interlayer insulating film is covered by the first insulating film, and the side surface of the opening is covered by the second insulating film as the side surface of the interlayer insulating film. as well as (j) After step (i), a plug made of conductive material is formed inside the opening. Step (i) is performed under the condition that each of the first insulating film, the second insulating film, and the metal silicide layer is etched less than the insulating layer. If the insulating layer is not exposed at the bottom of the opening by step (h), then the insulating layer below the opening was not etched in step (i), and If the insulating layer is exposed at the bottom of the opening via step (h), the insulating layer below the opening is etched in step (i), thereby exposing the semiconductor substrate.

2. The method according to claim 1, Step (i) is performed under the condition that each of the first insulating film and the second insulating film is etched less than the interlayer insulating film.

3. The method according to claim 2, Step (i) is performed by one of the following: wet etching using hydrofluoric acid, and dry etching using fluorocarbons.

4. The method according to claim 3, The insulating layer is composed of a first thickness. Wherein the first thickness is equal to or greater than 10 nm and equal to or less than 30 nm, and Step (i) is performed under the condition that at least the first thickness of the insulating layer is etched.

5. The method according to claim 1, The insulating layer and the interlayer insulating film are made of the same material as each other.

6. The method according to claim 5, Each of the insulating layer and the interlayer insulating film is made of silicon oxide.

7. The method according to claim 1, The first insulating film and the second insulating film are made of the same material.

8. The method according to claim 7, Each of the first insulating film and the second insulating film is made of silicon nitride.

9. The method according to claim 1, Step (i) is performed by anisotropic dry etching.

10. The method according to claim 1, further comprising the following step: (d1) After step (c) and before step (d), a third insulating film is formed on the substrate to cover the gate electrode and the metal silicide layer. In step (d), the interlayer insulating film is formed on the third insulating film. In step (f), the opening is formed such that the opening penetrates the first insulating film and the interlayer insulating film, and such that the third insulating film is retained at the bottom of the opening; In step (h), each of the following is removed by etching: the second insulating film formed at the bottom of the opening, the third insulating film formed at the bottom of the opening, and the second insulating film formed on the upper surface of the first insulating film.

11. The method according to claim 10, The first insulating film, the second insulating film, and the third insulating film are made of the same material as each other.

12. The method according to claim 10, Each of the first insulating film, the second insulating film, and the third insulating film is made of silicon nitride.

13. The method according to claim 1, further comprising the following step: (d1) After step (c) and before step (d), a third insulating film is formed on the substrate to cover the gate electrode and the metal silicide layer. In step (d), the interlayer insulating film is formed on the third insulating film, and In step (f), the opening is formed such that it penetrates the first insulating film, the interlayer insulating film, and the third insulating film.

14. The method according to claim 1, further comprising the following step: (b1) After step (b) and before step (c), a source region is formed in each of the epitaxial layer and the semiconductor layer located on one side of the gate electrode, and a drain region is formed in each of the epitaxial layer and the semiconductor layer located on the other side of the gate electrode.

Images