Semiconductor device and method for manufacturing the same

Abstract

A method for forming a semiconductor device includes forming a conductive component and a first through-stop layer, wherein the conductive component has a first top surface, and the first through-stop layer has a second top surface substantially horizontal to the first top surface. The method also includes forming a resistor element on the first through-stop layer. The method also includes etching through a first portion of the resistor element to form a first trench, the trench simultaneously exposing the second top surface of the first through-stop layer and the first sidewall surface of the resistor element. The method also includes forming a first conductive via in the first trench, wherein the first conductive via contacts the first sidewall surface of the resistor element. Embodiments of the present application provide semiconductor devices and methods for manufacturing the same.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices that are simultaneously capable of supporting a greater number of increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved to a large extent by reducing the size (e.g., minimum component size) of semiconductor ICs and thereby increasing production efficiency and reducing associated costs. However, such scaling has also increased the complexity of semiconductor manufacturing processes. As a result, the challenge of manufacturing reliable electronic devices has increased.

[0003] Therefore, the realization of continued advancements in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and techniques. However, the prior art has not proven to be completely satisfactory in all respects. Summary of the invention

[0004] An embodiment of the present application provides a method for manufacturing a semiconductor device, comprising: forming a conductive component and a first punch-through stop layer, wherein the conductive component has a first top surface, and wherein the first punch-through stop layer has a second top surface substantially flush with the first top surface; forming a resistor element above the first punch-through stop layer; etching through a first portion of the resistor element to form a first trench, the first trench exposing the second top surface of the first punch-through stop layer and a first side wall surface of the resistor element; and forming a first conductive via in the first trench, wherein the first conductive via contacts the first side wall surface of the resistor element.

[0005] On the other hand, an embodiment of the present application provides a method for manufacturing a semiconductor device, including: forming a first punch-through stop layer and a second punch-through stop layer in a first dielectric layer disposed above a substrate, wherein the first punch-through stop layer and the second punch-through stop layer are substantially flush with each other; depositing a plurality of layers above the first punch-through stop layer and the second punch-through stop layer, the plurality of layers including a resistive layer; forming a first trench exposing the first punch-through stop layer and a second trench exposing the second punch-through stop layer; and forming a first conductive via in the first trench and a second conductive via in the second trench, wherein the first conductive via contacts a first region of the resistive layer, and wherein the second conductive via contacts a second region of the resistive layer.

[0006] An embodiment of the present application also provides a semiconductor device, comprising: a first metal line; a first punch-stop layer, a first top surface of the first punch-stop layer being substantially flush with a second top surface of the first metal line; a resistor element, disposed above the first punch-stop layer; and a first conductive via, contacting both the first top surface of the first punch-stop layer and the first side wall surface of the resistor element. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1 When read together, various aspects of the present disclosure can be best understood from the following detailed description. It should be emphasized that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, for the sake of clarity of discussion, the sizes of various components can be arbitrarily increased or reduced.

[0008] Figure 1 is a flow chart of a method of manufacturing a semiconductor device including a resistance element according to one or more aspects of the present disclosure;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 is based on Figure 1 A cross-sectional view of an embodiment of a semiconductor device 200 at various stages of a method;

[0010] Figure 8 is a top view of a resistor region of a semiconductor device 200 according to some embodiments;

[0011] Fig. 9 is a top view of a resistor region of a semiconductor device including a plurality of conductive vias at each end of a resistor element according to some embodiments;

[0012] Fig.10 , Fig.11 , Fig.12 and Fig.13 is a top view of a resistor region of a semiconductor device having alternative punch-through stop layer (PSL) dimensions according to some embodiments;

[0013] Fig.14 and Fig.15 is a top view of a resistor region of a semiconductor device having an alternative resistor element geometry according to some embodiments; and

[0014] Fig.16 , Fig.17 and Fig.18 is a top view of a resistor region of a semiconductor device with alternative PSL and conductive via geometries according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first component formed above or on a second component may include an embodiment in which the first and second components are formed to be in direct contact, and may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or structures discussed.

[0016] Additionally, spatially relative terms, such as "below," "beneath," "below," "above," "above," and the like, may be used herein for convenience in describing the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein likewise interpreted accordingly.

[0017] The present disclosure is generally directed to structures and related methods for forming semiconductor devices including resistive elements, wherein the resistive elements are used as resistors. In some cases, the resistive elements can be formed as part of a back-end-of-line (BEOL) process, for example, between metal layers of a multilayer metal interconnect structure. The multilayer metal interconnect structure can be used to interconnect various front-end-of-line (FEOL) devices (e.g., such as transistors) to each other and to the resistive elements to form an integrated circuit including the resistive elements. In some examples, the resistive elements disclosed herein can be formed as part of an analog circuit. However, the disclosed resistive elements are generally applicable to any type of circuit using a resistor.

[0018] In at least some existing embodiments, as the size of the resistor decreases, the uniformity of the resistor (including both its manufacturing and resistance value) becomes increasingly poor. For example, in a BEOL process, a metal interconnect layer coupled to a conductive via can be used to achieve electrical connection to a resistor element, wherein the conductive via is in contact with the resistor element. However, in at least some existing embodiments, the conductive via in contact with the resistor element extends into the resistor element (e.g., extending about 10-40 angstroms) and terminates within the resistor element. In addition, the amount by which the conductive via extends into the resistor element can vary from conductive via to conductive via, for example, depending on the through-hole etching process used to form the through-hole groove, a conductive via is formed in the through-hole groove. This phenomenon can be referred to as a recess depth variation, and this variation will directly affect the uniformity of the resistor (e.g., including the resistance value). These variations will reduce the performance and reliability of devices and circuits. In addition, as the size of the resistor continues to decrease, the challenges of recess depth variation are expected to increase. Therefore, the prior art has not yet proven to be completely satisfactory in all aspects.

[0019] Embodiments of the present disclosure provide advantages over the prior art, although it should be understood that other embodiments may provide different advantages, it is not necessary to discuss all advantages herein, and all embodiments do not require specific advantages. For example, the embodiments discussed herein include structures and related methods for forming semiconductor devices including resistor elements with enhanced uniformity. In various examples, and in order to solve the problem of recessed depth variation present in some existing embodiments, embodiments of the present disclosure provide a through stop layer (PSL) disposed below the resistor element and directly below the conductive via for contacting the resistor element. In various embodiments, and as described in more detail below, the conductive via can penetrate the resistor element (and one or more other layers) and stop on the PSL. Therefore, instead of terminating the conductive via at a certain uncertain and variable position within the resistor element, the conductive via for contacting the resistor element can completely pass through the corresponding resistor element they contact and stop on the following PSL. Ultimately, the problem of through hole groove depth variation can be ignored while improving the uniformity of the resistor, especially for highly scaled resistor sizes. By reading this disclosure, other embodiments and advantages will be apparent to those skilled in the art.

[0020] Figure 1 A method 100 of manufacturing a resistor element with enhanced uniformity according to various embodiments is shown in FIG. Figure 2-Figure 7 Describing method 100, Figure 2-Figure 7 Provided based on Figure 11 and 1 . The method 100 of FIG. 1 is a cross-sectional view of an embodiment of a semiconductor device 200 at various stages of the method 100. It will be appreciated that the method 100 includes steps that are part of a complementary metal oxide semiconductor (CMOS) technology process flow and is therefore only briefly described herein. Moreover, additional steps may be performed before, after, and / or during the method 100. Furthermore, it should be noted that the process steps of the method 100, including any description given with reference to the accompanying drawings, are exemplary only and are not intended to limit what is specifically recited in the appended claims.

[0021] The method 100 begins at block 102 where a substrate is provided. Figure 2 In an example of, in an embodiment of box 102, a substrate 202 is provided. In some embodiments, substrate 202 may be a semiconductor substrate such as a silicon substrate. Substrate 202 may include various layers, including a conductive or insulating layer formed on a semiconductor substrate. As is known in the art, depending on design requirements, substrate 202 may include various doping configurations. Substrate 202 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 202 may include compound semiconductors and / or alloy semiconductors. In addition, substrate 202 may optionally include an epitaxial layer (epitaxial layer), may be strained to improve performance, may include a silicon on insulator (SOI) structure, and / or have other suitable enhancement components.

[0022] In some embodiments, various device elements are formed in and / or on the substrate 202. Examples of various device elements that can be formed in and / or on the semiconductor substrate 202 include metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors (PFETs, NFETs), diodes, other suitable elements, or combinations thereof. In some examples, the various device elements include FEOL devices, as described above. Various processes can be performed to form the various device elements, such as deposition, etching, implantation, lithography, annealing, planarization, one or more other applicable processes, or combinations thereof. In addition, in some embodiments, isolation components can be formed in the substrate 202 to define and isolate the various device elements formed in and / or on the substrate 202. Isolation components include, for example, shallow trench isolation (STI) components, or local oxidation of silicon (LOCOS) components.

[0023] The method proceeds to block 104 where a dielectric layer is formed. In some embodiments, the dielectric layer includes an interlayer dielectric (ILD) layer. Still referring to Figure 2In an example of the present invention, in an embodiment of block 104, a dielectric layer 204 is formed over the device 200. In some embodiments, the dielectric layer 204 includes a material such as tetraethyl orthosilicate (TEOS) oxide, carbon-containing silicon oxide, silicon oxide, a porous dielectric material, undoped silicate glass or doped silicon oxide [e.g., borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG)], another suitable low-K or additional low-K dielectric material, one or more other suitable dielectric materials, or a combination thereof.

[0024] The method proceeds to block 106 where a conductive feature and a punch-through stop layer (PSL) are formed. Figure 2 In an example of a device 200, in an embodiment of block 106, a conductive feature 206 and punch-through stop layers (PSLs) 208, 210 are formed within the dielectric layer 204. The conductive feature 206 includes a conductive line that provides part of a metal interconnect structure, which may include other conductive lines as well as conductive vias. In various embodiments, the PSLs 208, 210 are not part of the metal interconnect structure (e.g., may not be electrically active), but rather provide an etch stop layer (e.g., for a via etch process) beneath the resistor element and directly beneath a conductive via for contacting the resistor element, where such a conductive via can punch through the resistor element (and one or more other layers) and stop on the PSLs 208, 210. The conductive feature 206 can be formed in the logic region 205 of the device 200, and the PSLs 208, 210 can be formed in the resistor region 207 of the device 200. In some cases, a trench can be initially formed within the dielectric layer 204 using a combination of photolithography and etching processes. The trenches may define areas within each of the logic region 205 and the resistor region 207 where the conductive features 206 and PSLs 208 , 210 , respectively, will be formed.

[0025] In some embodiments, the trenches in the logic region 205 may be filled with a conductive material such as copper, cobalt, tungsten, titanium, nickel, gold, platinum, silicide, another suitable conductive material, or a combination thereof. The conductive material for filling the trenches in the logic region 205 may be deposited using a CVD process, an ALD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof. The trenches in the resistor region 207 may be filled with a conductive material such as aluminum, copper, other suitable metal materials, or a combination thereof. In some examples, the trenches in the resistor region 207 may alternatively be filled with cobalt, tungsten, titanium, nickel, gold, platinum, silicide, other suitable metal materials, or a combination thereof. The conductive material for filling the trenches in the resistor region 207 may be deposited using a CVD process, an ALD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

[0026] After filling the trenches in each of the logic region 205 and the resistor region 207 with appropriate conductive materials, a chemical mechanical polishing (CMP) process (planarization process) may be performed to remove excess conductive material from outside the trenches. Thus, the remainder of the conductive material in the trenches forms the conductive component 206 (in the logic region 205) and the PSL 208, 210 (in the resistor region 207). After the planarization process, the top surfaces of the conductive components 206, PSL 208, 210, and the dielectric layer 204 may be substantially coplanar (flush). Note that in various embodiments, the conductive component 206 and the PSL 208, 210 may be formed simultaneously. Thus, in some examples, as described above, the formation process of the PSL 208, 210 may be substantially the same as the formation process for the conductive component 206. In at least one example, the thickness of PSL208, 210 can be substantially the same as the thickness of conductive component 206, because the trenches defining the areas in which conductive component 206 and PSL208, 210 will be formed can be manufactured simultaneously and by the same process. Other dimensions of PSL208, 210 (e.g., such as top-view area) will depend on the top-view area of ​​the subsequently formed resistive element, as described in more detail below. In some embodiments, conductive component 206 includes one of the third to seventh level metal lines of the back-end multi-layer metal interconnect structure. Moreover, it will be understood that although a single conductive component 206 has been shown, more conductive components can be used without departing from the scope of the present disclosure. Similarly, although two PSL208, 210 have been shown, it should be understood that more or fewer PSLs can be used without departing from the scope of the present disclosure. Furthermore, in various embodiments, the formation of each of the conductive features 206 and PSLs 208, 210 (e.g., including one or more of patterning and etching of trenches, filling with conductive materials, and planarization) can be performed simultaneously, or each of the conductive features 206 and PSLs 208, 210 can be performed separately. For example, in some cases, if the materials used for each of the conductive features 206 and PSLs 208, 210 are the same, the formation of the conductive features 206 and PSLs 208, 210 can be performed simultaneously. In other examples, if the materials used for each of the conductive features 206 and PSLs 208, 210 are different, the formation of the conductive features 206 and PSLs 208, 210 can be performed separately.

[0027] In some embodiments, a barrier layer may also be formed between the conductive feature 206 and the dielectric layer 204 and / or between the PSL 208, 210 and the dielectric layer 204 to prevent diffusion of conductive materials used to form the conductive feature 206 and the PSL 208, 210. For example, a barrier layer may be deposited on the sidewalls and bottom surfaces of the trenches in the logic region 205 and the resistor region 207 before depositing the conductive materials used to form the conductive feature 206 and the PSL 208, 210. If present, such a barrier layer may include tantalum nitride, titanium nitride, one or more other suitable materials, or combinations thereof.

[0028] As previously described, the conductive feature 206 includes a conductive line that provides part of a metal interconnect structure, which may include other conductive lines and conductive vias. As described above, various device elements formed in and / or on the substrate 202 will be interconnected by a multi-layer metal interconnect structure formed on the semiconductor substrate 202. Thus, an integrated circuit device is formed. The integrated circuit device may include a logic device, a memory device (e.g., DRAM, SRAM), a radio frequency (RF) device, an input / output (I / O) device, a system-on-chip (SoC) device, an image sensor device, one or more other applicable types of devices, or a combination thereof. In addition to interconnecting various FEOL devices, the multi-layer metal interconnect structure may also be used to connect one or more resistive elements to each other and / or to various FEOL devices to form an integrated circuit including one or more resistive elements.

[0029] The method proceeds to block 108 where a film deposition process is performed. Figure 2In one embodiment of block 108, one or more layers (including a resistive layer) are deposited on the device 200 (including on the dielectric layer 204, the conductive feature 206, and the PSL 208, 210). For example, a first barrier layer 212 may be deposited on the device 200, including on the dielectric layer 204, the conductive feature 206, and the PSL 208, 210. In some embodiments, the first barrier layer 212 is made of a material different from the dielectric layer 204. The first barrier layer 212 may include silicon carbide (SiC), nitrogen-doped SiC, oxygen-doped SiC, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide, one or more other suitable materials, or a combination thereof. The first barrier layer 212 may be deposited using a CVD process, an ALD process, a PVD process, one or more other suitable processes, or a combination thereof. In some cases, a dielectric layer 214 may be formed on the first barrier layer 212. In some cases, the dielectric layer 214 may include a tetraethyl orthosilicate (TEOS) oxide layer. In addition, or alternatively, dielectric layer 214 may include carbon-containing silicon oxide, silicon oxide, porous dielectric material, undoped silicate glass or doped silicon oxide (e.g., BPSG, FSG, PSG, BSG), another suitable low-K or ultra-low-K dielectric material, one or more other suitable dielectric materials, or a combination thereof. Dielectric layer 214 may be deposited using a CVD process, an ALD process, a PVD process, one or more other suitable processes, or a combination thereof.

[0030] After the dielectric layer 214 is formed, and in various embodiments, a resistive layer 216 is deposited on the dielectric layer 214. In some embodiments, the resistive layer 216 includes tantalum nitride (TaN), titanium nitride (TiN), amorphous silicon, one or more other suitable materials, or a combination thereof. More generally, and in some embodiments, the resistive layer 216 is made of a nitrogen-containing material. In some examples, the atomic concentration of nitrogen in the resistive layer 216 is in the range of about 40% to about 70%. In some embodiments, the resistive layer 216 is deposited using a CVD process, an ALD process, a PVD process, one or more other suitable processes, or a combination thereof. The resistive layer 216 can be patterned to subsequently form a resistive element, as discussed in more detail below.

[0031] In some embodiments, the resistive layer 216 is thinner than the conductive component 206. The ratio of the thickness of the resistive layer 216 to the thickness of the conductive component 206 can be in the range of about 1 / 20 to about 1 / 15. In some cases, if the ratio is greater than about 1 / 15, the resistance of the resistive layer 216 may not be high enough for some applications. In some other cases, if the ratio is less than about 1 / 20, the quality or reliability of the resistive layer 216 may need to be improved for some applications. By way of example only, and in some embodiments, the thickness of the resistive layer 216 may be equal to about 45 angstroms. More broadly, and in some embodiments, the thickness of the resistive layer 216 may be in the range of about 40-70 angstroms. For example, to provide a target sheet resistance (resistivity / thickness). In some examples, if the thickness of the resistive layer 216 is greater than about 70 angstroms, the resistivity of the resistive layer 216 may be too low to meet the target sheet resistance. In addition, in some cases, if the thickness of the resistive layer 216 is less than about 40 angstroms, the quality or reliability of the resistive layer 216 may not be sufficient to meet some applications. Generally, as the thickness of the resistive layer 216 decreases, the resistance value of the resistive layer 216 increases. In some embodiments, the target sheet resistance value of the resistive layer 216 is in the range of about 500-900 ohms-per-square.

[0032] After forming the resistive layer 216, in some embodiments, a second barrier layer 218 may be deposited on the resistive layer 216. In some embodiments, the second barrier layer 218 is made of the same material as the first barrier layer 212. However, in some cases, the second barrier layer 218 may be made of a material different from the first barrier layer 212. The second barrier layer 218, like the first barrier layer 212, may include SiC, nitrogen-doped SiC, oxygen-doped SiC, SiN, SiON, silicon oxide, one or more other suitable materials, or a combination thereof. The second barrier layer 218 may be deposited using a CVD process, an ALD process, a PVD process, one or more other suitable processes, or a combination thereof. In some embodiments, a dielectric layer 220 may be formed on the second barrier layer 218. In some examples, the dielectric layer 220 may be made of the same material as the dielectric layer 214. However, in some cases, the dielectric layer 220 is made of a material different from the dielectric layer 214. The dielectric layer 220, like the dielectric layer 214, may include a TEOS oxide layer. In addition, or alternatively, the dielectric layer 220 may include carbon-containing silicon oxide, silicon oxide, porous dielectric material, undoped silicate glass or doped silicon oxide (such as BPSG, FSG, PSG, BSG), another suitable low-K or ultra-low-K dielectric material, one or more other suitable dielectric materials, or a combination thereof. The dielectric layer 220 may be deposited using a CVD process, an ALD process, a PVD process, one or more other suitable processes, or a combination thereof.

[0033] In some embodiments, the thickness of the first barrier layer 212 and the second barrier layer 218 are substantially the same. Thus, in various embodiments, the ratio of the thickness of the first barrier layer 212 to the thickness of the second barrier layer 218 may be in the range of about 0.9 to 1.1. By way of example only, the thickness of the first barrier layer 212 and the second barrier layer 218 may be in the range of about 90-110 angstroms (e.g., such as about 100 angstroms). In some examples, if the thickness of the first barrier layer 212 or the thickness of the second barrier layer 218 is less than about 90 angstroms, excessive silicide may be formed during subsequent formation of the conductive contact feature (e.g., block 118 of method 100), resulting in increased leakage current and reduced device performance. In some cases, if the thickness of the first barrier layer 212 is greater than about 110 angstroms of the thickness of the second barrier layer 218, it may be difficult to control the etching depth of a subsequent etching process (e.g., block 116 of method 100). Likewise, in some cases, if the ratio of the thickness of the first barrier layer 212 to the thickness of the second barrier layer 218 falls outside the range between approximately 0.9 and 1.1, then the etch depth of a subsequent etching process may again be difficult to control (eg, block 116 of method 100).

[0034] In some cases, the thickness of dielectric layer 220 is greater than the thickness of dielectric layer 214. In some cases, the thickness of dielectric layer 220 can be greater than the thickness of dielectric layer 214 to provide protection from greater recessing of dielectric layer 220 (compared to dielectric layer 214) during an etching process in a subsequent patterning step (block 110), as described below. After the film deposition process and before a subsequent patterning process, the ratio of the thickness of dielectric layer 220 to the thickness of dielectric layer 214 can be in a range between about 1.4 and 1.6. In some cases, if the ratio of the thickness of dielectric layer 220 to the thickness of dielectric layer 214 falls outside the range between about 1.4 and 1.6, the etch depth of a subsequent power-on etching process (e.g., block 116 of method 100) may be difficult to control, and / or dielectric layer 220 or dielectric layer 214 may not provide sufficient electrical isolation or sufficient protection from stresses applied by adjacent layers, which may damage resistive layer 216. Furthermore, if the dielectric layer 220 is too thin, the dielectric layer 220 may be inadvertently completely consumed in the etching process of the subsequent patterning step (block 110), and the resistive layer 216 may be damaged. In one example, the thickness of the dielectric layer 220 may be in the range of about 270-330 angstroms (e.g., such as about 300 angstroms), and the thickness of the dielectric layer 214 may be in the range of about 180-220 angstroms (e.g., such as about 200 angstroms).

[0035] Regarding the resistive layer 216, and in some embodiments, the ratio of the thickness of the resistive layer 216 to the thickness of the first barrier layer 212 (or the second barrier layer 218) may be in the range between about 0.4 and 0.5. In some embodiments, after the film deposition process and before the subsequent patterning process, the ratio of the thickness of the resistive layer 216 to the thickness of the dielectric layer 220 may be in the range between about 0.1 and 0.2. In some examples, after the film deposition process and before the subsequent patterning process, the ratio of the thickness of the resistive layer 216 to the thickness of the dielectric layer 214 may be in the range between about 0.2 and 0.3. In various cases, if the thickness ratio of the resistive layer 216 to the other layers (e.g., such as the first barrier layer 212, the second barrier layer 218, the dielectric layer 220, and the dielectric layer 214) falls outside the above range, the etching depth of the subsequent via etching process (e.g., block 116 of the method 100) may again be difficult to control, the resistance of the resistive layer may be too low to meet the target sheet resistance (e.g., if the resistive layer 216 is too thick), or the quality or reliability of the resistive layer (or one or more of the other adjacent layers) may be insufficient for certain applications (e.g., if the resistive layer 216 or the adjacent layers are too thin). In addition, as described above, the first barrier layer 212 and the second barrier layer 218 may be formed in various embodiments to reduce the formation of excess silicide during the subsequent formation of conductive contact features, which may help reduce leakage current through the path provided by the excess silicide, thereby improving device performance.

[0036] The method proceeds to block 110 where a patterning process is performed. Figure 2 and Figure 3For example, in one embodiment of block 110, a patterning process is performed to provide a resistor element 216A. The formation of the resistor element 216A may include a suitable combination of photolithography and etching processes. For example, a photoresist (resist) layer may be deposited on the dielectric layer 220 and patterned using a photolithography process to provide a patterned resist layer that will define the desired geometry (e.g., top view shape) of the resistor element 216A. The top view of the resistor element 216A may have any suitable shape. For example, the top view of the resistor element 216A has a rectangular shape or a square shape. After forming the patterned resistor layer, an etching process (e.g., dry etching, wet etching, or a combination thereof) is performed. In some embodiments, the etching process removes portions of the dielectric layer 220, the second barrier layer 218, and the resistor layer 216 that are not protected by the patterned barrier layer (e.g., portions outside the resistor region 207) to provide a patterned dielectric layer 220A, a patterned second barrier layer 218A, and a resistor element 216A. In some embodiments, as shown, the etching process may also partially recess the exposed portions of the dielectric layer 214. In some embodiments, the etching process may recess the dielectric layer 214 by a recess depth 'R1' in areas not protected by the patterned resist layer (e.g., portions outside the resistor region 207, such as portions within the logic region 205). In some cases, the recess depth 'R1' is in a range between about 90-110 angstroms (e.g., such as about 100 angstroms). It is also noted that in some cases, the etching process may consume the patterned resist layer (e.g., within the resistor region 207) and partially recess the patterned dielectric layer 220A by a recess depth 'R2', such that the thickness of the patterned dielectric layer 220A is less than the thickness of the dielectric layer 220 prior to the etching process. In some cases, the recess depth 'R2' is in a range between about 180-220 angstroms (e.g., such as about 200 angstroms). Additionally, and in various cases, the dielectric layer 214 and the first barrier layer 212 may function to protect the dielectric layer 204 , the conductive features 206 , and the PSLs 208 , 210 during the patterning process of the block 110 to form the resistive element 216A.

[0037] After the patterning process of block 110, including after the recessing of dielectric layer 214 (in logic region 205) and the recessing of dielectric layer 220A (in resistance region 207), some thickness ratios will be different from the ranges previously indicated (e.g., before the patterning process). For example, after the patterning process (block 110), the ratio of the thickness of dielectric layer 220A to the thickness of dielectric layer 214 (in logic region 205) can be in a range between about 0.9 and 1.1. In other words, after the patterning process, the thickness of dielectric layer 220A and the thickness of dielectric layer 214 (in logic region 205) can be substantially the same. In some examples, and after the patterning process (block 110), the thickness of dielectric layer 220A and dielectric layer 214 (in logic region 205) can be in a range between about 90-110 angstroms (e.g., such as about 100 angstroms). As another example, and again after the patterning process (block 110), the ratio of the thickness of dielectric layer 220A to the thickness of dielectric layer 214 (in the resistive region 207) can be in a range between about 0.4 and 0.6. In other words, after the patterning process, the thickness of dielectric layer 220A can be about half the thickness of dielectric layer 214 (in the resistive region 207). In some examples, and after the patterning process (block 110), the thickness of dielectric layer 220A can be in a range between about 90-110 angstroms (e.g., such as about 100 angstroms), and the thickness of dielectric layer 214 (in the resistive region 207) can be in a range between about 180-220 angstroms (e.g., such as about 200 angstroms). In some cases, if the ratio of the thickness of the dielectric layer 220A to the thickness of the dielectric layer 214 (within the resistive region 207) falls outside the range between about 0.4 and 0.6, the etch depth for a subsequent etching process (e.g., block 116 of method 100) may be difficult to control, and / or the dielectric layer 220A or the dielectric layer 214 may not provide sufficient electrical isolation or sufficient protection from stresses applied by adjacent layers, thereby potentially damaging the resistive layer 216. Furthermore, after the patterning process (block 110), and in some embodiments, the ratio of the thickness of the resistive layer 216 to the thickness of the dielectric layer 220A may be within the range between about 0.4 and 0.5. In some embodiments, if the thickness ratio of the resistive layer 216 to the dielectric layer 220A falls outside the range (after the patterning process), the etching depth of the subsequent via etching process (e.g., box 116 of method 100) may be difficult to control again, the resistance of the resistive layer may be too low to meet the target sheet resistance (e.g., if the resistive layer 216 is too thick), or the quality or reliability of the resistive layer and / or the dielectric layer 220A may be insufficient for certain applications (e.g., if the resistive layer 216 and / or the dielectric layer 220A are too thin).

[0038] The method proceeds to block 112 where a dielectric layer is deposited. Figure 3 and Figure 4 In one embodiment of block 112, a dielectric layer 402 is deposited on the device 200. In some embodiments, the dielectric layer 402 includes TEOS oxide, carbon-containing silicon oxide, silicon oxide, a porous dielectric material, undoped silicate glass or doped silicon oxide (e.g., BPSG, FSG, PSG, BSG), another suitable low-K or ultra-low-K dielectric material, one or more other suitable dielectric materials, or a combination thereof. The dielectric layer 402 may be deposited using a CVD process, an ALD process, a PVD process, one or more other suitable processes, or a combination thereof. In some embodiments, the material used to form the dielectric layer 402 is the same as the material used to form the dielectric layer 204. In some embodiments, the thickness of the dielectric layer 402 may be greater than about 1400 angstroms. For example, in one case, the thickness of the dielectric layer 402 may be about 1410 angstroms. In various embodiments, the thickness of the dielectric layer 402 may be selected to provide sufficient protection and formation space for the resistor element 216A and to provide sufficient separation (e.g., to avoid crosstalk) between metal lines of adjacent layers within the multi-layer metal interconnect structure. For example, in some embodiments, the distance between a given metal interconnect layer 'Mx' and a vertically adjacent metal interconnect layer 'Mx+1' may be equal to at least about 1500 angstroms.

[0039] The method proceeds to block 114 where an antireflective coating and a barrier layer are deposited. Figure 4In one embodiment of block 114, an anti-reflective coating (ARC) 404 is deposited on dielectric layer 402, and a barrier layer 406 is deposited on ARC 404. In some embodiments, ARC 404 includes SiN, SiON, SiOC, SiCN, SiOCN, another suitable material, or a combination thereof. ARC 404 may be deposited using a CVD process, an ALD process, a PVD process, one or more other applicable processes, or a combination thereof. In some embodiments, barrier layer 406 includes TiN, TaN, a nitrogen-containing layer, another suitable material, or a combination thereof. Barrier layer 406 may be deposited using a CVD process, an ALD process, a PVD process, one or more other applicable processes, or a combination thereof. In some embodiments, the thickness of ARC 404 is in a range between about 270-330 angstroms (e.g., about 300 angstroms, for example). In some examples, the thickness of barrier layer 406 may be greater than the thickness of ARC 404. For example, in some embodiments, the thickness of the barrier layer may be in a range between about 340-420 angstroms (e.g., about 380 angstroms, for example). It should also be noted that due to the presence of patterned dielectric layer 220A, patterned second barrier layer 218A and resistive element 216A in resistive region 207, dielectric layer 402, ARC 404 and barrier layer 406 may include raised segments 408 within resistive region 207, which generally follow the contour of the underlying surface.

[0040] The method proceeds to block 116 where trenches for the conductive lines and conductive vias are formed. In some embodiments, the trenches for the conductive lines and vias may be formed using a suitable combination of photolithography and etching processes (eg, wet etching, dry etching, or a combination thereof). Figure 4 and Figure 5 As an example, in one embodiment of block 116, the trench formed in the logic region 205 includes a conductive trench portion 502 and a conductive via trench portion 504, the first trench formed in the resistor region 207 includes a conductive trench portion 506 and a conductive via trench portion 508, and the second trench formed in the resistor region 207 includes a conductive trench portion 510 and a conductive via trench portion 512.

[0041] In some embodiments, the conductive line trench portions 502, 506, 510 may be initially formed by etching through portions of the barrier layer 406, the ARC 404, and the dielectric layer 402. As an example, the conductive line trench portions 502, 506, 510 have a first width 'W1' and a first height 'H1'. In some examples, and due to the raised segment 408 within the resistance region 207, the conductive line trench portions 506, 510 may be offset by a vertical distance 'Z' relative to the conductive line trench portion 502. After forming the conductive line trench portions 502, 506, 510, and in some embodiments, the conductive via trench portions 504, 508, 512 may be formed. For example, the conductive via trench portion 504 may be formed by etching through another portion of the dielectric layer 402, and through portions of the dielectric layer 214 and the first barrier layer 212 to expose the top surface of the conductive feature 206. Conductive via trench portions 508, 512 are formed by etching through another portion of dielectric layer 402, and through portions of patterned dielectric layer 220A, patterned second barrier layer 218A, resistive element 216A, dielectric layer 214, and first barrier layer 212 to expose top surfaces of PSLs 208, 210. It is noted that the formation of conductive via trench portions 508, 512 also exposes sidewall surfaces of resistive element 216A.

[0042] Therefore, in the etching process for forming the conductive via trench portions 508, 512, the PSL 208, 210 can effectively act as an etch stop layer. In various embodiments, the material used for the PSL 208, 210 (e.g., such as aluminum, copper, etc.) can have a different (e.g., lower) etching rate than one or more layers formed on the PSL 208, 210 (e.g., such as the dielectric layer 214, the first barrier layer 212 and / or other layers located on the PSL 208, 210), thereby providing an etch stop function of the PSL 208, 210. It should be noted that etching through the layers to form the conductive line trench portions and the conductive via trench portions can be equivalently referred to as "punching through" the layers. Therefore, the etch stop function of the PSL 208, 210 can be equivalently referred to as a punch-through stop function. Compared to at least some prior art embodiments, in which the conductive vias terminate at some uncertain and varying locations within the resistor element, by having the conductive via trench portions 508, 512 completely penetrate the resistor element and stop on the underlying PSL 208, 210, the via recess depth variation problem can be ignored while improving resistance uniformity. It is also noted that the conductive via trench portions 504, 508, 512 have a second width 'W2'. In some cases, the second width 'W2' is less than the first width 'W1'. In some cases, the conductive via trench portion 504 has a second height 'H2' and the conductive via trench portions 508, 512 have a third height 'H3', wherein the third height 'H3' is greater than the second height 'H2'.

[0043] The method proceeds to block 118 where a metal deposition process is performed. Figure 5 and Figure 6 In one embodiment of block 118, a metal layer 602 is deposited on the device 200 and in each of the conductive trench portions 502, 506, 510 and the conductive via trench portions 504, 508, 512 formed at block 116. The deposited metal layer 602 thus contacts the exposed top surface of the conductive feature 206, the exposed sidewall surface of the resistive element 216A (providing contact for the resistive element 216A), and the exposed top surface of the PSL 208, 210. In some cases, the metal layer 602 includes copper. In some cases, the metal layer 602 includes another conductive material, such as aluminum, cobalt, tungsten, titanium, nickel, gold, platinum, silicide, another suitable conductive material, or a combination thereof. In some examples, the metal layer 602 can be deposited by electrochemical deposition, or electrochemical plating (e.g., electroplating). Additionally, the metal layer 602 may be deposited using a CVD process, an ALD process, a PVD process, an electroless plating process, one or more other suitable processes, or a combination thereof. In some cases, the material used for the metal layer 602 may be the same as the material used for the conductive feature 206 and one or both of the PSLs 208, 210. Additionally, the material used for the metal layer 602 may be different than the material used for the conductive feature 206 and the PSLs 208, 210.

[0044] In some embodiments, a barrier layer may also be formed between the metal layer 602 and the sidewalls / bottom surfaces of the conductive line trench portions 502, 506, 510 and the conductive via trench portions 504, 508, 512 to prevent diffusion of the metal layer 602. For example, the barrier layer may be deposited on the sidewalls and bottom surfaces of the conductive line trench portions 502, 506, 510 and the conductive via trench portions 504, 508, 512 before depositing the metal layer 602. Such a barrier layer, if present, may include tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof.

[0045] The method proceeds to block 120 where a planarization process is performed. Figure 6 and Figure 7As an example, in an embodiment of block 120, a CMP process (planarization process) may be performed to remove excess portions of metal layer 602 from the exterior of the trenches (conductor trench portions 502, 506, 510 and conductive via trench portions 504, 508, 512) and planarize the top surface of device 200. The CMP process may also remove the remaining portions of ARC 404 and barrier layer 406 while exposing the top surface of dielectric layer 402. In particular, the deposition of metal layer 602 and the subsequent CMP process serve to form conductive line 702 connected to conductive via 704, conductive line 706 connected to conductive via 708, and conductive line 710 connected to conductive via 712. In various embodiments, a first electrical connection is provided to resistor element 216A through conductive line 706 and conductive via 708, and a second electrical connection is provided to resistor element 216A through conductive line 710 and conductive via 712. In addition, a separate electrical connection is provided to the conductive feature 206 by way of the conductive line 702 and the conductive via 704. After the CMP process, the top surface of the conductive lines 702, 706, 710 and the top surface of the dielectric layer 402 may be substantially coplanar. In various embodiments, the conductive feature 206 may be formed in a metal interconnect layer 'Mx', and the conductive lines 702, 706, 710 may be formed in a vertically adjacent metal interconnect layer 'Mx+1'. In addition, the PSL 208, 210 may be formed in the same metal interconnect layer 'Mx' as the conductive feature 206.

[0046] It is also noted that the resistive element 216A can be electrically connected to adjacent metal lines and / or vias to activate (e.g., to include as part of an active circuit) the resistive element 216A. For example, a first end of the resistive element 216A can be connected to the conductive component 206 (in metal interconnect level 'Mx') via a conductive line 706 and a conductive via 708 coupled to the first end of the resistive element 216A, a conductive line 702 and a conductive via 704 coupled to the conductive component 206, and one or more horizontal and / or vertical interconnect lines coupling the conductive line 706 to the conductive line 702. Similarly, a second end of the resistive element 216A can be connected to another conductive component via a conductive line 710 and a conductive via 712 coupled to the second end of the resistive element 216A, a conductive line and a conductive via coupled to another conductive component, and one or more horizontal and / or vertical interconnect lines coupling the conductive line 710 to a conductive line connected to another conductive component.

[0047] The semiconductor device 200 may be further processed to form various components and regions known in the art. For example, subsequent processing may form additional conductive vias, wires, resistor elements, barrier layers, interlayer dielectrics, or other appropriate layers on the substrate 202. In a further example, the multilayer metal interconnect structure disclosed herein may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. Various interconnect components may be made of various conductive materials, including copper, tungsten, silicide, or other conductive materials disclosed above. In one example, damascene and / or dual damascene processes are used to form the disclosed multilayer metal interconnect structure. In addition, additional process steps may be implemented before, during, and after the method 100, and some of the process steps described above may be replaced or eliminated according to various embodiments of the method 100. In addition, although the method 100 has been shown and described as including a single resistor element, it will be understood that other device configurations are possible. In some embodiments, the method 100 may be used to manufacture a device 200 including multiple resistor elements.

[0048] Now refer to Figure 8 , which shows Figure 7 FIG. 2 is a top view of the resistive region 207 of the device 200 shown. Figure 7 The cross-sectional view of the resistor region 207 shown in FIG. Figure 8 For clarity of discussion, some layers are omitted from the top view of the resistor region 207. In particular, the top view of the resistor region 207 shows the resistor element 216A, PSL 208, 210, conductive via 708, and conductive via 712. Figure 8 As shown in the top view of FIG. 1 , each of the PSLs 208, 210 may have three sides substantially aligned with the three bottom sides of the resistor element 216A. As described above, each of the conductive vias 708, 712 provides electrical contact to the resistor element 216A. It should also be noted that the top view shape / area of ​​the resistor element 216A, for example, Figure 8 As shown, it can be defined in the patterning process of the above-mentioned frame 110. Generally speaking, as the top view area of ​​the resistor element increases, the resistance value of the resistor element increases. As an example, Figure 7 and Figure 8 Also shown is an exemplary current flow 'IR' direction from the conductive / voltage line through and through the resistive element 216A during operation of the device 200.

[0049] In some embodiments, the top-view area 'W3 x L1' of the resistor element 216A can be in the range of about 0.1 microns x 0.1 microns to about 2 microns x 24 microns. In addition, the number of conductive vias (e.g., such as conductive vias 708, 712) used to contact the resistor element 216A at each end of the resistor element 216A and the area of ​​each conductive via 'W5×L3' will depend on the size (e.g., top-view area) of the resistor element 216A. As an example, the conductive via length 'L3' can be equal to less than half of the length 'L1' of the resistor element 216A. Therefore, in some embodiments, the conductive via length 'L3' can be in the range of less than about 0.05 microns to less than about 12 microns. Similarly, the area of ​​each 'W4×L2' in the PSL208, 210 will depend on the size (e.g., top-view area) of the resistor element 216A. In one example, the width 'W4' of the PSL 208, 210 can be substantially the same as the width 'W3' of the resistor element 216A, and the length 'L2' of the PSL 208, 210 can also be equal to less than half the length 'L1' of the resistor element 216A, while being greater than the conductive via length 'L3'. Thus, in some cases, the length 'L2' of the PSL 208, 210 can be in a range of less than about 0.05 microns to less than about 12 microns. In various cases, the width 'W5', the length 'L3', and the number of conductive vias contacting the resistor element 216A at both ends of the resistor element 216A are selected to provide sufficient overlap of the PSL 208, 210 with the conductive vias (e.g., as viewed in a top view), thereby ensuring that the conductive vias fall on the PSL 208, 210 with sufficient margin between the edges of the conductive vias and the edges of the PSL 208, 210.

[0050] In addition, although Figure 8 The example of FIG. 2 shows two vias (conductive vias 708, 712) in contact with the resistor element 216A (e.g., one at each end of the resistor element 216A), but more vias may be used. For example, for a resistor element having a larger top-view shape / area, more vias may be used in contact with the resistor element (e.g., at each end of the resistor element). As an example only, and with reference to FIG. 2 , ... Fig. 9 For example, an array of three (3) vias (conductive vias 902, 904, 906) can be formed to contact each end of the resistor element 916A, wherein each of the plurality of conductive vias 902, 904, 906 stops on and contacts the underlying punch-stop layer 908, 910. In some cases, the number of conductive vias formed to contact each end of the resistor element can be between about 1 conductive via and 15 conductive vias. It should also be noted that as the top view area of ​​the resistor element increases and / or the number of conductive vias contacting the resistor element increases, the top view area of ​​the PSL can also increase accordingly.

[0051] As mentioned above Figure 8 and 9 The exemplary top view of the resistor region 207 shown and discussed is not meant to be limiting, and other shapes and / or relative sizes of the various elements depicted therein may also be used without departing from the scope of the present disclosure. Figure 10-13 , which shows a top view of the resistor region 207, wherein the PSLs 208, 210 are sized differently relative to the conductive vias 708, 712 and the resistor element 216A (e.g., Figure 8 ). Fig.10 In the example of FIG. 1 , the width 'W4' and length 'L2' of PSL 208, 210 may be increased (e.g., with Figure 8 210) such that none of the sides are aligned with the bottom side of the resistor element 216A. In this example, the width 'W4' of the PSL 208, 210 is greater than the width 'W3' of the resistor element 216A, and the length 'L2' of the PSL 208, 210 has been increased such that the PSL 208, 210 overlaps the end of the resistor element 216A by a dimension 'D1'. In some examples, the dimension 'D1' is substantially equal to the difference between the width 'W4' and the width 'W3'. Fig.11 In the example, the width 'W4' of the PSLs 208, 210 has been increased (e.g., with Figure 8 210) such that the side edges of each of the PSLs 208, 210 are aligned with the bottom layer side edges of the resistor element 216A (while the lateral side edges of the PSLs 208, 210 are not aligned with the side edges of the resistor element 216A). In this example, the width 'W4' of the PSLs 208, 210 is greater than the width 'W3' of the resistor element 216A. Fig.12 In the example of FIG. 1 , the width 'W4' and length 'L2' of PSL 208, 210 may be reduced (e.g., with Figure 8 210) such that none of the sides are aligned with the bottom side of the resistor element 216A. In this example, the width 'W4' of the PSL 208, 210 is less than the width 'W3' of the resistor element 216A, and the length 'L2' of the PSL 208, 210 has been reduced such that the PSL 208, 210 pushes the end of the resistor element 216A down by a dimension 'D2'. In some examples, the dimension 'D2' is substantially equal to the difference between the width 'W4' and the width 'W3'. Fig.13 In the example, the width 'W4' of PSL 208, 210 has been reduced (e.g., with Figure 8210) such that the side edges of each of the PSLs 208, 210 are aligned with the bottom layer side edges of the resistor element 216A (while the lateral side edges of the PSLs 208, 210 are not aligned with the side edges of the resistor element 216A). In this example, the width 'W4' of the PSLs 208, 210 is less than the width 'W3' of the resistor element 216A.

[0052] refer to Figure 14-15 , which shows a top view of the resistor region 207, wherein the resistor element 216A has a different shape (e.g., Figure 8 ). Fig.14 In the example, the resistor element 216A has a serpentine pattern. In some embodiments, and for a resistor region 207 having a fixed area, the serpentine pattern resistor can provide a greater resistance than a linear resistor (e.g., Figure 8 ). Fig.15 In the example of FIG. 2 , the resistor element 216A has an L-shaped pattern. It should be noted that in some cases, a resistor having a bend (e.g. Fig.14 A serpentine pattern resistor or Fig.15 The electrical properties (e.g., resistance value) of a serpentine or L-shaped pattern resistor) may be difficult to control because of current crowding effects that occur at the bends of the resistive element 216A. Furthermore, it will be appreciated that in some cases, the various linear segments of a serpentine or L-shaped pattern resistor may have different dimensions (e.g., such as segment length) or the same dimensions, and that adjacent segments (e.g., segments of a serpentine pattern resistor) may be aligned or not aligned.

[0053] Reference Figure 16-18 , which shows a top view of the resistor region 207, wherein the PSL 208, 210 and / or the conductive vias 708, 712 have a circular / oval shape (e.g., Figure 8 In contrast to the embodiment in which the PSL 208, 210 and the conductive vias 708, 712 have a square / rectangular shape). Fig.16 In the example of FIG. 1 , the conductive vias 708 , 712 have a circular / oval shape, while the PSLs 208 , 210 have a square / rectangular shape. Fig.17 In the example of FIG. 1 , the conductive vias 708 , 712 have a square / rectangular shape, while the PSLs 208 , 210 have a circular / elliptical shape. Fig.18 In the example of FIG. 1 , the conductive vias 708, 712 and the PSLs 208, 210 all have a circular / oval shape. In some embodiments, for example, when the PSLs 208, 210 have a circular / oval shape, the edges of the PSLs 208, 210 may overlap or underlap the edges of the resistive element 216A (e.g., similar to Figure 10-13). Furthermore, in some examples, when the PSL 208, 210 has a circular / oval shape, the diameter of the PSL 208, 210 can be substantially the same as the width 'W3' of the resistive element 216A discussed above.

[0054] With respect to the description provided herein, a structure and related methods for forming a semiconductor device including a resistor element with enhanced uniformity are disclosed. In order to solve the problem of groove depth variation existing in some existing embodiments, embodiments of the present disclosure provide a PSL located below the resistor element and directly below the conductive via for contacting the resistor element. In various embodiments, the conductive via penetrates the resistor element (and one or more other layers) and stops on the PSL. Therefore, instead of allowing the conductive via to terminate at some uncertain and variable positions within the resistor element, it is better to allow the conductive vias contacting the resistor element to completely pass through the resistor element they are contacted with and stop on the bottom PSL. Therefore, the problem of through-hole groove depth variation can be ignored while improving the uniformity of resistance, particularly for high-scale resistor sizes. It will be readily appreciated by those skilled in the art that the methods and structures described herein can be applied to various other semiconductor devices to advantageously obtain similar advantages from these other devices without departing from the scope of the present disclosure.

[0055] Thus, one of the embodiments of the present disclosure describes a method comprising forming a conductive component and a first through-stop layer, wherein the conductive component has a first top surface, and the first through-stop layer has a second top surface substantially horizontal to the first top surface. The method further comprises forming a resistive element on the first through-stop layer. The method further comprises etching through a first portion of the resistive element to form a first trench, the trench simultaneously exposing the second top surface of the first through-stop layer and a first sidewall surface of the resistive element. The method further comprises forming a first conductive via in the first trench, wherein the first conductive via contacts the first sidewall surface of the resistive element.

[0056] In another embodiment, a method is discussed, including forming a first punch-stop layer and a second punch-stop layer in a first dielectric layer located on a substrate, wherein the first and second punch-stop layers are substantially horizontal to each other. The method also includes depositing a plurality of layers on the first and second punch-stop layers, the plurality of layers including a resistive layer. The method also includes forming a first trench exposing the first punch-stop layer and a second trench exposing the second punch-stop layer. The method also includes forming a first conductive via in the first trench and forming a second conductive via in the second trench, wherein the first conductive via contacts a first region of the resistive layer, and the second conductive via contacts a second region of the resistive layer.

[0057] In another embodiment, a semiconductor device is discussed, including a first metal line and a first through-stop layer having a second top surface substantially level with the first metal line. The semiconductor device also includes a resistor element located on the first through-stop layer, and a first conductive via contacting both the first top surface of the first through-stop layer and the first sidewall surface of the resistor element.

[0058] An embodiment of the present application provides a method for manufacturing a semiconductor device, comprising: forming a conductive component and a first through-stop layer, wherein the conductive component has a first top surface, and wherein the first through-stop layer has a second top surface substantially flush with the first top surface; forming a resistor element above the first through-stop layer; etching through a first portion of the resistor element to form a first trench, the first trench exposing the second top surface of the first through-stop layer and a first sidewall surface of the resistor element; and forming a first conductive via in the first trench, wherein the first conductive via contacts the first sidewall surface of the resistor element. In some embodiments, the conductive component is formed in a logic region of the semiconductor device, and wherein the first through-stop layer is formed in a resistor region of the semiconductor device. In some embodiments, the conductive component provides a portion of a multi-layer metal interconnect structure. In some embodiments, the conductive component and the first through-stop layer are formed in the same metal interconnect level of the multi-layer metal interconnect structure. In some embodiments, it also includes: before forming the resistor element, forming a resistor layer on both the conductive component and the first through-stop layer; and patterning the resistor layer to remove a portion of the resistor layer located above the conductive component and forming a resistor element above the first through-stop layer. In some embodiments, the present invention further includes: before forming the resistor element, forming a second through-stop layer, wherein the second through-stop layer has a third top surface, and the third top surface is substantially flush with the first top surface and the second top surface. In some embodiments, the present invention further includes: before forming the first conductive via, etching through the second portion of the resistor element to form a second trench, the second trench exposing both the third top surface of the second through-stop layer and the second sidewall surface of the resistor element; and forming a second conductive via in the second trench, wherein the second conductive via contacts the second sidewall surface of the resistor element. In some embodiments, the present invention further includes: before etching through the first portion of the resistor element, depositing a dielectric layer above the resistor element; etching through both the portion of the dielectric layer and the first portion of the resistor element to form the first trench; forming the first conductive via in the first trench; and forming a first conductor in the first trench above the first conductive via. In some embodiments, it also includes: before forming the resistor element, forming a first barrier layer above the first punch-stop layer; before etching through the first portion of the resistor element, forming a second barrier layer above the resistor element; etching through a portion of the first barrier layer, a portion of the second barrier layer, and the first portion of the resistor element to form a first trench; and forming a first conductive via in the first trench.

[0059] Another aspect of the present application provides a method for manufacturing a semiconductor device, comprising: forming a first punch-through stop layer and a second punch-through stop layer in a first dielectric layer disposed above a substrate, wherein the first punch-through stop layer and the second punch-through stop layer are substantially flush with each other; depositing a plurality of layers above the first punch-through stop layer and the second punch-through stop layer, the plurality of layers including a resistive layer; forming a first trench exposing the first punch-through stop layer and a second trench exposing the second punch-through stop layer; and forming a first conductive via in the first trench and a second conductive via in the second trench, wherein the first conductive via contacts a first region of the resistive layer, and wherein the second conductive via contacts a second region of the resistive layer. In some embodiments, the substrate comprises a transistor device. In some embodiments, forming the first trench comprises etching through a first portion of the plurality of layers to expose a first sidewall surface of the first punch-through stop layer and the plurality of layers, and wherein forming the second trench comprises etching through a second portion of the plurality of layers to expose a second sidewall surface of the second punch-through stop layer and the plurality of layers. In some embodiments, the method further includes: before forming the first trench and the second trench, patterning the resistor layer to remove the portion of the resistor layer outside the resistor region, and forming a resistor element above the first punch-through stop layer and the second punch-through stop layer. In some embodiments, the plurality of layers further include a barrier layer and a tetraethyl orthosilicate (TEOS) oxide layer disposed above and below the resistor layer. In some embodiments, the first punch-through stop layer and the second punch-through stop layer have an etching rate lower than one or more layers of the plurality of layers. In some embodiments, the method further includes: before depositing the plurality of layers, forming a conductive component within the first dielectric layer and within the logic region, wherein the conductive component, the first punch-through stop layer, and the second punch-through stop layer are substantially flush with each other, wherein the conductive component provides a portion of a multilayer metal interconnect structure, and wherein the first punch-through stop layer and the second punch-through stop layer are formed within a resistor region adjacent to the logic region.

[0060] An embodiment of the present application also provides a semiconductor device, comprising: a first metal line; a first punch-through stop layer, wherein the first top surface of the first punch-through stop layer is substantially flush with the second top surface of the first metal line; a resistor element, which is disposed above the first punch-through stop layer; and a first conductive via, which contacts both the first top surface of the first punch-through stop layer and the first sidewall surface of the resistor element. In some embodiments, the first punch-through stop layer comprises Al, Cu, or a combination thereof. In some embodiments, it further comprises: a second metal line, which contacts the first conductive via, wherein the second metal line is disposed in a metal interconnect layer above the first metal line. In some embodiments, it further comprises: a second punch-through stop layer, which has a third top surface substantially flush with the first top surface and the second top surface, wherein the first punch-through stop layer and the second punch-through stop layer are disposed below opposite ends of the resistor element; and a second conductive via, which contacts both the third top surface of the second punch-through stop layer and the second sidewall surface of the resistor element.

[0061] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should recognize that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a conductive feature and a first punch-through stop layer, wherein the conductive feature has a first top surface, and wherein the first punch-through stop layer has a second top surface substantially flush with the first top surface; forming a resistance element over the first punch-through stop layer; etching through a first portion of the resistor element to form a first trench, the first trench exposing the second top surface of the first punch-through stop layer and a first sidewall surface of the resistor element; forming a first conductive via in the first trench, wherein the first conductive via contacts the first sidewall surface of the resistor element; and A third conductive via is formed in contact with the first top surface of the conductive feature, wherein a top edge of the first conductive via is vertically offset from a top edge of the third conductive via.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The conductive feature is formed in a logic region of the semiconductor device, and wherein the first punch-through stop layer is formed in a resistor region of the semiconductor device.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The conductive features provide part of a multi-layer metal interconnect structure.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The conductive feature and the first punch-through stop layer are formed within a same metal interconnect level of the multi-layer metal interconnect structure.

5. The method for manufacturing a semiconductor device according to claim 1, further comprising: before forming the resistance element, forming a resistance layer on both the conductive member and the first punch-through stop layer; as well as The resistor layer is patterned to remove a portion of the resistor layer above the conductive feature and to form a resistor element above the first punch-through stop layer.

6. The method for manufacturing a semiconductor device according to claim 1, further comprising: Before forming the resistance element, a second punch-through stop layer is formed, wherein the second punch-through stop layer has a third top surface that is substantially flush with the first top surface and the second top surface.

7. The method for manufacturing a semiconductor device according to claim 6, further comprising: before forming the first conductive via, etching through a second portion of the resistive element to form a second trench, the second trench exposing both the third top surface of the second punch-through stop layer and a second sidewall surface of the resistive element; as well as A second conductive via is formed in the second trench, wherein the second conductive via contacts the second sidewall surface of the resistor element.

8. The method for manufacturing a semiconductor device according to claim 1, further comprising: depositing a dielectric layer over the resistive element prior to etching through the first portion of the resistive element; etching through both the portion of the dielectric layer and the first portion of the resistive element to form the first trench; forming the first conductive via in the first trench; as well as A first conductive line is formed in a first trench above the first conductive via.

9. The method for manufacturing a semiconductor device according to claim 1, further comprising: Before forming the resistance element, forming a first barrier layer over the first punch-through stop layer; forming a second barrier layer over the resistive element before etching through the first portion of the resistive element; etching through a portion of the first barrier layer, a portion of the second barrier layer, and the first portion of the resistive element to form a first trench; as well as A first conductive via is formed in the first trench.

10. A method for manufacturing a semiconductor device, comprising: forming a first punch-through stop layer and a second punch-through stop layer in a first dielectric layer disposed above the substrate, wherein the first punch-through stop layer and the second punch-through stop layer are substantially flush with each other; depositing a plurality of layers over the first and second punch-stop layers, the plurality of layers including a resistive layer; forming a first trench exposing the first punch-through stop layer and a second trench exposing the second punch-through stop layer; forming a first conductive via in the first trench and forming a second conductive via in the second trench, wherein the first conductive via contacts a first region of the resistive layer, and wherein the second conductive via contacts a second region of the resistive layer; forming a conductive feature in the first dielectric layer, a top surface of the conductive feature being flush with a top surface of the first punch-through stop layer; and A third conductive via is formed in contact with the conductive feature, wherein top edges of the first conductive via and the second conductive via are vertically offset from a top edge of the third conductive via.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The substrate includes a transistor device.

12. The method for manufacturing a semiconductor device according to claim 10, wherein the forming of the first trench comprises etching through a first portion of the multiple layers to expose the first punch-through stop layer and a first sidewall surface of the multiple layers, and wherein the forming of the second trench comprises etching through a second portion of the multiple layers to expose the second punch-through stop layer and a second sidewall surface of the multiple layers.

13. The method for manufacturing a semiconductor device according to claim 10, further comprising: Before forming the first trench and the second trench, the resistance layer is patterned to remove a portion of the resistance layer outside the resistance region, and a resistance element is formed over the first through stop layer and the second through stop layer.

14. The method for manufacturing a semiconductor device according to claim 10, wherein: The plurality of layers also includes a barrier layer and a tetraethyl orthosilicate (TEOS) oxide layer disposed above and below the resistive layer.

15. The method for manufacturing a semiconductor device according to claim 10, wherein: The first and second punch-through stop layers may have lower etching rates than one or more of the plurality of layers.

16. The method for manufacturing a semiconductor device according to claim 10, wherein: Prior to depositing the plurality of layers, the conductive feature is formed within the first dielectric layer and within a logic region, wherein the conductive feature, the first punch-through stop layer, and the second punch-through stop layer are substantially flush with one another, wherein the conductive feature provides a portion of a multi-layer metal interconnect structure, and wherein the first punch-through stop layer and the second punch-through stop layer are formed within a resistor region adjacent to the logic region.

17. A semiconductor device comprising: a first metal wire; a first punch-through stop layer, wherein a first top surface of the first punch-through stop layer is substantially flush with a second top surface of the first metal line; a resistance element, disposed above the first punch-through stop layer; a first conductive via contacting both the first top surface of the first punch-stop layer and a first sidewall surface of the resistive element; as well as A third conductive via contacts the second top surface of the first metal line, wherein a top edge of the first conductive via is vertically offset from a top edge of the third conductive via.

18. The semiconductor device according to claim 17, wherein: The first punch-through stop layer includes Al, Cu or a combination thereof.

19. The semiconductor device according to claim 17, further comprising: A second metal line contacts the first conductive via, wherein the second metal line is disposed in a metal interconnection layer above the first metal line.

20. The semiconductor device according to claim 17, further comprising: a second punch-stop layer having a third top surface substantially flush with the first top surface and the second top surface, wherein the first punch-stop layer and the second punch-stop layer are disposed below opposite ends of the resistor element; as well as A second conductive via contacts both the third top surface of the second punch-through stop layer and the second sidewall surface of the resistance element.

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