Semiconductor device and method for manufacturing the same

Abstract

According to some embodiments, a semiconductor device includes a semiconductor substrate, at least one semiconductor fin, and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion, and a first neck portion located between the first portion and the second portion. The width of the first portion decreases as the first portion becomes closer to the first neck portion, and the width of the second portion increases as the second portion becomes closer to the bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same. Background Art

[0002] As the size of semiconductor devices continues to scale down, three-dimensional multi-gate structures (e.g., fin-type field effect transistors (FinFETs)) have been developed to replace planar Complementary Metal Oxide Semiconductor (CMOS) devices. The FinFET device is characterized in that this structure has one or more silicon-based fins surrounded by a gate to define the channel of the device. The gate surrounding structure also provides better electrical control of the channel. Summary of the Invention

[0003] Embodiments of the present invention provide a semiconductor device including a semiconductor substrate, at least one semiconductor fin, and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion, and a first neck portion located between the first portion and the second portion. The width of the first portion decreases as the first portion becomes closer to the first neck portion, and the width of the second portion increases as the second portion becomes closer to the bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.

[0004] Embodiments of the present invention provide a semiconductor device including a semiconductor substrate, at least one semiconductor fin, and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The sidewall of the semiconductor fin includes a zigzag portion. The gate stack partially covers the semiconductor fin.

[0005] Embodiments of the present invention provide a method of manufacturing a semiconductor device including at least the following steps. Forming a plurality of openings in a semiconductor substrate. Performing at least one etching cycle on the plurality of openings to form a plurality of trenches and at least one semiconductor fin located between the trenches. The etching cycle includes: forming a plurality of polymer layers on the surface of the openings; performing a first etching process on the openings; and performing a second etching process on the openings while the upper sidewalls of the openings are covered by by-products formed during the first etching process. Forming a plurality of insulators in the trenches. Forming a gate stack to partially cover the semiconductor fin and the insulators. Brief Description of the Drawings

[0006] Various aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1Q is a perspective view showing various stages of a method of manufacturing a semiconductor device in accordance with some embodiments of the present disclosure.

[0008] Figure 2 is along Figure 1H a cross-sectional view of the semiconductor device taken along line I-I' shown. Detailed Description

[0009] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0010] Furthermore, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0011] The fin can be patterned by any suitable method. For example, one or more lithography processes including double patterning process or multiple patterning process can be used to pattern the fin. Generally, the double patterning process or multiple patterning process combines the lithography process with a self - aligned process, so that the pattern to be generated has a pitch smaller than, for example, the pitch that could be obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and the sacrificial layer is patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self - aligned process. Then the sacrificial layer is removed, and then the remaining spacer can be used to pattern the fin.

[0012] Figures 1A to 1Q is a perspective view showing various stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. Referring to Figure 1A , a semiconductor substrate 200 is provided. In some embodiments, the semiconductor substrate 200 can be a bulk semiconductor substrate, a semiconductor - on - insulator (SOI) substrate, etc. Generally, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate (usually a silicon or glass substrate). Other substrates can also be used, such as a multi - layer substrate or a gradient substrate.

[0013] In some embodiments, the semiconductor substrate 200 includes a crystalline silicon substrate (e.g., a wafer). In some alternative embodiments, the semiconductor substrate 200 can be made of: some other suitable elemental semiconductors, such as diamond or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; or suitable alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. Depending on design requirements (e.g., a p - type semiconductor substrate or an n - type semiconductor substrate), the semiconductor substrate 200 can include various doped regions. In some embodiments, the doped regions can be doped with a p - type dopant or an n - type dopant. For example, the doped regions can be doped with: a p - type dopant, such as boron or BF 2 ; an n - type dopant, such as phosphorus or arsenic; and / or a combination thereof. In some embodiments, the dopant concentration can be equal to or less than 10 18 cm -3 , for example, between about 10 17 cm -3 and about 10 18 cm -3within a range. Depending on the dopant type, an n-type FinFET or a p-type FinFET may be formed on the semiconductor substrate 200 in subsequent processes. In some embodiments, the dopant concentrations in various doped regions may be different.

[0014] In some embodiments, a dielectric layer 202 is formed on the semiconductor substrate 200. In some embodiments, the dielectric layer 202 may include silicon oxide, silicon nitride, or silicon oxynitride. The dielectric layer 202 can be formed using suitable processes such as Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), thermal oxidation, UV-ozone oxidation, or a combination thereof.

[0015] In some embodiments, a patterned cushion layer 204a and a patterned mask layer 204b are sequentially formed on the dielectric layer 202. The patterned cushion layer 204a and the patterned mask layer 204b can be formed by sequentially forming a cushion layer and a mask layer on the dielectric layer 202 and then etching the cushion layer and the mask layer using a patterned photoresist layer. In some embodiments, the material of the patterned mask layer 204b is silicon oxide, silicon nitride, silicon oxide / silicon nitride / silicon oxide, silicon nitride / silicon oxide / silicon nitride, and combinations thereof. The patterned cushion layer 204a can be a silicon oxide thin film formed by, for example, a thermal oxidation process. In some embodiments, the patterned cushion layer 204a can act as an adhesion layer between the semiconductor substrate 200 and the patterned mask layer 204b. In some embodiments, the patterned cushion layer 204a can also act as an etch stop layer for etching the patterned mask layer 204b. In some embodiments, the patterned mask layer 204b can be a silicon nitride layer formed by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). In some alternative embodiments, the patterned mask layer 204b can be formed by thermal nitridation of silicon. The patterned mask layer 204b is used as a hard mask during subsequent lithography processes.

[0016] Refer to Figures 1B to 1H , a plurality of trenches 220 and a plurality of semiconductor fins 230 located between the trenches 220 are formed. First, as Figure 1BAs shown, by using the patterned mask layer 204b and the patterned cushion layer 204a as masks, a portion of the semiconductor substrate 200 is etched to form a plurality of openings 206-1. In some embodiments, a portion of the dielectric layer 202 is etched simultaneously with the semiconductor substrate 200. The semiconductor substrate 200 and the dielectric layer 202 can be etched by an isotropic etching process or an anisotropic etching process. For example, the semiconductor substrate 200 and the dielectric layer 202 can be etched by reactive ion etching (RIE), neutral beam etching (NBE), similar etching, or a combination thereof.

[0017] In some embodiments, Figure 1B the width-to-depth ratio of the openings 206-1 in [reference] ranges from 0.375 to 0.75. In some embodiments, the width of the openings 206-1 ranges from about 8 nm to about 16 nm. In some embodiments, the depth of the openings 206-1 ranges from about 3 nm to about 6 nm. Although Figure 1B the openings 206-1 are shown to have straight sidewalls, this configuration is only used as an exemplary illustration. In some alternative embodiments, the openings 206-1 may not have straight sidewalls. In other words, in some alternative embodiments, at least a portion of the sidewalls of the openings 206-1 is inclined or tapered.

[0018] Referring to Figures 1C to 1F , an etching cycle is performed. The etching cycle may include a flush process F, a first etching process E1, and a second etching process E2. First, as Figure 1C shown in [reference], a plurality of polymer layers 208 are formed on the surface of the openings 206-1 through the flush process F to form openings 206-2. In some embodiments, the flush process F can be performed by using a polymer gas (e.g., a gas containing SO 2 and O 2 ). During the flush process F, the polymer gas can react with the silicon of the semiconductor substrate 200 to form a silicon-containing polymer on the surface of the openings 206-1 (i.e., the surfaces of the sidewalls 206a and the bottom 206b). For example, when using a polymer gas containing SO 2 and O 2 , the polymer gas can react with silicon to form a SO 2 -S polymer. In some embodiments, the polymer layer 208 can be a SO 2 -S polymer layer. However, the present disclosure is not limited thereto. In some alternative embodiments, the polymer gas contains at least one of the elements nitrogen, carbon, oxygen, and hydrogen. For example, the polymer gas contains CO 2 and / or N 2 .

[0019] Refer to Figure 1D , and then perform a first etching process E1 on the opening 206-2 (i.e., the opening 206-1 with the polymer layer 208 thereon) to form an opening 206-3. The first etching process E1 can be an anisotropic etching with a vertical etching rate greater than the lateral etching rate. In some embodiments, the polymer layer 208 and the semiconductor substrate 200 at the sidewalls 206a and the bottom 206b of the opening 206-1 are etched away by the first etching process E1. The polymer layer 208 can protect the fin structure from being etched or damaged by lateral etching, thereby achieving better control of the fin profile. After performing the first etching process E1, compared with the opening 206-1 of Figure 1B , the opening 206-3 of Figure 1D can have more tapered sidewalls 206a and a deeper bottom 206b. In some embodiments, the width of the opening 206-3 ranges from about 8 nm to about 16 nm. In some embodiments, the depth of the opening 206-3 ranges from about 10 nm to about 18 nm. In some embodiments, the included angle θ formed between the sidewall 206a and the bottom 206b ranges from about 65 degrees to about 88 degrees. The opening 206-3 can have an inverted trapezoidal shape. In some embodiments, the first etching process E1 includes a halogen-based etchant. For example, the first etching process E1 is a chlorine-based or fluorine-based etching process. The chlorine-based etching process can use chlorine gas (Cl 2 ), boron trichloride gas (BCl 3 ) and / or silicon tetrachloride gas (SiCl 4 ), optionally mixed with nitrogen gas (N 2 ) or oxygen gas (O 2 ) and a noble gas (such as argon (Ar) or helium (He)). The fluorine-based etching process can use sulfur hexafluoride gas (SF 6 ), trifluoromethane gas (CHF 3 ) and / or carbon tetrafluoride gas (CF 4 ), optionally mixed with nitrogen gas (N 2 ) or oxygen gas (O 2 ) and a noble gas (such as argon (Ar) or helium (He)). However, the present disclosure is not limited thereto. In some alternative embodiments, other suitable etching processes are used.

[0020] Refer to Figure 1E and Figure 1F , and perform a second etching process E2 on the opening 206-3 of Figure 1D to form an opening 206-4. The second etching process E2 can be an isotropic etching with a vertical etching rate substantially the same as the lateral etching rate. It should be noted that during the second etching process E2, as Figure 1EAs shown, etch by-products can be continuously deposited on the upper portion 206a1 of the sidewall 206a of the opening 206-3 to form a protective layer 210. Due to the presence of the protective layer 210, the upper portion 206a1 of the sidewall 206a of the opening 206-4 can be substantially intact and not etched compared to the lower portion 206a2 of the sidewall 206a of the opening 206-3. In some embodiments, the second etch process E2 includes a halogen-based etchant. For example, the second etch process E2 is a chlorine-based or fluorine-based etch process. The chlorine-based etch process can use chlorine gas (Cl 2 ), boron trichloride gas (BCl 3 ), and / or silicon tetrachloride gas (SiCl 4 ), optionally mixed with nitrogen gas (N 2 ) or oxygen gas (O 2 ) and a noble gas (such as argon (Ar) or helium (He)). The fluorine-based etch process can use sulfur hexafluoride gas (SF 6 ), trifluoromethane gas (CHF 3 ), and / or carbon tetrafluoride gas (CF 4 ), optionally mixed with nitrogen gas (N 2 ) or oxygen gas (O 2 ) and a noble gas (such as argon (Ar) or helium (He)). The protective layer 210 can be a fluoropolymer layer. However, the present disclosure is not limited thereto. In some embodiments, the first etch process E1 uses the same etchant as the second etch process E2. In some embodiments, the first etch process E1 uses a different etchant from the second etch process E2. In some embodiments, the first etch process E1 is performed by a dry etch process or a wet etch process. In some embodiments, the second etch process E2 is performed by a dry etch process or a wet etch process. In some alternative embodiments, other suitable etch processes are used.

[0021] As Figure 1F shown, after performing the second etch process E2, the etch cycle ends, and the opening 206-5 is formed. In some embodiments, as Figure 1F shown, the opening 206-5 can include a portion 212 and a portion 214 connected to each other. For example, the portion 212 has an inverted trapezoidal shape, and the portion 214 has a diamond-shaped profile. In some embodiments, the portion 214 has a protruding portion PP1 on the sidewall. In some embodiments, the depth Dp1 of the protruding portion PP1 (i.e., the vertical distance between the protruding portion PP1 and the top surface of the semiconductor substrate 200) is in the range of about 20 nm to about 28 nm.

[0022] In some embodiments, after a first etching cycle is completed, another etching cycle (i.e., a second etching cycle) may be performed. In other words, the etching cycle is repeated. For example, a rinse process is performed on the opening 206-5 of Figure 1F to form a plurality of polymer layers (not shown) on the sidewall surface and the bottom surface of the opening 206-5. Thus, the opening 206-6 is formed. Then, a first etching process and a second etching process are sequentially performed on the opening. In some embodiments, after the second etching cycle is completed, as Figure 1G shown, a plurality of portions 216 are formed to connect to the portions 214 and 212 of the opening 206-6. The portion 216 may have a diamond-like profile similar to that of the portion 214. The portion 216 has a protruding portion PP2 on the sidewall of the portion 216. In some embodiments, the depth Dp2 of the protruding portion PP2 (i.e., the vertical distance between the protruding portion PP2 and the top surface of the semiconductor substrate 200) is in the range of about 50 nm to about 60 nm. In some embodiments, the etching cycle is performed twice. However, the present disclosure is not limited thereto. In some alternative embodiments, the etching cycle is performed once or more than twice. Additionally, in some alternative embodiments, the rinse process may be omitted in at least one etching cycle.

[0023] Figure 2 is a cross-sectional view of the semiconductor device taken along the line I-I' shown in Figure 1H . Referring to Figure 1H and Figure 2 , after the etching cycle is performed, the opening 206-6 of Figure 1G is deepened to a predetermined depth Dp using the patterned mask layer 204b and the patterned cushion layer 204a to form the opening 206-7. In some embodiments, a portion of the semiconductor substrate 200 is etched to form a plurality of portions 218. The semiconductor substrate 200 may be etched by an isotropic etching process or an anisotropic etching process. For example, the semiconductor substrate 200 may be etched by reactive ion etching (RIE), neutral beam etching (NBE), similar etching, or a combination thereof. In some embodiments, before the portions 218 are formed, a rinse process is performed to form a plurality of polymer layers on the surface of the opening 206-6 of Figure 1G . Although Figure 1H and Figure 2 show that the portion 218 has straight sidewalls and a flat bottom, this configuration is only used as an exemplary illustration. In some alternative embodiments, the portion 218 may not have straight sidewalls and / or a flat bottom. In other words, in some alternative embodiments, at least a portion of the sidewall of the portion 218 is inclined or tapered. Additionally, in some alternative embodiments, at least a portion of the bottom of the portion 218 is recessed.

[0024] AsFigure 1H and Figure 2 As shown in Figure 2 , after forming the portion 218, a trench 220 is formed, and semiconductor fins 230 are formed between the trenches 220. In other words, the configuration of the semiconductor fins 230 is defined by the profile of the trenches 220. In some embodiments, by performing at least one etching cycle, the trench 220 is formed to have protruding portions PP1, PP2. Correspondingly, the semiconductor fins 230 are formed to have neck portions NP1, NP2. In some embodiments, the semiconductor fins 230 have portions 232, 234, 236, and 238. The configurations of the portions 232, 234, 236, and 238 respectively correspond to the profiles of the portions 212, 214, 216, and 218. For example, the portion 232 has an inverted trapezoidal shape, the portion 234 has a narrow middle profile, the portion 236 has a narrow middle profile, and the portion 238 has a straight profile. The portions 234 and 236 have neck portions NP1, NP2. In some embodiments, the portion 234 includes a portion 234a (also referred to as the first portion), a portion 234b (also referred to as the second portion), and a neck portion NP1 (also referred to as the first neck portion) located between the portion 234a and the portion 234b. The width W a1 of the portion 234a decreases as the portion 234a gets closer to the neck portion NP1, and the width W b1 of the portion 234b increases as the portion 234b gets closer to the bottom surface 200a of the semiconductor substrate 200. Similarly, the portion 236 includes a portion 236a (also referred to as the third portion), a portion 236b (also referred to as the fourth portion), and a neck portion NP2 (also referred to as the second neck portion) located between the portion 236a and the portion 236b. The portions 236a and 236b are disposed between the portion 234b and the semiconductor substrate 200. The width W a2 of the portion 236a decreases as the portion 236a gets closer to the neck portion NP2, and the width W b2 of the portion 236b increases as the portion 236b gets closer to the bottom surface 200a of the semiconductor substrate 200.

[0025] As Figure 2 shown in Figure 2 , the neck portions NP1, NP2 cause the semiconductor fins 230 to have a significantly reduced width. In other words, the neck portions NP1, NP2 of the semiconductor fins 230 have a width W s1 that is smaller than those of the other portions, W s2 . In some embodiments, one of the widths W s1 of the semiconductor fins 230, W s2 can be the minimum width of the semiconductor fins 230. For example, the widths W s1 of the semiconductor fins 230, Ws2 is in the range of about 5 nm to 7 nm. The widths of portions 232, 238 are in the range of about 5 nm to 7 nm. The width W of the neck portions NP1, NP2 (also referred to as recessed portions) s1 , W s2 to the ratio of the widths of portions 232, 238 (also referred to as non-recessed portions) may be in the range of about 0.75 to 1. The necking profile is used to reduce I off current. When the ratio is less than 0.75, the risk of fin bending is high. When the ratio is greater than 1, I off reduction efficiency is low.

[0026] In some embodiments, as Figure 2 shown, the sidewall SW of the semiconductor fin 230 includes a zig-zag portion SWZ and a substantially vertical portion SWV. The substantially vertical portion SWV is substantially perpendicular (i.e., slightly inclined or slightly tapered) to the bottom surface 200a of the semiconductor substrate 200. The substantially vertical portion SWV may be physically connected to the zig-zag portion SWZ. In some embodiments, the substantially vertical portion SWV is disposed between the semiconductor substrate 200 and the zig-zag portion SWZ. In other words, the zig-zag portion SWZ forms the upper portion of the sidewall SW. However, the present disclosure is not limited thereto. In some alternative embodiments, the zig-zag portion SWZ forms the middle portion of the sidewall SW, that is, the zig-zag portion SWZ is disposed between the upper portion and the lower portion. The upper portion and / or the lower portion may be the substantially vertical portion SWV. In some embodiments, the ratio of the zig-zag portion SWZ to the sidewall SW (i.e., height ratio) is in the range of 1 / 3 to 1 / 2. Since leakage is likely to occur at about 1 / 3 to 1 / 2 of the fin of the fin field-effect transistor (FinFET) structure (e.g., fin height of 16 nm to 25 nm), the necking profile formed at about 1 / 3 to 1 / 2 of the fin of the FinFET structure can efficiently reduce leakage.

[0027] In some embodiments, the neck portion NP1 (i.e., the topmost neck portion) is configured to be adjacent to the turning point of the source / drain structure (i.e., the turning point TP of the source / drain structure 244 as Figure 1N shown). For example, when the height H of the semiconductor fin 230 is in the range of about 110 nm to about 120 nm, the distance between the neck portion NP1 and the top surface T1 of the semiconductor fin 230 is in the range of 24 nm to 28 nm. In other words, when the depth Dp of the trench 220 is in the range of about 110 nm to about 120 nm, the depth Dp1 of the protruding portion PP1 is in the range of 24 nm to 28 nm. Although Figure 1H and Figure 2It is shown that the semiconductor fin 230 has two neck portions NP1 and NP2, but this configuration is only used as an exemplary illustration. In some alternative embodiments, the semiconductor fin 230 may have only one neck portion or more than two neck portions. In other words, the etching cycle may be performed once or more than twice. In some embodiments, a P-well (not shown) or an N-well may be formed in the semiconductor fin 230 or the semiconductor substrate 200.

[0028] Referring Figure 1I , an insulating material 240 is formed over the semiconductor substrate 200. In some embodiments, the insulating material 240 fills the trenches 220 and covers the semiconductor fins 230, the patterned liner 204a, and the patterned mask layer 204b. The insulating material 240 may include silicon oxide, silicon nitride, silicon oxynitride, spin-on dielectric material, or a low-k dielectric material. A low-k dielectric material generally refers to a dielectric material having a dielectric constant lower than 3.9. The insulating material 240 may be formed by high-density-plasma chemical vapor deposition (HDPCVD), sub-atmospheric CVD (SACVD), spin coating, or other suitable processes.

[0029] Referring Figure 1J , a planarization process is performed on the insulating material 240. In some embodiments, a portion of the insulating material 240 is removed to form a polished insulating material 240'. The planarization process includes, for example, a chemical mechanical polish (CMP) process, an etch-back process, a combination thereof, and the like. In some embodiments, after the insulating material 240 is planarized, the top surface of the polished insulating material 240' is substantially coplanar with the top surface of the patterned mask layer 204b. In other words, the top surface of the semiconductor fin 230 is protected by the dielectric layer 202, the patterned liner 204a, and the patterned mask layer 204b and is not exposed.

[0030] Referring Figure 1K , the polished insulating material 240' filled in the trenches 220 is partially removed by an etching process to form a plurality of insulators 240a in the trenches 220. In some embodiments, the polished insulating material 240' may be etched away by a wet etching process using hydrofluoric acid (HF). As another option, the polished insulating material 240' may be etched away by a dry etching process using HF 3 gas and NH 3 gas. During the dry etching process, a plasma may be generated and may also include argon. As Figure 1KAs shown, each semiconductor fin 230 is sandwiched between two adjacent insulators 240a. In some embodiments, the top surface T2 of the insulator 240a is lower than the top surface T1 of the semiconductor fin 230. The top surface T2 of the insulator 240a may be lower than the neck portion NP2 (i.e., the bottommost neck portion). For example, the semiconductor fin 230 protrudes from the top surface T2 of the insulator 240a. In some embodiments, the height difference between the top surface T1 of the semiconductor fin 230 and the top surface T2 of the insulator 240a ranges from about 15 nm to about 50 nm. In some embodiments, the insulator 240a may be referred to as "Shallow Trench Isolation (STI)". In some embodiments, the top surface T2 of the insulator 240a may have a flat surface, a convex surface, a concave surface, or a combination thereof.

[0031] Referring to Figure 1L , a plurality of dummy gate structures 242 are formed over a portion of the semiconductor fin 230 and a portion of the insulator 240a. In some embodiments, the dummy gate structures 242 span the semiconductor fin 230. For example, the extending direction D1 of the dummy gate structures 242 may be perpendicular to the extending direction D2 of the semiconductor fin 230. In some embodiments, each dummy gate structure 242 includes a dummy gate dielectric layer 242a, a dummy gate 242b disposed over the dummy gate dielectric layer 242a, and a mask layer 242d disposed over the dummy gate 242b. In some embodiments, the dummy gate dielectric layer 242a is conformally formed over a portion of the insulator 240a and a portion of the semiconductor fin 230. In some embodiments, the dummy gate dielectric layer 242a may include silicon oxide, silicon nitride, or silicon oxynitride. The dummy gate dielectric layer 242a may be formed using a suitable process (such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, ultraviolet-ozone oxidation, or a combination thereof). The dummy gate dielectric layer 242a may be formed to separate the semiconductor fin 230 from the dummy gate 242b and serve as an etch stop layer.

[0032] As Figure 1LAs shown, dummy gate 242b is formed on dummy gate dielectric layer 242a. In some embodiments, dummy gate 242b can be a single-layer structure or a multi-layer structure. In some embodiments, dummy gate 242b comprises a silicon-containing material, such as polysilicon, amorphous silicon, or a combination thereof. In some embodiments, the thickness of dummy gate 242b ranges between 30 nm and 90 nm. Dummy gate 242b can be formed by a suitable process, such as ALD, CVD, PVD, plating, or a combination thereof. In some embodiments, mask layer 242d is formed on dummy gate 242b. In some embodiments, mask layer 242d can be formed of silicon nitride, silicon oxide, silicon carbonitride, a combination thereof, etc.

[0033] In addition to the dummy gate structure 242, a plurality of pairs of spacers 242c are also formed over a portion of the semiconductor fin 230 and a portion of the insulator 240a. As Figure 1L shown, spacers 242c are disposed on the sidewalls of the dummy gate structure 242. For example, dummy gate dielectric layer 242a, dummy gate 242b, and mask layer 242d are sandwiched between a pair of spacers 242c. In some embodiments, spacers 242c have the same extending direction D1 as the dummy gate structure 242. Similar to the dummy gate structure 242, spacers 242c also span across the semiconductor fin 230. In some embodiments, spacers 242c are formed of a dielectric material, such as silicon oxide, silicon nitride, silicon carbonitride, silicon carbon oxynitride, or a combination thereof. In some embodiments, spacers 242c can be formed by thermal oxidation or deposition followed by anisotropic etching. It should be noted that spacers 242c can be a single-layer structure or a multi-layer structure.

[0034] Referring to Figure 1M , the semiconductor fin 230 exposed by the dummy gate structure 242 and the spacers 242c is removed / recessed to form a plurality of recessed regions R. A portion of the semiconductor fin 230 can be removed by, for example, anisotropic etching, isotropic etching, or a combination thereof. In some embodiments, a portion of the semiconductor fin 230 is recessed below the top surface T2 of the insulator 240a. In other words, the semiconductor fin 230 exposed by the dummy gate structure 242 and the spacers 242c is not completely removed. As Figure 1M shown, the semiconductor fin 230 covered by the dummy gate structure 242 and the spacers 242c is not etched and is exposed at the sidewalls of the spacers 242c.

[0035] Referring to Figure 1N, a plurality of source / drain structures 244 are grown over the recessed region R of the semiconductor fin 230, and the plurality of source / drain structures 244 extend beyond the top surface T2 of the insulator 240a. That is, the source / drain structures 244 are formed over the portions of the semiconductor fin 230 that are exposed by the dummy gate structures 242 and the spacers 242c. In some embodiments, the source / drain structures 244 are grown to apply strain or stress to the semiconductor fin 230. In some embodiments, the source / drain structures 244 are formed such that each dummy gate structure 242 is disposed between respective adjacent pairs of source / drain structures 244. For example, the source / drain structures 244 include a source disposed at one side of one of the spacers 242c in the spacers 242c and a drain disposed at one side of the other spacer 242c in the spacers 242c. As Figure 1N shown, the dummy gate structures 242 are separated from the adjacent source / drain structures 244 by corresponding spacers 242c. Thus, an appropriate lateral distance is maintained between the dummy gate structures 242 and the source / drain structures 244, so that the source / drain structures 244 do not short-circuit with the subsequently formed gates of the resulting device.

[0036] In some embodiments, the source / drain structures 244 have a diamond-shaped profile. Thus, the sidewalls of the source / drain structures 244 have turning points TP (also referred to as source / drain proximity pushpoints). In some embodiments, the neck portion NP1 of the semiconductor fin 230 is designed to be adjacent to the turning point TP of the source / drain structures 244. For example, the height H1 of the neck portion NP1 of the semiconductor fin 230 (as Figure 1M shown) is substantially equal to the height H2 of the turning point TP of the source / drain structures 244 (as Figure 1N shown). Thus, the leakage current occurring at the turning point TP of the source / drain structures 244 can be significantly reduced.

[0037] In some embodiments, the source / drain structures 244 may be doped with a conductive dopant. In some embodiments, the source / drain structures 244 (such as SiGe, SiGeB, Ge, GeSn, etc.) are epitaxially grown using a p-type dopant to apply strain to a p-type FinFET. That is, the source / drain structures 244 are doped with a p-type dopant to serve as the source and drain of a p-type FinFET. The p-type dopant includes boron or BF 2. In some alternative embodiments, the source / drain structure 244 (such as SiC, SiP, SiCP, a combination of SiC / SiP, etc.) is epitaxially grown using an n-type dopant to apply strain to the n-type FinFET. That is, the source / drain structure 244 is doped with an n-type dopant to serve as the source and drain of the n-type FinFET. The n-type dopant includes arsenic and / or phosphorus. In some embodiments, the source / drain structure 244 can be epitaxially grown by LPCVD process using in-situ doping. In some embodiments, the concentration of the dopant in the source / drain structure 244 can be between about 10 19 cm -3 and about 10 21 cm -3 . Depending on the type of the device, the source / drain structures 244 in different regions can be doped with different types of dopants. Similarly, depending on the function of the device, the source / drain structures 244 in different regions can be doped with different dopant concentrations. In some embodiments, each of the source / drain structures 244 can be a single-layer structure or a multi-layer structure.

[0038] As described above, the source / drain structure 244 can include SiGe, SiGeB, Ge, GeSn, SiC, SiP, SiCP, a combination of SiC / SiP, etc. However, the present disclosure is not limited thereto. In some alternative embodiments, the source / drain structure 244 can also include III-V compound semiconductors, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, or a combination thereof. After the source / drain structure 244 grows to reach the top surface of the insulator 240a, the epitaxial growth of the source / drain structure 244 continues. In some embodiments, the source / drain structure 244 above the top surface of the insulator 240a expands in the horizontal direction, and a facet is formed for each of the source / drain structures 244. As Figure 1N shown, the source / drain structures 244 are separated from each other. However, the present disclosure is not limited thereto. In some alternative embodiments, the further growth of the source / drain structure 244 above the top surface of the insulator 240a may cause adjacent source / drain structures 244 to merge with each other.

[0039] It should be noted that, in some embodiments, the recessing step shown in Figure 1M can be omitted. For example, the source / drain structure 244 can be formed on the non-recessed semiconductor fin 230. That is, the source / drain structure 244 can be formed on the non-recessed semiconductor fin 230.

[0040] Referring to Figure 1O, an etch stop layer 246 and an interlayer dielectric layer 248 are sequentially formed over the source / drain structure 244 and the insulator 240a. In some embodiments, the etch stop layer 246 is formed adjacent to the spacer 242c. The etch stop layer 246 may be conformally formed on the top surface of the insulator 240a and the top surface of the source / drain structure 244. That is, the etch stop layer 246 follows the contour (facet) of the source / drain structure 244. In some embodiments, the etch stop layer 246 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc. In some embodiments, the etch stop layer 246 may be formed by, for example, CVD, SACVD, Molecular Layer Deposition (MLD), ALD, etc. In some embodiments, the etch stop layer 246 may be referred to as a "contact etch stop layer (CESL)".

[0041] As Figure 1O shown, the interlayer dielectric layer 248 is formed on the etch stop layer 246. In some embodiments, the interlayer dielectric layer 248 includes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), polyimide, and / or combinations thereof. In some alternative embodiments, the interlayer dielectric layer 248 includes a low dielectric constant dielectric material. Examples of low dielectric constant dielectric materials include BLACK DIAMOND (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, bis-benzocyclobutenes (BCB), Flare, SILK (Dow Chemical, Midland, Mich.), hydrogen silsesquioxane (HSQ) or fluorinated silicon oxide (SiOF) and / or combinations thereof. It should be understood that the interlayer dielectric layer 248 may include one or more dielectric materials and / or one or more dielectric layers. In some embodiments, the interlayer dielectric layer 248 is formed to a suitable thickness by flowable chemical vapor deposition (FCVD), CVD, HDPCVD, SACVD, spin coating, sputtering, or other suitable methods. For example, an interlayer dielectric material layer (not shown) may be formed to cover the etch stop layer 246, the dummy gate structure 242, and the spacers 242c. Subsequently, the thickness of the interlayer dielectric material layer is reduced until the top surface of the dummy gate structure 242 is exposed, thereby forming the interlayer dielectric layer 248. The reduction of the thickness of the interlayer dielectric material layer can be achieved by a chemical mechanical polishing (CMP) process, an etching process, or other suitable processes. After reducing the thickness of the interlayer dielectric material layer, the top surfaces of the dummy gate structure 242, the top surfaces of the spacers 242c, and the top surface of the interlayer dielectric layer 248 are substantially coplanar.

[0042] Referring to Figure 1P , the dummy gate structure 242 is removed to form a hollow portion 249 that exposes a portion of the semiconductor fin 230. For example, the mask layer 242d, the dummy gate 242b, and the dummy gate dielectric layer 242a are removed to form a hollow portion 249 between two adjacent spacers 242c. In some embodiments, the exposed portion of the semiconductor fin 230 may serve as the channel region of the semiconductor fin 230. In some embodiments, the dummy gate structure 242 is removed by an etching process or other suitable processes. The etching process includes, for example, a wet etching process or a dry etching process. Examples of wet etching processes include chemical etching, and examples of dry etching processes include plasma etching. However, other commonly known etching methods may also be used to remove the dummy gate structure 242. In some embodiments, during the etching process of the dummy gate 242b, the underlying dummy gate dielectric layer 242a may serve as an etch stop layer. The dummy gate dielectric layer 242a may be removed after removing the dummy gate 242b.

[0043] Referring to Figure 1Q , a gate dielectric layer 252, a work function layer 254a, and a metal layer 254b are sequentially deposited into the hollow portion 249 to form a gate structure 250. For example, each gate structure 250 is located in a corresponding hollow portion 249 and sandwiched between adjacent spacers 242c. As Figure 1QAs shown, the gate structure 250 is disposed across the semiconductor fin 230. For example, the gate structure 250 is disposed over the channel region of the semiconductor fin 230. The source / drain structures 244 are disposed on opposite sides of the gate structure 250. In some embodiments, the work function layer 254a and the metal layer 254b may be collectively referred to as the gate 254 of the gate structure 250. In some embodiments, the gate dielectric layer 252 is conformally deposited into the hollow portion 249. For example, the gate dielectric layer 252 covers the top surface and sidewalls of the semiconductor fin 230 exposed by the hollow portion 249. At the same time, the gate dielectric layer 252 also covers the sidewalls of the spacer 242c and the top surface of the insulator 240a. In some embodiments, the material of the gate dielectric layer 252 may be the same as or different from the material of the dummy gate dielectric layer 242a. For example, the gate dielectric layer 252 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some alternative embodiments, the gate dielectric layer 252 is made of a high-k dielectric material. In some embodiments, a high-k dielectric material refers to a dielectric material having a dielectric constant greater than about 7.0 and may include metal oxides or silicides of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. In some embodiments, the gate dielectric layer 252 may be formed by, for example, Molecular-Beam Deposition (MBD), ALD, PECVD, thermal oxidation, ultraviolet-ozone oxidation, combinations thereof, etc. In some embodiments, the gate dielectric layer 252 may further include an interface layer (not shown). In some embodiments, the interface layer may be used to form a good interface between the semiconductor fin 230 and the gate 254 and to suppress the mobility degradation of the channel carriers of the subsequently formed semiconductor device. In some embodiments, the interface layer is formed by a thermal oxidation process, a CVD process, or an ALD process. The interface layer includes, for example, silicon oxide or silicon oxynitride. In some embodiments, a liner layer, a seed layer, an adhesion layer, or a combination thereof may be further included between the gate 254 and the semiconductor fin 230.

[0044] As Figure 1Q shown, the work function layer 254a is conformally disposed on the gate dielectric layer 252. In some embodiments, the work function layer 254a includes a p-type work function metal or an n-type work function metal. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 , MoSi 2 , TaSi 2 , NiSi 2, WN, other suitable p-type work function materials, or combinations thereof. On the other hand, exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. In some embodiments, the work function layer 254a can be formed by, for example, CVD, PECVD, ALD, Remote Plasma Atomic Layer Deposition (RPALD), Plasma-Enhanced Atomic Layer Deposition (PEALD), MBD, etc. In some embodiments, the work function layer 254a can be used to adjust the threshold voltage (Vt) of a subsequently formed semiconductor device.

[0045] A metal layer 254b is disposed on the work function layer 254a. In some embodiments, the metal layer 254b can include tungsten, cobalt, etc. In some embodiments, the precursor gas used to form the tungsten metal layer 254b can include tungsten hexafluoride (WF 6 ), silane (SiH 4 ), and / or hydrogen (H 2 ). In some embodiments, the metal layer 254b is formed by CVD. In some embodiments, a barrier layer (not shown) can be present between the metal layer 254b and the work function layer 254a. The barrier layer includes, for example, TiN, etc., and is formed by ALD.

[0046] During the formation of the gate dielectric layer 252, the work function layer 254a, and the metal layer 254b, an excess portion of these layers may be formed outside the hollow portion 249. For example, an excess portion of these layers is formed on the etch stop layer 246 and the interlayer dielectric layer 248. Thus, a planarization process (e.g., a CMP process) can be performed to remove the excess portion of these layers, thereby presenting Figure 1Q the structure shown in Figure 1Q As shown in

[0047] Figures 1O to 1Q , the steps shown are generally referred to as the "metal gate replacement process". In some embodiments, the dummy gate structure 242 including polysilicon is replaced by the gate structure 250 including metal. In some embodiments, the semiconductor device 10 is formed, and the semiconductor device 10 can be referred to as a "FinFET".

[0048] In some embodiments, a semiconductor fin is formed to have at least one neck portion by performing at least one etching cycle including a rinse process, a first etching process, and a second etching process. Additionally, by designing the neck portion adjacent to the turning point of the source / drain structure, leakage current occurring at the protruding portion of the source / drain structure can be significantly reduced.

[0049] According to some embodiments of the present disclosure, a semiconductor device includes a semiconductor substrate, at least one semiconductor fin, and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion, and a first neck portion located between the first portion and the second portion. The width of the first portion decreases as the first portion becomes closer to the first neck portion, and the width of the second portion increases as the second portion becomes closer to the bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.

[0050] According to some embodiments of the present disclosure, the semiconductor device further includes a source / drain structure located on opposite sides of the gate stack, wherein the sidewall of the source / drain structure has a turning point, and the height of the turning point is substantially the same as the height of the first neck portion.

[0051] According to some embodiments of the present disclosure, the at least one semiconductor fin has a minimum width at the first neck portion.

[0052] According to some embodiments of the present disclosure, the at least one semiconductor fin further includes a third portion, a fourth portion, and a second neck portion. The third portion is located between the second portion and the semiconductor substrate, the second neck portion is located between the third portion and the fourth portion, the width of the third portion decreases as the third portion becomes closer to the second neck portion, and the width of the fourth portion increases as the fourth portion becomes closer to the bottom surface of the semiconductor substrate.

[0053] According to some embodiments of the present disclosure, the at least one semiconductor fin further includes a top portion located above the first portion, the first neck portion, and the second portion, and the top portion has substantially vertical sidewalls.

[0054] According to some embodiments of the present disclosure, the at least one semiconductor fin further includes a bottom portion located below the first portion, the first neck portion, and the second portion, and the bottom portion has substantially vertical sidewalls.

[0055] According to some embodiments of the present disclosure, the first portion has an inverted trapezoidal shape, and the second portion has a trapezoidal shape.

[0056] According to some embodiments of the present disclosure, a semiconductor device includes a semiconductor substrate, at least one semiconductor fin, and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. A sidewall of the semiconductor fin includes a zigzag portion. The gate stack partially covers the semiconductor fin.

[0057] According to some embodiments of the present disclosure, the sidewall of the at least one semiconductor fin further includes a substantially vertical portion that is physically connected to the zigzag portion.

[0058] According to some embodiments of the present disclosure, the substantially vertical portion is disposed between the semiconductor substrate and the zigzag portion.

[0059] According to some embodiments of the present disclosure, a ratio of the zigzag portion to the sidewall ranges from 1 / 3 to 1 / 2.

[0060] According to some embodiments of the present disclosure, the at least one semiconductor fin has a minimum width at the zigzag portion.

[0061] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes at least the following steps. Forming a plurality of openings in a semiconductor substrate. Performing at least one etching cycle on the plurality of openings to form a plurality of trenches and at least one semiconductor fin between the trenches. The etching cycle includes: forming a plurality of polymer layers on a surface of the opening; performing a first etching process on the opening; and performing a second etching process on the opening while an upper sidewall of the opening is covered with by-products formed during the first etching process. Forming a plurality of insulators in the trenches. Forming a gate stack to partially cover the semiconductor fin and the insulator.

[0062] According to some embodiments of the present disclosure, forming the plurality of polymer layers includes performing a rinse process by using a polymer gas containing SO 2 and O 2 .

[0063] According to some embodiments of the present disclosure, the first etching process is a chlorine-based dry etching process, and the second etching process is a fluorine-based dry etching process.

[0064] According to some embodiments of the present disclosure, the plurality of trenches include diamond-shaped openings formed by the second etching process.

[0065] According to some embodiments of the present disclosure, a method of forming the plurality of openings in the semiconductor substrate includes: forming a patterned cushion layer on the semiconductor substrate; and forming the plurality of openings by using the patterned cushion layer as a mask.

[0066] According to some embodiments of the present disclosure, after performing the at least one etching cycle, it further includes deepening the plurality of openings to a predetermined depth.

[0067] According to some embodiments of the present disclosure, the method further includes forming source / drain structures on opposite sides of the gate stack.

[0068] According to some embodiments of the present disclosure, the at least one semiconductor fin is formed to have at least one neck portion.

[0069] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a semiconductor substrate and an insulator on the semiconductor substrate; at least one semiconductor fin on the semiconductor substrate, the at least one semiconductor fin including a first portion, a second portion, and a first neck portion between the first portion and the second portion, wherein the width of the first portion decreases as the first portion becomes closer to the first neck portion, and the width of the second portion increases as the second portion becomes closer to the bottom surface of the semiconductor substrate; and a gate stack partially covering the at least one semiconductor fin; and a source / drain structure on opposite sides of the gate stack, wherein the sidewall of the source / drain structure has a turning point, and the height of the turning point is substantially the same as the height of the first neck portion, and the portion of the source / drain structure between the insulators has a substantially constant width.

2. The semiconductor device according to claim 1, wherein the at least one semiconductor fin has a minimum width at the first neck portion.

3. The semiconductor device according to claim 1, wherein the at least one semiconductor fin further includes a third portion, a fourth portion, and a second neck portion, the third portion being between the second portion and the semiconductor substrate, the second neck portion being between the third portion and the fourth portion, the width of the third portion decreasing as the third portion becomes closer to the second neck portion, and the width of the fourth portion increasing as the fourth portion becomes closer to the bottom surface of the semiconductor substrate.

4. The semiconductor device according to claim 1, wherein the at least one semiconductor fin further includes a top portion over the first portion, the first neck portion, and the second portion, and the top portion has substantially vertical sidewalls.

5. The semiconductor device according to claim 1, wherein the at least one semiconductor fin further includes a bottom portion under the first portion, the first neck portion, and the second portion, and the bottom portion has substantially vertical sidewalls.

6. The semiconductor device according to claim 1, wherein the first portion has an inverted trapezoidal shape, and the second portion has a trapezoidal shape.

7. A semiconductor device, comprising: a semiconductor substrate and an insulator on the semiconductor substrate; at least one semiconductor fin on the semiconductor substrate, wherein the sidewall of the at least one semiconductor fin includes a zigzag portion including a neck portion; a gate stack partially covering the at least one semiconductor fin; and a source / drain structure on opposite sides of the gate stack, wherein the sidewall of the source / drain structure has a turning point, and the height of the turning point is substantially the same as the height of the neck portion, and the portion of the source / drain structure between the insulators has a substantially constant width.

8. The semiconductor device according to claim 7, wherein the sidewalls of the at least one semiconductor fin further include substantially vertical portions that are physically connected to the zigzag portion.

9. The semiconductor device according to claim 8, wherein the substantially vertical portions are disposed between the semiconductor substrate and the zigzag portion.

10. The semiconductor device according to claim 7, wherein the ratio of the zigzag portion to the sidewall is in the range of 1 / 3 to 1 / 2.

11. The semiconductor device according to claim 7, wherein the at least one semiconductor fin has a minimum width at the neck portion.

12. A method of manufacturing a semiconductor device, comprising: forming a plurality of openings in a semiconductor substrate; performing at least one etching cycle on the plurality of openings to form a plurality of trenches and at least one semiconductor fin between the plurality of trenches, the etching cycle including: forming a plurality of polymer layers on the surfaces of the plurality of openings; performing a first etching process on the plurality of openings; and performing a second etching process on the plurality of openings while the upper sidewalls of the plurality of openings are covered with by-products formed during the first etching process; forming a plurality of insulators in the plurality of trenches; forming a gate stack to partially cover the at least one semiconductor fin and the plurality of insulators; and forming source / drain structures on opposite sides of the gate stack, wherein the sidewalls of the source / drain structures have turning points, and the height of the turning points is substantially the same as the height of the neck portion of the at least one semiconductor fin.

13. The method according to claim 12, wherein forming the plurality of polymer layers includes performing a rinsing process by using a polymer gas containing SO 2 and O 2 .

14. The method according to claim 12, wherein the plurality of trenches include diamond-shaped openings formed by the second etching process.

15. The method according to claim 12, wherein the method of forming the plurality of openings in the semiconductor substrate comprises: forming a patterned cushion layer on the semiconductor substrate; and forming the plurality of openings by using the patterned cushion layer as a mask.

16. The method according to claim 12, wherein after performing the at least one etching cycle, further comprising deepening the plurality of openings to a predetermined depth.

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