Semiconductor device and method for manufacturing the semiconductor device

Abstract

A semiconductor device and a method for manufacturing the semiconductor device. A semiconductor device includes: a stacked structure including a plurality of insulating layers and a plurality of conductive layers stacked alternately; a channel structure penetrating the stacked structure; a plurality of data storage patterns respectively inserted between the conductive layers and the channel structures; a plurality of barrier patterns respectively inserted between the conductive layers and the data storage patterns; a plurality of insulating patterns respectively inserted between the insulating layers and the channel structures; and a plurality of insulating pads inserted between the insulating layers and the insulating patterns, the plurality of insulating pads respectively surrounding the insulating patterns.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] A nonvolatile memory device is a memory device that maintains stored data even when power is interrupted. As improvements in the integration of two-dimensional nonvolatile memory devices in which memory cells are formed in a single layer over a semiconductor substrate have reached their limits, three-dimensional nonvolatile memory devices in which memory cells are formed in a vertical direction over a semiconductor substrate have been proposed.

[0003] The three-dimensional memory device includes interlayer insulating layers and gate electrodes alternately stacked and channel layers penetrating the interlayer insulating layers and the gate electrodes, and memory cells are stacked along the channel layers. Various structures and manufacturing methods have been developed to improve the operational reliability of the three-dimensional nonvolatile memory device. Summary of the invention

[0004] According to one aspect of the present disclosure, a semiconductor device is provided, which includes: a stacked structure, which includes a plurality of insulating layers and a plurality of conductive layers stacked alternately; a channel structure, which penetrates the stacked structure; a plurality of data storage patterns, which are respectively inserted between the conductive layers and the channel structures; a plurality of blocking patterns, which are respectively inserted between the conductive layers and the data storage patterns; a plurality of insulating patterns, which are respectively inserted between the insulating layers and the channel structures; and a plurality of insulating pads, which are inserted between the insulating layers and the insulating patterns, and the plurality of insulating pads respectively surround the insulating patterns.

[0005] According to another aspect of the present disclosure, a semiconductor device is provided, which includes: a stacked structure, which includes a plurality of insulating layers and a plurality of conductive layers stacked alternately; a channel structure, which penetrates the stacked structure; a plurality of insulating patterns, which are respectively inserted between the insulating layers and the channel structures, and the insulating patterns protrude farther toward the channel structures than the conductive layers; a plurality of data storage patterns, which are respectively inserted between the conductive layers and the channel structures, and the data storage patterns protrude farther toward the channel structures than the insulating patterns; and a plurality of blocking patterns, which are respectively inserted between the conductive layers and the data storage patterns.

[0006] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising the following steps: forming a stack structure including a plurality of first sacrificial layers and a plurality of insulating layers alternately stacked; forming a first opening penetrating the stack structure; forming a second opening by etching the insulating layer; forming a protection pattern on the first sacrificial layer; forming a data storage layer in the first opening and the second opening; forming an insulating pattern in the second opening; forming a channel structure in the first opening; forming a third opening exposing the protection pattern by selectively removing the first sacrificial layer; removing the protection pattern to partially expose the data storage layer; and forming insulating pads respectively surrounding the insulating patterns by partially oxidizing the data storage layer through the third opening.

[0007] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising the following steps: forming a stack structure including a plurality of first sacrificial layers and a plurality of insulating layers alternately stacked; forming a first opening penetrating the stack structure; forming a second opening by etching the insulating layer; forming a blocking pattern on the first sacrificial layer; forming a data storage layer in the first opening and the second opening; forming an insulating pattern in the second opening; forming a channel structure in the first opening; forming a third opening by selectively removing the first sacrificial layer; etching the insulating layer through the third opening to partially expose the data storage layer; and forming insulating pads respectively surrounding the insulating patterns by partially oxidizing the data storage layer through the third opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments are described below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will enable those skilled in the art.

[0009] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

[0010] Figure 1A and Figure 1B is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figures 2A to 2Q 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 3 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0013] Figure 4is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0014] Figure 5 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure.

[0015] Figure 6 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] In order to describe the embodiments of the concepts according to the present disclosure, the specific structural or functional descriptions disclosed herein are only illustrative. The embodiments of the concepts according to the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0017] Various embodiments relate to a semiconductor device having a stable structure and improved characteristics. Some embodiments relate to a method for manufacturing the semiconductor device.

[0018] Figure 1A and Figure 1B is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 1B yes Figure 1A An enlarged view of area A is shown.

[0019] Reference Figure 1A , the semiconductor device may include a stack structure ST, a memory layer M, a channel structure CH, an insulating pattern 13 and an insulating liner 14 .

[0020] The stacked structure ST may include conductive layers 11 and insulating layers 12 that are alternately stacked. The conductive layer 11 may be a gate electrode of a selection transistor, a memory cell, etc. The conductive layer 11 may include a conductive material such as polysilicon, tungsten, or a metal. The insulating layer 12 is used to insulate the stacked conductive layers 11 from each other. The insulating layer 12 may include an insulating material such as an oxide or a nitride.

[0021] Each conductive layer 11 may have a first thickness T1 defined in the second direction II. In each conductive layer 11, a thickness of a portion of the conductive layer 11 closer to the channel structure CH may be thinner than a thickness T1 of a portion spaced apart from the channel structure CH. In each conductive layer 11, a portion interposed between the insulating pads 14 may have a thickness thinner than a thickness of a portion interposed between the insulating layers 12. The interface between the first conductive layer 11 and the insulating pad 14 may be an interface defined by an oxidation process. The interface may include a curved surface.

[0022] Each insulating layer 12 may have a second thickness T2 defined in a second direction II. The insulating layer 12 may have a thickness thinner than that of the conductive layer 11 (T2 < T1). The interface between the insulating layer 12 and the insulating spacer 14 may include a curved surface.

[0023] The channel structure CH may penetrate the stack structure ST. The channel structure CH may extend in the second direction II. The channel structure CH may include a channel layer 18 and also include a gap-fill layer 19. The channel layer 18 may be a region forming a channel of a select transistor, a memory cell, etc. The channel layer 18 may include a semiconductor material such as silicon (Si) or germanium (Ge), or include a nanostructured material such as nanodots, nanotubes, or graphene. The gap-fill layer 19 may be formed in the channel layer 18 and include an insulating material such as an oxide.

[0024] The memory layer M may be interposed between the stack structure ST and the channel structure CH. The memory layer M may include at least one of a blocking pattern 15, a data storage pattern 16, and a tunnel insulating layer 17. The tunnel insulating layer 17 may be formed to surround the sidewalls of the channel structure CH. The tunnel insulating layer 17 may be a layer through which charges tunnel such as by F-N tunneling, and includes an insulating material such as an oxide or a nitride. The tunnel insulating layer 17 may be in contact with the data storage pattern 16 and the insulating pattern 13. Additionally, the tunnel insulating layer 17 may be in contact with the insulating spacer 14.

[0025] The data storage patterns 16 may be respectively interposed between the conductive layer 11 and the channel structure CH. The data storage patterns 16 may be formed to surround the tunnel insulating layer 17. Each data storage pattern 16 may include a first surface facing the tunnel insulating layer 17, a second surface facing the blocking pattern 15, and a third surface facing the insulating spacer 14. At least one of the first to third surfaces may include a curved surface. The first surface or the second surface may include a curved surface protruding toward the channel structure CH. The third surface may include a curved surface recessed into the storage pattern 16. The data storage pattern 16 may include a floating gate, a charge trapping material, polysilicon, nitride, a variable resistance material, a phase change material, a nanostructure, etc.

[0026] The data storage pattern 16 may have a thickness defined in a first direction I. Additionally, each data storage pattern 16 may have different thicknesses according to regions. Each data storage pattern 16 may include two end portions EP in contact with the insulating spacer 14 and a central portion CP located between the two end portions EP. The thickness T6 of the end portion EP and the thickness T5 of the central portion CP may be different from each other. The central portion CP may be thicker than the end portion EP (T5 > T6). When the end portion EP or the central portion CP has a non-uniform thickness, the thickness difference may be determined by comparing the thickest thickness or the average thickness of the end portion EP and the central portion CP with each other.

[0027] The barrier patterns 15 may be respectively interposed between the conductive layer 11 and the data storage patterns 16. The barrier patterns 15 may be formed to respectively surround the data storage patterns 16. The barrier patterns 15 may prevent charges from moving to the conductive layer 11 and include a high dielectric constant material such as aluminum oxide (Al2O3).

[0028] The insulating patterns 13 may be interposed between the insulating layers 12 and the channel structures CH, respectively. The insulating patterns 13 may be disposed to correspond to the insulating layers 12, respectively, and be located at substantially the same level as the insulating layers 12. The insulating patterns 13 may contact the tunnel insulating layer 17.

[0029] The insulating pads 14 may be interposed between the insulating layer 12 and the insulating pattern 13. The respective insulating pads 14 may extend between the conductive layer 11 and the insulating pattern 13, between the barrier pattern 15 and the insulating pattern 13, and between the data storage pattern 16 and the insulating pattern 13. The insulating pads 14 may be formed to surround the insulating patterns 13, respectively. The insulating pads 14 may include an insulating material such as an oxide.

[0030] The insulating pads 14 may be formed by partially oxidizing the data storage layer. Therefore, the insulating pads 14 may include data storage materials that are not oxidized but retained. For example, each insulating pad 14 may include an oxide layer 14A and a charge trapping material 14B included in the oxide layer 14A. The interface between the insulating pad 14 and the data storage pattern 16 may be an interface defined by an oxidation process. Therefore, the interface may include a curved surface.

[0031] The insulating liner 14 may be formed by a different process from the tunnel insulating layer 17 or the barrier pattern 15, and have different properties from the tunnel insulating layer 17 or the barrier pattern 15. The tunnel insulating layer 17 may correspond to a layer formed by a deposition process, and the insulating liner 14 may correspond to a layer formed by an oxidation process. The barrier pattern 15 may correspond to a layer formed by oxidizing polysilicon, and the insulating liner 14 may correspond to a layer formed by oxidizing a charge trapping material such as nitride. The insulating liner 14 may have a different etching rate from the tunnel insulating layer 17 or the barrier pattern 16. The insulating liner 14 may have a lower etching rate than the tunnel insulating layer 17 or the barrier pattern 16.

[0032] Each insulating pad 14 may have different thicknesses according to regions. Each insulating pad 14 may include two end portions EP in contact with the memory layer M and a central portion CP in contact with the insulating layer 12. The thickness T4 of the end portions EP and the thickness T3 of the central portion CP may be different from each other. The central portion CP may be thicker than the end portions EP (T3>T4). When the end portions EP or the central portion CP has a non-uniform thickness, the thickness difference may be determined by comparing the thickest thickness or the average thickness of the end portions EP and the central portion CP with each other.

[0033] Reference Figure 1A and Figure 1B , the conductive layer 11 may include a first side wall SW1 in contact with the barrier pattern 15. The insulating pattern 13 may include a second side wall SW2 in contact with the tunnel insulating layer 17. The second side wall SW2 may be an etched surface. The insulating liner 14 may include a third side wall SW3 in contact with the tunnel insulating layer 17 and the data storage pattern 16. The third side wall SW3 may be a surface defined by an oxidation process. The data storage pattern 16 may include a fourth side wall SW4 in contact with the tunnel insulating layer 17. The fourth side wall SW4 may be a surface defined by a deposition process.

[0034] The first to fourth side walls SW1 to SW4 may be disposed to be spaced apart from each other in the first direction I. The second side wall SW2 may protrude farther toward the channel structure CH than the first side wall SW1. The third side wall SW3 may protrude farther toward the channel structure CH than the first side wall SW1 and the second side wall SW2. The fourth side wall SW4 may protrude farther toward the channel structure CH than the second side wall SW2 and the third side wall SW3. When the first side wall SW1, the second side wall SW2, the third side wall SW3, or the fourth side wall SW4 includes a curved surface, the positions between the side walls may be compared relative to the point that protrudes most toward the channel structure CH in the first direction I. The first direction I may be parallel to a surface of a base such as a substrate. The first direction I and the second direction II may intersect each other.

[0035] Since the insulating patterns 13 and the insulating pads 14 protrude further than the conductive layer 11, a space may be defined between the insulating patterns 13 and the insulating pads 14 adjacent in the second direction II. In addition, the memory layer M may be formed to fill the space. The blocking pattern 15 and the data storage pattern 16 may fill the space between the insulating patterns 13 or the space between the insulating pads 14.

[0036] A recess C may be defined between the barrier pattern 15 and the data storage pattern 16 . Interfaces between the barrier pattern 15 and the insulating liner 14 and between the data storage pattern 16 and the insulating liner 14 are connected in a “V” or “U” shape, thereby defining the recess C. The recess C may be filled with the insulating liner 14 .

[0037] According to the above structure, the memory cell or the selection transistor may be located at the intersection of the channel structure CH and the conductive layer 11. The memory cell and the selection transistor sharing the channel structure CH may constitute a memory string. The memory string may include at least one drain selection transistor, a memory cell, and at least one source selection transistor.

[0038] In addition, the data storage patterns 16 are isolated from each other by the insulating pattern 13 and the insulating liner 14. Therefore, the data storage patterns 16 of the stacked memory cells are isolated from each other, and data retention characteristics may be improved.

[0039] Figures 2A to 2Q 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions of contents overlapping with those described above will be omitted.

[0040] Reference Figure 2A , forming a stacked structure ST. The stacked structure ST may include first sacrificial layers 21 and insulating layers 22 that are alternately stacked. The first sacrificial layers 21 and the insulating layers 22 may be stacked in the second direction II. The first sacrificial layer 21 may include a material having a high etching selectivity relative to the insulating layer 22. In an example, the first sacrificial layer 21 may include a sacrificial material such as a nitride, and the insulating layer 22 may include an insulating material such as an oxide.

[0041] Subsequently, a first opening OP1 penetrating the stacked structure is formed. The first opening OP1 may be formed by etching the first sacrificial layer 21 and the insulating layer 22. The first opening OP1 may be extended in the second direction II. The first opening OP1 may have a width W1 defined by the sidewall (i.e., etching surface) of the first sacrificial layer 21. The first opening OP1 may have a cross section of a circular shape, an elliptical shape, a polygonal shape, etc.

[0042] Subsequently, the second opening OP2 is formed by selectively etching the insulating layer 22. The first sacrificial layer 21 may protrude further toward the inside of the first opening OP1 than the insulating layer 22. The second opening OP2 may be located between the protruding first sacrificial layers 21. The sidewall of the insulating layer 22 may be newly defined by the etching process, and the sidewall may include a curved surface.

[0043] Subsequently, a first protection pattern 23 is formed on the first sacrificial layer 21. An oxidation process may be used to form the first protection pattern 23. The first protection pattern 23 may include a material having a high etch selectivity with respect to the first sacrificial layer 21. The first sacrificial layer 21 may include nitride, and the first protection pattern 23 may include oxide.

[0044] The first protection patterns 23 may be formed on the first sacrificial layers 21, respectively, and may be isolated from each other. The sidewalls of the first sacrificial layers 21 may be newly defined by an oxidation process. The corners of the first sacrificial layers 21 contacting the insulating layer 22 may be rounded in the oxidation process. Each of the first protection patterns 23 may include an end EP1 having a curved tail shape to surround the corners of each of the first sacrificial layers 21.

[0045] Reference Figure 2B, a second protective layer 24 is formed in the first opening OP1 and the second opening OP2. The second protective layer 24 may be formed using a deposition process. The second protective layer 24 may be formed along the surfaces of the first protection pattern 23 and the insulating layer 22. The second protective layer 24 may include a corner portion E surrounding an end portion EP1 of the first protection pattern 23. The corner portion E may be located at a portion where the first opening OP1 and the second opening OP2 are connected to each other.

[0046] The second protection layer 24 may include a material having a high etch selectivity with respect to the first protection pattern 23. The second protection layer 24 may include a material having a high etch selectivity with respect to the insulating layer 22. The first protection pattern 23 and the insulating layer 22 may include oxide, and the second protection layer 24 may include polysilicon.

[0047] The second protective layer 24 may be formed to have a thickness such that the second protective layer 24 fills a portion of the first opening OP1 and a portion of each second opening OP2. The second protective layer 24 may be formed to have a thickness thicker than that of the first protective pattern 23 (T2>T1).

[0048] Reference Figure 2C , a second sacrificial layer 25 is formed in the second protective layer 24. The second sacrificial layer 25 may include a material having a high etching selectivity with respect to the second protective layer 24. The second protective layer 24 may include polysilicon, and the second sacrificial layer 25 may include nitride.

[0049] The second sacrificial layer 25 may be formed using a deposition process and formed along the surface of the second protection layer 24. The second sacrificial layer 25 may be formed to have a thickness (T3>T1, T2) thicker than the first protection pattern 23 and the second protection layer 24. The second sacrificial layer 25 may be formed to have a thickness such that the second sacrificial layer 25 fills the second opening OP2 and fills a portion of the first opening OP1.

[0050] Reference Figure 2D , forming the second sacrificial patterns 25A. The second sacrificial patterns 25A may be formed by etching the second sacrificial layer 25. The second sacrificial patterns 25A may be respectively located in the second openings OP2 and isolated from each other.

[0051] A portion of the second protective layer 24 corresponding to the insulating layer 22 may be covered by the second sacrificial pattern 25A, and a portion of the second protective layer 24 corresponding to the first sacrificial layer 21 may not be covered by the second sacrificial pattern 25A but may be exposed.

[0052] Reference Figure 2E, forming the blocking pattern 26. The blocking pattern 26 may be formed using an oxidation process. The blocking pattern 26 may be formed by partially oxidizing the second protective layer 24. A portion of the second protective layer 24 exposed by the second sacrificial pattern 25 may be oxidized. The blocking pattern 26 may include an oxide.

[0053] The interface between the second protective layer 24 and the blocking pattern 26 may be newly defined by the oxidation process. Therefore, the position of the corner portion E' may be newly defined. The corner portion E' may be surrounded by the blocking pattern 26 or the second sacrificial pattern 25A. Each blocking pattern 26 may include an end portion EP2 having a curved tail shape to surround each corner portion E'. The blocking pattern 26 may have a thickness thicker than that of the first protective pattern 23 or the second protective layer 24 (T4>T1, T2).

[0054] Reference Figure 2F , the second sacrificial pattern 25A is removed. The second sacrificial pattern 25A may be removed by selectively etching the second sacrificial pattern 25A. Thus, a portion of the protective layer 24 corresponding to the insulating layer 22 is exposed.

[0055] Reference Figure 2G , forming the second protection pattern 24A. The second protection pattern 24A may be interposed between the first protection pattern 23 and the barrier pattern 26, respectively. The second protection pattern 24A may be formed by selectively etching the second protection layer 24. Therefore, the second opening OP2 may be opened again.

[0056] The portion of the second protective layer 24 exposed by the barrier pattern 26 may be etched, and the portion of the second protective layer 24 covered by the barrier pattern 26 may remain. The remaining portion may become the second protective pattern 24A. When the second protective layer 24 is etched, the portion interposed between the end EP1 of each first protective pattern 23 and the end EP2 of each barrier pattern 26 may be etched. Therefore, the second opening OP2 may expand between the first protective pattern 23 and the barrier pattern 26 and include an expansion portion EX1.

[0057] The width of the first opening OP1 is reduced by the first protection pattern 23, the second protection pattern 24A, and the barrier pattern 26 formed on the first sacrificial layer 21. The first opening OP1 has a width W2 reduced from the region corresponding to the first sacrificial layer 21. When it is considered that the memory cell is located at the portion corresponding to the first sacrificial layer 21 in the final structure, the portion corresponding to the first sacrificial layer 21 may correspond to the memory cell region, and the portion corresponding to the insulating layer 22 may correspond to the space region between the stacked memory cells. Therefore, the width of the memory cell region in the first opening OP1 can be selectively reduced by the first protection pattern 23, the second protection pattern 24A, and the barrier pattern 26. In addition, since the memory cell region of the first opening OP1 has the second width W2, the same effect as if the first opening OP1 was formed to have the second width W2 can be obtained.

[0058] Reference Figure 2H , a data storage layer 27 is formed in the first opening OP1 and the second opening OP2. The data storage layer may be formed to fill the extended portion EX1. The data storage layer 27 may be formed using a deposition process and is formed along the surfaces of the barrier pattern 26, the second protection pattern 24A, the first protection pattern 23, and the insulating layer 22. The data storage layer 27 may be formed in a curved shape in a cross section defined by the first direction I and the second direction II. The data storage layer 27 may be formed in a shape in which a portion of the data storage layer 27 corresponding to the first sacrificial layer 21 protrudes further toward the inside of the first opening OP1 than a portion of the data storage layer 27 corresponding to the insulating layer 22.

[0059] The portion of the data storage layer 27 corresponding to the first sacrificial layer 21 (ie, the portion corresponding to the memory cell region) is used for substantial data storage. Therefore, the same effect as if the data storage layer 27 is formed in the first opening having the second width W2 can be obtained.

[0060] The data storage layer 27 may be formed to have a thickness such that the data storage layer 27 fills a portion of the first opening OP1 and partially fills each of the second openings OP2. The data storage layer 27 may have a thickness thicker than that of the first protection pattern 23 or the second protection pattern 24A (T5>T1, T2). The data storage layer 27 may have a thickness thinner than that of the blocking pattern 26 (T5>T1, T2). <T4)。

[0061] Reference Fig.2I , an insulating layer 28 is formed in the first opening OP1 and the second opening OP2. The insulating layer 28 may be formed to have a thickness such that the insulating layer 28 fills the second opening OP2. The insulating layer 28 may completely fill the first opening OP1 or partially fill the first opening OP1.

[0062] Reference Figure 2J, an insulating pattern 28 is formed. The insulating pattern 28A located in the second opening OP2 respectively can be formed by etching the insulating layer 28. The portion of the data storage layer 27 corresponding to the insulating layer 22 can be covered by the insulating pattern 28A. The portion of the data storage layer 27 corresponding to the first sacrificial layer 21 is not covered by the insulating pattern 28A but can be exposed in the first opening OP1.

[0063] Referring to Figure 2K , a tunnel insulating layer 29 is formed in the first opening OP1. The tunnel insulating layer 29 can be formed using a deposition process and is formed along the surfaces of the data storage layer 27 and the insulating pattern 28A.

[0064] The tunnel insulating layer 29 can have a thickness thicker than that of the first protective pattern 23 (T6>T1). The tunnel insulating layer 29 can have a thickness thinner than that of the barrier pattern 26 or the second protective pattern 24A (T6<T4, T2). The tunnel insulating layer 29 can have a thickness substantially the same as that of the data storage layer 27 (T5=T6), or have a different thickness (T5≠T6). The tunnel insulating layer 29 can be formed to have a thickness such that the tunnel insulating layer 29 partially fills the first opening OP1.

[0065] Subsequently, a channel structure CH is formed in the first opening OP1. The channel structure CH can include a channel layer 30 and also include a gap filling layer 31. The channel layer 30 can be formed using a deposition process and is formed along the surface of the tunnel insulating layer 29. The channel layer 30 can have a thickness thicker than that of the first protective pattern 23, the second protective pattern 24A, the barrier pattern 26, the data storage layer 27, or the tunnel insulating layer 29 (T7>T1, T2, T4, T5, T6). The gap filling layer 31 can be formed in the channel layer 30 and includes voids.

[0066] Referring to Figure 2L , a third opening OP3 is formed by removing the first sacrificial layer 21. After forming a slit (not shown) that penetrates the stacked structure ST, the third opening OP3 can be formed by selectively etching the first sacrificial layer 21 via the slit. The first protective pattern 23 can be exposed through the third opening OP3. When the first sacrificial layer 21 is removed, the data storage layer 27 can be protected by the first protective pattern 23 and the second protective pattern 24A.

[0067] Referring to Figure 2M, the data storage layer 27 is partially exposed. The third opening OP3 is extended by etching the insulating layer 22. An isotropic etching process can be used to etch the insulating layer 22. The isotropic etching process can be a wet etching process. The etched insulating layer 22A can have a thickness thinner than the thickness of the insulating layer 22 (T9 < T8). The etched insulating layer 22A can have a width defined in the first direction I, and the width of the etched insulating layer 22A can also be reduced due to the etching process.

[0068] When the insulating layer 22A is etched, the first protective pattern 23 can be etched together with the insulating layer 22A. Therefore, the second protective pattern 24A can be exposed through the extended third opening OP3'. In addition, the data storage layer 27 can be partially exposed through the extended third opening OP3'.

[0069] Refer to Figure 2N , the second protective pattern 24A is removed. A lift-off process can be used to remove the second protective pattern 24A. Therefore, the third opening OP3' is further extended. The data storage layer 27 can be further exposed through the exposed third opening OP3'. In addition, the barrier pattern 26 can be exposed through the exposed third opening OP3'. The ends of each barrier pattern 26 can be covered by the data storage layer 27, and only other parts can be exposed.

[0070] Refer to Fig.2O , the data storage layer 27 is etched through the third opening OP3'. Therefore, the third opening OP3' is further extended. An isotropic etching process can be used to etch the data storage layer 27. The isotropic etching process can be a wet etching process. The part of the data storage layer 27 exposed through the third opening OP3' can be etched by the etching process. The part of the data storage layer 27 covering the barrier pattern 26 can be etched. In addition, the part of the data storage layer 27 in contact with the insulating layer 22A can be etched. Therefore, the barrier pattern 26 can be further exposed through the extended third opening OP3'. In addition, the third opening OP3' can be extended between the etched data storage layer 27A and the insulating layer 22A, and each third opening OP3' can include an extended part EX2.

[0071] Refer to Figure 2P , an insulating liner 27C is formed by partially oxidizing the data storage layer 27A. The part of the data storage layer 27A exposed through the third opening OP3' can be oxidized. The part of the data storage layer 27A exposed between the barrier pattern 26 and the insulating layer 22A can be oxidized.

[0072] The insulating pads 27C may have a shape in which the insulating pads 27C surround the insulating patterns 28A, respectively. Each insulating pad 27C may be interposed between the insulating layer 22A and the insulating pattern 28A. In addition, each insulating pad 27C may extend along the surface of each insulating pattern 28A. Each insulating pad 27C may extend between the blocking pattern 26 and the insulating pattern 28A and between the data storage pattern 27B and the insulating pattern 28A.

[0073] The portion of the data storage layer 27A covered by the blocking pattern 26 is not oxidized but may remain. The remaining portion may be the data storage pattern 27B. The interface between the data storage pattern 27B and the insulating liner 27C may be defined by an oxidation process. The interface may include a curved surface.

[0074] Reference Figure 2Q , a conductive layer 32 is formed in the third opening OP3'. Since the conductive layer 32 is formed in the expanded third opening OP3', the gap filling property of the conductive layer 32 can be improved compared with the existing conductive layer. In addition, since the thickness of the conductive layer 32 is increased, the resistance of the conductive layer 32 can be reduced.

[0075] The conductive layer 32 may contact the insulating liner 27C. The insulating liner 27C may be interposed between the conductive layer 32 and the insulating pattern 28A. The conductive layer 32 may include a metal such as tungsten.

[0076] According to the above-mentioned manufacturing method, the thickness of the data storage pattern 27B is determined according to the deposition thickness of the data storage layer 27, and the change of the thickness of the data storage pattern 27B due to the process variable can be minimized. In addition, the data storage pattern 27B is formed by partially oxidizing the data storage layer 27A. Therefore, it is not necessary to etch the data storage layer 27A to isolate the data storage patterns 27B from each other, and the data storage pattern 27B can be prevented from being damaged in the etching process.

[0077] Conventionally, a process of expanding the first opening OP1 in a region corresponding to the first sacrificial layer 21 is used to isolate the data storage patterns 27B from each other. According to this process, the chip size increases as the first opening OP1 expands. On the other hand, according to an embodiment of the present disclosure, the data storage layer 27 is formed by narrowing the first opening OP1 inward, so that the integration can be improved compared with the conventional process. In addition, an effect like a reduction in the width W2 of the first opening OP1 can be obtained, so the programming speed or the erasing speed can be increased compared with the conventional process.

[0078] Figure 3 is a block diagram showing a configuration of a memory system 1000 according to an embodiment of the present disclosure.

[0079] Reference Figure 3, the memory system 1000 includes a memory device 1200 and a controller 1100 .

[0080] The memory device 1200 is used to store data information in various data formats such as text, graphics, and software codes. The memory device 1200 may be a non-volatile memory. In addition, the memory device 1200 may have a reference Figures 1A to 2Q The structure described, and according to the reference Figures 1A to 2Q The memory device 1200 is manufactured by the manufacturing method described. In an embodiment, the memory device 1200 may include: a stacked structure including a plurality of insulating layers and a plurality of conductive layers alternately stacked; a channel structure penetrating the stacked structure; a plurality of data storage patterns respectively inserted between the conductive layers and the channel structure; a plurality of blocking patterns respectively inserted between the conductive layers and the data storage patterns; a plurality of insulating patterns respectively inserted between the insulating layers and the channel structure; and a plurality of insulating pads inserted between the insulating layers and the insulating patterns, the plurality of insulating pads respectively surrounding the insulating patterns. The structure and manufacturing method of the memory device 1200 are the same as those described above, and therefore, a detailed description thereof will be omitted.

[0081] The controller 1100 is connected to the host and the memory device 1200, and accesses the memory device 1200 in response to a request from the host. For example, the controller 1100 is configured to control a read operation, a write operation, an erase operation, and a background operation of the memory device 1200.

[0082] The controller 1100 includes a random access memory (RAM) 1110 , a central processing unit (CPU) 1120 , a host interface 1130 , an error correction code (ECC) circuit 1140 , a memory interface 1150 , and the like.

[0083] The RAM 1110 may be used as a working memory of the CPU 1120, a cache memory between the memory device 1200 and the host, and a buffer memory between the memory device 1200 and the host. The RAM 1110 may be replaced by a static random access memory (SRAM), a read only memory (ROM), or the like.

[0084] The CPU 1120 controls the overall operation of the controller 1100. For example, the CPU 1120 is configured to operate firmware such as a flash translation layer (FTL) stored in the RAM 1110.

[0085] The host interface 1130 is configured to interface with the host. For example, the controller 1100 uses at least one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a proprietary protocol to communicate with the host.

[0086] The ECC circuit 1140 is configured to detect and correct errors included in data read from the memory device 1200 using an error correction code (ECC).

[0087] The memory interface 1150 may be configured to interface with the memory device 1200. For example, the memory interface 1150 includes a NAND interface or a NOR interface.

[0088] The controller 1100 may further include a buffer memory (not shown) for temporarily storing data. The buffer memory may be used to temporarily store data transmitted to the outside through the host interface 1130 or data transmitted from the memory device 1200 through the memory interface 1150. The controller 1100 may further include a ROM storing code data for interfacing with the host.

[0089] As described above, the memory system 1000 according to the embodiment of the present disclosure includes the memory device 1200 having improved integration and improved characteristics, and thus the integration and characteristics of the memory system 1000 may be improved.

[0090] Figure 4 1 is a block diagram showing a configuration of a memory system 1000 ′ according to an embodiment of the present disclosure. Hereinafter, descriptions of contents overlapping with those described above will be omitted.

[0091] Reference Figure 4 , the memory system 1000' includes a memory device 1200' and a controller 1100. The controller 1100 includes a RAM 1110, a CPU 1120, a host interface 1130, an ECC circuit 1140, a memory interface 1150, and the like.

[0092] The memory device 1200' may be a non-volatile memory. In addition, the memory device 1200' may have a reference Figures 1A to 2Q The structure described, and according to the reference Figures 1A to 2QThe memory device 1200' may be manufactured by the manufacturing method described. In an embodiment, the memory device 1200' may include: a stacked structure including a plurality of insulating layers and a plurality of conductive layers alternately stacked; a channel structure penetrating the stacked structure; a plurality of data storage patterns respectively inserted between the conductive layers and the channel structure; a plurality of blocking patterns respectively inserted between the conductive layers and the data storage patterns; a plurality of insulating patterns respectively inserted between the insulating layers and the channel structure; and a plurality of insulating pads inserted between the insulating layers and the insulating patterns, the plurality of insulating pads respectively surrounding the insulating patterns. The structure and manufacturing method of the memory device 1200' are the same as those described above, and therefore, a detailed description thereof will be omitted.

[0093] The memory device 1200' may be a multi-chip package including a plurality of memory chips. The plurality of memory chips are divided into a plurality of groups, which are configured to communicate with the controller 1100 via the first channel to the kth channel (CH1 to CHk). In addition, the memory chips included in one group may be configured to communicate with the controller 1100 via a common channel. For reference, the memory system 1000' may be modified so that one memory chip is connected to one channel.

[0094] As described above, the memory system 1000' according to the embodiment of the present disclosure includes a memory device 1200' having improved integration and improved characteristics, so the integration and characteristics of the memory system 1000' can be improved. Specifically, the memory device 1200' is configured as a multi-chip package so that the data storage capacity of the memory system 1000' can be increased and the operating speed of the memory system 1000' can be improved.

[0095] Figure 5 2 is a block diagram showing a configuration of a computing system 2000 according to an embodiment of the present disclosure. Hereinafter, descriptions of contents overlapping with those described above will be omitted.

[0096] Reference Figure 5 , the computing system 2000 includes a memory device 2100, a CPU 2200, a RAM 2300, a user interface 2400, a power supply 2500, a system bus 2600, and the like.

[0097] The memory device 2100 stores data provided through the user interface 2400, data processed by the CPU 2200, and the like. In addition, the memory device 2100 is electrically connected to the CPU 2200, the RAM 2300, the user interface 2400, the power supply 2500, and the like through the system bus 2600. For example, the memory device 2100 may be connected to the system bus 2600 through a controller (not shown) or directly. When the memory device 2100 is directly connected to the system bus 2600, the function of the controller may be performed by the CPU 2200, the RAM 2300, and the like.

[0098] The memory device 2100 may be a non-volatile memory. The memory device 2100 may have a reference Figures 1A to 2Q The structure described, and according to the reference Figures 1A to 2Q The memory device 2100 is manufactured by the manufacturing method described. In an embodiment, the memory device 2100 may include: a stacked structure including a plurality of insulating layers and a plurality of conductive layers alternately stacked; a channel structure penetrating the stacked structure; a plurality of data storage patterns respectively inserted between the conductive layers and the channel structure; a plurality of blocking patterns respectively inserted between the conductive layers and the data storage patterns; a plurality of insulating patterns respectively inserted between the insulating layers and the channel structure; and a plurality of insulating pads inserted between the insulating layers and the insulating patterns, the plurality of insulating pads respectively surrounding the insulating patterns. The structure and manufacturing method of the memory device 2100 are the same as those described above, and therefore, a detailed description thereof will be omitted.

[0099] The memory device 2100 may include a Figure 4 A multi-chip package of multiple memory chips is described.

[0100] The computing system 2000 configured as described above may be a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3D television, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a device for communicating information in a wireless environment, one of the various electronic devices constituting a home network, one of the various electronic devices constituting a computer network, one of the various electronic devices constituting a remote information network, an RFID device, and the like.

[0101] As described above, the computing system 2000 according to the embodiment of the present disclosure includes the memory device 2100 having improved integration and improved characteristics, and thus the characteristics of the computing system 2000 may also be improved.

[0102] Figure 6 30 is a block diagram showing a configuration of a computing system 3000 according to an embodiment of the present disclosure.

[0103] Reference Figure 6 , the computing system 3000 includes a software layer, which includes an operating system 3200, an application 3100, a file system 3300, a conversion layer 3400, etc. In addition, the computing system 3000 includes a hardware layer of a memory device 3500, etc.

[0104] The operating system 3200 may manage software resources, hardware resources, etc. of the computing system 3000 and control program execution of the central processing unit. The application 3100 is one of various application programs running on the computing system 3000 and may be a utility program executed by the operating system 3200.

[0105] The file system 3300 means a logical structure for managing data, files, etc. in the computing system 3000, and organizes data or files stored in the memory device 3500 according to rules. The file system 3300 may be determined according to the operating system 3200 used in the computing system 3000. For example, when the operating system 3200 is one of Microsoft's Windows operating systems, the file system 3300 may be a file allocation table (FAT) or an NT file system (NTFS). When the operating system 3200 is one of the Unix / Linux operating systems, the file system 3300 may be an extended file system (EXT), a Unix file system (UFS), or a journaled file system (JFS).

[0106] In the drawing, the operating system 3200 , the application 3100 , and the file system 3300 are shown as separate blocks. However, the application 3100 and the file system 3300 may be included in the operating system 3200 .

[0107] In response to a request from the file system 3300, the translation layer 3400 translates the address into a form suitable for the memory device 3500. For example, the translation layer 3400 translates the logical address generated by the file system 3300 into a physical address of the memory device 3500. The mapping information between the logical address and the physical address may be stored as an address translation table. For example, the translation layer 3400 may be a flash translation layer (FTL), a universal flash link layer (ULL), etc.

[0108] The memory device 3500 may be a non-volatile memory. The memory device 3500 may have a reference Figures 1A to 2Q The structure described, and according to the reference Figures 1A to 2Q The memory device 3500 is manufactured by the manufacturing method described. In an embodiment, the memory device 3500 may include: a stacked structure including a plurality of insulating layers and a plurality of conductive layers alternately stacked; a channel structure penetrating the stacked structure; a plurality of data storage patterns respectively inserted between the conductive layers and the channel structure; a plurality of blocking patterns respectively inserted between the conductive layers and the data storage patterns; a plurality of insulating patterns respectively inserted between the insulating layers and the channel structure; and a plurality of insulating pads inserted between the insulating layers and the insulating patterns, the plurality of insulating pads respectively surrounding the insulating patterns. The structure and manufacturing method of the memory device 3500 are the same as those described above, and therefore, a detailed description thereof will be omitted.

[0109] The computing system 3000 configured as described above may be divided into an operating system layer executed in an upper region and a controller layer executed in a lower region. The application 3100, the operating system 3200, and the file system 3300 are included in the operating system layer and may be driven by a working memory of the computing system 3000. In addition, the conversion layer 3400 may be included in the operating system layer or the controller layer.

[0110] As described above, the computing system 3000 according to the embodiment of the present disclosure includes the memory device 3500 having improved integration and improved characteristics, and thus the characteristics of the computing system 3000 may also be improved.

[0111] According to the present disclosure, a semiconductor device having a stable structure and improved reliability can be provided.

[0112] Embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, those terms are only used to illustrate the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-mentioned embodiments, and many changes can be made within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications can also be made based on the technical scope of the present disclosure.

[0113] As long as they are not defined differently, all terms (including technical or scientific terms) used herein have the meanings commonly understood by those skilled in the art to which the present disclosure belongs. Terms with definitions defined in dictionaries should be understood so that they have meanings consistent with the context of the relevant technology. As long as they are not clearly defined in this application, terms should not be understood in an ideal or overly formal manner.

[0114] CROSS-REFERENCE TO RELATED APPLICATIONS

[0115] This application claims the benefit of Korean Patent Application No. 10-2020-0021275 filed on February 20, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor device, comprising: A stacked structure comprising a plurality of insulating layers and a plurality of conductive layers stacked alternately; a channel structure penetrating the stacked structure; a plurality of data storage patterns, wherein the plurality of data storage patterns are respectively interposed between the conductive layer and the channel structure; a plurality of barrier patterns, wherein the plurality of barrier patterns are respectively interposed between the conductive layer and the data storage pattern; a plurality of insulating patterns, wherein the plurality of insulating patterns are respectively interposed between the insulating layer and the channel structure; as well as A plurality of insulating pads are interposed between the insulating layer and the insulating pattern, and the plurality of insulating pads respectively surround the insulating pattern, wherein the plurality of insulating pads are spaced apart from each other along a direction in which the plurality of insulating layers and the plurality of conductive layers are stacked.

2. The semiconductor device according to claim 1, wherein Each of the insulating pads extends between the conductive layer and the insulating pattern, between the barrier pattern and the insulating pattern, and between the data storage pattern and the insulating pattern.

3. The semiconductor device according to claim 1, wherein Each of the insulating pads includes an oxide layer and a charge trapping material included in the oxide layer.

4. The semiconductor device according to claim 1, wherein A recess is defined between the data storage pattern and the barrier pattern, wherein the recess is filled with the insulating liner. 5 . The semiconductor device of claim 1 , further comprising a tunnel insulating layer surrounding the channel structure, the tunnel insulating layer contacting the insulating pattern and the data storage pattern.

6. The semiconductor device according to claim 5, wherein: The tunnel insulating layer contacts the insulating liner.

7. The semiconductor device according to claim 1, wherein For each of the data storage patterns, a thickness at an end portion is different from a thickness at a central portion.

8. The semiconductor device according to claim 1, wherein A sidewall of the insulating pattern protrudes further toward the channel structure than a sidewall of the conductive layer.

9. The semiconductor device according to claim 1, wherein: A sidewall of the insulating liner protrudes further toward the channel structure than a sidewall of the conductive layer.

10. The semiconductor device according to claim 1, wherein A sidewall of the data storage pattern protrudes further toward the channel structure than a sidewall of the insulation pattern and a sidewall of the insulation liner.

11. A semiconductor device, comprising: A stacked structure comprising a plurality of insulating layers and a plurality of conductive layers stacked alternately; a channel structure penetrating the stacked structure; a plurality of insulating patterns, the plurality of insulating patterns being respectively interposed between the insulating layer and the channel structure, the insulating patterns protruding further toward the channel structure than the conductive layer; a plurality of data storage patterns, the plurality of data storage patterns being respectively interposed between the conductive layer and the channel structure, the data storage patterns protruding further toward the channel structure than the insulating patterns; a plurality of barrier patterns, wherein the plurality of barrier patterns are respectively interposed between the conductive layer and the data storage pattern; as well as A plurality of insulating pads are respectively interposed between the insulating layers and the insulating patterns, wherein the plurality of insulating pads are spaced apart from each other in a direction in which the plurality of insulating layers and the plurality of conductive layers are stacked.

12. The semiconductor device according to claim 11, wherein The plurality of insulating pads surround the insulating patterns, respectively.

13. The semiconductor device according to claim 12, wherein: Each of the insulating pads extends between the conductive layer and the insulating pattern, between the barrier pattern and the insulating pattern, and between the data storage pattern and the insulating pattern.

14. The semiconductor device according to claim 12, wherein: Each of the insulating pads includes an oxide layer and a charge trapping material included in the oxide layer.

15. The semiconductor device according to claim 12, wherein: A recess is defined between the data storage pattern and the barrier pattern, wherein the recess is filled with the insulating liner. 16 . The semiconductor device of claim 11 , further comprising a tunnel insulating layer surrounding the channel structure, the tunnel insulating layer contacting the insulating pattern and the data storage pattern.

17. The semiconductor device according to claim 11, wherein For each of the data storage patterns, a thickness at an end portion is different from a thickness at a central portion.

18. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a stacked structure including a plurality of first sacrificial layers and a plurality of insulating layers stacked alternately; forming a first opening penetrating the stacked structure; forming a second opening by etching the insulating layer; forming a protection pattern on a sidewall of the first sacrificial layer; forming barrier patterns on the protection patterns respectively; forming a data storage layer in the first opening and the second opening; forming an insulating pattern on a portion of the data storage layer corresponding to the second opening; forming a channel structure on the insulating pattern and the data storage layer; forming a third opening exposing the protection pattern by selectively removing the first sacrificial layer; removing the protection pattern to partially expose the data storage layer; as well as A plurality of insulating pads respectively surrounding the insulating patterns are formed by partially oxidizing the data storage layer through the third openings, wherein portions of the data storage layer covered by the blocking pattern are not oxidized but remain.

19. The method according to claim 18, further comprising the steps of: After forming the insulating liner, a conductive layer is formed in the third opening.

20. The method according to claim 18, wherein: When the first sacrificial layer is removed, the data storage layer is protected by the protection pattern.

21. The method according to claim 18, wherein: The step of forming the third opening includes etching the protection pattern and the insulating layer.

22. The method according to claim 18, wherein: The step of forming the protection pattern comprises the following steps: forming a first protection pattern by oxidizing the first sacrificial layer; and A second protection pattern is formed on the first protection pattern.

23. The method according to claim 22, wherein: The second protection pattern includes a material having an etch selectivity with respect to the first protection pattern.

24. The method according to claim 22, wherein: The step of forming the blocking pattern comprises the following steps: forming a second protection layer in the first opening and the second opening along the first protection pattern and the surface of the insulating layer; forming a second sacrificial pattern on a portion of the second protective layer corresponding to the second opening; and The blocking pattern is formed by partially oxidizing the second protection layer exposed by the second sacrificial pattern.

25. The method according to claim 24, further comprising the steps of: After forming the blocking pattern, removing the second sacrificial pattern; as well as The second protection pattern interposed between the first protection pattern and the blocking pattern is formed by etching the second protection layer exposed by the blocking pattern.

26. The method of claim 18, wherein: The step of forming the insulating liner includes oxidizing the data storage layer exposed between the barrier pattern and the insulating layer.

27. The method according to claim 18, further comprising the steps of: Before forming the insulating liner, the insulating layer is etched through the third opening.

28. The method according to claim 18, further comprising the steps of: Before forming the insulating liner, the data storage layer exposed through the third opening is etched.

29. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a stacked structure including a plurality of first sacrificial layers and a plurality of insulating layers that are alternately stacked; forming a first opening penetrating the stacked structure; forming a second opening by etching the insulating layer; forming a blocking pattern on a sidewall of the first sacrificial layer; forming a data storage layer in the first opening and the second opening; forming an insulating pattern on a portion of the data storage layer corresponding to the second opening; forming a channel structure on the insulating pattern and the data storage layer; forming a third opening by selectively removing the first sacrificial layer; etching the insulating layer through the third opening to partially expose the data storage layer; as well as A plurality of insulating pads respectively surrounding the insulating patterns are formed by partially oxidizing the data storage layer through the third openings. 30 . The method of claim 29 , further comprising forming a conductive layer in the third opening.

31. The method of claim 29, wherein: The step of forming the blocking pattern comprises the following steps: forming a protective layer in the first opening and the second opening along surfaces of the first opening and the second opening; forming a second sacrificial pattern on a portion of the protection layer corresponding to the second opening; and The blocking pattern is formed by partially oxidizing the protection layer exposed by the second sacrificial pattern.

32. The method according to claim 31, further comprising the steps of: After forming the blocking pattern, removing the second sacrificial pattern; as well as A protection pattern interposed between the first sacrificial layer and the blocking pattern is formed by etching the protection layer exposed by the blocking pattern.

33. The method according to claim 29, further comprising the steps of: Before forming the insulating liner, the data storage layer exposed through the third opening is etched.

34. The method of claim 29, wherein: The step of forming the insulating liner includes protecting other portions of the data storage layer using the barrier pattern.

35. The method of claim 29, wherein: The step of forming the insulating liner includes oxidizing a portion of the data storage layer interposed between the insulating layer and the insulating pattern.

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