Integrated Chip, Memory Device and Method for Forming the Same

Abstract

In some embodiments, the present disclosure relates to an integrated chip, a memory device, and a method of forming the same. The memory device includes a bottom electrode over a lower interconnect within a lower interlayer dielectric (ILD) layer disposed over a substrate. A data storage structure is located over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is located on the first top electrode layer. The second top electrode layer is less prone to oxidation compared to the first top electrode layer. A top electrode via is located over the second top electrode layer and is electrically coupled to the second top electrode layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to an integrated chip, a memory device, and a method of forming the same. Background Art

[0002] Many modern electronic devices include an electronic memory configured to store data. The electronic memory can be a volatile memory or a non-volatile memory. A volatile memory stores data when powered on, while a non-volatile memory is capable of storing data when powered off. Resistive random access memory (RRAM) devices are a promising candidate for next-generation non-volatile memory technology. This is because RRAM devices have many advantages, including fast write times, high durability, low power consumption, and low sensitivity to radiation damage. Summary of the Invention

[0003] According to one aspect of the present invention, there is provided a memory device including: a bottom electrode disposed above a lower interconnect, the lower interconnect being within a lower interlayer dielectric layer above a substrate; a data storage structure disposed above the bottom electrode; a first top electrode layer disposed above the data storage structure; a second top electrode layer located on the first top electrode layer, wherein the second top electrode layer is more oxidation-resistant than the first top electrode layer; and a top electrode via located above the second top electrode layer and electrically coupled to the second top electrode layer.

[0004] According to another aspect of the present invention, there is provided an integrated chip including: a memory device disposed above a substrate, the memory device including a data storage structure disposed between a bottom electrode and a multi-layer top electrode; a top electrode via disposed above the multi-layer top electrode and electrically coupled to the multi-layer top electrode; wherein the multi-layer top electrode includes a first top electrode layer disposed above the data storage structure and a second top electrode layer located on the first top electrode layer, and includes a material different from that of the first top electrode layer; and wherein the second top electrode layer has a greater corrosion potential than the first top electrode layer.

[0005] According to yet another aspect of the present invention, there is provided a method of forming a memory device, including: forming a data storage layer on a bottom electrode layer above a substrate; forming a first top electrode layer above the data storage layer and forming a second top electrode layer above the first top electrode layer, wherein the corrosion potential of the first top electrode layer is less than that of the second top electrode layer; performing a first patterning process on the first top electrode layer and the second top electrode layer to define the multi-layer top electrode; and performing a second patterning process on the data storage layer and the bottom electrode layer to define the data storage structure and the bottom electrode. Brief Description of the Drawings

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings, aspects of the present invention are best understood. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clear discussion, the dimensions of the various components can be increased or decreased arbitrarily.

[0007] Figure 1 A cross-sectional view of some embodiments of an integrated chip having a memory device is shown, the memory device including a multi-layer top electrode configured to mitigate oxide formation during manufacturing.

[0008] Figure 2 A cross-sectional view of some additional embodiments of an integrated chip having a memory device is shown, the memory device including a multi-layer top electrode configured to mitigate oxide formation during manufacturing.

[0009] Figure 3 A cross-sectional view of some additional embodiments of an integrated chip having a memory device including a multi-layer top electrode is shown.

[0010] Figures 4A to 6C A cross-sectional view of some additional embodiments of an integrated chip having a memory device including a multi-layer top electrode is shown.

[0011] Figures 7 to 17 A cross-sectional view of some embodiments of a method of forming an integrated chip having a memory device is shown, the memory device including a multi-layer top electrode configured to mitigate oxide formation during manufacturing.

[0012] Figure 18 A flowchart of some embodiments of a method of forming an integrated chip having a memory device is shown, the memory device including a multi-layer top electrode configured to mitigate oxide formation during manufacturing. Detailed Description

[0013] The following disclosure provides many different embodiments or examples for implementing the features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in the various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] In addition, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. Except for the orientation shown in the figures, the spatial relationship terms are intended to include different orientations of the device during use or operation. The device may be positioned otherwise (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly.

[0015] Resistive random access memory (RRAM) devices are typically formed within an interlayer dielectric (ILD) layer on the back-end-of-line (BEOL) of an integrated chip. Such RRAM devices generally include a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode may be coupled to an underlying interconnect, while the top electrode may be coupled to an overlying interconnect through a top electrode via. The top electrode may be formed by depositing and patterning a conductive material over the data storage structure. After patterning, the top electrode is covered by an upper interlayer dielectric (ILD) layer, which is subsequently etched to define a top electrode via aperture that exposes the upper surface of the top electrode. The top electrode via aperture is filled with a conductive material to define the top electrode via.

[0016] However, between forming the top electrode via aperture and filling the aperture of the top electrode via with a conductive material, the upper surface of the top electrode may be exposed to the surrounding environment (e.g., air). The surrounding environment may cause an oxide to form along the exposed upper surface of the top electrode. When the top electrode via is subsequently formed, the oxide separates the top electrode from the top electrode via. Since the oxide may have a relatively large thickness (e.g., greater than or equal to about 20 angstroms), it increases the resistance between the top electrode and the top electrode via. The increased resistance may result in a degradation of the performance of the associated RRAM device.

[0017] In addition, due to process tolerances, along the outer edge of the wafer, the increase in resistance between the top electrode and the top electrode via may be worse. For example, process tolerances may cause the oxide to form with a greater thickness along the outer edge of the wafer within the central region of the wafer. The difference in oxide thickness results in the RRAM devices along the outer edge of the wafer having a resistance between the top electrode and the top electrode via that is about 30% to 40% higher than that of the RRAM devices within the central region of the wafer. The difference in resistance may exacerbate the degradation of the performance of the RRAM devices and / or cause other difficulties in reading and / or writing data to / from the RRAM array.

[0018] In some embodiments, the present disclosure relates to a memory device (e.g., an RRAM device) having a multi-layer top electrode configured to mitigate oxide formation between the multi-layer top electrode and an overlying top electrode via. The memory device includes a data storage structure disposed between a bottom electrode and the multi-layer top electrode. The multi-layer top electrode includes a first top electrode layer having a first corrosion potential and an overlying second top electrode layer having a second corrosion potential higher than the first corrosion potential. The top electrode via is disposed on the second top electrode layer. Because the second corrosion potential is higher than the first corrosion potential, the second top electrode layer can mitigate the formation of oxide between the multi-layer top electrode and the top electrode via. By mitigating the formation of oxide between the multi-layer top electrode and the top electrode via, the resistance between the multi-layer top electrode and the top electrode via can be reduced, and the performance of the memory device can be improved.

[0019] Figure 1 A cross-sectional view of some embodiments of an integrated chip 100 having a memory device including a multi-layer top electrode configured to mitigate oxide formation is shown.

[0020] The integrated chip 100 includes a memory device 108 within a dielectric structure 104 disposed above a substrate 102. The dielectric structure 104 includes a plurality of stacked interlayer dielectric (ILD) layers. In some embodiments, the plurality of stacked ILD layers may include one or more lower ILD layers 104L disposed between the memory device 108 and the substrate 102, and an upper ILD layer 104U surrounding the memory device 108. The lower ILD layer 104L surrounds a lower interconnect 106 disposed below the memory device 108.

[0021] The memory device 108 includes a bottom electrode 110, a data storage structure 112 disposed above the bottom electrode 110, and a multi-layer top electrode 114 disposed above the data storage structure 112. The multi-layer top electrode 114 includes a first top electrode layer 114a and a second top electrode layer 114b located above the first top electrode layer 114a. The first top electrode layer 114a includes a material different from the second top electrode layer 114b. The first top electrode layer 114a separates the second top electrode layer 114b from the data storage structure 112. In some embodiments, the second top electrode layer 114b completely covers the top surface of the first top electrode layer 114a.

[0022] The top electrode via 116 extends through the upper ILD layer 104U to contact the multi-layer top electrode 114. The first top electrode layer 114a is separated from the bottom of the top electrode via 116 by the second top electrode layer 114b. In some embodiments, the top electrode via 116 extends to a non-zero distance 118 below the top of the multi-layer top electrode 114 such that the bottom of the top electrode via 116 is embedded within the multi-layer top electrode 114. In some such embodiments, the second top electrode layer 114b has a first non-zero thickness directly below the top electrode via 116 and a second thickness outside the top electrode via 116, the second thickness being greater than the first non-zero thickness.

[0023] The second top electrode layer 114b is less prone to oxidation than the first top electrode layer 114a. Because the second top electrode layer 114b is less prone to oxidation than the first top electrode layer 114a, the formation of an oxide along the upper surface of the multi-layer top electrode 114 (e.g., between the top electrode via 116 and the multi-layer top electrode 114) during the fabrication of the memory device 108 is alleviated. By alleviating the formation of the oxide along the upper surface of the multi-layer top electrode 114, the resistance between the top electrode via 116 and the multi-layer top electrode 114 is reduced. For example, compared to a memory device without a multi-layer top electrode, the resistance between the top electrode via 116 and the multi-layer top electrode 114 can be reduced by about 50% to about 100% (e.g., from about 200 ohms per square to about 50 ohms per square).

[0024] Figure 2 A cross-sectional view of some other embodiments of an integrated chip 200 having a memory device is shown, the memory device including a multi-layer top electrode configured to alleviate oxide formation during fabrication.

[0025] The integrated chip 200 includes a memory device 108 disposed within a dielectric structure 104 disposed above a substrate 102. In some embodiments, the dielectric structure 104 includes a plurality of stacked interlayer dielectric (ILD) layers 104a - 104e. The plurality of stacked ILD layers 104a - 104e includes one or more lower ILD layers 104a - 104d, the one or more lower ILD layers 104a - 104d laterally surrounding one or more lower interconnect layers configured to couple the memory device 108 to access devices 202 disposed within the substrate 102. The one or more lower interconnect layers may include conductive contacts 204, interconnect lines 206, and interconnect vias 208. In some embodiments, the access devices 202 may include transistor devices (e.g., MOSFET devices, BJTs, etc.).

[0026] In some embodiments, a lower insulating structure 210 is disposed over one or more lower ILD layers 104a - 104d. The lower insulating structure 210 includes sidewalls that define an opening extending through the lower insulating structure 210. In various embodiments, the lower insulating structure 210 may include one or more of silicon nitride, silicon dioxide, silicon carbide, etc. In some embodiments, an upper insulating structure 220 is disposed over the memory device 108 and on the lower insulating structure 210. The upper insulating structure 220 extends continuously from a first position directly over the memory device 108 to a second position adjacent to the upper surface of the lower insulating structure 210. The upper insulating structure 220 separates the memory device 108 from the upper ILD layer 104e. In some embodiments, the upper insulating structure 220 may include one or more of silicon nitride, silicon dioxide, silicon carbide, etc.

[0027] The memory device 108 is disposed between the sidewalls of the lower insulating structure 210 and over the lower insulating structure 210. In some embodiments, the memory device 108 includes a bottom electrode 110 separated from a multi - layer top electrode 114 by a data storage structure 112. In some embodiments, the bottom electrode 110 may include a diffusion barrier layer 110a and a bottom metal layer 110b over the diffusion barrier layer 110a. In some embodiments, a capping layer 212 may be disposed between the data storage structure 112 and the multi - layer top electrode 114. The capping layer 212 is configured to store oxygen, which can facilitate a resistance change within the data storage structure 112.

[0028] In some embodiments, a hard mask layer 216 may be disposed on the multi - layer top electrode 114. One or more sidewall spacers 218 may be disposed on opposite sides of the multi - layer top electrode 114 and the hard mask layer 216. In some embodiments, the hard mask layer 216 may include a metal (e.g., titanium, tantalum, etc.) and / or a dielectric (e.g., nitride, carbide, etc.). In some embodiments, one or more sidewall spacers 218 may include an oxide (e.g., silicon - rich oxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), etc. A top electrode via 116 extends through the upper ILD layer 104e to electrically contact the multi - layer top electrode 114. In some embodiments, a top electrode oxide 222 separates the multi - layer top electrode 114 from the top electrode via 116.

[0029] The multi-layer top electrode 114 includes a first top electrode layer 114a and a second top electrode layer 114b above the first top electrode layer 114a. The second top electrode layer 114b has higher oxidation resistance than the first top electrode layer 114a. For example, in some embodiments, the first top electrode layer 114a has a first corrosion potential, and the second top electrode layer 114b has a second corrosion potential greater than the first corrosion potential. In some embodiments, the first corrosion potential can be less than -0.8V, while the second corrosion potential can be greater than or equal to -0.8V. In other embodiments, the first corrosion potential can be less than -0.4V, while the second corrosion potential can be greater than or equal to -0.4V. Compared with the first top electrode layer 114a, the greater corrosion potential of the second top electrode layer 114b makes the second top electrode layer 114b less susceptible to corrosion (e.g., oxidation).

[0030] In other embodiments, the first top electrode layer 114a can include a material that forms an oxide using a first Gibbs free energy, and the second top electrode layer 114b can include a material that forms an oxide using a larger second Gibbs free energy. In some embodiments, the first top electrode layer 114a can include a material that forms an oxide using a Gibbs free energy less than about -1,900 kJ / mol, while the second top electrode layer 114b can include a material that forms an oxide using a Gibbs free energy greater than about -1100 kJ / mol. In other embodiments, the second top electrode layer 114b can include a material that forms an oxide using a Gibbs free energy greater than about -600 kJ / mol. In other embodiments, the second top electrode layer 114b can include a material that forms an oxide using a Gibbs free energy greater than about -400 kJ / mol.

[0031] Because the second top electrode layer 114b is more oxidation-resistant than the first top electrode layer 114a, the thickness of the top electrode oxide 222 on the second top electrode layer 114b is relatively small. For example, in some embodiments, the thickness of the top electrode oxide 222 can be less than or equal to about In other embodiments, the thickness of the top electrode oxide 222 can be less than or equal to about The relatively small thickness of the top electrode oxide 222 provides a relatively low resistance (e.g., less than about 60 Ohms per square) between the multi-layer top electrode 114 and the top electrode via 116.

[0032] In addition, the oxidation resistance of the second top electrode layer 114b also limits the position of the oxygen storage in the multi-layer top electrode 114 to be very close to the data storage structure 112. By placing the oxygen storage closely to the data storage structure 112, the resistance switching is improved because the distance that oxygen molecules have to travel between the oxygen storage and the conductive filament is reduced.

[0033] To prevent the etchant used to form the top electrode via 116 from over-etching through the second top electrode layer 114b (i.e., to prevent the exposure of the first top electrode layer 114a during manufacturing), the second top electrode layer 114b may also include a material with high etch resistance (e.g., using a fluorine-based etch gas). The high etch resistance allows the second top electrode layer 114b to separate the top electrode via 116 from the first top electrode layer 114a. By separating the top electrode via 116 from the first top electrode layer 114a, the first top electrode layer 114a is not exposed to the surrounding environment during manufacturing, thereby preventing the formation of a thick oxide between the multi-layer top electrode 114 and the top electrode via 116.

[0034] In some embodiments, the second top electrode layer 114b may include a material that has a higher boiling point than the first top electrode layer 114a when exposed to an etchant containing fluorine gas. The higher boiling point of the second top electrode layer 114b makes it more difficult to etch the second top electrode layer 114b. In some embodiments, the second top electrode layer 114b may include a material that has a boiling point greater than or equal to about 550 °C when exposed to an etchant containing fluorine gas. In other embodiments, the second top electrode layer 114b may include a material that has a boiling point greater than or equal to about 800 °C when exposed to an etchant containing fluorine gas. In other embodiments, the second top electrode layer 114b may include a material that has a boiling point greater than or equal to about 1500 °C when exposed to an etchant containing fluorine gas. In some embodiments, when exposed to an etchant containing fluorine gas, the second top electrode layer 114b may include a material with a boiling point greater than or equal to about 300 °C, while the first top electrode layer 114a may include a material with a boiling point lower than about 300 °C when exposed to an etchant containing fluorine gas.

[0035] In some embodiments, the thickness of the second top electrode layer may also be in the range of about 20 angstroms and about The second top electrode layer 114b having a thickness greater than allows the second top electrode layer 114b to prevent the top electrode via 116 from extending through the second top electrode layer 114b during manufacturing.

[0036] In addition, in some other embodiments, the first top electrode layer 114a may include a material having a first resistivity, and the second top electrode layer 114b may include a material having a second resistivity greater than the first resistivity. For example, in some embodiments, the first top electrode layer 114a may include a material with a resistivity less than about 20 ohm-cm, while the second top electrode layer 114b may have a resistivity greater than about 100 μohm-cm. In such embodiments, the lower resistance of the first top electrode layer 114a can reduce the overall resistance of the multi-layer top electrode 114. Additionally, limiting the thickness of the second top electrode layer 114b to be less than about allows the multi-layer top electrode 114 to have a relatively low total resistance, thereby providing good performance of the memory device 108. In some embodiments, the thickness of the first top electrode layer 114a is greater than the thickness of the second top electrode layer 114b to further improve the relatively low overall resistance.

[0037] In some embodiments, the first top electrode layer 114a may include a metal such as titanium, tantalum, etc. In some embodiments, the second top electrode layer 114b may include a metal and / or a metal nitride. For example, in various embodiments, the second top electrode layer 114b may include titanium nitride, ruthenium, tungsten, tin, zirconium, aluminum nitride, silver, strontium, thallium, vanadium, zirconium nitride, hafnium nitride, etc.

[0038] Figure 3 A cross-sectional view of some additional embodiments of an integrated chip 300 having a memory device including a multi-layer top electrode is shown.

[0039] The integrated chip 300 includes a substrate 102, and the substrate 102 includes an embedded memory region 302 and a logic region 304. A dielectric structure 104 is disposed above the substrate 102. The dielectric structure 104 includes a plurality of stacked ILD layers 104a - 104c. In some embodiments, the plurality of stacked ILD layers 104a - 104c may include silicon dioxide, SiCOH, fluorosilicate glass, silicate glass (e.g., borophosphate silicate glass (BSG)), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), etc. In some embodiments, two or more adjacent layers of the plurality of stacked ILD layers 104a - 104c may be separated by an etch stop layer (not shown) including nitride, carbide, etc.

[0040] Logic region 304 includes transistor devices 306 disposed within substrate 102. Transistor devices 306 include a source region 306a, a drain region 306b separated from source region 306a by a channel region, and a gate structure 306c over the channel region. Source region 306a is coupled to a first plurality of interconnect layers 308 surrounded by dielectric structure 104. The first plurality of interconnect layers 308 includes conductive contacts, interconnect lines, and / or interconnect vias. In some embodiments, the first plurality of interconnect layers 308 may include one or more of copper, tungsten, aluminum, etc.

[0041] Embedded memory region 302 includes access devices 202 disposed within substrate 102. In some embodiments, access devices 202 may include MOSFET devices having a gate structure 202c that is laterally disposed between a source region 202a and a drain region 202b. In some embodiments, gate structure 202c may include a gate electrode separated from substrate 102 by a gate dielectric. In some such embodiments, source region 202a is coupled to a source line SL, and gate structure 202c is coupled to a word line WL. In other embodiments, access devices 202 may include HEMTs, BJTs, JFETs, etc.

[0042] Access devices 202 are coupled to memory device 108 via a plurality of lower interconnect layers 310 disposed within a plurality of lower ILD layers 104a - 104b. In some embodiments, a lower insulating structure 210 vertically separates the plurality of lower ILD layers 104a - 104b from memory device 108. In such embodiments, a bottom electrode 110 extends through an opening in lower insulating structure 210 to make electrical contact with one of the plurality of lower interconnect layers 310. In some embodiments, lower insulating structure 210 includes a first dielectric layer 210a and a second dielectric layer 210b over the first dielectric layer 210a. In some embodiments, first dielectric layer 210a may include silicon-rich oxide, silicon carbide, silicon nitride, etc. In some embodiments, second dielectric layer 210b may include silicon carbide, silicon nitride, etc.

[0043] Memory device 108 includes a bottom electrode 110 separated from a multi-layer top electrode 114 by a data storage structure 112. In some embodiments, bottom electrode 110 may include a diffusion barrier layer 110a and a bottom metal layer 110b over the diffusion barrier layer 110a. In some embodiments, diffusion barrier layer 110a may include tantalum nitride, titanium nitride, etc. In some embodiments, bottom metal layer 110b may include tantalum, titanium, tantalum nitride, titanium nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, etc.

[0044] In some embodiments, the memory device 108 includes RRAM devices. In such embodiments, the data storage structure 112 includes a high-k dielectric material, such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), hafnium aluminum oxide (HfAlO), hafnium zirconium oxide (HfZrO), and the like. In other embodiments, the memory device 108 may include magnetoresistive random access memory (MRAM) devices, ferroelectric random access memory (FRAM) devices, and the like. In such embodiments, the data storage structure 112 may include magnetic tunnel junctions, ferroelectric materials, and the like.

[0045] In some embodiments, a capping layer 212 is disposed between the data storage structure 112 and the multi-layer top electrode 114. In some embodiments, the capping layer 212 may include a metal or metal oxide with a relatively low oxygen concentration. For example, in some embodiments, the capping layer 212 may include a metal, such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), hafnium (Hf), platinum (Pt), aluminum (Al), and the like. In other embodiments, the capping layer 212 may include a metal oxide, such as titanium oxide (TiO), hafnium oxide (HfO), zirconium oxide (ZrO), germanium oxide (GeO), cerium oxide (CeO).

[0046] The multi-layer top electrode 114 includes a first top electrode layer 114a and a second top electrode layer 114b. A top electrode via 116 is provided on the second top electrode layer 114b, and an upper interconnect 312 is coupled to the top electrode via 116. The upper interconnect 312 extends laterally beyond the opposing sidewalls of the top electrode via 116. The top electrode via 116 and the upper interconnect 312 may include one or more of aluminum, copper, tungsten, and the like. In some embodiments, the upper interconnect 312 is further coupled to a bit line BL. During operation, signals (e.g., voltage and / or current) can be selectively applied to the word line WL, the source line SL, and the bit line BL to read data from and write data to the memory device 108.

[0047] Figures 4A to 4B Some additional embodiments of an integrated chip having a memory device including a multi-layer top electrode are shown. Figure 4A A cross-sectional view 400 of the integrated chip is shown. Figure 4B A top view 406 is shown, which shows the top electrode via and the second top electrode layer (but not other layers such as the upper ILD layer).

[0048] As Figure 4AAs shown in the cross-sectional view 400, the memory device 108 is disposed within a dielectric structure 104 above a substrate 102. In some embodiments, the memory device 108 may be located above a lower insulating structure 210 having sidewalls that define an opening extending through the lower insulating structure 210. The opening may be directly above the lower interconnect 106. In some embodiments, the lower interconnect 106 may include a conductive core 106a and a diffusion barrier layer 106b surrounding the conductive core 106a. The diffusion barrier layer 106b may include titanium nitride, tantalum nitride, etc. The conductive core 106a may include a metal such as copper, aluminum, tungsten, etc.

[0049] The memory device 108 includes a data storage structure 112 disposed between a bottom electrode 110 and a multi-layer top electrode 114. The bottom electrode 110 includes a diffusion barrier layer 110a and a bottom metal layer 110b located above the diffusion barrier layer 110a. In some embodiments, the diffusion barrier layer 110a extends from within the opening in the lower insulating structure 210 to above the lower insulating structure 210. In some embodiments, the memory device 108 includes a central region 402 disposed above the opening and a peripheral region 404 that laterally surrounds the central region 402. The multi-layer top electrode 114 has a first upper surface within the central region 402 that is recessed below a second upper surface of the multi-layer top electrode 114 within the peripheral region 404.

[0050] A top electrode via 116 is disposed above the multi-layer top electrode 114. The top electrode via 116 includes a barrier layer 116a surrounding a conductive core 116b. In some embodiments, the barrier layer 116a may be separated from a second top electrode layer 114b by a top electrode oxide 222. In various embodiments, the barrier layer 116a may be configured to function as a diffusion barrier layer and / or an adhesive layer. The barrier layer 116a may include titanium nitride, tantalum nitride, etc. The conductive core 116b may include a metal such as copper, aluminum, tungsten, etc.

[0051] As Figure 4B shown in the top view 406, the peripheral region 404 extends completely around the central region 402 of the memory device 108. Additionally, the barrier layer 116a of the top electrode via 116 extends completely around the conductive core 116b of the top electrode via 116.

[0052] Referring again to Figure 4ACross-sectional view 400, the multi-layer top electrode 114 includes a first top electrode layer 114a and a second top electrode layer 114b. In some embodiments, the second top electrode layer 114b has a first curved surface facing the first top electrode layer 114a. In some additional embodiments, the second top electrode layer 114b has a second curved surface facing away from the first top electrode layer 114a. In some embodiments, the top electrode oxide 222 is disposed along the second curved surface.

[0053] In some embodiments, the data storage structure 112, the bottom electrode 110, and the multi-layer top electrode 114 may have different widths. For example, in some embodiments, the data storage structure 112 may have a greater width than the multi-layer top electrode 114 and the bottom metal layer 110b. In such embodiments, the data storage structure 112 projects laterally outward from the sidewalls of the multi-layer top electrode 114 and the bottom metal layer 110b.

[0054] Figure 5 A cross-sectional view shows some additional embodiments of an integrated chip 500 having a memory device including a multi-layer top electrode.

[0055] The integrated chip 500 includes a memory device 108 within a dielectric structure 104 disposed above a substrate 102. The memory device 108 includes a bottom electrode 110 separated from the multi-layer top electrode 114 by a data storage structure 112 and a capping layer 212. In some embodiments, the bottom electrode 110 includes a diffusion barrier layer 110a and a bottom metal layer 110b. The multi-layer top electrode 114 includes a first top electrode layer 114a and a second top electrode layer 114b above the first top electrode layer 114a. The second top electrode layer 114b has a higher corrosion potential than the first top electrode layer 114a. A hard mask layer 216 may be disposed above the second top electrode layer 114b.

[0056] A first oxide 502 may be disposed along the outer edge of the first top electrode layer 114a, and a second oxide 504 may be disposed along the outer edge of the second top electrode layer 114b. In some embodiments, the first oxide 502 may have a greater thickness than the second oxide 504. In some embodiments, the first oxide 502 may include a first material (e.g., tantalum oxide), and the second oxide 504 may include a second material different from the first material (e.g., titanium oxynitride). In some embodiments, the first oxide 502 and / or the second oxide 504 may extend laterally beyond the outermost sidewall of the hard mask layer 216.

[0057] The top electrode via 116 is disposed on the second top electrode layer 114b. The top electrode oxide 222 may be disposed between the second top electrode layer 114b and the top electrode via 116. In some embodiments, the top electrode oxide 222 may include the same material as the second oxide 504 (e.g., titanium oxynitride). In some embodiments, the bottom electrode 110 may be surrounded by a third oxide 506 disposed along the sidewall of the bottom metal layer 110b and / or a fourth oxide 508 disposed along the sidewall of the diffusion barrier layer 110a.

[0058] In some embodiments, an upper insulating structure 220 may be disposed over the memory device 108. The upper insulating structure 220 separates the memory device 108 from the upper ILD layer 104U. In some embodiments, the upper insulating structure 220 may include a plurality of insulating layers 220a - 220c. In some embodiments, the plurality of insulating layers 220a - 220c may include one or more of silicon carbide, silicon nitride, silicon oxynitride, plasma enhanced (PE) silicon oxynitride (PE - SiON), PE oxide (PE - Ox), etc. For example, in some embodiments, the first insulating layer 220a may include silicon nitride, the second insulating layer 220b may include silicon carbide, and the third insulating layer 220c may include silicon oxide.

[0059] It has been recognized that during the fabrication of a wafer, memory devices formed on different portions of the wafer may be exposed to different tolerances. For example, memory devices formed along the outer edge of the wafer may be exposed to different etching and / or deposition tolerances compared to memory devices formed within the central region of the wafer. It has also been recognized that different tolerances may result in different etching rates and / or oxidation thicknesses, which may lead to performance issues in the memory devices. However, due to the high resistance to oxidation and etching, the disclosed second top electrode layer is capable of reducing performance variations across different regions of the wafer.

[0060] For example, Figure 6A A top view 600 of some embodiments of a wafer 602 is shown, the wafer 602 including a plurality of die regions 604 corresponding to integrated chip dies, respectively. The plurality of die regions 604 include a central die region 604c and an edge die region 604e. The central die region 604c is closer to the center of the wafer 602 than the edge die region 604e.

[0061] Figure 6B A cross - sectional view 606 of some embodiments of a first die within the central die region ( Figure 6A of 604c) is shown, Figure 6C A cross - sectional view 608 of some embodiments of a second die within the edge die region ( Figure 6A of 604e) is shown.

[0062] As shown Figure 6B in cross-sectional view 606 of Figure 6A 604c), the first die within the central die region

[0063] As shown Figure 6C in cross-sectional view 608 of Figure 6A 604e), the second die within the edge die region includes second memory devices, each having a second top electrode layer 114b disposed on the first top electrode layer 114a. The second memory devices also include a hard mask layer 216 disposed on the second top electrode layer 114b. Due to differences in process tolerances, the hard mask layer 216 of the second memory devices includes a second thickness t2 that is greater than the first thickness t1. In some embodiments, the first thickness t1 may be between about 50% and about 75% of the second thickness t2.

[0064] The top electrode via 116 extends through the hard mask layer 216 to electrically contact the second top electrode layer 114b. In some embodiments, the top electrode oxide 222 may separate the top electrode via 116 from the second top electrode layer 114b. In some embodiments, the top electrode via 116 may have a third width w3 at the height of the second top electrode layer 114b and a fourth width w4 at the top of the top electrode via 116. In some embodiments, the third width w3 may be between about 50% and about 70% of the fourth width w4. In some embodiments, the top electrode via 116 may extend to a second depth d2 below the top of the second top electrode layer 114b, and the second depth d2 is greater than the first depth d1.

[0065] Because the second top electrode layer 114b can be configured to have high etch resistance, the second top electrode layer 114b can prevent the top electrode via 116 from contacting the first top electrode layer 114a within the two first memory devices 108a and the second memory device 108b. Additionally, because the second top electrode layer 114b has a low corrosion potential, despite variations in process tolerances, the thicknesses of the top electrode oxides 222 within the first memory device ( Figure 6B ) and within the second memory device ( Figure 6C ) are relatively similar, thereby providing a relatively small memory device resistance across different regions of the wafer 602. For example, the second top electrode layer can reduce the variation in the top electrode via resistance across the wafer to less than about 10% (e.g., compared to a variation between about 40 - 50% for a wafer with memory devices having a single-layer top electrode).

[0066] Figures 7 to 17 Cross-sectional views 700 - 1700 of some embodiments of a method of forming an integrated chip having memory devices are shown, the memory devices including a multi-layer top electrode configured to mitigate oxide formation during manufacturing. Although described with respect to the method Figures 7 to 17 , it should be understood that Figures 7 to 17 the disclosed structures are not limited to this method and may exist separately as structures independent of the method.

[0067] As Figure 7As shown in the cross-sectional view 700, a substrate 102 is provided. In various embodiments, the substrate 102 can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more die on the wafer, and any other type of semiconductor and / or associated epitaxial layer. The substrate 102 includes an embedded memory region 302 and a logic region 304. In some embodiments, access devices 202 are formed within the embedded memory region 302, and transistor devices 306 are formed within the logic region 304. In some embodiments, the access devices 202 and / or the transistor devices 306 can include transistors. In some such embodiments, the access devices 202 and / or the transistor devices 306 can be formed by depositing a gate dielectric film and a gate electrode film over the substrate 102. Subsequently, the gate dielectric film and the gate electrode film are patterned to form a gate dielectric and a gate electrode. Subsequently, the substrate 102 can be implanted to form source regions and drain regions within the substrate 102 on opposite sides of the gate electrode.

[0068] In some embodiments, one or more lower interconnect layers 310 can be formed within one or more lower ILD layers 104L formed over the substrate 102. In some embodiments, the one or more lower ILD layers 104L can include a first lower ILD layer 104a and a second lower ILD layer 104b. In some embodiments, the one or more lower interconnect layers 310 can include one or more of conductive contacts, interconnect lines, and interconnect vias. The one or more lower interconnect layers 310 can be formed by forming lower ILD layers (e.g., oxide, low-k dielectric, or ultra-low-k dielectric) within the one or more lower ILD layers 104a - 104b. Over the substrate 102, the lower ILD layers are selectively etched to define via apertures and / or trenches within the lower ILD layers, conductive material (e.g., copper, aluminum, etc.) is formed within the via apertures and / or trenches, and a planarization process (e.g., a chemical mechanical planarization process) is performed to remove excess conductive material from above the lower ILD layers.

[0069] As Figure 8As shown in the cross-sectional view 800, a lower insulating structure 210 is formed on one or more lower interconnect layers 310. In some embodiments, the lower insulating structure 210 includes a plurality of different stacked dielectric materials. For example, in some embodiments, the lower insulating structure 210 includes a first dielectric layer 210a and a second dielectric layer 210b above the first dielectric layer 210a. In some embodiments, the first dielectric layer 210a may include silicon-rich oxide, silicon carbide, silicon nitride, etc. In some embodiments, the second dielectric layer 210b may include silicon carbide, silicon nitride, etc. In some embodiments, the lower insulating structure 210 may be formed by one or more deposition processes (e.g., physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, plasma-enhanced CVD (PE-CVD) process, etc.).

[0070] As Figure 9 shown in the cross-sectional view 900, a diffusion barrier layer 110a is formed within an opening 902 that extends through the lower insulating structure 210. In some embodiments, the lower insulating structure 210 is selectively etched to define the opening 902. The opening 902 extends through the lower insulating structure 210 and exposes the upper surface of one of the one or more lower interconnect layers 310. Subsequently, the diffusion barrier layer 110a is formed within the opening 902. In some embodiments, the diffusion barrier layer 110a may be formed by a deposition process (e.g., PVD process, CVD process, PE-CVD process, etc.). In some embodiments, a planarization process (e.g., chemical mechanical planarization (CMP) process) may be performed after the deposition process to remove excess material of the diffusion barrier layer 110a above the top of the lower insulating structure 210. In other embodiments (not shown), the planarization process is not performed. In such embodiments, the diffusion barrier layer 110a may completely cover the lower insulating structure 210 until it is patterned at a later time (e.g., according to a second patterning process performed in Figure 14 ).

[0071] As Figure 10 shown in the cross-sectional view 1000, a memory device stack 1002 is formed above the diffusion barrier layer 110a and the lower insulating structure 210. In some embodiments, the memory device stack 1002 may include a bottom electrode layer 1004, a data storage layer 1006 formed above the bottom electrode layer 1004, a first top electrode material 1008 formed above the data storage layer 1006, and a second top electrode material 1010 formed above the first top electrode material 1008.

[0072] In some embodiments, the bottom electrode layer 1004 may comprise a metal such as titanium, tantalum, etc. In some embodiments, the data storage layer 1006 may comprise a high-k dielectric material such as aluminum oxide, hafnium oxide, etc. In some embodiments, the first top electrode material 1008 may comprise a metal such as titanium, tantalum, etc. In some embodiments, the second top electrode material 1010 may comprise a metal and / or a metal nitride. For example, in various embodiments, the second top electrode material 1010 may comprise titanium nitride, ruthenium, tungsten, tin, zirconium, aluminum nitride, silver, strontium, thallium, vanadium, zirconium nitride, hafnium nitride, etc. The second top electrode material 1010 has higher oxidation resistance than the first top electrode material 1008. For example, in some embodiments, the first top electrode material 1008 has a first corrosion potential and the second top electrode material 1010 has a second corrosion potential greater than the first corrosion potential.

[0073] In some embodiments, the bottom electrode layer 1004, the data storage layer 1006, the first top electrode material 1008, and the second top electrode material 1010 may be formed by a plurality of different deposition processes (e.g., CVD, PE-CVD, sputtering, ALD, etc.). In some embodiments, the first top electrode material 1008 and the second top electrode material 1010 may be formed in-situ (e.g., without breaking the vacuum on the processing chamber).

[0074] In some embodiments, the second top electrode material 1010 may be deposited by a sputtering process. The sputtering process may be performed by introducing an inert sputtering gas into the processing chamber and then applying a bias voltage to the sputtering target. In some embodiments, the second top electrode material 1010 may comprise a nitride. In such embodiments, nitrogen gas may be further introduced into the processing chamber to form the second top electrode material 1010 comprising a metal nitride (e.g., titanium nitride). In some such embodiments, the inert sputtering gas may comprise argon and the sputtering target may comprise titanium. In some embodiments, a bias voltage of about 18000 W may be applied to the sputtering target and the flow ratio of nitrogen gas (N2) / argon gas (Ar) may be about 160:8. The resulting titanium nitride layer has a roughness less than about (e.g., about ), a resistivity less than about 119 ohm-centimeters (e.g., about ohm-centimeters), and a density greater than about 5.

[0075] As Figure 11 shown in the cross-sectional view 1100 of, a first patterning process is performed to define a multi-layer top electrode 114 having a first top electrode layer 114a and a second top electrode layer 114b. In some embodiments, according to the hard mask layer 216, the first patterning process selectively patterns the first top electrode material ( Figure 10 1008 of) and the second top electrode material (Figure 10 1010) is exposed to a first etchant 1102. In various embodiments, the hard mask layer 216 may include a metal (e.g., titanium, titanium nitride, tantalum, etc.) and / or a dielectric material (e.g., silicon nitride, silicon carbide, etc.). In other embodiments (not shown), the first patterning process may selectively expose the first top electrode layer 114a and the second top electrode layer 114b to the first etchant 1102 according to a photosensitive material (e.g., photoresist).

[0076] As Figure 12 shown in the cross-sectional view 1200 of, after the first patterning process, the first top electrode layer 114a and the second top electrode layer 114b may be exposed to the surrounding environment (e.g., air). For example, in some embodiments, after the first patterning process, when the substrate 102 is moved from a first processing chamber for performing the first patterning process to a second processing chamber for performing subsequent manufacturing processes, the substrate 102 may be exposed to the surrounding environment. When exposed to the surrounding environment, a first oxide 502 may be formed along the outer edge of the first top electrode layer 114a, and a second oxide 504 may be formed along the outer edge of the second top electrode layer 114b. In some embodiments, the first oxide 502 may have a greater thickness than the second oxide 504. In some embodiments, the first oxide 502 may include a first material (e.g., tantalum oxide), and the second oxide 504 may include a second material different from the first material (e.g., titanium oxynitride).

[0077] As Figure 13 shown in the cross-sectional view 1300 of, one or more sidewall spacers 218 are formed along the sidewalls of the first top electrode layer 114a, the second top electrode layer 114b, and the hard mask layer 216. In various embodiments, the one or more sidewall spacers 218 may include silicon nitride, silicon dioxide, silicon oxynitride, and / or the like. In some embodiments, the one or more sidewall spacers 218 may be formed by forming a spacer layer over the substrate 102. The spacer layer is then exposed to an etchant (e.g., a dry etchant) that removes the spacer layer from the horizontal surfaces. Removing the spacer layer from the horizontal surfaces causes portions of the spacer layer to remain as the one or more sidewall spacers 218 along the opposing sidewalls of the first top electrode layer 114a, the second top electrode layer 114b, and the hard mask layer 216.

[0078] As Figure 14 shown in the cross-sectional view 1400 of, in the data storage layer ( Figure 13 of 1006) and the bottom electrode layer ( Figure 13A second patterning process is performed on the 1004) to define a memory device 108 having a data storage structure 112 and a bottom electrode 110 including a diffusion barrier layer 110a and a bottom metal layer 110b. In some embodiments, the second patterning process selectively exposes the data storage structure ( Figure 13 of 1006) and the bottom electrode layer ( Figure 13 of 1004) to a second etchant 1402 in regions not covered by the hard mask layer 216 and one or more sidewall spacers 218.

[0079] As Figure 15 shown in cross-sectional view 1500 of, an upper insulating structure 220 is formed over the memory device 108. In some embodiments, the upper insulating structure 220 can be formed using one or more deposition techniques (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). In various embodiments, the upper insulating structure 220 can include one or more of silicon carbide, tetraethyl orthosilicate (TEOS), etc. An upper ILD layer 104U is formed over the upper insulating structure 220 to define a dielectric structure 104 on the substrate 102. In some embodiments, the upper ILD layer 104U can be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). In various embodiments, the upper ILD layer 104U can include one or more of silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, USG, porous dielectric materials, etc.

[0080] As Figure 16 shown in cross-sectional view 1600 of, via apertures 1604a - 1604b are formed within the upper ILD layer 104U. Within the embedded memory region 302, the via apertures 1604a - 1604b include a top electrode via aperture 1604a that extends from the top surface of the upper ILD layer 104U to expose the top surface of the second top electrode layer 114b. Within the logic region 304, the via apertures 1604a - 1604b include a via aperture 1604b that extends from the top surface of the upper ILD layer 104U and vertically beyond the top electrode via aperture 1604a. In some embodiments, a top electrode oxide 222 can be formed along the exposed top surface of the second top electrode layer 114b exposed by the top electrode via aperture 1604b.

[0081] In some embodiments, the upper interconnect via apertures 1604a - 1604b can be formed by a third patterning process that uses a third etchant 1602 to selectively etch the upper ILD layer 104U according to a mask layer 1606. The etchant 1602 can include a dry etchant having an etch chemistry including a fluorine - based etchant (e.g., CF4, CH2F2, CHF8, etc.). In some embodiments, the mask layer 1606 can include a multi - layer hard mask. For example, in some embodiments, the mask layer 1606 can include a first hard mask layer 1608, a second hard mask layer 1610 above the first hard mask layer 1608, and a third hard mask layer 1612 above the second hard mask layer 1610. In some embodiments, the first hard mask layer 1608 can include an oxide, the second hard mask layer 1610 can include a nitride, and the third hard mask layer 1612 can include an oxide.

[0082] As Figure 17 shown in the cross - sectional view 1700 of, a conductive material (e.g., copper, aluminum, etc.) is formed in the upper interconnect via apertures 1604a - 1604b. In some embodiments, after the conductive material is formed within the upper interconnect via apertures 1604a - 1604b, a planarization process (e.g., a CMP process) is performed to remove excess conductive material above the top of the upper ILD layer 104U. In some embodiments, the planarization process can also remove the mask layer 1606.

[0083] Figure 18 A flowchart showing some embodiments of a method 1800 for forming an integrated chip having a memory device, the memory device including a multi - layer top electrode configured to mitigate oxide formation during manufacturing.

[0084] Although the method 1800 is illustrated and described herein as a series of actions or events, it should be understood that the illustrated order of such actions or events should not be construed in a limiting sense. For example, certain actions can occur in a different order and / or concurrently with other actions or events in addition to those illustrated and / or described herein. Moreover, not all of the illustrated actions may be required to implement one or more aspects or embodiments described herein. In addition, one or more of the actions described herein can be performed in one or more separate actions and / or phases.

[0085] At action 1802, a lower interconnect layer is formed within a lower inter - layer dielectric (ILD) layer above a substrate. Figure 7 A cross - sectional view 700 showing some embodiments corresponding to action 1802 is shown.

[0086] At action 1804, a lower insulating structure is formed above the lower ILD layer and the lower interconnect layer.Figure 8 Cross-sectional view 800 corresponding to some embodiments of operation 1804 is shown.

[0087] At operation 1806, a memory device having a multi-layer top electrode is formed over the lower insulating structure. In some embodiments, the memory device may be formed according to operations 1808 - 1822.

[0088] At operation 1808, a diffusion barrier layer is formed over the lower interconnect layer. Figure 9 Cross-sectional view 900 corresponding to some embodiments of operation 1808 is shown.

[0089] At operation 1810, a bottom electrode layer is formed over the diffusion barrier layer. Figure 10 Cross-sectional view 1000 corresponding to some embodiments of operation 1810 is shown.

[0090] At operation 1812, a data storage layer is formed over the bottom electrode layer. Figure 10 Cross-sectional view 1000 corresponding to some embodiments of operation 1812 is shown.

[0091] At operation 1814, a first top electrode layer having a first corrosion potential is formed over the data storage layer. Figure 10 Cross-sectional view 1000 corresponding to some embodiments of operation 1814 is shown.

[0092] At operation 1816, a second top electrode layer having a second corrosion potential is formed over the first top electrode layer. The second corrosion potential is greater than the first corrosion potential. Figure 10 Cross-sectional view 1000 corresponding to some embodiments of operation 1816 is shown.

[0093] At operation 1818, a first patterning process is performed over the first top electrode layer and the second top electrode layer to define the multi-layer top electrode. Figure 11 Cross-sectional view 1100 corresponding to some embodiments of operation 1818 is shown.

[0094] At operation 1820, one or more sidewall spacers are formed along opposite sides of the multi-layer top electrode. Figure 13 Cross-sectional view 1300 corresponding to some embodiments of operation 1820 is shown.

[0095] At operation 1822, a second patterning process is performed over the data storage layer and the bottom electrode layer. The second patterning process defines the data storage structure and the bottom electrode of the memory device. Figure 14 Cross-sectional view 1400 corresponding to some embodiments of operation 1822 is shown.

[0096] At operation 1824, an upper ILD layer is formed over the memory device. Figure 15 Cross-sectional view 1500 corresponding to some embodiments of operation 1824 is shown.

[0097] At operation 1826, a third patterning process is performed on the upper ILD layer to define a top electrode via aperture exposing the upper surface of the second top electrode layer. Figure 16 Cross-sectional view 1600 corresponding to some embodiments of operation 1826 is shown.

[0098] At operation 1828, the top electrode via aperture is filled with a conductive material to define a top electrode via. Figure 17 Cross-sectional view 1700 corresponding to some embodiments of operation 1828 is shown.

[0099] Thus, in some embodiments, the present disclosure relates to a memory device (e.g., a RRAM device) having a multi-layer top electrode layer configured to mitigate the formation of oxides between the multi-layer top electrode layer and an overlying top electrode via.

[0100] In some embodiments, the present disclosure relates to a memory device. The memory device includes: a bottom electrode disposed above a lower interconnect, the lower interconnect being within a lower interlayer dielectric (ILD) layer above a substrate; a data storage structure disposed above the bottom electrode; a first top electrode layer disposed above the data storage structure; a second top electrode layer located on the first top electrode layer, wherein the second top electrode layer is more resistant to oxidation than the first top electrode layer. A top electrode via is disposed above the second top electrode layer and is electrically coupled to the second top electrode layer. In some embodiments, the top electrode via extends from above the top surface of the second top electrode layer to below the top surface of the second top electrode layer; the top electrode via is separated from the first top electrode layer by the second top electrode layer. In some embodiments, the memory device includes a top electrode oxide disposed between the top electrode via and the second top electrode layer. In some embodiments, the memory device includes a first oxide disposed along one or more sidewalls of the first top electrode layer, the thickness of the first oxide being greater than the thickness of the top electrode oxide. In some embodiments, the second top electrode layer includes titanium nitride, ruthenium, tungsten, tin, zirconium, aluminum nitride, silver, strontium, thallium, vanadium, zirconium nitride, or hafnium nitride. In some embodiments, the first top electrode layer includes tantalum and the second top electrode layer includes titanium nitride. In some embodiments, the thickness of the second top electrode layer ranges between about 20 angstroms and about 300 angstroms. In some embodiments, the second top electrode layer has a corrosion potential greater than or equal to about -0.4 V. In some embodiments, the boiling point of the second top electrode layer in fluorine gas is greater than about 1500 °C. In some embodiments, the second top electrode layer includes a material that forms an oxide with a Gibbs free energy greater than -600 kJ / mol. In some embodiments, the second top electrode layer has a first non-zero thickness directly below the top electrode via and a second thickness outside the top electrode via, the second thickness being greater than the first non-zero thickness.

[0101] In other embodiments, the present disclosure relates to an integrated chip. The integrated chip includes: a memory device disposed above a substrate, the memory device including a data storage structure disposed between a bottom electrode and a multi-layer top electrode; a top electrode via disposed above the multi-layer top electrode and electrically coupled to the multi-layer top electrode; wherein the multi-layer top electrode includes a first top electrode layer disposed above the data storage structure and a second top electrode layer located on the first top electrode layer, and includes a material different from that of the first top electrode layer; and wherein the second top electrode layer has a greater corrosion potential than the first top electrode layer. In some embodiments, the integrated chip further includes a hard mask layer disposed above the second top electrode layer and having a first thickness, wherein the top electrode via extends through the hard mask layer to a first bottom surface, the first bottom surface being located between sidewalls of the second bottom electrode layer and separated from the first top electrode layer by the second top electrode layer. In some embodiments, the integrated chip further includes: a second memory device disposed above the substrate and including a second data storage structure, the second data storage structure being disposed between a second bottom electrode and a second multi-layer top electrode, wherein the second multi-layer top electrode includes a fourth top electrode layer separated from the second data storage structure by a third top electrode layer, the third top electrode layer having a smaller corrosion potential than the fourth top electrode layer; a second top electrode via disposed above the second multi-layer top electrode and electrically coupled to the second multi-layer top electrode; and a second hard mask layer disposed above the fourth top electrode layer and having a second thickness greater than the first thickness, wherein the second top electrode via extends through the second hard mask layer to a second bottom surface, the second bottom surface being separated from the third top electrode layer by the fourth top electrode layer.

[0102] In other embodiments, the present disclosure relates to a method of forming a memory device. The method includes: forming a data storage layer on a bottom electrode layer located above a substrate; forming a first top electrode layer above the data storage layer and forming a second top electrode layer above the first top electrode layer, wherein the corrosion potential of the first top electrode layer is less than the corrosion potential of the second top electrode layer; performing a first patterning process on the first top electrode layer and the second top electrode layer to define a multi-layer top electrode; and performing a second patterning process on the data storage layer and the bottom electrode layer to define a data storage structure and a bottom electrode. In some embodiments, the method further includes: forming an upper interlayer dielectric layer above the multi-layer top electrode; etching the upper interlayer dielectric layer to form a top electrode via aperture extending to the second top electrode layer; and forming a top electrode via in the top electrode via aperture. In some embodiments, the method further includes etching the upper interlayer dielectric layer using an etchant containing fluorine gas. In some embodiments, the second top electrode layer has a corrosion potential greater than or equal to about -0.4V. In some embodiments, the thickness of the first top electrode layer is greater than the thickness of the second top electrode layer. In some embodiments, the method further includes: exposing the first top electrode layer and the second top electrode layer to a surrounding environment, wherein the surrounding environment forms a first oxide along the side surface of the first top electrode layer and forms a second oxide along the side surface of the second top electrode layer. The thickness of the first oxide is greater than the thickness of the second oxide.

[0103] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and alterations in the present invention without departing from the spirit and scope of the present invention.

Claims

1. A memory device, comprising: A bottom electrode disposed above a lower interconnect, the lower interconnect being within a lower interlayer dielectric layer above a substrate; A data storage structure disposed above the bottom electrode; A first top electrode layer disposed above the data storage structure; A second top electrode layer located on the first top electrode layer, wherein the second top electrode layer is less oxidizable than the first top electrode layer; and A top electrode via located above the second top electrode layer and electrically coupled to the second top electrode layer; A top electrode oxide disposed between the top electrode via and the second top electrode layer and formed along a bottom surface and a portion of a sidewall of the top electrode via; A first oxide disposed along one or more sidewalls of the first top electrode layer; and A second oxide disposed along an outer edge of the second top electrode layer, wherein a thickness of the first oxide is greater than a thickness of the top electrode oxide, and the second oxide is separated from the top electrode oxide.

2. The memory device according to claim 1, Among them, The top electrode via extends from above a top surface of the second top electrode layer to below the top surface of the second top electrode layer; And Wherein the top electrode via is separated from the first top electrode layer by the second top electrode layer.

3. The memory device according to claim 1, further comprising: A hard mask layer disposed above the second top electrode layer.

4. The memory device according to claim 3, wherein: The first oxide and / or the second oxide laterally extends beyond an outermost sidewall of the hard mask layer.

5. The memory device according to claim 1, wherein, The second top electrode layer includes titanium nitride, ruthenium, tungsten, tin, zirconium, aluminum nitride, silver, strontium, thallium, vanadium, zirconium nitride, or hafnium nitride.

6. The memory device according to claim 1, wherein, The first top electrode layer includes tantalum, and the second top electrode layer includes titanium nitride.

7. The memory device according to claim 1, wherein, The thickness of the second top electrode layer is in a range between 20 angstroms and 300 angstroms.

8. The memory device according to claim 1, wherein, The second top electrode layer has a corrosion potential greater than or equal to -0.4V.

9. The memory device according to claim 1, wherein, The second top electrode layer has a boiling point greater than 1500°C in fluorine gas.

10. The memory device according to claim 1, wherein, The second top electrode layer includes a material that forms an oxide with a Gibbs free energy greater than -600 kJ / mol.

11. The memory device according to claim 1, wherein, The second top electrode layer has a first non-zero thickness directly below the top electrode via and a second thickness outside the top electrode via, the second thickness being greater than the first non-zero thickness.

12. An integrated chip, comprising: A memory device disposed above a substrate, the memory device including a data storage structure disposed between a bottom electrode and a multi-layer top electrode; A top electrode via disposed above the multi-layer top electrode and electrically coupled to the multi-layer top electrode; Wherein the multi-layer top electrode includes a first top electrode layer disposed above the data storage structure and a second top electrode layer located on the first top electrode layer, and includes a material different from that of the first top electrode layer; and Wherein, a top electrode oxide is disposed between the top electrode via hole and the second top electrode layer and is formed along a bottom surface of the top electrode via hole and a part of a sidewall of the top electrode via hole. The second top electrode layer has a greater corrosion potential than the first top electrode layer. A first oxide is disposed along one or more sidewalls of the first top electrode layer, and a second oxide is disposed along an outer edge of the second top electrode layer. The thickness of the first oxide is greater than the thickness of the top electrode oxide, and the second oxide is separated from the top electrode oxide.

13. The integrated chip according to claim 12, further comprising: A hard mask layer disposed above the second top electrode layer and having a first thickness. Wherein, the top electrode via hole extends through the hard mask layer to a first bottom surface, and the first bottom surface is located between sidewalls of the second top electrode layer and is separated from the first top electrode layer by the second top electrode layer.

14. The integrated chip according to claim 13, further comprising: A second memory device disposed above the substrate and including a second data storage structure disposed between a second bottom electrode and a second multi-layer top electrode. Wherein, the second multi-layer top electrode includes a fourth top electrode layer separated from the second data storage structure by a third top electrode layer, and the third top electrode layer has a smaller corrosion potential than the fourth top electrode layer; A second top electrode via hole disposed above the second multi-layer top electrode and electrically coupled to the second multi-layer top electrode; and A second hard mask layer disposed above the fourth top electrode layer and having a second thickness greater than the first thickness. Wherein, the second top electrode via hole extends through the second hard mask layer to a second bottom surface, and the second bottom surface is separated from the third top electrode layer by the fourth top electrode layer.

15. A method for forming a memory device, comprising: Forming a data storage layer on a bottom electrode layer located above a substrate; Forming a first top electrode layer above the data storage layer and forming a second top electrode layer above the first top electrode layer, wherein the corrosion potential of the first top electrode layer is less than the corrosion potential of the second top electrode layer; Performing a first patterning process on the first top electrode layer and the second top electrode layer to define a multi-layer top electrode; Exposing the first top electrode layer and the second top electrode layer to a surrounding environment, wherein the surrounding environment forms a first oxide along a side surface of the first top electrode layer and forms a second oxide along a side surface of the second top electrode layer; Performing a second patterning process on the data storage layer and the bottom electrode layer to define a data storage structure and a bottom electrode; Forming an upper interlayer dielectric layer above the multi-layer top electrode; Etching the upper interlayer dielectric layer to form a top electrode via hole orifice extending to the second top electrode layer; and A top electrode via hole is formed within the orifice of the top electrode via hole, wherein a top electrode oxide is formed along the bottom surface of the top electrode via hole and a portion of the sidewall of the top electrode via hole. Wherein, the thickness of the first oxide is greater than the thickness of the top electrode oxide, and the second oxide and the top electrode oxide are spaced apart from each other.

16. The method according to claim 15, wherein, The second top electrode layer includes titanium nitride, ruthenium, tungsten, tin, zirconium, aluminum nitride, silver, strontium, thallium, vanadium, zirconium nitride, or hafnium nitride.

17. The method according to claim 16, further comprising: Etching the upper interlayer dielectric layer using an etchant containing fluorine gas.

18. The method according to claim 15, wherein, The second top electrode layer has a corrosion potential greater than or equal to -0.4V.

19. The method according to claim 15, wherein The thickness of the first top electrode layer is greater than the thickness of the second top electrode layer.

20. The method according to claim 15, wherein: Among them, The thickness of the first oxide is greater than the thickness of the second oxide.

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