Biasing Arrangement for Improved Amplifier Linearity

Abstract

The present disclosure relates to biasing arrangements for improving amplifier linearity. A biasing arrangement for an amplifier is disclosed. An example biasing arrangement for an amplifier includes: a bias circuit configured to generate a bias signal for the amplifier; a linearization circuit configured to improve the linearity of the amplifier by modifying the bias signal generated by the bias circuit to generate a modified bias signal to be provided to the amplifier; and a coupling circuit configured to couple the bias circuit and the linearization circuit. Providing separate biasing and linearization circuits coupled to each other through the bias circuit allows the linearization operation to be separated from the bias loop to overcome some disadvantages of prior art biasing arrangements that utilize a single bias loop.

Description

Technical Field

[0001] The present disclosure relates generally to radio frequency (RF) systems, and more particularly to biasing and linearization techniques for amplifiers in RF systems. Background Art

[0002] Radio systems are systems that send and receive signals in the form of electromagnetic waves in the RF range of approximately 3 kilohertz (kHz) to 300 gigahertz (GHz). Radio systems are commonly used for wireless communications, cellular / wireless mobile technology being a prominent example, but can also be used for cable communications such as cable television. In both types of systems, the linearity of the various components plays a crucial role.

[0003] The linearity of an RF component or system is easy to understand in theory. That is, linearity generally refers to the ability of a component or system to provide an output signal that is proportional to the input signal. In other words, if the component or system were perfectly linear, the ratio of the output signal to the input signal would be a straight line. Achieving this behavior in real-life components and systems is much more complex, and many challenges in linearity must be addressed, often at the expense of some other performance parameter, such as efficiency.

[0004] Power amplifiers, which are made of inherently nonlinear semiconductor materials and must operate at relatively high power levels, are often the first components to be analyzed when considering RF system design in terms of linearity. Power amplifier outputs with nonlinear distortion can lead to reduced modulation accuracy (e.g., reduced error vector magnitude (EVM)) and / or out-of-band emissions. Therefore, wireless communication systems (e.g., long-term evolution (LTE) and fifth-generation (5G) systems) and cable communication systems have strict specifications on power amplifier linearity.

[0005] While linearity is also important for small signal amplifiers such as low noise amplifiers, the challenge of linearity is particularly evident for power amplifiers because such amplifiers are often required to produce relatively high output power levels and are therefore particularly susceptible to certain operating conditions where nonlinear behavior cannot be ignored. On the one hand, when an amplifier is operated on signals at high power levels, the nonlinear characteristics of the semiconductor materials used to form the amplifier tend to deteriorate (an operating condition often referred to as "saturated operation"), thereby increasing the amount of nonlinear distortion in its output signal, which is highly undesirable. On the other hand, an amplifier operating in saturation also typically operates at its highest efficiency, which is highly desirable.

[0006] As previously mentioned, linearity and efficiency are two performance parameters for which an acceptable compromise must usually be found, since an improvement in one of these parameters comes at the expense of the other being less than optimal. For this reason, the term "backoff" is used in the art to describe a measure of how far the input power (i.e., the power of the signal supplied to the amplifier to be amplified) should be reduced in order to achieve a desired output linearity (e.g., backoff may be measured as the ratio of the input power that provides maximum power to the input power that provides the desired linearity). Amplifiers (particularly power amplifiers) that are linear and efficient (i.e., backoff may be minimized or eliminated) are essential for modern communication systems. Therefore, further improvements in amplifier design and operation are always needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To provide a more complete understanding of the present disclosure and its features and advantages, reference is made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, and wherein:

[0008] FIG1 provides a schematic diagram of a circuit diagram of a biasing arrangement having a single loop for biasing and linearization according to the prior art;

[0009] Figure 2 A block diagram illustrating a biasing arrangement having separate biasing and linearization circuits coupled through a coupling circuit according to various embodiments of the present disclosure is provided;

[0010] Figures 3 to 7 Provide various embodiments according to the present disclosure Figure 2 A schematic diagram of a circuit diagram of an example implementation of a biasing arrangement.

[0011] Figure 8 A block diagram is provided according to some embodiments of the present disclosure, which shows an antenna device with an amplifier that can be biased by a biasing arrangement with separate bias and linearization circuits coupled by a coupling circuit.

[0012] Fig. 9 A block diagram is provided illustrating an example data processing system that may be configured to implement or control at least a portion of the operation of an amplifier biased by a biasing arrangement having separate biasing and linearization circuits coupled by a coupling circuit, according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] Overview

[0014] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein.The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the drawings.

[0015] In order to illustrate the biasing arrangements for amplifiers for wireless and cable communication systems proposed herein, it may be useful to first understand the phenomena that may work in such systems. The following basic information may be considered as a basis for appropriately interpreting the present disclosure. Such information is provided for explanation purposes only and, therefore, should not be construed in any way as limiting the broad scope of the present disclosure and its potential applications. Although the following description may be provided for the example of an amplifier as a power amplifier, embodiments of the present disclosure are equally applicable to other types of amplifiers, such as low noise amplifiers, variable gain amplifiers, etc.

[0016] In the context of wireless radio systems, an antenna is a device that acts as an interface between radio waves that propagate wirelessly in space and electric currents that move in a metallic conductor used with a transmitter or receiver. During transmission, a radio transmitter can provide an electrical signal, which is amplified by a power amplifier, and an amplified version of the signal is provided to the terminals of the antenna. The antenna can then radiate energy from the signal output by the power amplifier as radio waves. Similarly, in a wired radio system, the electrical signal is first amplified by a power amplifier before being transmitted over a wired cable connection. Therefore, linear and efficient power amplifiers are essential for both wireless and cable communication systems.

[0017] One method of improving the linearity of a power amplifier includes carefully controlling a bias signal provided thereto. For example, adaptive bias circuits have been developed in an attempt to optimize the linearity of a power amplifier. Such circuits are "adaptive" because the bias signal provided to the power amplifier depends on the signal to be amplified by the power amplifier, which may be advantageous in improving the linearity of the power amplifier. In another example, a bias circuit has been developed that includes one or more linearization transistors in addition to a mirror transistor. However, the inventors of the present disclosure have realized that conventional adaptive / linearization biasing techniques and circuits may still have disadvantages that may make them less than optimal for the latest communication systems such as 5G systems. For example, conventional adaptive / linearization biasing techniques and circuits may be sensitive to process, voltage, and temperature (PVT) variations, may have limited envelope bandwidth, and may not always be applicable to power amplifiers that utilize stacked transistors.

[0018] Various embodiments of the present disclosure provide systems and methods that are intended to improve one or more of the above-mentioned shortcomings in providing a linear and efficient amplifier (such as but not limited to a power amplifier, a low noise amplifier, or a variable gain amplifier) ​​for an RF system (such as but not limited to a phased antenna array for a 5G cellular technology or a cable communication system). In one aspect of the present disclosure, an exemplary bias arrangement for an amplifier includes a bias circuit configured to generate a bias signal for the amplifier; a linearization circuit configured to improve the linearity of the amplifier by modifying the bias signal generated by the bias circuit to generate a modified bias signal to be provided to the amplifier; and a coupling circuit for coupling the bias circuit and the linearization circuit. Providing separate bias and linearization circuits coupled to each other by a coupling circuit allows the linearization operation to be separated from the bias loop to overcome some of the shortcomings of prior art bias arrangements that utilize a single bias loop.

[0019] As will be appreciated by those skilled in the art, as described herein, aspects of the present disclosure, particularly in the specific aspects of the bias arrangement using separate bias and linearization circuits coupled to each other by a coupling circuit to provide a modified bias signal to an amplifier, can be embodied in various ways - for example, as a method, system, computer program product, or computer-readable storage medium. Thus, aspects of the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which aspects can be generally collectively referred to herein as a "circuit," "arrangement," "module," or "system." At least some of the functions described in the present disclosure can be implemented as algorithms executed by one or more hardware processing units (e.g., one or more microprocessors) of one or more computers. In various embodiments, different steps and portions of steps of any method described herein can be performed by different processing units. In addition, aspects of the present disclosure can take the form of a computer program product embodied in one or more computer-readable media, preferably non-transitory, on which computer-readable program code is embodied (e.g., stored). In various embodiments, such a computer program may, for example, be downloaded (updated) to various devices and systems (eg, various components and arrangements of components of a radio frequency system and / or its controller, etc.), or stored when these devices and systems are manufactured.

[0020] The following detailed description gives various descriptions of certain embodiments. However, the innovations described herein may be embodied in a variety of different ways, for example, as defined and covered by the claims or selected examples. In the following description, reference is made to the accompanying drawings in which similar reference numerals may indicate identical or functionally similar elements. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. In addition, it will be understood that some embodiments may include more elements than shown in the figures and / or a subset of the elements shown in the figures. In addition, some embodiments may combine any suitable combination of features from two or more of the accompanying drawings.

[0021] The description may use the phrase "in one embodiment" or "in an embodiment", which may refer to one or more of the same or different embodiments, respectively. Unless otherwise indicated, the use of ordinal adjectives "first", "second" and "third" etc. to describe a common object only represents that different instances of the same object are referenced, and does not mean that the described object must be in a given sequence in time, space, grade or any other manner. In addition, for the purposes of this disclosure, the phrase "A and / or B" or the symbol "A / B" represents (A), (B) or (A and B), and the phrase "A, B, and / or C" represents (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). As used herein, the symbol "A / B / C" refers to (A, B and / or C). When used with reference to a measurement range, the term "between..." includes the ends of the measurement range.

[0022] Various aspects of the illustrative embodiments are described using terms commonly employed by those skilled in the art to convey the essence of their work to other technicians in the field. For example, the term "connected" refers to a direct electrical connection between connected objects without any intermediate devices / components, while the term "coupled" refers to a direct electrical connection between connected objects, or an indirect connection through one or more passive or active intermediate devices / components. In another example, the term "circuit" refers to one or more passive and / or active components that are arranged to cooperate with each other to provide the desired functionality. If used, based on the context of specific values ​​described herein or known in the art, the terms "substantially", "approximately", "roughly", etc. can be used to generally refer to within + / -20% of the target value, for example, within + / -10% of the target value.

[0023] Prior art biasing arrangement with a single loop for biasing and linearization

[0024] FIG. 1 provides a schematic diagram of a bias arrangement 100 having a single loop for biasing and linearization according to the prior art. As shown in FIG. 1 , a bias signal 102 (e.g., a bias current) may be provided to a bias circuit transistor 112, which is coupled in a loop 118 (shown in dashed dashed lines in FIG. 1 ) with a linearization transistor 122. In FIG. 1 and subsequent figures, various transistors are shown within dashed elliptical / circular outlines. The inset 104 shown in FIG. 1 illustrates an example transistor, which indicates the references to the first, second, and third terminals, respectively, in the remainder of the specification, labeled T1, T2, and T3, which apply to all of the present figures. If a given transistor described herein is implemented as a field effect transistor (FET) (as shown for the two transistors of the bias arrangement 100 ), then according to conventional terminology, the first terminal T1 is the gate terminal, the second terminal T2 is the drain terminal, and the third terminal T3 is the source terminal. The terminals T1-3T are not specifically labeled in the bias arrangement 100 or the remaining figures to avoid cluttering the figures.

[0025] As shown in FIG. 1 , a first terminal of the linearizing transistor 122 may be coupled to the bias signal 102, for example, via a node 138. A second terminal of the bias circuit transistor 112 may also be coupled to the node 138 and, therefore, to the linearizing transistor 122. In addition, a capacitor 150 may be coupled between the node 138 and a ground potential (the ground potential labeled “Vgnd” in FIG. 1 and subsequent figures). A second terminal of the linearizing transistor 122 may be coupled to a supply voltage (the supply voltage labeled “Vs” in FIG. 1 and subsequent figures), and a third terminal of the linearizing transistor 122 may be coupled to the output 162. FIG. 1 also shows a resistor 164, which may be coupled between the third terminal of the linearizing transistor 122 and the output 162. FIG. 1 also shows a resistor 174 (coupled between the first terminal of the bias circuit transistor 112 and the output 162) and a resistor 184 (coupled between the third terminal of the linearizing transistor 122 and the ground potential) coupled.

[0026] The inventors of the present disclosure have realized that the biasing arrangement 100 has several disadvantages. One disadvantage is that the bias circuit transistor 112 and the linearizing transistor 122 share the same loop 118, which may limit the linearization that can be achieved by the linearizing transistor 122 and limit the mirroring accuracy that can be achieved by the bias circuit transistor 112. In addition, sharing the loop 118 in the manner shown in FIG. 1 may compromise the stability of the loop 118. This in turn may result in a limited envelope bandwidth because the linearizer loop bandwidth may be limited by its stability. In addition, the inventors of the present disclosure have realized that using a single bias circuit transistor 112 can make the design very sensitive to current mirroring in the case of using stacked transistors in the amplifier.

[0027] Biasing arrangement with independent biasing and linearization circuits coupled via a coupling circuit

[0028] Embodiments of the present disclosure are based on the recognition that separating the bias circuit transistor and the linearization transistor, such that they are not coupled in a single loop, may provide improvements over conventional biasing arrangements such as that shown in FIG. 1 .

[0029] Figure 2 A block diagram is provided showing a bias arrangement 200 having separate bias and linearization circuits 210, 220 coupled via a coupling circuit 230 according to some embodiments of the present disclosure. Figure 2 As shown, the bias circuit 210 can be configured to receive an input signal 202 and generate an output signal 211. The input signal 202 can be a bias signal, such as a bias current, and the bias circuit 210 can be configured to mirror the input signal 202 to the output, that is, the output signal 211 can be substantially a mirrored version of the bias signal 202 or the bias voltage. The coupling circuit 230 is configured to receive the output signal 211 from the bias circuit 210 as an input to the coupling circuit 230 and provide an output signal 231 based on the bias signal 211 output by the bias circuit 210. The linearization circuit 220 can be configured to receive the output signal 231 from the coupling circuit 230 and generate the output signal 221, which can then be provided to the amplifier ( Figure 2 Specifically, the linearization circuit 220 may be configured to improve the linearity of the amplifier by modifying the bias signal 211 generated by the bias circuit 210 to generate an output signal 221, which may be referred to as a "corrected bias signal" 221 provided to the amplifier.

[0030] like Figure 2 As shown, the coupling circuit 230 is configured to couple the bias circuit 210 and the linearization circuit 220. Providing separate bias and linearization circuits 210, 220 coupled to each other through the coupling circuit 230 allows the linearization operation to be separated from the bias loop, which can help overcome some of the shortcomings of the prior art bias arrangement 100, provide improvements in PVT variations, and achieve better linearization. In particular, a feedback path 240 can be provided that couples the output of the coupling circuit 230 to the input of the bias circuit 202, thereby forming a bias loop 218.

[0031] In contrast to the bias loop 118 shown in FIG1 , the bias loop 218 does not include components of the linearizer 220. This can allow the components of the linearizer 220 to be optimized without any bias or stability considerations / limitations as described above. Furthermore, the linearizer 220 can be designed without any closed loops, which can advantageously reduce or eliminate the limiting envelope bandwidth of the bias arrangement 200.

[0032] It should be noted that although Figure 2 Any additional components in the feedback path 240 are not shown, but in various embodiments, various active or passive components may be included therein. For example, in some embodiments, the feedback path 240 from the output of the coupling circuit 230 to the input of the bias circuit 202 may include a voltage level shifter, which may help provide a compliance voltage for one or more transistors of the amplifier to provide the modified bias signal 221 thereto. Thus, in various embodiments, one or more of a voltage level shifter, a transistor, a resistor, a capacitor, an amplifier, an operational amplifier (op-amp), etc. may be coupled between the output of the coupling circuit 230 and the input of the bias circuit 202 in the feedback path 240.

[0033] The precise design of the biasing arrangement 200 as described above can be achieved in many different ways, all of which are within the scope of the present disclosure. Figure 2 As specifically shown in FIG. 2 , each of the bias circuit 210, the linearization circuit 220, and the coupling circuit 230 may include one or more transistors. Therefore, in one example of design variations according to various embodiments of the present disclosure, a selection may be made for each of the bias circuit 210, the linearization circuit 220, and the coupling circuit 230 to employ a FET, a bipolar transistor, or a combination of one or more FETs and one or more bipolar transistors. In another example, in various embodiments, a selection may be made for each of the bias circuit 210, the linearization circuit 220, and the coupling circuit 230 to employ an N-type transistor (e.g., an N-type metal oxide semiconductor (NMOS) transistor for a transistor implemented as a FET, or an NPN transistor for a transistor implemented as a bipolar transistor), a P-type transistor (e.g., a P-type metal oxide semiconductor (PMOS) transistor for a transistor implemented as a FET, or a PNP transistor for a transistor implemented as a bipolar transistor), or a combination of the two. In other examples, in various embodiments, it may be selected which type of transistor architecture to employ. For example, any transistor of bias arrangement 200 implemented as a FET may be a planar transistor or a non-planar transistor, such as a FinFET, a nanowire transistor, or a nanoribbon transistor. Other possible design variations may include implementing output 221 of bias arrangement 200 as an output provided as an input to a differential amplifier or a single-ended amplifier, employing a cascode arrangement of two or more transistors in any of bias circuit 210, linearization circuit 220, coupling circuit 230, and the like. Some example implementations of bias arrangement 200 are Figure 3-7 However, any implementation of the biasing arrangement 200 consistent with the description provided herein is within the scope of the present disclosure.

[0034] exist Figure 3-7 middle, Figure 2 The reference numerals used in the Figure 2 For example, Figure 3-7 20, a linearization circuit 220, and a coupling circuit 230 are illustrated in each of FIG. 1 , although details of their specific implementations are not Figure 3-7 can be different in different figures.

[0035] Figure 3 A schematic diagram of a circuit diagram of a biasing arrangement 300 , which is a first example implementation of the biasing arrangement 200 , is provided according to some embodiments of the present disclosure.

[0036] like Figure 3 As shown, in this example, the bias circuit 210 may include a first transistor 312 and a second transistor 314 in a cascade arrangement, which may be referred to as first and second "bias circuit transistors". As is known in the art, a "cascade arrangement" of a first transistor and a second transistor refers to a third terminal of the second transistor being coupled to a second terminal of the first transistor (continuing the notation of the first, second, and third terminals explained with reference to FIG. 1 ). In this case, this means that the third terminal of the second transistor 314 (i.e., the source terminal for a FET implementation of transistor 314, as shown in FIG. 1 ) is coupled to the second terminal of the first transistor. Figure 3 ) can be coupled to a second terminal of the first transistor 312 (i.e., a drain terminal for a FET implementation of the transistor 312, as shown Figure 3 1 , in that it is used to mirror the bias signal 202 to the output of the bias circuit, which is the first terminal of the first transistor 312 (i.e., the gate terminal for a FET implementation of the transistor 312, as shown in FIG. 1 ). Figure 3 This is shown in Figure 3 300 by showing the output signal 211 at the first terminal of the first transistor 312. In some embodiments of the bias arrangement 300, the second transistor 314 may be omitted, in which case the second terminal of the transistor 312 will be coupled to the bias signal 202 and ultimately to the supply voltage (for Figure 3 N-type transistor shown), for example, coupled to Vdd (for Figure 3 FET implementation shown). However, embodiments in which the second transistor 314 is used may be advantageous because the bias circuit 210 having at least two transistors in a cascade arrangement may provide better mirroring accuracy when mirroring the bias signal 202 to the output of the bias circuit 210. When the second transistor 314 is used, its second terminal may be coupled to the bias signal 202 and further coupled to the supply voltage (for Figure 3N-type transistor shown), for example, coupled to Vdd (for Figure 3 1 ), and the first terminal can be coupled to a reference voltage Vcas1, which can be a fixed DC voltage. In some embodiments, the reference voltage Vcas1 can be substantially the same as the voltage used to bias the cascode in the main power amplifier (an amplifier not shown in arrangement 200). Similar to the bias circuit transistor 112 shown in FIG. 1 , for Figure 3 In the illustrated N-type transistor implementation, the third terminal of the first transistor 312 may be coupled to the ground potential Vgnd.

[0037] As in Figure 2 , the output signal 211 provided at the first terminal of the transistor 312 may be provided from the bias circuit 210 to the coupling circuit 230 . Figure 3 The example shown in FIG. 2 illustrates coupling circuit 230 as a circuit including transistor 332, which may be referred to as a “coupling transistor.” Output 211 of bias circuit 210 may be provided as an input to coupling circuit 230 by being applied to a third terminal of coupling transistor 332. Figure 3 In the N-type transistor implementation shown, the third terminal of the coupling transistor 332 can be further coupled to the ground potential Vgnd, for example, via a resistor 336, while the second terminal of the coupling transistor 332 can be coupled to a power supply voltage (e.g., Vdd). The first terminal of the coupling transistor 332 can be the terminal at which the output 231 of the coupling circuit 230 is provided. The output 231 of the coupling circuit 230 can then be coupled to the input of the bias circuit 210, thereby forming a feedback path 240, as shown in reference Figure 2 described. Figure 3 The example specifically illustrates another component 342, which in some embodiments may be included in the feedback path 240 (in other embodiments, the feedback path 240 may not include any intermediate components and the first terminal of the coupling transistor 332 may be directly connected to the input of the bias circuit 210). Figure 3 Node 338 is shown, which can be viewed as a node where the first terminals of coupling transistor 332 and linearizing transistor 322 are coupled together, and each of these first terminals is coupled to feedback path 240. In an embodiment, node 338 may also be coupled to capacitor 350, similar to capacitor 150 shown in FIG. 1, i.e., coupled to a first capacitor electrode of capacitor 350, where a second capacitor electrode of capacitor 350 may be coupled to ground potential (for Figure 3 In some embodiments, capacitor 350 may be used to stabilize bias loop 218.

[0038] Turning to the linearization circuit 220, Figure 3The linearization circuit 220 shown is configured to provide the output of the differential amplifier as output 221. Therefore, compared to the single linearization transistor 122 shown in FIG. 1, the linearization circuit 220 includes two branches: one branch includes a first linearization transistor 322-1 and is coupled to the first output node 362-1, and the other branch includes a second linearization transistor 322-2 and is coupled to the output node 362-2. The outputs 362-1 and 362-2 together form a differential amplifier (not shown). Figure 3 2 (i.e., the same bias signal), except that output node 362-1 may be coupled to the positive input of the differential amplifier and output node 362-2 may be coupled to the negative input of the differential amplifier, or vice versa.

[0039] For each of the two linearizing transistors 322, the first terminal may be coupled to the coupling transistor 332, for example, via node 338, and may also be coupled to the bias signal 202 via feedback path 240, and to capacitor 350. In addition, for each of the two linearizing transistors 322, for Figure 3 In the N-type transistor embodiment shown, the second terminal can be coupled to the supply voltage Vs and the third terminal can be coupled to the ground potential Vgnd, for example, through the resistor 326-1 for the linearizing transistor 322-1 and through the resistor 326-2 for the linearizing transistor 322-2. Resistors 364-1 and 364-2 sense the RF input of the power amplifier and couple it to the linearizing transistor. Resistors 326-1 and 326-2 set the bias current of the linearizing transistor. In some embodiments, one or more of resistors 326-1, 326-2 and 336 can be replaced by respective current sources (not shown in the drawings). In some embodiments, coupling transistor 332 can be substantially a copy of one of linearizing transistors 322, 322, for example, coupling transistor 332 can have substantially the same size as one of linearizing transistors 322 and be formed of substantially the same material. In other embodiments, coupling transistor 332 can have any multiple of the size of one of linearizing transistors 322.

[0040] Figure 4 A schematic diagram of a circuit diagram of a bias arrangement 400 according to some embodiments of the present disclosure is provided, which is a second example implementation of the bias arrangement 200. The bias arrangement 400 is substantially the same as the bias arrangement 300, except that it further illustrates additional components enclosed within a dash-dot outline 440. Therefore, for the sake of brevity, the schematic diagram has been provided. Figure 4 The description of the components shown in FIG. will not be repeated. Figure 3 , and only the differences between these figures are described. Biasing arrangement 400 shows that in some embodiments, a common-source common-gate transistor can be added to one or both of coupling circuit 230 and linearization circuit 220. For example, in some embodiments, second coupling transistor 432 can be coupled to coupling transistor 332 in a cascade arrangement. In this case, the second terminal of coupling transistor 332 can be coupled to supply voltage Vs by coupling to a third terminal of second coupling transistor 432, coupled to supply voltage Vs through second coupling transistor 432, and then coupling the second terminal of second coupling transistor 432 to the supply voltage. Similarly, in some embodiments, second linearization transistor 422 (at Figure 4 2 (shown as a transistor 422-1 for the first branch of the linearization circuit 220, and a transistor 422-2 for the second branch of the linearization circuit 220) can be coupled to the corresponding linearization transistor 322 in a cascade arrangement. In this case, the second terminal of the linearization transistor 322-1 can be coupled to the power supply voltage Vs via the second linearization transistor 422-1 by being coupled to the third terminal of the second linearization transistor 422-1, and the second terminal of the second linearization transistor 422-1 is then coupled to the power supply voltage. In addition, the second terminal of the linearization transistor 322-2 can be coupled to the power supply voltage Vs via the second linearization transistor 422-2 by being coupled to the third terminal of the second linearization transistor 422-2, and then the second terminal of the second linearization transistor 422-2 is coupled to the power supply voltage. The first terminal of each cascode transistor of portion 440 may be coupled to a voltage source 442, which may provide a suitable voltage to match, for example, the drain-source voltage (Vds) of linearizing transistors 322-1, 322-2 and / or transistors included in the amplifier, to provide the modified bias signal 221 thereto. If the amplifier also includes such cascode transistors, then Figure 4 The addition of the cascode transistors of the illustrated portion 440 may be particularly advantageous. Figure 4 Cascode transistors are shown added to both coupling circuit 230 and linearizer circuit 220 , but in other embodiments of biasing arrangement 400 , such cascode transistors may be added to one of coupling circuit 230 and linearizer circuit 220 but not both.

[0041] Figure 5 A schematic diagram of a circuit diagram of a bias arrangement 500 according to some embodiments of the present disclosure is provided, which is a third example implementation of the bias arrangement 200. The bias arrangement 500 is substantially the same as the bias arrangement 300, and therefore, for the sake of brevity, reference has been made to the bias arrangement 500. Figure 3 Provided Figure 5The description of the elements shown in FIG. 1 is not repeated, and only the differences between these drawings are described. Figure 5 and Figure 3 The difference is that the bias arrangement 500 has a single output branch, rather than Figure 3 2 shows the output of the linearization circuit 220 for the differential amplifier. Figure 5 Does not exist Figure 3 One of the two branches of the linearization circuit 220 is shown (eg, the second branch, where the reference numerals of the various elements have the number 2 after the dash, such as having the linearization transistor 322 - 2 ).

[0042] Figure 6 A schematic diagram of a circuit diagram of a bias arrangement 600 according to some embodiments of the present disclosure is provided, which is a fourth example implementation of the bias arrangement 200. The bias arrangement 600 is substantially the same as the bias arrangement 500, except that it further illustrates additional components enclosed within a dash-dot outline 640. Therefore, for the sake of brevity, reference has been made to Figure 5 Provided Figure 6 The description of the elements shown in FIG. 6 is not repeated, and only the differences between these figures are described. Similar to bias arrangement 400, bias arrangement 600 shows that, in some embodiments, a cascode transistor can be added to one or both of coupling circuit 230 and linearization circuit 220. Such a cascode transistor can be used in conjunction with reference to FIG. Figure 4 Same as those described, therefore, in Figure 6 Use in Figure 4 For example, in some embodiments, the second coupling transistor 432 can be coupled to the coupling transistor 332 in a cascade arrangement, as described above. Similarly, in some embodiments, the second linearizing transistor 422-1 can be coupled to the linearizing transistor 322-1 in a cascade arrangement, also as described above. If the amplifier also includes such a cascode transistor, then Figure 6 The addition of cascode transistors of portion 640 as shown may be particularly advantageous.

[0043] Figure 3-6 Each of the embodiments shows an embodiment in which various transistors of the bias circuit 210, the linearization circuit 220, and the coupling circuit 230 are implemented using NMOS transistors. Figure 3-6In other embodiments of the bias arrangement shown in , one or more NMOS transistors of any one of the bias arrangements 300, 400, 500 and 600 may be replaced by an N-type bipolar transistor, i.e., an NPN transistor. For such embodiments, the description provided above still applies, except that in addition to such bipolar transistors, the above-mentioned "first terminal" is a base terminal (i.e., a terminal that serves as a gate terminal of the above-mentioned FET), the "second terminal" is a collector terminal (i.e., a terminal that serves as a drain terminal of the above-mentioned FET), and the "third terminal" is an emitter terminal (i.e., a terminal that serves as a source terminal of the above-mentioned FET). Therefore, in various embodiments of the bias arrangement 200, the transistors used in the bias circuit 210, the linearization circuit 220 and the coupling circuit 230 may be NMOS transistors, NPN transistors, or a combination of NMOS and NPN transistors.

[0044] In addition, despite Figure 3-6 Each of the above descriptions indicates that the bias arrangement 200 may include various transistors of N-type transistors (e.g., NMOS or NPN transistors), but in further embodiments, any of these transistors may be implemented as P-type transistors (e.g., PMOS or PNP transistors). For such embodiments, except for the P-type transistors, the description provided above still applies, and for the P-type transistors, the power supply voltage Vs described above for the N-type transistors will be replaced with the ground potential Vgnd, and vice versa. An example thereof is shown in FIG. Figure 7 , a circuit diagram of a bias arrangement 700 according to some embodiments of the present disclosure is provided, which is a fifth example implementation of the bias arrangement 200. The bias arrangement 700 is substantially the same as the bias arrangement 500, except that the bias arrangement 700 is used. Figure 7 The PMOS transistor in the Figure 5 All NMOS transistors shown in . Therefore, Figure 7 Transistors 712, 714, 722-1 and 732 are shown similar to Figure 5 The transistors 312, 314, 322-1 and 332 are shown except Figure 7 The transistor is a PMOS transistor. Figure 3 , Figure 4 and Figure 6Similar modifications of can be performed in the same manner and are therefore not shown in this figure. In addition, in various embodiments of the bias arrangement 200, the transistors used in the bias circuit 210, the linearization circuit 220, and the coupling circuit 230 may be P-type transistors other than PMOS transistors, such as PNP transistors. Therefore, in various embodiments of the bias arrangement 200, the transistors used in the bias circuit 210, the linearization circuit 220, and the coupling circuit 230 may be PMOS transistors, PNP transistors, or a combination of PMOS and PNP transistors. Further, in various embodiments of the bias arrangement 200, the transistors used in the bias circuit 210, the linearization circuit 220, and the coupling circuit 230 may be N-type transistors, P-type transistors, or a combination of N-type transistors and P-type transistors.

[0045] Antenna Installation Examples

[0046] As described above, embodiments of the present disclosure relating to bias arrangements for amplifiers may be applied to wireless as well as cable communication systems. For illustrative purposes only, Figure 8 As shown in and described below, the exemplary communication system / device (particularly an example of a wireless communication system / device) may include one or more amplifiers biased by any of the biasing arrangements described herein.

[0047] Figure 8 A schematic diagram of an antenna device 800, such as a phased array system / device, is provided according to some embodiments of the present disclosure. Figure 8 As shown, the antenna device 800 may include an antenna array 810, a beamformer array 820, and an up / down converter (UDC) circuit 840. Any amplifier of the antenna device 800 described herein, for example, any of the amplifiers 828, 832, 842, and 846 may be, for example, referenced Figure 2-7 Any embodiment of the biasing arrangement described may be used to bias the biasing arrangement.

[0048] Typically, the antenna array 810 may include one or more, typically multiple, antenna elements 812 (in order not to clutter the drawing). Figure 8 Only one of them is labeled with a reference number. In various embodiments, antenna element 812 can be a radiating element or a passive element. For example, antenna element 812 can include a dipole, an open waveguide, a slotted waveguide, a microstrip antenna, etc. In some embodiments, antenna element 812 can include any suitable element configured to wirelessly transmit and / or receive RF signals. Although Figure 8A certain number of antenna elements 812 are shown, but it should be understood that various embodiments may be implemented using arrays of any number of two or more antenna elements. In addition, various embodiments of the biasing arrangements disclosed herein may be implemented in different types of antenna arrays, such as time domain beamformers, frequency domain beamformers, dynamic antenna arrays, antenna arrays, passive antenna arrays, etc.

[0049] Similarly, the beamformer array 820 may include one or more, typically a plurality of, beamformers 822 (in order not to clutter the drawing). Figure 8 810 ). The beamformer 822 may be viewed as a transceiver (e.g., a device that can send and / or receive signals, in this case RF signals) that feeds the antenna element 812. In some embodiments, a single beamformer 822 of the beamformer array 820 may be associated with a single antenna element 812 of the antenna array 810 in a one-to-one correspondence (i.e., different beamformers 822 may be associated with different antenna elements 812). In other embodiments, more than one beamformer 822 may be associated with a single antenna element 812, such as two beamformers 822 may be associated with a single antenna element 812, such as if such an antenna element is a dual-polarized antenna element.

[0050] In some embodiments, each beamformer 822 may include a switch 824 to switch the path from the corresponding antenna element 812 to the receiver or transmitter path. Figure 8 As specifically shown in FIG. 8 , in some embodiments, each beamformer 822 may also include another switch to switch the path from the signal processor (also not shown) to the receiver or transmitter path. Figure 8As shown, in some embodiments, the transmitter path (TX path) of each beamformer 822 may include a phase shifter 826 and an amplifier 828, while the receiver path (RX path) may include a phase adjusted 830 and an amplifier 832. In some embodiments, one or more of the amplifiers 828, 832 may be a variable (e.g., programmable) gain amplifier. In some embodiments, the amplifier 828 may be a power amplifier, such as a variable (e.g., programmable) gain power amplifier biased by any bias arrangement described herein. In various such embodiments, the amplifier 828 may include any suitable power amplifier, such as, but not limited to, one of a Doherty power amplifier, a class A power amplifier, a class B power amplifier, a class AB power amplifier, or a class C power amplifier. In some embodiments, the amplifier 832 may be a low noise amplifier, such as a variable (e.g., programmable) gain low noise amplifier biased by any bias arrangement described herein. The phase shifter 826 may be configured to adjust the phase of the RF signal (TX signal) to be transmitted by the antenna element 812, and the amplifier 828 may be configured to adjust the amplitude of the TX signal to be transmitted by the antenna element 812. Similarly, the phase shifter 830 and the amplifier 832 may be configured to adjust the RF signal (RX signal) received by the antenna element 812 before providing the RX signal to further circuits (e.g., the UDC circuit 840) of the signal processor (not shown). Because the signal passing through the beamformer 822 is an RF signal, the beamformer 822 may be considered to be "in the RF path" of the antenna device 800 (i.e., the TX signal that may pass through the beamformer 822 is an RF signal that is up-converted by the UDC circuit 840 from a low frequency signal, such as from an intermediate frequency (IF) signal or from a baseband signal, while the RX signal that may pass through the beamformer 822 is an RF signal that has not yet been down-converted by the UDC circuit 840 to a low frequency signal, such as an IF signal or a baseband signal).

[0051] Despite Figure 8 8 shows a switch (i.e., switch 824) for switching from the transmitter path to the receive path, but in other embodiments of the beamformer 822, other components, such as a duplexer, may be used. Figure 8An embodiment is shown in which the beamformer 822 includes phase shifters 826, 830 (also referred to as "phase adjusters") and variable gain amplifiers 828, 832, but in other embodiments, any of the beamformers 822 may include other components to adjust the amplitude and / or phase of the TX and / or RX signals. In yet another embodiment, one or more of the beamformers 822 may not include the phase shifter 826 and / or the phase shifter 830, because alternatively, a phase shifting module in the LO path may be used to perform the desired phase adjustment. In other embodiments, the phase shifters of the beamformer 822 may be used to combine the phase adjustment performed in the LO path with the phase adjustment performed in the RF path.

[0052] Turning to the details of the UDC circuit, in general, the UDC circuit 840 may include an upconverter and / or a downconverter circuit, i.e., in various embodiments, the UDC circuit 840 may include:

[0053] 1) Upconverter circuit, but no downconverter circuit,

[0054] 2) Downconverter circuit but no upconverter circuit, or

[0055] 3) Up-converter circuit and down-converter circuit.

[0056] like Figure 8 As shown, the downconverter circuit of the UDC circuit 840 may include an amplifier 842 and a mixer 844, while the upconverter circuit of the UDC circuit 840 may include an amplifier 846 and a mixer 848. In addition, the UDC circuit 840 may further include a phase shift module 850 configured to provide a phase shift in the LO path.

[0057] In some embodiments, a single UDC circuit 840 can provide upconverted RF signals to any of the beamformers 822 and / or receive RF signals to be downconverted from these beamformers 822. Thus, a single UDC circuit 840 can be associated with multiple beamformers 822 in the beamformer array 820 (e.g., there may be 48 beamformers 822 in the beamformer array 820, associated with 48 antenna elements 812 of the antenna array 810). Figure 8 The dashed and dotted lines are schematically shown in FIG. 8 , which connect the various elements of the beamformer array 820 and the UDC circuit 840. That is, Figure 8 It is shown that a dashed line can connect the downconverter circuit (i.e., amplifier 842) of the UDC circuit 840 to the RX paths of two different beamformers 822, and a dashed line can connect the upconverter circuit (i.e., amplifier 846) of the UDC circuit 840 to the TX paths of two different beamformers 822.

[0058] In some embodiments, the mixer 844 in the downconverter path of the UDC circuit 840 can have two inputs and one output. The two inputs of the mixer 844 include an input from an amplifier 842, which can be, for example, a low noise amplifier, and an input from a phase shift module 850. The amplifier 842 can be an amplifier biased by any bias arrangement described herein. One output of the mixer 844 is an output that provides a downconverted signal 856, which can be, for example, an IF signal 856. The mixer 844 can be configured to receive an RF RX signal from the RX path of one of the beamformers 822, after it is amplified by the amplifier 842, receive a signal from the phase shift module 850 at its second input at its first input, and mix the two signals to downconvert the RF RX signal to a lower frequency, thereby generating a downconverted RX signal 856, for example, an RX signal at an IF. Therefore, the mixer 844 in the downconverter path of the UDC circuit 840 can be referred to as a "downconversion mixer".

[0059] In some embodiments, the mixer 848 in the up-converter path of the UDC circuit 840 can have two inputs and one output. The two inputs of the mixer 848 include the input from the phase shift module 850 and the lower frequency TX signal 858, for example, the TX signal at the IF. One output of the mixer 848 is the output to the amplifier 846. The amplifier 846 can be an amplifier biased by any bias arrangement described herein. In some embodiments, the amplifier 846 can be a power amplifier. In various such embodiments, the amplifier 846 can include any suitable power amplifier, such as, but not limited to, one of a Doherty power amplifier, a class A power amplifier, a class B power amplifier, a class AB power amplifier, or a class C power amplifier. The mixer 848 may be configured to receive an IF TX signal 858 (i.e., a lower frequency, e.g., IF, signal to be transmitted) at its first input and receive a signal from the phase shift module 850 at its second input, and mix the two signals to up-convert the IF TX signal to a desired RF frequency, generating an up-converted RF TX signal, which is provided to the TX path of one of the beamformers 822 after being amplified by the power amplifier 846. Therefore, the mixer 848 in the up-converter path of the UDC circuit 840 may be referred to as an “up-conversion mixer”.

[0060] As known in communications and electronic engineering, an IF is the frequency to which a carrier can be shifted as an intermediate step in transmission or reception. An IF signal can be created by mixing a carrier signal with an LO signal in a process called heterodyning, resulting in a difference or beat frequency signal. Converting to an IF can be useful for a number of reasons. One reason is that when several stages of filters are used, they can all be set to a fixed frequency, making them easier to build and adjust. Another reason is that low frequency transistors generally have higher gain, so fewer stages may be needed. Yet another reason is to improve frequency selectivity, as it may be easier to make a sharply selective filter at a lower fixed frequency.

[0061] It should also be noted that although some of the descriptions provided herein refer to signals 856 and 858 as IF signals, these descriptions are equally applicable to embodiments in which signals 856 and 858 are baseband signals. In such embodiments, the frequency mixing of mixers 844 and 848 can be zero-IF mixing (also known as "zero-IF conversion"), where the center frequency of the LO signal used to perform the mixing can be at the RF RX / TX frequency.

[0062] In some embodiments, the phase shift module 850 in the LO path can be configured to provide a desired phase shift to the LO signal 860 before providing the LO signal to the mixers 844, 848. Thus, in some embodiments, instead of receiving the LO signal 860 (which may be generated by the LO) at one of their inputs, each mixer 844, 848 can receive a phase shifted version of the LO signal 860. Moving the phase shift operation to the LO path (e.g., between the LO signal generator and the mixers 844, 848) outside the signal path (e.g., between the digital circuits that process the signal 856, 858 and the antenna element 812, and in the wireless domain past the antenna element 812) can advantageously reduce the negative impact of the phase shift on signal quality.

[0063] In other embodiments, the Figure 8 Phase shift module 850 is shown. In such an embodiment, instead of receiving a phase shifted version of the LO signal 860 that would be generated by the phase shift module 850, each mixer 844, 848 may receive the LO signal 860 itself.

[0064] Although not in Figure 8 , but in other embodiments, the UDC circuit 840 may also include a balancer in each of the TX and RX paths, the balancer being configured to mitigate in-phase and quadrature (IQ) signal imbalances caused by mismatches. Figure 8Although not specifically shown in the figure, in other embodiments, the antenna device 800 may include other examples of the combination of the antenna array 810, the beamformer array 820 and the UDC circuit 840 as described herein.

[0065] The antenna device 800 can direct the electromagnetic radiation pattern of the antenna array 810 in a particular direction, thereby enabling the antenna array 810 to generate a main beam in that direction and side lobes in other directions. The main beam of the radiation pattern can be generated based on a constructive inference of the transmitted RF signal based on the phase of the transmitted signal. The sidelobe level can be determined by the amplitude of the RF signal transmitted by the antenna element. The antenna device 800 can generate a desired antenna pattern for the antenna element 812, for example, by providing a phase shifter setting using a beamformer 822 and / or a phase shifter of a phase shift module 850 (if the phase shift module 850 is included).

[0066] Example Data Processing System

[0067] Fig. 9 A block diagram is provided showing an example data processing system 900 that may be configured to implement or control at least a portion of an amplifier biased by a biasing arrangement having separate biasing and linearization circuits coupled by a coupling circuit as described herein, for example, with reference to Figure 2-8 The offset arrangement described.

[0068] like Fig. 9 As shown, the data processing system 900 may include at least one processor 902, such as a hardware processor 902 coupled to a memory element 904 via a system bus 906. In this way, the data processing system may store program codes in the memory element 904. In addition, the processor 902 may execute program codes accessed from the storage element 904 via the system bus 906. On the one hand, the data processing system may be implemented as a computer suitable for storing and / or executing program codes. However, it should be understood that the data processing system 900 may be implemented in the form of any system including a processor and a memory that can perform or enable other components to perform the functions described in the present disclosure.

[0069] In some embodiments, the processor 902 may execute software or algorithms to perform or cause other components to perform the activities discussed in this specification, particularly activities related to the implementation and / or operation of a bias arrangement with independent bias and linearization circuits coupled by a coupling circuit as described herein. The processor 902 may include any combination of hardware, software, or firmware that provides programmable logic, including but not limited to a microprocessor, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic array (PLA), an application specific integrated circuit (IC) (ASIC), or a virtual machine processor. The processor 902 may be communicatively coupled to the memory element 904, for example, in a direct memory access (DMA) configuration, so that the processor 902 can read from or write to the memory element 904.

[0070] In general, storage element 904 may include any suitable volatile or non-volatile storage technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash memory, read-only memory (ROM), optical media, virtual memory areas, magnetic or tape storage, or any other suitable technology. Unless otherwise specified, any storage element discussed herein should be interpreted as being encompassed within the broad term "memory". Information measured, processed, tracked, or sent to or from any component of data processing system 900 may be provided in any database, register, control list, cache, or storage structure, all of which may be referenced at any appropriate time. Any such storage option may be included within the broad term "memory" used herein. Similarly, any potential processing elements, modules, and machines described herein should be interpreted as being encompassed within the broad term "processor". Each element shown in the current figures, for example, Figure 2-8 Any circuits / components shown in the drawings may also include appropriate interfaces for receiving, transmitting and / or otherwise communicating data or information in a network environment so that they can communicate with, for example, the data processing system 900 of another of these elements.

[0071] In certain exemplary embodiments, a biasing mechanism for implementing a biasing arrangement of a bias circuit and a linearization circuit having bias circuits respectively coupled by coupling circuits to provide a modified bias signal to an amplifier may be implemented by logic encoded in one or more tangible media, including, for example, non-transitory media such as embedded logic provided in an ASIC, DSP instructions, software (which may include object code and source code) to be executed by a processor or other similar machine, etc. In some of these examples, such as Fig. 9Memory elements such as the memory element 904 shown can store data or information used for the operations described herein. This includes storage elements that can store software, logic, code, or processor instructions that are executed to perform the activities described herein. The processor can execute any type of instructions associated with the data or information to implement the operations detailed herein. In one example, such as Fig. 9 A processor, such as processor 902, shown, can transform an element or article (e.g., data) from one state or thing to another state or thing. In another example, the activities outlined herein can be implemented with fixed logic or programmable logic (e.g., software / computer instructions executed by a processor), and the elements identified herein can be some type of programmable processor, programmable digital logic (e.g., FPGA, DSP, Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM)), or ASIC, which includes digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0072] The memory element 904 may include one or more physical memory devices, such as a local memory 908 and one or more mass storage devices 910. Local memory may refer to a RAM or other non-persistent storage device commonly used during the actual execution of the program code. The mass storage device may be implemented as a hard drive or other persistent data storage device. The processing system 900 may also include one or more cache memories (not shown) that provide temporary storage of at least some program codes to reduce the number of times that program codes must be retrieved from the mass storage device 910 during execution.

[0073] like Fig. 9 As shown, memory element 904 may store application programs 918. In various embodiments, application programs 918 may be stored in local memory 908, one or more mass storage devices 910, or separate from local memory and mass storage devices. It should be understood that data processing system 900 may further execute an operating system (OS) that may facilitate the execution of application programs 918. Fig. 9 918 implemented in the form of executable program code may be executed by the data processing system 900, for example, by the processor 902. In response to executing the application, the data processing system 900 may be configured to perform one or more operations described herein.

[0074] Input / output (I / O) devices depicted as input devices 912 and output devices 914 may optionally be coupled to the data processing system. Examples of input devices may include, but are not limited to, keyboards, pointing devices such as mice, and the like. Examples of output devices may include, but are not limited to, monitors or displays, speakers, and the like. In some embodiments, output device 914 may be any type of screen display, such as a plasma display, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electroluminescent (EL) display, or any other indicator, such as a dial, a barometer, or an LED. In some embodiments, the system may include a driver (not shown) for output device 914. Input and / or output devices 912, 914 may be coupled to the data processing system directly or through an intermediate I / O controller.

[0075] In one embodiment, the input and output devices may be implemented as a combined input / output device (in Fig. 9 912 and output device 914). An example of such a combined device is a touch-sensitive display, sometimes referred to as a "touch screen display" or simply a "touch screen." In such an embodiment, input to the device can be provided by movement of a physical object, such as a stylus or a user's finger, on or near the touch screen display.

[0076] Network adapter 916 may also be optionally coupled to the data processing system to enable it to couple to other systems, computer systems, remote network devices, and / or remote storage devices through an intervening private or public network. The network adapter may include: a data receiver for receiving data transmitted to the data processing system 900 by the system, device, and / or network; and a data transmitter for transmitting data from the data processing system 900 to the system, device, and / or network. Modems, cable modems, and Ethernet cards are examples of different types of network adapters that can be used with the data processing system 900.

[0077] Select Examples

[0078] Example 1 provides a bias arrangement for an amplifier, wherein the amplifier may be a power amplifier (e.g., a Doherty amplifier, a class A amplifier, a class B amplifier, a class AB amplifier, or a class C amplifier), a linear amplifier, a low noise amplifier, or a variable gain amplifier. The bias arrangement includes: a bias circuit including a bias circuit transistor, the bias circuit being configured to generate a bias signal for the amplifier; a linearization circuit including a linearization transistor, the linearization circuit being configured to improve the linearity of the amplifier by modifying the bias signal to generate a modified bias signal to be provided to the amplifier; and a coupling circuit implemented between the bias circuit and the linearization circuit, the coupling circuit including a coupling transistor.

[0079] Example 2 provides a biasing arrangement according to Example 1, wherein the output of the coupling transistor is coupled to the input of the bias circuit transistor. In various embodiments, the output of the coupling transistor can be coupled to the input of the bias circuit transistor through a direct electrical connection or through one or more passive or active electronic components therebetween. For example, in various embodiments, the output of the coupling transistor can be coupled to the input of the bias circuit transistor through, but not limited to, a short circuit, a resistor, an amplifier, an operational amplifier (op-amp), an inductor, a shunt capacitor, or any component configured to set / modify a desired voltage.

[0080] Example 3 provides a biasing arrangement according to Example 2, wherein the output of the coupling transistor is: if the coupling transistor is a field effect transistor, then the gate terminal of the coupling transistor, or if the coupling transistor is a bipolar transistor, then the base terminal of the coupling transistor.

[0081] Example 4 provides a biasing arrangement according to Example 2 or 3, wherein the input of the bias circuit transistor is: if the bias circuit transistor is a field effect transistor, then the drain terminal of the bias circuit transistor, or if the bias circuit transistor is a bipolar transistor, then the collector terminal of the bias circuit transistor.

[0082] Example 5 provides a biasing arrangement according to any of Examples 2-4, wherein the bias circuit transistor is a first bias circuit transistor, the biasing arrangement further includes a second bias circuit transistor, the second bias circuit transistor is arranged in a cascade arrangement with the first bias circuit transistor (wherein "cascade arrangement" means that the emitter / source terminal of the second transistor is coupled to the drain / collector terminal of the first transistor), and the output of the coupling transistor is coupled to the input of the first bias circuit transistor by coupling the output of the coupling transistor to the input of the second bias circuit transistor and coupling the output of the second bias circuit transistor to the input of the first bias circuit transistor.

[0083] Example 6 provides a biasing arrangement according to Example 5, wherein the input of the second bias circuit transistor is: if the second bias circuit transistor is a field effect transistor, then the drain terminal of the second bias circuit transistor, or if the second bias circuit transistor is a bipolar transistor, then the collector terminal of the second bias circuit transistor.

[0084] Example 7 provides a biasing arrangement according to Example 5 or 6, wherein the output of the second bias circuit transistor is: if the second bias circuit transistor is a field effect transistor, then the source terminal of the second bias circuit transistor, or if the second bias circuit transistor is a bipolar transistor, then the emitter terminal of the second bias circuit transistor.

[0085] Example 8 provides a biasing arrangement according to any one of Examples 2-7, wherein the output of the coupling transistor is also coupled to the input of the linearizing transistor (if the linearizing transistor is a field effect transistor, the input may be the gate terminal of the linearizing transistor, or if the linearizing transistor is a bipolar transistor, the input may be the base terminal of the linearizing transistor).

[0086] Example 9 provides a biasing arrangement according to any of Examples 2-8, wherein the biasing arrangement further comprises a capacitor, the capacitor comprising a first capacitor electrode and a second capacitor electrode, the output of the coupling transistor is also coupled to the first capacitor electrode, and the second capacitor electrode is coupled to ground potential. Because the output of the coupling transistor is coupled to the input of the linearizing transistor, the first capacitor electrode is also coupled to the input of the linearizing transistor.

[0087] Example 10 provides a biasing arrangement according to any of the preceding examples, wherein each of the bias circuit transistor, the linearization transistor, and the coupling transistor comprises a first terminal, a second terminal, and a third terminal. Additionally, the first terminal of the bias circuit transistor is coupled to the third terminal of the coupling transistor, and the first terminal of the coupling transistor is coupled to the first terminal of the linearization transistor.

[0088] Example 11 provides a biasing arrangement according to Example 10, wherein the first terminal of the coupling transistor is further coupled to a second terminal of the bias circuit transistor.

[0089] In various embodiments, therefore, the first terminal of the coupling transistor can be coupled to the second terminal of the bias circuit transistor by a direct electrical connection or one or more passive or active electronic components therebetween. For example, in various embodiments, the first terminal of the coupling transistor can be coupled to the second terminal of the bias circuit transistor by, but not limited to, a short circuit, a resistor, an amplifier, an operational amplifier (op-amp), an inductor, a shunt capacitor, or any component configured to set / modify a desired voltage.

[0090] Example 12 provides a biasing arrangement according to Example 10 or 11, wherein the second terminal of the coupling transistor is coupled to: a power supply voltage if the coupling transistor is an N-type transistor (e.g., an NMOS or NPN transistor); or a ground potential if the coupling transistor is a P-type transistor (e.g., a PMOS or PNP transistor).

[0091] Example 13 provides a biasing arrangement according to Example 12, wherein the coupling transistor is a first coupling transistor, the biasing arrangement further comprising a second coupling transistor, the second coupling transistor being arranged in a cascade arrangement with the first coupling transistor (wherein "cascade arrangement" means that the emitter / source terminal of the second transistor is coupled to the drain / collector terminal of the first transistor). If the first coupling transistor is an N-type transistor, the second terminal of the first coupling transistor is coupled to the power supply voltage by coupling the second terminal of the first coupling transistor to the third terminal of the second coupling transistor and coupling the second terminal of the second coupling transistor to the power supply voltage. If the first coupling transistor is a P-type transistor, the second terminal of the first coupling transistor is coupled to the ground potential by coupling the second terminal of the first coupling transistor to the third terminal of the second coupling transistor and coupling the second terminal of the second coupling transistor to the ground potential.

[0092] In further such embodiments, the first terminal of the second transistor may be coupled to a voltage source that may be configured to provide an optimal voltage to match the linearization and / or Vds of the transistor of the amplifier.

[0093] Example 14 provides a biasing arrangement according to any of Examples 10-13, wherein the second terminal of the linearization transistor is coupled to: a supply voltage if the linearization transistor is an N-type transistor (e.g., an NMOS or NPN transistor); or a ground potential if the linearization transistor is a P-type transistor (e.g., a PMOS or PNP transistor).

[0094] Example 15 provides a biasing arrangement according to Example 14, wherein the linearizing transistor is a first linearizing transistor, the biasing arrangement further comprising a second linearizing transistor, the second linearizing transistor being arranged in a cascade arrangement with the first linearizing transistor (wherein "cascade arrangement" means that the emitter / source terminal of the second transistor is coupled to the drain / collector terminal of the first transistor). If the first linearizing transistor is an N-type transistor, the second terminal of the first linearizing transistor is coupled to the supply voltage by coupling the second terminal of the first linearizing transistor to the third terminal of the second linearizing transistor and coupling the second terminal of the second linearizing transistor to the supply voltage. If the first linearizing transistor is a P-type transistor, the second terminal of the first linearizing transistor is coupled to the ground potential by coupling the second terminal of the first linearizing transistor to the third terminal of the second linearizing transistor and coupling the second terminal of the second linearizing transistor to the ground potential.

[0095] In further such embodiments, the first terminal of the second linearizing transistor may be coupled to a voltage source that may be configured to provide an optimal voltage to match the drain-source voltage (Vds) of the linearizing transistor and / or of the amplifier.

[0096] Example 16 provides a bias arrangement for an amplifier, the bias arrangement comprising: a first transistor configured to provide a bias signal for the amplifier at an output of the first transistor; a second transistor; and a third transistor, wherein the output of the first transistor is coupled to the input of the second transistor, the output of the second transistor is coupled to the input of the first transistor, the output of the second transistor is also coupled to the input of the third transistor, and the third transistor is configured to provide a modified bias signal to be provided to the amplifier at the output of the third transistor, wherein the modified bias signal is based on the bias signal provided at the output of the first transistor.

[0097] Example 17 provides a biasing arrangement according to Example 16, wherein the first transistor is an output transistor among a plurality of transistors in a first cascade arrangement, and / or the second transistor is an output transistor among a plurality of transistors in a second cascade arrangement, and / or the third transistor is an output transistor among a plurality of transistors in a third cascade arrangement.

[0098] Example 18 provides a biasing arrangement according to Example 16 or 17, wherein the biasing arrangement also includes a capacitor, the capacitor including a first capacitor electrode and a second capacitor electrode, the first capacitor electrode is coupled to each of the output of the second transistor and the input of the third transistor, and the second capacitor electrode is coupled to a ground potential.

[0099] Example 19 provides a bias arrangement for an amplifier, the bias arrangement comprising: a first transistor configured to provide a bias signal for the amplifier at an output of the first transistor; a second transistor; a third transistor; and a fourth transistor, wherein the output of the first transistor is coupled to the input of the second transistor, the output of the second transistor is coupled to the input of the first transistor, the output of the second transistor is also coupled to each of the inputs of the third transistor and the fourth transistor, the third transistor is configured to provide a first modified bias signal at the output of the third transistor to be provided to the first input of the amplifier, wherein the first modified bias signal is based on the bias signal provided at the output of the first transistor, and the fourth transistor is configured to provide a second modified bias signal at the output of the fourth transistor to be provided to the second input of the amplifier, wherein the second modified bias signal is based on the bias signal provided at the output of the first transistor.

[0100] Example 20 provides a biasing arrangement according to Example 19, wherein the amplifier is a differential amplifier, and the first input and the second input are respectively a positive input and a negative input of the differential amplifier.

[0101] Example 21 provides an RF system comprising: an amplifier configured to receive an input signal and generate an output signal based on the input signal; a bias arrangement configured to provide a bias signal to the amplifier, wherein the bias arrangement is a bias arrangement according to any one of the preceding examples.

[0102] Example 22 provides the RF system according to Example 21, further comprising an antenna element configured to wirelessly transmit the RF signal based on the output signal generated by the amplifier.

[0103] Example 23 provides an RF system according to Example 21 or 22, further comprising a beamforming element configured to receive a first signal and generate a second signal phase-shifted relative to the first signal, wherein the input signal of the amplifier is based on the second signal generated by the beamforming element.

[0104] Example 24 provides an RF system according to any of Examples 21-23, wherein the amplifier is one of a power amplifier (e.g., a Doherty amplifier, a class A amplifier, a class B amplifier, a class AB amplifier, or a class C amplifier), a linear amplifier, a low noise amplifier, or a variable gain amplifier.

[0105] Example 25 provides an RF system according to any of Examples 21-24, wherein the RF system is a mobile device (e.g., an IE of a wireless cellular network).

[0106] Example 26 provides an RF system according to any of Examples 21-24, wherein the RF system is a base station of a wireless cellular network or a transmitter of a cable communication network.

[0107] Variants and implementations

[0108] Although the above references Figure 2-9 The exemplary embodiments shown describe embodiments of the present disclosure, but those skilled in the art will appreciate that the various teachings described above may be applied to a variety of other embodiments. For example, the description provided herein is applicable not only to 5G systems, which provide an example of a wireless communication system (particularly an example of a high frequency / short wavelength spectrum, for example, a frequency in the range of about 20 to 60 GHz, corresponding to a wavelength between about 5 and 15 mm), but also to other wireless communication systems, such as but not limited to Wi-Fi technology (e.g., a 2.4 GHz band, corresponding to a wavelength of about 12 cm, or a 5.8 GHz spectrum, corresponding to a wavelength of about 5 cm) or Bluetooth technology (e.g., a frequency band of about 2.4 to 2.485 GHz, corresponding to a wavelength of about 12 cm). In another example, the description provided herein is applicable not only to wireless communication systems, but also to any other system in which an amplifier may be used, such as radar systems, automotive radars, and cable communication systems (e.g., cable television systems, etc.).

[0109] In some cases, the features discussed herein may be applicable to automotive systems, medical systems, scientific instrumentation, wireless and wired communications, radio, radar, and digital processing-based systems.

[0110] In the discussion of the above embodiments, components of the system, such as phase shifters, mixers, transistors, resistors, capacitors, amplifiers, and / or other components, can be easily replaced, substituted, or otherwise modified to suit specific circuit needs. In addition, it should be noted that the use of complementary electronic devices, hardware, software, etc. provides an equally viable option for implementing the teachings of the present disclosure, which relates to a biasing arrangement having separate biasing and linearization circuits that are coupled by a coupling circuit to provide a modified bias signal to the amplifier described herein.

[0111] As proposed herein, portions of various systems for implementing a bias arrangement having separate bias and linearization circuits coupled by a coupling circuit may include electronic circuits to perform the functions described herein. In some cases, one or more portions of the system may be provided by a processor specifically configured to perform the functions described herein. For example, the processor may include one or more dedicated components, or may include programmable logic gates configured to perform the functions described herein. The circuit may operate in an analog domain, a digital domain, or a mixed signal domain. In some cases, the processor may be configured to perform the functions described herein by executing one or more instructions stored on a non-transitory computer-readable storage medium.

[0112] In an example embodiment, any number of circuits of the present invention can be implemented on a board of an associated electronic device. The board can be a general circuit board that can accommodate various components of the internal electronic system of the electronic device, and connectors for other peripheral devices can also be provided. More specifically, the board can provide an electrical connection through which other components of the system can communicate electrically. Any suitable processor (including DSP, microprocessor, supporting chipset, etc.), computer-readable non-transient storage element, etc. can be appropriately coupled to the board based on specific configuration requirements, processing requirements, computer design, etc. Other components, such as external memory, additional sensors, controllers for audio / video display, and peripherals, can be connected to the board as plug-in cards via cables, or integrated onto the board. In various embodiments, the functions described herein can be implemented in simulated form as software or firmware running in one or more configurable (e.g., programmable) elements arranged in a structure that supports these functions. Software or firmware providing simulation can be provided on a non-transient computer-readable storage medium that includes instructions to allow the processor to perform those functions.

[0113] In another example embodiment, the circuits of the present figures may be implemented as stand-alone modules (e.g., devices with associated components and circuits that are configured to perform specific applications or functions) or as plug-in modules in dedicated hardware for an electronic device. Note that certain embodiments of the present disclosure may be readily included in part or in whole in a system-on-chip (SOC) package. SOC stands for an IC that integrates the components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and typically RF functions: all of which can be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM), in which multiple separate ICs are located within a single electronic package and are configured to interact closely with each other through the electronic package.

[0114] It is also important to note that all specifications, dimensions, and relationships outlined herein (e.g. Figure 2-9The components shown in the system (the number of components shown in the system) are provided for the purpose of example and teaching only. Without departing from the spirit of the present disclosure or the scope of the appended claims, considerable changes may be made to this information. It should be understood that the system can be combined in any suitable manner. Along similar design alternatives, any of the circuits, components, modules and elements shown in the present invention can be combined in various possible configurations, all of which are obviously within the broad scope of this specification. In the foregoing description, example embodiments have been described with reference to specific processors and / or component arrangements. Various modifications and changes may be made to these embodiments without departing from the scope of the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

[0115] It is also important to note that the functions associated with implementing the bias arrangement using separate bias and linearization circuits as proposed herein are merely illustrative of some of the possible functions that may be performed by or within the RF system. Some of these operations may be deleted or removed where appropriate, or may be substantially modified or altered without departing from the scope of the present disclosure. The embodiments described herein provide great flexibility in that any suitable arrangements, timings, configurations, and timing mechanisms may be provided without departing from the teachings of the present disclosure.

Claims

1. A bias arrangement circuit for an amplifier, the bias arrangement circuit comprising: a bias circuit including a first bias circuit transistor, the bias circuit being configured to generate a bias signal for the amplifier; a linearization circuit including a first linearization transistor, the linearization circuit for generating a modified bias signal for the amplifier based on the bias signal; and a coupling circuit implemented between the bias circuit and the linearization circuit, the coupling circuit comprising a first coupling transistor, in: Each of the first bias circuit transistor, the first linearizing transistor, and the first coupling transistor includes a first terminal, a second terminal, and a third terminal, a first terminal of the first bias circuit transistor coupled to a third terminal of the first coupling transistor, a first terminal of the first coupling transistor is coupled to a first terminal of the first linearizing transistor, The bias arrangement circuit further includes a second coupling transistor, the second coupling transistor being arranged in a communal source and communal gate form with the first coupling transistor, and The bias arrangement circuit further comprises a second linearization transistor, wherein the second linearization transistor is arranged in a communal source and communal gate form with the first linearization transistor, A first terminal of the second coupling transistor is coupled to a first terminal of the second linearization transistor. 2 . The bias arrangement circuit of claim 1 , wherein an output of the first coupling transistor is coupled to an input of the bias circuit.

3. The bias arrangement circuit according to claim 2, wherein: If the first coupling transistor is a field effect transistor, the output of the first coupling transistor is the gate terminal of the first coupling transistor, or If the first coupling transistor is a bipolar transistor, the output of the first coupling transistor is the base terminal of the first coupling transistor.

4. The bias arrangement circuit according to claim 2, wherein: If the first bias circuit transistor is a field effect transistor, the input to the first bias circuit transistor is the drain terminal of the first bias circuit transistor, or If the first bias circuit transistor is a bipolar transistor, the input to the first bias circuit transistor is the collector terminal of the first bias circuit transistor.

5. The bias arrangement circuit according to claim 2, wherein: The bias arrangement circuit further includes a second bias circuit transistor, the second bias circuit transistor being arranged in a cascode form with the first bias circuit transistor, and The output of the first coupling transistor is coupled to the input of the first bias circuit transistor by coupling the output of the first coupling transistor to the input of the second bias circuit transistor and coupling the output of the second bias circuit transistor to the input of the first bias circuit transistor.

6. The bias arrangement circuit according to claim 5, wherein: If the second bias circuit transistor is a field effect transistor, the input to the second bias circuit transistor is the drain terminal of the second bias circuit transistor, or If the second bias circuit transistor is a bipolar transistor, the input to the second bias circuit transistor is the collector terminal of the second bias circuit transistor.

7. The bias arrangement circuit according to claim 5, wherein: If the second bias circuit transistor is a field effect transistor, the output of the second bias circuit transistor is the source terminal of the second bias circuit transistor, or If the second bias circuit transistor is a bipolar transistor, the output of the second bias circuit transistor is the emitter terminal of the second bias circuit transistor.

8. The bias arrangement circuit of claim 2, wherein the output of the first coupling transistor is also coupled to the input of the first linearization transistor.

9. The bias arrangement circuit of claim 2, wherein the bias arrangement circuit further comprises a capacitor, the capacitor comprising a first capacitor electrode and a second capacitor electrode, the output of the first coupling transistor is also coupled to the first capacitor electrode, and the second capacitor electrode is coupled to ground potential.

10. The bias arrangement circuit of claim 1, wherein the first terminal of the first coupling transistor is also coupled to the second terminal of the first bias circuit transistor.

11. The bias arrangement circuit according to claim 1, wherein: If the first coupling transistor is an N-type transistor, the second terminal of the first coupling transistor is coupled to a power supply voltage; or If the first coupling transistor is a P-type transistor, the second terminal of the first coupling transistor is coupled to the ground potential.

12. The bias arrangement circuit according to claim 11, wherein: If the first coupling transistor is an N-type transistor, coupling the second terminal of the first coupling transistor to the supply voltage by coupling the second terminal of the first coupling transistor to the third terminal of the second coupling transistor and coupling the second terminal of the second coupling transistor to the supply voltage, or If the first coupling transistor is a P-type transistor, the second terminal of the first coupling transistor is coupled to the ground potential by coupling the second terminal of the first coupling transistor to the third terminal of the second coupling transistor and coupling the second terminal of the second coupling transistor to the ground potential.

13. The bias arrangement circuit according to claim 1, wherein: If the first linearizing transistor is an N-type transistor, the second terminal of the first linearizing transistor is coupled to a supply voltage; or If the first linearizing transistor is a P-type transistor, the second terminal of the first linearizing transistor is coupled to ground potential.

14. The bias arrangement circuit according to claim 13, wherein: If the first linearizing transistor is an N-type transistor, coupling the second terminal of the first linearizing transistor to the supply voltage by coupling the second terminal of the first linearizing transistor to the third terminal of the second linearizing transistor and coupling the second terminal of the second linearizing transistor to the supply voltage, or If the first linearizing transistor is a P-type transistor, the second terminal of the first linearizing transistor is coupled to the ground potential by coupling the second terminal of the first linearizing transistor to the third terminal of the second linearizing transistor and coupling the second terminal of the second linearizing transistor to the ground potential.

15. The bias arrangement circuit of claim 5, wherein the second bias circuit transistor is coupled to receive a reference voltage that is substantially the same as a voltage used to bias a cascode in the amplifier.

16. The bias arrangement circuit according to claim 12, wherein: If the first linearizing transistor is an N-type transistor, coupling the second terminal of the first linearizing transistor to the supply voltage by coupling the second terminal of the first linearizing transistor to the third terminal of the second linearizing transistor and coupling the second terminal of the second linearizing transistor to the supply voltage, or If the first linearizing transistor is a P-type transistor, the second terminal of the first linearizing transistor is coupled to the ground potential by coupling the second terminal of the first linearizing transistor to the third terminal of the second linearizing transistor and coupling the second terminal of the second linearizing transistor to the ground potential.

17. The bias arrangement circuit according to claim 15, wherein the bias arrangement further comprises a third linearization transistor, in: an input of the third linearizing transistor coupled to an input of the first linearizing transistor, The first linearizing transistor is configured to provide a first modified bias signal at an output of the first linearizing transistor to provide the first modified bias signal to a first input of the amplifier, wherein the first modified bias signal is based on the bias signal, and The third linearization transistor is configured to provide a second modified bias signal at an output of the third linearization transistor to provide the second modified bias signal to a second input of the amplifier, wherein the second modified bias signal is based on the bias signal.

18. A system comprising: A bias arrangement circuit for an amplifier according to any one of claims 1 to 17; as well as The amplifier.

19. The system of claim 18, wherein the amplifier is a differential amplifier, and the first input of the amplifier and the second input of the amplifier are respectively a positive input and a negative input of the differential amplifier.

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