Display device

Abstract

A display device includes a first substrate including a first side surface, a second side surface, and a third side surface each of which is coplanar with each other, a second substrate facing the first substrate, and a sealing layer; a first recess defined by being recessed from each of the first side surface, the second side surface, and the third side surface; a first conductive pattern located in the first recess; and a first driver facing each of the first side surface, the second side surface, and the third side surface. At the first recess: the first conductive pattern is exposed to the outside of the first substrate, the second substrate, and the sealing layer, and the first driver is electrically connected to the first conductive pattern.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0022000 filed on February 24, 2020, as well as all derivative benefits thereof, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a display device and a manufacturing method thereof. BACKGROUND

[0003] A display device includes a display panel including a plurality of pixels for displaying an image, a gate driver for providing a gate signal to the pixels, and a data driver for providing a data voltage to the pixels. The gate driver and the data driver are connected to the display panel.

[0004] The gate driver generates the gate signal and provides the generated gate signal to the pixels. The data driver generates the data voltage and provides the generated data voltage to the pixels. The pixels receive the data voltage in response to the gate signal and display the image. SUMMARY

[0005] One or more embodiments provide a display device and a manufacturing method thereof that increase a contact area between a conductive layer of a display panel and a signal line and minimize external exposure of the conductive layer to the outside of the display panel.

[0006] An embodiment provides a display device including a first substrate including a first side surface, a second substrate facing the first substrate and including a second side surface coplanar with the first side surface, a sealing layer located between the first substrate and the second substrate and extending along an edge of each of the first substrate and the second substrate, the sealing layer including a third side surface coplanar with the second side surface, a first recess defined from each of the first side surface, the second side surface, and the third side surface, a first conductive pattern located in the first recess, and a first driver facing each of the first side surface, the second side surface, and the third side surface. At the first recess: the first conductive pattern is exposed to the outside of the first substrate, the second substrate, and the sealing layer, and the first driver is electrically connected to the first conductive pattern.

[0007] In an embodiment, a method of manufacturing a display device includes: providing a display panel including a first substrate including a first side surface, a second substrate facing the first substrate and including a second side surface coplanar with the first side surface, and a sealing layer extending along an edge of each of the first substrate and the second substrate, the sealing layer including a third side surface coplanar with the second side surface; providing a first recess defined by being recessed from each of the first side surface, the second side surface, and the third side surface; providing a first conductive pattern in the first recess; and providing a first driver facing each of the first side surface, the second side surface, and the third side surface, electrically connected to the first conductive pattern. BRIEF DESCRIPTION OF DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application. In the drawings:

[0009] Figure 1 is a top view showing an embodiment of a display device;

[0010] Figure 2 is a perspective view showing an embodiment of a display device in Figure 1 ;

[0011] Figure 3 is a view showing an embodiment of a pixel in Figure 1 ;

[0012] Figure 4 is a sectional view showing an embodiment of a pixel in Figure 3 ;

[0013] Figure 5 is a perspective view showing an embodiment of a side surface of a display panel with respect to a gate driver in Figure 2 ;

[0014] Figure 6 is a sectional view taken along line I-I' of Figure 5 ;

[0015] Figure 7 is a sectional view taken along line II-II' of Figure 5 ;

[0016] Figure 8 is a perspective view showing an embodiment of an end of a gate line in Figure 7 ;

[0017] Figure 9 is a view showing an embodiment of a side surface of a display panel with respect to a data driver in Figure 2 ;

[0018] Figure 10 is a cross-sectional view taken along the line III-III' of Figure 9

[0019] Figure 11 is a cross-sectional view taken along the line IV-IV' of Figure 9

[0020] Figure 12 is a perspective view of an embodiment showing the end of a data line in Figure 11

[0021] Figure 13 and Figure 14 are views respectively showing the shape of an embodiment of the end of a gate line; and

[0022] Figures 15 to 22 is a view of a structure in an embodiment of a method for manufacturing a display device. DETAILED DESCRIPTION

[0023] The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments of the application are shown. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0024] In this specification, it will also be understood that when a component (or region, layer, part) is referred to as being "on" another component (or region, layer, part), it can be directly on the other component (or region, layer, part) or intervening third components (or regions, layers, parts) can also be present. In contrast, when a component (or region, layer, part) is referred to as being "directly on" another component (or region, layer, part), there are no intervening third components (or regions, layers, parts) interposed therebetween.

[0025] The same reference numerals refer to the same elements throughout the specification. Also, in the drawings, the thickness, proportions, and dimensions of components can be exaggerated for clarity of explanation.

[0026] It will be understood that, although the terms "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from another. For example, an element referred to as a first element in one embodiment can be referred to as a second element in another embodiment without departing from the scope of the appended claims.

[0027] ​​​The singular form "a," "an," and "the" can include plural references unless the context clearly dictates otherwise. As used herein, the terms "one," "a," and "the" do not exclude the presence of zero, or more than one, of a referenced item. For example, a reference to "an element" can mean zero, one, or more than one element. "At least one" is not to be interpreted as limiting "one." The term "or" is used in its inclusive sense (i.e., "and / or") unless the context clearly indicates otherwise.

[0028] In addition, "below," "under," "above," and "on" are used to describe the relative positioning relationship of the components shown in the drawings. These terms can be relative concepts and can be described based on the direction expressed in the drawings.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Terms, as defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in the description.

[0030] The meaning of "include" or "comprise" specifies attributes, fixed numbers, steps, operations, elements, components, or combinations thereof, but does not exclude other attributes, fixed numbers, steps, operations, elements, components, or combinations thereof.

[0031] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can often have rough and / or nonlinear features. Moreover, sharp angles that are illustrated can be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

[0032] An area of a display device in which a driver such as a gate driver or a data driver is disposed is defined as a bezel area. In order to reduce the size of the bezel area, a technique of connecting a gate driver and a data driver to a side surface of a display panel has been developed.

[0033] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0034] Figure 1 is a top view showing an embodiment of a display device DD.

[0035] Reference Figure 1 The display device DD includes a display panel DP, first and second gate drivers GDR1 and GDR2 (e.g., gate drivers GDR1 and GDR2), a data driver DDR, and a circuit board such as a printed circuit board PCB. The display panel DP can have a rectangular shape having long sides each extending in a first direction DR1 and short sides each extending in a second direction DR2 intersecting the first direction DR1. However, the shape of the display panel DP is not limited thereto.

[0036] Hereinafter, a direction intersecting a plane defined by the first direction DR1 and the second direction DR2 will be defined as a third direction DR3. The third direction DR3 can intersect the plane in a substantially perpendicular manner, but is not limited thereto. The third direction DR3 can define a thickness direction of the display device DD and various components thereof. In addition, in the present specification, the expression “when viewed from the plane” or “in a plan view” can mean a view in the third direction DR3.

[0037] The display panel DP can be a liquid crystal display panel including a liquid crystal layer LC (see Figure 3 ) but is not limited thereto. In an embodiment, for example, the display panel DP can be an electrophoretic display panel including an electrophoretic layer or an electro wetting display panel including an electro wetting layer. Each of the liquid crystal layer LC, the electrophoretic layer, and the electro wetting layer can be defined as an image display layer.

[0038] The display panel DP can include a plurality of pixels PX (e.g., a plurality of pixels PX) provided as a plurality, a plurality of gate lines GL1 to GLm as signal lines, and a plurality of data lines DL1 to DLn as signal lines. Here, reference numerals “m” and “n” are natural numbers. The gate lines GL1 to GLm and the data lines DL1 to DLn can extend to cross each other in an insulating manner.

[0039] The pixels PX are connected to the gate lines GL1 to GLm and the data lines DL1 to DLn. Each of the pixels PX can display one of primary colors. The primary colors can include red, green, blue, and white, but are not limited thereto. In an embodiment, for example, the primary colors can further include various colors such as yellow, cyan, and magenta.

[0040] The gate lines GL1 to GLm can each extend in the first direction DR1, and the data lines DL1 to DLn can each extend in the second direction DR2. The gate drivers GDR1 and GDR2 can be connected to the display panel DP, and particularly, to the gate lines GL1 to GLm of the display panel DP. The data driver DDR can be connected to the display panel DP, and particularly, to the data lines DL1 to DLn of the display panel DP.

[0041] Exemplarily, the gate drivers GDR1 and GDR2 and the data driver DDR are separated from the display panel DP (e.g., outside the display panel DP) so as to show a plan view of the gate drivers GDR1 and GDR2 and the data driver DDR. The configuration in which the gate drivers GDR1 and GDR2 and the data driver DDR are connected to the display panel DP will be described in detail below.

[0042] The gate drivers GDR1 and GDR2 can include the first gate driver GDR1 and the second gate driver GDR2 disposed in respective sides opposite to each other in the first direction DR1 among opposite sides of the display panel DP. The first gate driver GDR1 and the second gate driver GDR2 can be adjacent to short sides of the display panel DP, respectively.

[0043] The first gate driver GDR1 can be connected to odd gate lines among the gate lines GL1 to GLm. The second gate driver GDR2 can be connected to even gate lines among the gate lines GL1 to GLm.

[0044] Although two gate drivers GDR1 and GDR2 are shown, the number of gate drivers is not limited thereto. In an embodiment, for example, one gate driver can be disposed at one side of the display panel DP and connected to the gate lines GL1 to GLm.

[0045] Each of the first gate driver GDR1 and the second gate driver GDR2 can include a first flexible circuit board FPC1 (e.g., a first circuit board or a gate circuit board) provided as a plurality (e.g., a plurality of first flexible circuit boards FPC1) and a first driving chip IC1 (e.g., a gate driving chip) mounted to the first flexible circuit board FPC1, respectively (e.g., a plurality of first driving chips IC1). The first driving chip IC1 can be connected to the display panel DP through the first flexible circuit board FPC1.

[0046] The first driving chip IC1 of the first gate driver GDR1 can be connected to the odd gate lines through the first flexible circuit board FPC1 of the first gate driver GDR1. The first driving chip IC1 of the second gate driver GDR2 can be connected to the even gate lines through the first flexible circuit board FPC1 of the second gate driver GDR2.

[0047] Figure 1 Four first driving chips IC1 and four first flexible circuit boards FPC1 located within each of the first gate driver GDR1 and the second gate driver GDR2 are exemplarily shown, but the number of each of the first driving chip IC1 and the first flexible circuit board FPC1 is not limited thereto.

[0048] The data driver DDR can be disposed at a side of the display panel DP intersecting each of sides at which the first gate driver GDR1 and the second gate driver GDR2 are disposed. The side can be one of opposite sides of the display panel DP facing each other in the second direction DR2. The data driver DDR can be disposed adjacent to one of long sides of the display panel DP.

[0049] The data driver DDR can include a plurality of second flexible circuit boards FPC2 (e.g., second circuit boards or data circuit boards) (e.g., a plurality of second flexible circuit boards FPC2) and a plurality of second driving chips IC2 (e.g., data driving chips) (e.g., a plurality of second driving chips IC2) respectively mounted to the second flexible circuit boards FPC2. The second driving chips IC2 can be connected to the display panel DP through the second flexible circuit boards FPC2.

[0050] Figure 1 Five second driving chips IC2 and five second flexible circuit boards FPC2 are exemplarily illustrated, but the number of each of the second driving chips IC2 and the second flexible circuit boards FPC2 is not limited thereto.

[0051] The second flexible circuit boards FPC2 can be connected to a printed circuit board PCB (e.g., a third circuit board). The second driving chips IC2 can be connected to the printed circuit board PCB through the second flexible circuit boards FPC2.

[0052] A timing controller (not illustrated) can be disposed on the printed circuit board PCB. The timing controller can be mounted on the printed circuit board PCB in the form of an integrated circuit chip. The timing controller can be connected to the first gate driver GDR1 and the second gate driver GDR2 and the data driver DDR. The timing controller can output electrical signals, such as a gate control signal, a data control signal, and image data. The printed circuit board PCB can provide the electrical signals from outside the display panel DP.

[0053] The first gate driver GDR1 and the second gate driver GDR2 can receive the gate control signal from the timing controller and generate a plurality of gate signals as electrical signals in response to the gate control signal. The gate control signal can be provided to the first gate driver GDR1 and the second gate driver GDR2 through a portion of the second flexible circuit board FPC2 and the display panel DP. The gate signals can be sequentially output. The gate signals can be provided to the pixels PX through the gate lines GL1 to GLm.

[0054] The data driver DDR receives the image data and the data control signal from the timing controller. The data driver DDR can generate and output a data voltage of an analog type corresponding to the image data as an electrical signal in response to the data control signal. The data voltage can be provided to the pixels PX through the data lines DL1 to DLn.

[0055] The pixel PX can receive a data voltage through the data line DL1 to DLn in response to a gate signal provided through the gate line GL1 to GLm. The pixel PX can emit and / or display a gray level corresponding to the data voltage to display an image.

[0056] Figure 2 is a perspective view illustrating an embodiment of a display device DD in Figure 1

[0057] Referring to Figure 2 The display panel DP can include a first substrate SUB1, a second substrate SUB2, and an encapsulation layer SL (e.g., a sealing layer or a sealant) disposed between the first substrate SUB1 and the second substrate SUB2. That is, the first substrate SUB1 faces the second substrate SUB2, with the encapsulation layer SL therebetween. The outer side surfaces of the first substrate SUB1, the second substrate SUB2, and the encapsulation layer SL on the same side of the display panel DP can together define a corresponding outer side surface of the display panel DP. The outer side surfaces of the first substrate SUB1, the second substrate SUB2, and the encapsulation layer SL on the same side of the display panel DP can be coplanar with each other to define a corresponding outer side surface of the display panel DP. The display panel DP can include first outer side surfaces (e.g., a first side surface and a second side surface) opposite each other along a first direction DR1 and second outer side surfaces (e.g., a third side surface and a fourth side surface) opposite each other along a second direction DR2.

[0058] Each of the first substrate SUB1 and the second substrate SUB2 can have a rectangular shape having long sides each extending along the first direction DR1 and short sides each extending along the second direction DR2. The encapsulation layer SL can extend along edges (e.g., outer edges) of each of the first substrate SUB1 and the second substrate SUB2 to attach the first substrate SUB1 and the second substrate SUB2 to each other.

[0059] The display device DD can include a backlight unit BLU disposed under the display panel DP. The backlight unit BLU can generate and emit light, and provide the generated light to the display panel DP. The pixels PX of the display panel DP can display an image by using the light provided from the backlight unit BLU.

[0060] The first gate driver GDR1 and the second gate driver GDR2 can be disposed on side surfaces of the display panel DP. In an embodiment, for example, the first gate driver GDR1 and the second gate driver GDR2 can be disposed to respectively face side surfaces of the display panel DP opposite each other along the first direction DR1, and connected to the opposite side surfaces of the display panel DP. Although in Figure 2 ​Only the first gate driver GDR1 provided on one outer surface of the display panel DP is shown in the perspective view, but the second gate driver GDR2 can be provided on another outer surface of the display panel DP opposite to the one outer surface in the first direction DR1.

[0061] The data driver DDR can be provided on still another outer surface of the display panel DP different from the above-mentioned outer surfaces. In an embodiment, for example, the data driver DDR can be provided on one of the outer surfaces of the display panel DP opposite to each other in the second direction DR2, and connected to the outer surface of the display panel DP.

[0062] Hereinafter, both of the outer surfaces of the first substrate SUB1 on which the first gate driver GDR1 and the second gate driver GDR2 are provided are defined as first side surfaces SF1 (e.g., first outer surfaces). The first side surfaces SF1 can be defined by the short sides of the first substrate SUB1. The first side surfaces SF1 can each extend in the second direction DR2.

[0063] The side surface of the first substrate SUB1 on which the data driver DDR is provided is defined as a second side surface SF2 (e.g., a second outer surface). The second side surface SF2 can be defined by one of the long sides of the first substrate SUB1. The second side surface SF2 can extend in the first direction DR1.

[0064] The first gate driver GDR1 and the second gate driver GDR2 can be connected to the first side surfaces SF1 of the first substrate SUB1, corresponding side surfaces of the encapsulation layer SL provided in the same plane (e.g., coplanar with) as the first side surfaces SF1, and corresponding side surfaces of the second substrate SUB2 provided in the same plane as the first side surfaces SF1. The data driver DDR can be connected to the second side surface SF2, corresponding side surfaces of the encapsulation layer SL provided in the same plane as the second side surface SF2, and corresponding side surfaces of the second substrate SUB2 provided in the same plane as the second side surface SF2.

[0065] The first gate driver GDR1 and the second gate driver GDR2 can be electrically connected to the gate lines GL1 to GLm of which ends are provided at the first side surfaces SF1. The data driver DDR can be electrically connected to the data lines DL1 to DLn of which ends are provided at the second side surface SF2. The above-mentioned configuration will be described in detail below.

[0066] Figure 3 is a view showing an embodiment in a pixel PX in Figure 1

[0067] Figure 3 ​A pixel PXij in which a pixel PX is connected to a gate line GLi among the gate lines GL1 to GLm and a data line DLj among the data lines DL1 to DLn is shown in FIG. 1. Each of the pixels PX in the display panel DP can have the same configuration as the pixel PXij with respect to a corresponding gate line among the gate lines GL1 to GLm and a corresponding data line among the data lines DL1 to DLn. Figure 3 The pixel PXij in FIG. 1 can have the same configuration as the pixel PXij in FIG. 2.

[0068] Referring to FIG. 1, Figure 3 The first substrate SUB1 can include the gate line GLi, the data line DLj, and the pixel PXij connected to the gate line GLi and the data line DLj. Specifically, the pixel PXij can include a transistor TR connected to the gate line GLi and the data line DLj, a first capacitor such as a liquid crystal capacitor Clc connected to the transistor TR, and a second capacitor such as a storage capacitor Cst connected in parallel to the liquid crystal capacitor Clc. In an embodiment, the storage capacitor Cst can be omitted. In addition, the reference numerals “i” and “j” are natural numbers.

[0069] The transistor TR can include a gate electrode GE (see Figure 4 ) connected to the gate line GLi, a source electrode SE (see Figure 4 ) connected to the data line DLj, and a drain electrode DE (see Figure 4 ) connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

[0070] The liquid crystal capacitor Clc can include a pixel electrode PE of the first substrate SUB1 connected to the transistor TR, a common electrode CE of the second substrate SUB2, and a liquid crystal layer LC disposed between the pixel electrode PE and the common electrode CE. The liquid crystal layer LC can function as a dielectric material.

[0071] Although the pixel electrode PE has a non-slit structure in Figure 3 , the structure is not limited thereto. In an embodiment, for example, the pixel electrode PE can have a slit structure including a trunk portion having a cross shape and a plurality of branch portions extending radially from the trunk portion. The common electrode CE can be disposed over the entire second substrate SUB2, for example, corresponding to one or more pixels among the pixels PX.

[0072] The storage capacitor Cst can include the pixel electrode PE, a storage electrode (not shown) branched from a storage line (not shown), and an insulating layer disposed between the pixel electrode PE and the storage electrode. The storage line can be disposed in the first substrate SUB1 and can be provided in the same layer as the gate lines GL1 to GLm at the same time. The storage electrode can partially overlap the pixel electrode PE in a third direction DR3. When “in the same layer”, elements or features can be individual portions of the same material layer, but are not limited thereto.

[0073] The pixel PXij can further include a color filter CF having one of red, green, and blue colors. The color filter CF will be shown in Figure 4

[0074] The transistor TR can be turned on in response to a gate signal provided through the gate line GLi. A data voltage received through the data line DLj can be provided to the pixel electrode PE of the liquid crystal capacitor Clc through the turned-on transistor TR. A common voltage can be applied to the common electrode CE.

[0075] An electric field can be provided between the pixel electrode PE and the common electrode CE due to a difference between voltage levels of the data voltage and the common voltage. Liquid crystal molecules of the liquid crystal layer LC can be driven by the electric field provided between the pixel electrode PE and the common electrode CE. An image can be displayed when a transmittance is adjusted by the liquid crystal molecules driven by the electric field.

[0076] A storage voltage having a predetermined voltage level can be applied to the storage line, but is not limited thereto. In an embodiment, for example, a common voltage can be applied to the storage line. The storage capacitor Cst can be used to supplement an amount of charge in the liquid crystal capacitor Clc.

[0077] Figure 4 is a schematic cross-sectional view showing an embodiment of the pixel PXij in Figure 3 In a plane defined by a first direction DR1 and a second direction DR2 intersecting each other, Figure 4 The horizontal direction in can denote the first direction DR1 and / or the second direction DR2.

[0078] For ease of description, the storage capacitor Cst is omitted in Figure 4

[0079] Referring to Figure 4 The first base substrate BS1 can be a transparent or non-transparent insulating substrate. In an embodiment, for example, the first base substrate BS1 can include a silicon substrate, a glass substrate, or a plastic substrate.

[0080] The first base substrate BS1 can be a transparent or non-transparent insulating substrate. In an embodiment, for example, the first base substrate BS1 can include a silicon substrate, a glass substrate, or a plastic substrate.

[0081] ​​The gate electrode GE of the transistor TR can be disposed on the first base substrate BS1. The gate electrode GE can branch substantially from the gate line GLi. The first insulating layer INS1 can be disposed on the first base substrate BS1 to cover the gate electrode GE. The first insulating layer INS1 can be defined as a gate insulating layer. The first insulating layer INS1 can be an inorganic insulating layer including an inorganic material.

[0082] The semiconductor layer SM of the transistor TR can be disposed on the first insulating layer INS1 covering the gate electrode GE. Although not shown, the semiconductor layer SM can include an active layer and an ohmic contact layer.

[0083] The source electrode SE and the drain electrode DE of the transistor TR can be spaced apart from each other along the semiconductor layer SM and along the first insulating layer INS1. The semiconductor layer SM can provide a conductive channel of the transistor TR between the source electrode SE and the drain electrode DE.

[0084] The second insulating layer INS2 can be disposed on the first insulating layer INS1 to cover the source electrode SE and the drain electrode DE. The source electrode SE can branch substantially from the data line DLj. The second insulating layer INS2 can be defined as a passivation layer and can be an inorganic insulating layer including an inorganic material.

[0085] The color filter CF can be disposed on the second insulating layer INS2. The contact hole CH exposing the drain electrode DE can be defined to extend through a thickness of the color filter CF and a thickness of the second insulating layer INS2.

[0086] A portion of the pixel electrode PE located in the pixel area PA can be disposed on the color filter CF. The pixel electrode PE can extend from the pixel area PA to dispose a portion of the pixel electrode PE in the non-pixel area NPA. At the portion of the pixel electrode PE located in the non-pixel area NPA, the pixel electrode PE is electrically connected to the drain electrode DE at the contact hole CH.

[0087] The first substrate SUB1 is disposed facing the second substrate SUB2 with the liquid crystal layer LC therebetween. The second substrate SUB2 can include a second base substrate BS2, a black matrix BM (e.g., a light-shielding layer), a third insulating layer INS3, and a common electrode CE. The second base substrate BS2 can include the same material as the first base substrate BS1.

[0088] The black matrix BM corresponding to the non-pixel area NPA can be disposed under the second base substrate BS2. The third insulating layer INS3 can be disposed under the second base substrate BS2 to cover the black matrix BM. The common electrode CE can be disposed under the third insulating layer INS3.

[0089] The liquid crystal capacitor Clc can include a pixel electrode PE, a common electrode CE facing the pixel electrode PE, and a liquid crystal layer LC disposed between the pixel electrode PE and the common electrode CE.

[0090] Figure 5 is a view showing an embodiment of a perspective view of an outer side surface of the first gate driver GDR1 of the display panel DP. Figure 2

[0091] Referring to Figure 5 The first recessed portions RES1 (e.g., first recesses) provided as a plurality of first recessed portions RES1 (e.g., a plurality of first recessed portions RES1) can be defined in one outer side surface of the display panel DP. The first recessed portions RES1 can be arranged adjacent to each other along the second direction DR2, and can each extend along the third direction DR3. A length of the first recessed portions RES1 can be defined along the third direction DR3, while a width can be defined along the second direction DR2. The first recessed portions RES1 can be defined at the first side surface SF1 of the first substrate SUB1, and each extend from the first side surface SF1 to each of a corresponding side surface of the encapsulation layer SL and a corresponding side surface of the second substrate SUB2.

[0092] The same one of the first recessed portions RES1 can be defined recessed from the first side surface SF1 (e.g., a first outer side surface), a third side surface SF1_1 (e.g., a third outer side surface) of the encapsulation layer SL in the same plane as the first side surface SF1, and a fourth side surface SF1_2 (e.g., a fourth outer side surface) of the second substrate SUB2 in the same plane as the first side surface SF1. The first recessed portions RES1 can be continuously defined along the third direction DR3 and corresponding to each of the first side surface SF1, the third side surface SF1_1 defined by the encapsulation layer SL, and the fourth side surface SF1_2 defined by the second substrate SUB2.

[0093] The display panel DP can include first conductive layers CTL1 (e.g., first conductive patterns) provided as a plurality of first conductive layers CTL1 (e.g., a plurality of first conductive layers CTL1) respectively disposed in the first recessed portions RES1. The first conductive layers CTL1 can be arranged adjacent to each other along the second direction DR2, and can each extend along the third direction DR3. In a view along the first direction DR1, the first conductive layers CTL1 can each have a rectangular shape extending further along the third direction DR3 than along the second direction DR2. The first conductive layers CTL1 of the display panel DP can be exposed at their extremities to the outside of the display panel DP. An outer surface of the first conductive layers CTL1 exposed to the outside of the display panel DP can be coplanar with each of the first side surface SF1, the third side surface SF1_1, and the fourth side surface SF1_2. ​

[0094] The first flexible circuit board FPC1 of the first gate driver GDR1 can be disposed to collectively face the first side surface SF1, a third side surface SF1_1 defined by the encapsulation layer SL, and a fourth side surface SF1_2 defined by the second substrate SUB2. The first gate driver GDR1 can include first pads PD1 (e.g., a plurality of first pads PD1) provided as a plurality of pads disposed on or protruding from a first surface OSF1 (e.g., an inner surface) of the first flexible circuit board FPC1 facing the display panel DP. Each of the first pads PD1 can include a conductive material.

[0095] The first pads PD1 can be arranged adjacent to each other along the second direction DR2 and can each extend along the third direction DR3. Each of the first pads PD1 can have a rectangular shape in a view along the first direction DR1 that extends further along the third direction DR3 than along the second direction DR2.

[0096] The first pads PD1 can correspond to the first conductive layer CTL1 when viewed along the first direction DR1. The first gate driver GDR1 can include a first driving chip IC1 and first lines SNL1 (e.g., a plurality of first lines SNL1 or first conductive lines) provided as a plurality of lines electrically connected to the first pads PD1, respectively. The first driving chip IC1 and the first lines SNL1 can be disposed on or protrude from a surface (e.g., an outer surface) of the first flexible circuit board FPC1 opposite the first surface OSF1. A single first driving chip IC1 can correspond to each of the first lines SNL1, but is not limited thereto.

[0097] Although not shown, the first lines SNL1 located at the outer surface of the first flexible circuit board FPC1 can be electrically connected to the first pads PD1 located at the first surface OSF1 through a through-hole defined in or extending through a thickness of the first flexible circuit board FPC1. As Figure 5 and Figure 6 The thickness of the first flexible circuit board FPC1 is defined along the first direction DR1.

[0098] Figure 6 is a cross-sectional view taken along a line I-I' of Figure 5 . Figure 7 is a cross-sectional view taken along a line II-II' of Figure 5 . Figure 8 is a perspective view illustrating an embodiment of an end of a gate line GLi in Figure 7 .

[0099] In Figure 7 , the gate lines GLi to GLi+3 disposed on the first base substrate BS1 and the first conductive layer CTL1 are exemplarily shown.

[0100] refer to Figure 6 An encapsulation layer SL can be disposed at the edge (e.g., outer edge) of the first substrate SUB1 and the edge (e.g., outer edge) of the second substrate SUB2 to attach the first substrate SUB1 and the second substrate SUB2 to each other. A liquid crystal layer LC can be housed between the first substrate SUB1 and the second substrate SUB2 via the encapsulation layer SL located at the outer edge of the display panel DP.

[0101] The bottom of the first recessed portion RES1 can be defined by the end-side surface of each of the following: the first substrate BS1, the gate line GL1, the first insulating layer INS1 and the second insulating layer INS2, the color filter CF, the encapsulation layer SL, the common electrode CE, the third insulating layer INS3, the black matrix BM, and the second substrate BS2. The end-side surface can be defined by... Figure 5 Each of the first side surface SF1, the third side surface SF1_1, and the fourth side surface SF1_2 on the same side of the display panel DP is recessed. The end side surfaces may be coplanar with each other to collectively define the bottom of the first recessed portion RES1. The bottom of the first recessed portion RES1 may be maximally distanced from each of the first side surface SF1, the third side surface SF1_1, and the fourth side surface SF1_2 to be spaced apart from the outer surface of the display panel DP.

[0102] The end-side surface of the gate line GLi can be defined at the end (e.g., the distal end) of the gate line GLi and can contact the first conductive layer CTL1 at the first recessed portion RES1. Therefore, the gate line GLi can be electrically connected to the first conductive layer CTL1 at the first recessed portion RES1. Specifically, the gate line GLi can be electrically connected to the first conductive layer CTL1 at the bottom of the first recessed portion RES1.

[0103] The first pad PD1 can be electrically connected to the first conductive layer CTL1 and the gate line GLi. A first anisotropic conductive film ACF1 can be disposed between the first pad PD1 and the first conductive layer CTL1 to electrically connect the first conductive layer CTL1 and the gate line GLi to each other.

[0104] The first anisotropic conductive film ACF1 can bury the first conductive layer CTL1 within the first recessed portion RES1. The first anisotropic conductive film ACF1 can, for example, be along the second direction DR2 ( Figure 7 ) and / or along a third-party DR3 ( Figure 6) extends farther than the first conductive layer CTL1 to bury the first conductive layer CTL1 within the first recessed portion RES1. When the first conductive layer CTL1 is buried by the first anisotropic conductive film ACF1, the first conductive layer CTL1 can be least exposed outside the display panel DP. Thus, since the first anisotropic conductive film ACF1 blocks external moisture from entering the first conductive layer CTL1, the first conductive layer CTL1 can not be damaged by external moisture.

[0105] The first pad PD1 and the first conductive layer CTL1 can be electrically connected to each other by the first anisotropic conductive film ACF1. The first pad PD1 can be electrically connected to the gate line GLi through the first conductive layer CTL1.

[0106] Referring to Figure 7 , the first anisotropic conductive film ACF1 can be disposed between the first pad PD1 and the first conductive layer CTL1. The first anisotropic conductive film ACF1 can define a conductive layer commonly disposed corresponding to each of the first pad PD1 and the first conductive layer CTL1 and a region therebetween along the second direction DR2. In an embodiment, Figure 6 and Figure 7 The first flexible circuit board FPC1 can have been pressed along the first direction DR1 and toward the first side surface SF1, the third side surface SF1_1, and the fourth side surface SF1_2 in the display device DD. Figure 5

[0107] In an embodiment of the pressing operation within the method of providing the display device DD, the first conductive balls BO1 (e.g., a plurality of first conductive balls BO1) of the first anisotropic conductive film ACF1, which are provided as a plurality and disposed between the corresponding first pad PD1 and the first conductive layer CTL1 among the first pad PD1 and the first conductive layer CTL1, can contact each other to electrically connect the first pad PD1 and the first conductive layer CTL1 to each other. As a result, the first pad PD1 can be electrically connected to the gate lines GLi to GLi+3 among the gate lines GL1 to GLm through the first conductive layer CTL1.

[0108] Along the second direction DR2, each of the first recessed portions RES1 and each of the first conductive layers CTL1 can have a width greater than a width of each of the gate lines GLi to GLi+3.

[0109] Referring to Figure 6 and Figure 7 ​The first flexible circuit board FPC1 can be connected to the first conductive layer CTL1 and the gate lines GLi to GLi+3 through the first pads PD1, respectively. Accordingly, the first gate driver GDR1 can be connected to the display panel DP at the first outer side surface of the display panel DP. Although not shown, the second gate driver GDR2 can be connected to the second outer side surface of the display panel DP in the same manner.

[0110] The first flexible circuit board FPC1 can extend in parallel to the third direction DR3. That is, since the same first gate driver GDR1 is connected to the display panel DP at each of the first side surface SF1, the third side surface SF1_1, and the fourth side surface SF1_2, the first flexible circuit board FPC1 can extend in the third direction DR3 crossing a plane of the first substrate SUB1 (e.g., a plane defined by the first direction DR1 and the second direction DR2). The first flexible circuit board FPC1 can be disposed on a plane defined by the second direction DR2 and the third direction DR3 crossing each other.

[0111] In a conventional display device in which the first flexible circuit board FPC1 is disposed in parallel to a plane of the first substrate SUB1 and is connected to a top surface of the first substrate SUB1 extending from an outer side surface of the first substrate SUB1, a planar area (e.g., a bezel area) along a plane of the first substrate SUB1 in which the first gate driver GDR1 and the second gate driver GDR2 are disposed can increase. However, in one or more embodiments of the present disclosure, since the first gate driver GDR1 and the second gate driver GDR2 are connected to the display panel DP at the outer side surfaces opposite to each other along the first direction DR1, respectively, a planar area (e.g., a bezel area) along a plane of the first substrate SUB1 in which the first gate driver GDR1 and the second gate driver GDR2 are disposed can be minimized.

[0112] Reference Figure 7 and Figure 8 The terminal end of each of the gate lines GLi to GLi+3 can include first protruding portions PT1 (e.g., a plurality of first protruding portions PT1) provided as a plurality and first grooves GV1 (e.g., a plurality of first grooves GV1) provided as a plurality, which alternate with each other. The first protruding portions PT1 can define a terminal side surface extending in the third direction DR3. The first protruding portions PT1 can be spaced apart from each other along the second direction DR2. That is, the terminal side surfaces within the same one of the gate lines GLi to GLi+3 can be arranged along the second direction DR2. The first grooves GV1 can be defined between the first protruding portions PT1 consecutive along the second direction DR2. In a view along the third direction DR3 (e.g., a view along the third direction DR3 of FIG. 1), the first protruding portions PT1 can be arranged in a zigzag pattern along the second direction DR2. Figure 7In the gate line GLi to GLi+3, each of the first protruding portions PT1 can have a trapezoidal planar shape, and each of the first grooves GV1 can have a "V" shape. That is, the respective ends of the gate lines GLi to GLi+3 define a plurality of first protruding portions PT1 that protrude in the first direction DR1 and are arranged in the second direction DR2.

[0113] When the ends of each of the gate lines GLi to GLi+3 include the first protruding portions PT1, since a plurality of end side surfaces are defined for each of the gate lines GLi to GLi+3, the surface area at the ends of each of the gate lines GLi to GLi+3 can increase. Accordingly, the end of the gate lines GLi to GLi+3 can increase the planar area of the first conductive layer CTL1 that is contacted. The contact area can be defined by the planar area of the end surface along the plane defined by the second direction DR2 and the third direction DR3 and the planar area of the surface that is inclined from the end surface. Since the contact area increases, the electrical connection performance between the first conductive layer CTL1 and the corresponding first conductive layer and the gate line among the gate lines GLi to GLi+3 can be improved.

[0114] Figure 9 is a view showing a perspective view of an embodiment of the outer side surface of the display panel DP with respect to Figure 2 is a view showing a perspective view of an embodiment of the outer side surface of the display panel DP with respect to

[0115] Referring to Figure 9 A second recessed portion RES2 (e.g., a second recess) (e.g., a plurality of second recessed portions RES2) can be defined in the outer side surface of the display panel DP. The second recessed portions RES2 can be arranged adjacent to each other in the first direction DR1 and can each extend in the third direction DR3. The second recessed portions RES2 can be defined at the second side surface SF2 of the first substrate SUB1 and each extend from the second side surface SF2 to each of the corresponding side surface of the encapsulation layer SL and the corresponding side surface of the second substrate SUB2.

[0116] The same one of the second recessed portions RES2 can be defined recessed from the second side surface SF2, a fifth side surface SF2_1 (e.g., a fifth outer side surface) defined by the encapsulation layer SL that is disposed in the same plane as the second side surface SF2, and a sixth side surface SF2_2 (e.g., a sixth outer side surface) defined by the second substrate SUB2 that is disposed in the same plane as the second side surface SF2. The second recessed portions RES2 can be continuously defined along the third direction DR3 and with respect to each of the second side surface SF2, the fifth side surface SF2_1 defined by the encapsulation layer SL, and the sixth side surface SF2_2 defined by the second substrate SUB2.

[0117] The display panel DP can include a second conductive layer CTL2 (e.g., a second conductive pattern) provided as a plurality of second conductive layers CTL2 (e.g., a plurality of second conductive layers CTL2) respectively disposed in the second recessed portion RES2. The second conductive layers CTL2 can be arranged adjacent to each other along the first direction DR1 and each extend in the third direction DR3. In a view along the second direction DR2, the second conductive layers CTL2 can each have a rectangular shape that extends farther in the third direction DR3 than in the first direction DR1. The second conductive layers CTL2 of the display panel DP can be exposed outside the display panel DP at their ends. The outer surfaces of the second conductive layers CTL2 exposed outside the display panel DP can be coplanar with each of the second side surface SF2, the fifth side surface SF2_1 defined by the sealing layer SL, and the sixth side surface SF2_2 defined by the second substrate SUB2.

[0118] The second flexible circuit board FPC2 of the data driver DDR can be disposed to collectively face the second side surface SF2, the fifth side surface SF2_1 defined by the sealing layer SL, and the sixth side surface SF2_2 defined by the second substrate SUB2. The data driver DDR can include a second pad PD2 (e.g., a plurality of second pads PD2) provided as a plurality of second pads PD2 disposed on or protruding from a first surface OSF2 (e.g., an inner surface) of the second flexible circuit board FPC2 facing the display panel DP. Each of the second pads PD2 can include a conductive material.

[0119] The second pads PD2 can be arranged adjacent to each other along the first direction DR1 and can each extend in the third direction DR3. In a view along the second direction DR2, the second pads PD2 can each have a rectangular shape that extends farther in the third direction DR3 than in the first direction DR1.

[0120] The second pads PD2 can correspond to the second conductive layers CTL2 when viewed along the second direction DR2. The data driver DDR can include a second driving chip IC2 and a second wire SNL2 (e.g., a plurality of second wires SNL2 or second conductive lines) provided as a plurality of second wires SNL2 respectively electrically connected to the second pads PD2. The second driving chip IC2 and the second wire SNL2 can be disposed on or protrude from a surface (e.g., an outer surface) of the second flexible circuit board FPC2 opposite the first surface OSF2. A single second driving chip IC2 can correspond to each of the second wires SNL2, but is not limited thereto.

[0121] Although not shown, the second wire SNL2 located at the outer surface of the second flexible circuit board FPC2 can be electrically connected to the second pad PD2 at the first surface OSF2 through a through-hole defined in or extending through the thickness of the second flexible circuit board FPC2. As Figure 9 andFigure 10 The thickness of the second flexible circuit board FPC2 is defined in the second direction DR2.

[0122] Figure 10 is a cross-sectional view taken along the line III-III' of Figure 9 Figure 11 is a cross-sectional view taken along the line IV-IV' of Figure 9 Figure 12 is a perspective view of an embodiment showing the end of the data line DLj in Figure 10

[0123] In Figure 11 In

[0124] Referring to Figure 10 The bottom of the second recessed portion RES2 can be defined by the end side surfaces of each of the first base substrate BS1, the data line DLj, the first and second insulating layers INS1 and INS2, the color filter CF, the sealing layer SL, the common electrode CE, the third insulating layer INS3, the black matrix BM, and the second base substrate BS2. The end side surfaces can each be recessed from the second side surface SF2, the fifth side surface SF2_1, and the sixth side surface SF2_2 on the same side of the display panel DP in Figure 9 The bottom of the second recessed portion RES2 can be defined by the end side surfaces of each of the first base substrate BS1, the data line DLj, the first and second insulating layers INS1 and INS2, the color filter CF, the sealing layer SL, the common electrode CE, the third insulating layer INS3, the black matrix BM, and the second base substrate BS2. The end side surfaces can each be recessed from the second side surface SF2, the fifth side surface SF2_1, and the sixth side surface SF2_2 on the same side of the display panel DP in

[0125] The end side surface of the data line DLj can be defined at the end of the data line DLj and can contact the second conductive layer CTL2 at the second recessed portion RES2. Thus, the data line DLj can be electrically connected to the second conductive layer CTL2 at the second recessed portion RES2. In detail, the data line DLj can be electrically connected to the second conductive layer CTL2 at the bottom of the second recessed portion RES2.

[0126] The second pad PD2 can be electrically connected to the second conductive layer CTL2 and the data line DLj. The second anisotropic conductive film ACF2 can be provided between the second pad PD2 and the second conductive layer CTL2 to electrically connect the second conductive layer CTL2 and the data line DLj to each other.

[0127] The second anisotropic conductive film ACF2 can bury the second conductive layer CTL2 in the second recessed portion RES2. The second anisotropic conductive film ACF2 may, for example, be provided along the first direction DR1 Figure 11 ​​​) and / or along the third direction DR3 Figure 10 ) extends farther than the second conductive layer CTL2 to bury the second conductive layer CTL2 within the second recessed portion RES2. Thus, since the second conductive layer CTL2 is minimally exposed outside the display panel DP by the second anisotropic conductive film ACF2, external moisture is blocked from entering the second conductive layer CTL2, and the second conductive layer CTL2 is not damaged by the external moisture.

[0128] The second pad PD2 and the second conductive layer CTL2 can be electrically connected to each other by the second anisotropic conductive film ACF2. The second pad PD2 can be electrically connected to the data lines DLj through the second conductive layer CTL2.

[0129] Referring to Figure 11 , the second anisotropic conductive film ACF2 can be disposed between the second pad PD2 and the second conductive layer CTL2. The second anisotropic conductive film ACF2 can define a conductive layer commonly disposed corresponding to each of the second pad PD2 and the second conductive layer CTL2 and an area therebetween along the first direction DR1. In an embodiment, Figure 10 and Figure 11 The second flexible circuit board FPC2 can have been pressed toward the second side surface SF2, the fifth side surface SF2_1, and the sixth side surface SF2_2 in the second side surface SF2, the fifth side surface SF2_1, and the sixth side surface SF2_2 in the Figure 9

[0130] In an embodiment of the pressing operation within the method of providing the display apparatus DD, the second conductive balls BO2 (e.g., a plurality of second conductive balls BO2) of the second anisotropic conductive film ACF2 disposed between the second pad PD2 and the corresponding second pad PD2 and the second conductive layer CTL2 of the second conductive layer CTL2 provided as a plurality can contact each other to electrically connect the second pad PD2 and the second conductive layer CTL2 to each other. As a result, the second pad PD2 can be electrically connected to the data lines DLj to DLj+3 through the second conductive layer CTL2.

[0131] Along the first direction DR1, each of the second recessed portions RES2 and each of the second conductive layers CTL2 can have a width greater than a width of each of the data lines DLj to DLj+3.

[0132] Referring to Figure 10 and Figure 11 The second flexible circuit board FPC2 can be connected to the second conductive layer CTL2 and the data lines DLj to DLj+3, respectively, through the second pad PD2. Thus, the data driver DDR can be connected to the display panel DP at the second outer side surface of the display panel DP.

[0133] ​Since the same data driver DDR is connected to the display panel DP at each of the second side surface SF2, the fifth side surface SF2_1, and the sixth side surface SF2_2, the second flexible circuit board FPC2 can extend along a third direction DR3 crossing a plane of the first substrate SUB1. Since the data driver DDR is connected to one of the second side surfaces of the display panel DP opposite each other along the second direction DR2, a planar area in which the data driver DDR is disposed can be minimized when viewed in a plan view (e.g., along the third direction DR3).

[0134] Referring to Figure 11 and Figure 12 , an end of each of the data lines DLj to DLj+3 can include second protruding portions PT2 provided as a plurality (e.g., a plurality of second protruding portions PT2) and second grooves GV2 provided as a plurality (e.g., a plurality of second grooves GV2) alternating with each other. The second protruding portions PT2 can define end side surfaces extending along the third direction DR3. The second protruding portions PT2 can be spaced apart from each other along the first direction DR1. That is, the end side surfaces within the same one of the data lines DLj to DLj+3 can be arranged along the first direction DR1. The second grooves GV2 can be defined between the second protruding portions PT2 consecutive along the first direction DR1. In a view along the third direction DR3 (e.g., Figure 11 ), each of the second protruding portions PT2 can have a planar shape of a trapezoid, and each of the second grooves GV2 can have a "V" shape. That is, the respective ends of the data lines DLj to DLj+3 define a plurality of second protruding portions PT2 projecting along the second direction DR2 and arranged along the first direction DR1.

[0135] When the end of each of the data lines DLj to DLj+3 includes the second protruding portions PT2, since a plurality of end side surfaces are defined for each of the data lines DLj to DLj+3, a surface area at the end of each of the data lines DLj to DLj+3 can increase. Accordingly, a planar area of the end of the data lines DLj to DLj+3 contacting the second conductive layer CTL2 can increase, and thus an electrical connection performance between the second conductive layer CTL2 and the data lines DLj to DLj+3 can improve.

[0136] As a result, one or more embodiments of the display apparatus DD increase a contact area between signal lines of the display panel DP and respective conductive layers of an external member such as a circuit board. In addition, one or more embodiments of the display apparatus DD minimize external exposure of the conductive layers of the external member outside the display panel DP.

[0137] Figure 13 and Figure 14are plan views respectively showing the planar shape of the end of the gate lines GLi_1 and GLi_2.

[0138] Although not shown, the shape of the end of the data line DLj can be changed to a structure similar to that of each of the gate lines GLi_1 and GLi_2 in Figure 13 and 14 .

[0139] Referring to Figure 13 , the first conductive layer CTL1 can be disposed in the recessed portions RES1_1 provided as a plurality. The end of the gate line GLi_1 can include first protruding portions PT1_1 provided as a plurality (e.g., a plurality of first protruding portions PT1_1) each extending in the third direction DR3 and arranged in the second direction DR2, and first grooves GV1_1 provided as a plurality (e.g., a plurality of first grooves GV1_1) each defined between first protruding portions PT1_1 adjacent to each other. In a view in the third direction DR3, each of the first protruding portions PT1_1 can have a triangular shape, and each of the first grooves GV1_1 can have a "V" shape.

[0140] Referring to Figure 14 , the first conductive layer CTL1 can be disposed in the recessed portions RES1_2 provided as a plurality. The end of the gate line GLi_2 can include first protruding portions PT1_2 provided as a plurality (e.g., a plurality of first protruding portions PT1_2) each extending in the third direction DR3 and arranged in the second direction DR2, and first grooves GV1_2 provided as a plurality (e.g., a plurality of first grooves GV1_2) each defined between first protruding portions PT1_2 adjacent to each other. In a view in the third direction DR3, each of the first protruding portions PT1_2 can have a trapezoidal shape. In a view in the third direction DR3, each of the first grooves GV1_2 can have a trapezoidal shape.

[0141] Figures 15 to 22 are views of structures in an embodiment of a method for providing a display device DD.

[0142] Figures 15 to 22 The side surfaces and cross sections corresponding to those in Figure 6 and Figure 7 are exemplarily shown. In addition, although the bonding process of the first gate driver GDR1 is exemplarily described in Figures 15 to 22 , the second gate driver GDR2 and the data driver DDR can also be bonded to the display panel DP in the same manner.

[0143] Referring to Figure 15 and Figure 16A display panel DP including a first substrate SUB1 and a second substrate SUB2 attached to each other through a sealing layer SL can be provided. Here, the first substrate SUB1 can represent an initial form of the first substrate SUB1 in which the first recessed portion RES1 has not yet been defined. In Figure 15 Each of the outer side surfaces of the first side surface SF1, the third side surface SF1_1, and the fourth side surface SF1_2 can be coplanar with each other within the initial form of the display panel DP shown in FIG. 1. In detail, the terminal surfaces of the gate lines GLi to GLi+3 are coplanar with the first side surface SF1 of the first substrate SUB1.

[0144] Referring to Figure 17 and Figure 18 Laser light LAR can be irradiated to the first side surface SF1, the third side surface SF1_1, and the fourth side surface SF1_2. The first recessed portion RES1 recessed from each of the first side surface SF1, the third side surface SF1_1, and the fourth side surface SF1_2 can be provided or formed by the laser light LAR. The terminals of the gate lines GLi to GLi+3 can include the first protruding portions PT1 when the terminals of the gate lines GLi to GLi+3 are processed by the laser light LAR together with other layers within the display panel DP. The terminals of the gate lines GLi to GLi+3 and the other layers within the display panel DP can be exposed outside the display panel DP at the first recessed portion RES1.

[0145] Referring to Figure 19 and Figure 20 A first conductive layer CTL1 can be provided in the first recessed portion RES1. In an embodiment, a conductive material such as a conductive paste can be provided to the first recessed portion RES1 to form the first conductive layer CTL1 as a plurality of conductive patterns of the display panel DP within the first recessed portion RES1 of the display panel DP. The conductive paste can include silver (Ag). The conductive paste in an uncured form can be provided in the first recessed portion RES1 and then cured, thereby forming the first conductive layer CTL1 as a pattern of the cured conductive material.

[0146] The first conductive layer CTL1 can contact the exposed terminals of the gate lines GLi to GLi+3 at the first recessed portion RES1. In detail, the first conductive layer CTL1 can contact the gate lines GLi to GLi+3 at each of the first protruding portions PT1 and the first grooves GV1 of the gate lines GLi to GLi+3 exposed at the terminals of the gate lines GLi to GLi+3. The shape of the first conductive layer CTL1 can conform to the shape of the terminals of the gate lines GLi to GLi+3 defined together by the first protruding portions PT1 and the first grooves GV1. Accordingly, the first conductive layer CTL1 can be electrically connected to the gate lines GLi to GLi+3 within the first recessed portion RES1 (specifically, at the bottom thereof).

[0147] Reference Figure 21 and Figure 22 A first anisotropic conductive film ACF1 can be provided between the first gate driver GDR1 and the display panel DP. The first gate driver GDR1 can be pressed toward the outer surface of the display panel DP.

[0148] The first gate driver GDR1 can be electrically connected to the display panel DP at the first conductive layer CTL1 of the display panel DP through the first anisotropic conductive film ACF1. In an embodiment, for example, the first pad PD1 of the first gate driver GDR1 can be electrically connected to the display panel DP at the first conductive layer CTL1 through the first anisotropic conductive film ACF1.

[0149] In the same manner, the second gate driver GDR2 can be electrically connected to the display panel DP at the first conductive layer CTL1 provided in the first recessed portion RES1 defined by the laser LAR. In the same manner, the data driver DDR can be electrically connected to the display panel DP at the second conductive layer CTL2 provided in the second recessed portion RES2 defined by the laser LAR.

[0150] According to one or more embodiments, since the end of the signal line of the display panel DP is processed to have a protruding pattern that contacts the conductive layer of the display panel DP, the respective contact area between the signal line and the conductive layer can be improved.

[0151] In addition, since the conductive layer is provided in the recess defined at the side surface of the display panel DP and connected to the external member, the conductive layer of the display panel DP can be minimally exposed outside the display panel DP.

[0152] Although embodiments have been described, the present application is not limited thereto, but various changes and modifications can be made by those skilled in the art within the spirit and scope of the present application as claimed above. Accordingly, the scope of the present application is determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be bound by the foregoing detailed description to the maximum extent permitted by law.

Claims

1. A display device comprising: a first substrate including a first side surface and a plurality of signal lines, an end of each of the plurality of signal lines defining a plurality of protrusions and a plurality of grooves between protrusions adjacent to each other, respectively; a second substrate facing the first substrate and including a second side surface coplanar with the first side surface; a sealing layer between the first substrate and the second substrate and extending along an edge of each of the first substrate and the second substrate, the sealing layer including a third side surface coplanar with the second side surface; a first recess defined from each of the first side surface, the second side surface, and the third side surface, the first recess exposing the ends defining the plurality of protrusions and the plurality of grooves to an outside of the first substrate; a first conductive pattern in the first recess; and a first driver facing each of the first side surface, the second side surface, and the third side surface, wherein, at the first recess: the first conductive pattern is exposed to an outside of the first substrate, the second substrate, and the sealing layer, the first driver is electrically connected to the first conductive pattern, and the first conductive pattern in the first recess defines an outer surface exposed to an outside of the first substrate and the second substrate, and the outer surface of the first conductive pattern is coplanar with the first side surface of the first substrate and the second side surface of the second substrate. the first recess is continuously defined from each of the first side surface of the first substrate, the second side surface of the second substrate, and the third side surface of the sealing layer.

2. The display device according to claim 1, wherein the plurality of signal lines of the first substrate include:

3. The display device according to claim 1, wherein gate lines extending in a first direction and including an end at the first recess, and data lines insulated from the gate lines and extending in a second direction crossing the first direction, wherein the first substrate further includes: pixels connected to the gate lines and the data lines, and wherein the end of the gate lines is electrically connected to the first conductive pattern at the first recess. each of the first recess and the first conductive pattern continuously extends in a third direction crossing each of the first direction and the second direction.

4. The display device according to claim 3, wherein 5.The display device of claim 3, wherein, each of the first recess, the first conductive pattern, and the gate lines has a width extending in the second direction, and the width of the first recess and the width of the first conductive pattern are each greater than the width of the gate lines. 6.The display device of claim 3, wherein, the first driver includes: a first circuit board; a first driver chip on the first circuit board; and a first land connected to the first driver chip, the first circuit board faces each of the first side surface, the second side surface, and the third side surface, and the first land is electrically connected to the first conductive pattern at the first recess. ​ 7. The display device according to claim 6, further comprising a first anisotropic conductive film located between the first pad of the first driver and the first conductive pattern in the first recess, and electrically connecting the first pad and the first conductive pattern to each other.

8. The display device according to claim 7, wherein each of the first recess, the first conductive pattern, and the first anisotropic conductive film has a width extending along the second direction and a length extending along a third direction intersecting each of the first and second directions, and the width and the length of the first anisotropic conductive film are each greater than the width and the length of each of the first recess and the first conductive pattern.

9. The display device according to claim 3, wherein the first substrate further comprises a fourth side surface; the second substrate further comprises a fifth side surface coplanar with the fourth side surface; and the sealing layer further comprises a sixth side surface coplanar with the fifth side surface; wherein the display device further comprises: a second recess defined from each of the fourth, fifth, and sixth side surfaces; a second conductive pattern located in the second recess; and a second driver facing each of the fourth, fifth, and sixth side surfaces, wherein at the second recess: the second conductive pattern is exposed to an outside of the first substrate, the second substrate, and the sealing layer, and the second driver is electrically connected to the second conductive pattern. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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